TWI236712B - Method for forming oxide on ONO structure - Google Patents

Abstract

A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (""ONO"") structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.

Description

1236712 〇7672twf.doc / 〇〇6 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor device and a long-standing method-a kind of silicon oxide / silicon nitride / oxide i (〇 二〇d structure of semiconductor elements and the formation of oxides) ,,, ° [Previous technology] / In the traditional process, the Kaidu with 0N0 structure,: with the layer, nitride layer and top oxide layer ―Above the substrate '': A further etching process is performed to pattern the ONO structure. = N0 structure of the towel _ oxide layer can be cut by domain nitrogen. However, the traditional silicon nitride oxidation process must consume a high thermal budget. For example, in some pass:

HI is placed in the furnace grate, and the temperature is maintained at 60 degrees Celsius_S holding the item for 60 minutes to perform a wet oxidation process on silicon nitride. … The main system is that traditional plutonium will be used up during the oxidation step, but the next step may be the top oxide layer, which may cause leakage current between the gates. Therefore, the electricity stored in the nitrogen cutting layer will be lost, which will cause electrical problems in the device. In order to reduce the loss of the chemical layer in Qingsi, Wei Zhiyu first deposited the tunneling layer and the nitrogen cutting layer and patterned it, and then the top oxide layer was grown on the nitrided layer by the double oxidation method. However, the Cheng oxidation method has a relatively high oxidation selectivity ratio between the substrate and the nitrided layer. Therefore, the oxidation rate of the substrate by oxidation t will be much higher than the oxidation rate of the nitrided layer. For example, if a top oxide layer with a thickness of 150 Angstroms is to be formed by a clear oxidation method, 1236¾ f.doc / 006 i uses an oxide layer with a thickness of 1000 Angstroms. It can be known that after the formation, the top oxide layer is formed by the oxidation process, and then the thick oxide layer on the bottom of the top oxide layer is removed. In this way-it will increase the system, the impurity will also lead to an uneven substrate surface. There are several methods of Πη sit ^ upper-layer oxide layer—known as in-situ steam generation A bottom. 22 :: eneratlon, ISSG) process. The ISSG process is to heat the plate 2 of oxygen (5 rounds) to a high enough temperature to catalyze the gap between the body of oxygen and the stalk of lice. This base can effectively oxidize 忒 on the substrate =: Based on the appropriate two steps, please use the g process. After the fire two: === 厚 ί =: Temper in situ around. This two-step process can form a dioxide layer between-== and 0 Angstroms, which can be compared with the dioxide layer formed without using this 1 at == 卩; pre / or operation In the mode, a process system with a smaller number of M0Π6171911 is provided, which can sequentially and selectively form two different thickness openings in the execution time; the wafer is defined by the field isolation region. On the area. The traditional method of layering two layers is to form a layer on all exposed areas on the wafer. Then, a mask is placed on the wafer, and the military curtain is routed to the area where a thin oxide layer is to be formed. Next, the thick oxide layer in the exposed area of the mask layer was removed by using hydrofluoric acid under the Cheng surname Anfa. 6 division. The mask is then peeled off and the wafer is cleaned with an aqueous solution that does not contain hydrofluoric acid. The wafer is then placed in an environment containing hydrogen and nitrogen, and then the native oxide is removed and the silicon surface is passivated by means of low-temperature rapid thermal tempering to reduce the residual oxide thickness to about 4 angstroms. . The temperature in the thermal tempering process is about 600 ° C to 1050 ° C. The above method can improve the uniformity of the thickness of the oxide layer and its oxidation quality, and the remaining hafnium oxide film can become a stronger oxide after the above-mentioned tempering process. [Summary of the Invention] According to the present invention, after a tunneling layer and a silicon nitride layer are formed and patterned, an in-situ steam generation (in situ steam generati〇n) is performed in an environment containing oxygen radicals. (ISSG) process to simultaneously form a top oxide layer, a buried-type drain oxide layer, and an interlayer oxide layer in the MOS region. By exposing exposed silk to oxygen free radicals, it is possible to oxidize nitrided stones in 2 hours ’, for example, about! minute. Therefore, the time spent in the manufacturing process can be greatly shortened, and the thermal budget can be reduced. In addition, because the i-surface and the sidewall of the hair are covered with a top oxide layer, due to the reading of the heart H, the nitrogen: the contact area between the electrode and the top oxide layer can be exposed, and thus the semiconductor of the Cheng structure is introduced: Its oxygen: in 'to the top surface and side of the patterned gas-cut layer 1236207 total doc / 006 layer' and simultaneously form a buried diffusion in the substrate and an interlayer oxide layer in the MOS region of the substrate Λ . , /, Here, the so-called oxygen radical refers to an oxygen-containing oxygenate that exists independently. There are pairs of unpaired atoms or molecules: „while unpaired electrons refer to the rate of a IS; 吏, oxidation. Because = is different, so the oxidation selectivity of the base money slice is also Cong: 22 ^ Chemical layer, buried Ehua layer and thermal budget. Green and can check the process time and reduce the negative aspects of the process, the present invention is characterized by providing a structure material with // oxygen cut (⑽ / G) The capping method of the conductor element is to first form a first oxygen-cut layer and a nitride nitride layer covered with a: # oxygen-cut layer and hafnium nitride. Then perform a rapid hot-rolling process at the same time under the "utt 胄 wei", In order to facilitate the formation of a second oxygen on the surface of the button, and in the broad sense, the present invention is characterized in that it provides a method with the following formula: "Silicon silicon / silicon oxide Shi Xi'er, the basin's second method firstly forms the first oxidized oxidized layer and nitridation on the base: :: soil & the upper system has a memory region and a gold oxide semiconductor oxidized-oxidized oxidized layer And gasified stone layer 'to form the first oxide stone layer and nitride stone layer also patterned on the memory cell area ... then patterned ^ 367〇U wf.doc / 〇〇6 in the existence of her pole, and then: == exposed exposed conductor area on the cathode layer of the oxide layer. &Quot; Heterogene layer, the county gold and oxygen semi-based In one or two two ::; :: Cm! Including-oxygen self-memory memory element. The thickness of the layer is thicker than the thick base gas of the open-oxide layer. In some embodiments, the rapid thermal tempering process is one. In situ: Oxygen-containing gas and gas-containing gas, and their flow rates need to be maintained in a three-two-element osmium oxidation process. In some embodiments, humans are introduced simultaneously with ί = /, gas containing II ', and its carrier gas. The ratio of the ratio falls in the appropriate range. The gas containing oxygen is the wire (¾), and its flow rate is proportional to that of the hydrogen "gas 1236¾: twf.doc / 006 1 ·· 2. The temperature of the wafer is Maintained between about 700 ° C and 13,000 ° C, preferably between about 900 ° C and 1150 ° C. The time that the wafer is exposed to this mixed gas depends on the thickness of the oxide layer to be formed , Gas flow rate and temperature. The exposure time is as short as 1 to 10 seconds, and as long as 100 to 1000 seconds, or even longer. The exposure time of the wafer to the mixed gas is usually 10 In certain embodiments, it is 30 seconds, in some embodiments, it is 120 seconds, in other embodiments, it is 300 seconds, and in other embodiments, the wafer exposure time is 500 seconds. In the embodiment, when the temperature used in the manufacturing process is 850 degrees Celsius, 900 degrees, and 950 degrees Celsius, and 1000 degrees Celsius, the flow rate ratio of oxygen to hydrogen (h2 / h2 + 〇2), about 5%, 25 = 33 = (For example, the flow rate of hydrogen is 6-, and the flow rate of oxygen is 12 slm), the time required for the process is about 90 seconds or 120 seconds. ^ In a broad sense, the present invention is characterized by providing a Semiconductor device with silicon nitride / silicon oxide structure. This element includes =, the first oxygen-cutting layer on the soil bottom, the nitrided layer covering the partial layer, completely covering the nitrogen ^:? The first one and covering the second oxygen-cutting layer == buried type Electrode and buried electrode / source oxide layer, the second oxygen layer covering the / source oxide layer, the bottom of the earth, and the partially buried drain oxide layer, and the partial oxide-f layer. doc / 006 The hafnium nitride layer on the Shixi layer, the second hafnium oxide completely covering the nitride, and the second oxide J = conductor layer. In another broad sense, the feature of the present invention is to provide a memory cell with a oxidized stone structure / oxygen-cut structure in the hairpin, including the buried source and drain in the substrate, covering A buried oxide layer on the buried substrate, the substrate j covering the substrate / source, and the first oxide layer on the partially buried substrate / source oxide layer: covering The nitrided layer on a part of the first hafnium oxide layer, the second silicon oxide layer in contact with the first silicon oxide layer, and the gate conductor layer covering the first stone oxide layer. a In some embodiments of the present invention, the thickness ratio (SiN: Si) of the oxidation on Lb Shi Xi (SiN) to the oxide layer on Shi Xi (S!) is about 0: 6 to 1 to 0. .8: It is preferably about 0.68: 1 to 0.88: In order to make the above and other objects, features, and energy of the present invention more comprehensible, the preferred embodiments are described below with the accompanying The drawings are explained in detail as follows. & [Embodiment] The following description will be described in detail with reference to each of the embodiments of the present invention. These _ are schematic illustrations of the present invention = other_ and the structure is not according to a certain "example. If the components of the embodiment of the present invention are the same as those in the other illustrations: Although it can be easily recognized in all the drawings With these components, === Chu, this specification will not include all the same components 12 rf.doc / 006

According to an embodiment of the present invention, under the conditions of ISSG, hydrogen and oxygen are reacted on the surface of the heated wafer to form oxygen radicals. The in-situ steam generation process belongs to a low-pressure process. After mixing oxygen and hydrogen in a proportion, it is directly introduced into the process chamber without a prior combustion process. After the wafer is heated, it can be regarded as an ignition source, so that the reaction between hydrogen and oxygen will occur near the wafer surface (in situ). Generally, under the conditions of the ISSG process, the oxygen free radical is mainly generated by the following reaction formula. H2 + 〇2 — > 20H Η2 + 0Η- ^ Η20 + Η 〇2 + Η— > 0Η + 〇 " Η2 + Ο ^ ΟΗ + Η In the ISSG oxidation process, the presence of hydrogen can accelerate the free formation of oxygen molecules to form reactive oxygen atom. According to the present invention, during the ISSG process, the rate of oxide formation on silicon nitride (ie, the thickness of the oxide formed relative to the loss thickness of silicon nitride) shows its concentration with oxygen atoms (oxygen radicals 0 ·). It has a strong correlation and has nothing to do with other kinds of molecules or atoms. The concentration of oxygen radical 0 · does not depend on the volume of the reaction gas, but on the pressure, temperature, and the relative amount of hydrogen in the chamber. ^ The main function of pressure and temperature in the chamber is to cause collisions between molecules, and the main function of pressure or flow rate is to recombine molecules. During the collision and recombination of molecules, the balance of free radical generation will make the oxygen free radical reach the highest concentration. Therefore, the ISSG process depends on the process pressure, gas flow rate, and temperature used in the chamber, and the above values are all within a specific range. Therefore, in some embodiments of the present invention, the process using 13 1236712 07672twf.doc / 006 can obtain better performance: the temperature is in the range of 800 to 1000 degrees Celsius, and the pressure is about 1 Torr (torr) ) To 20 Torr, and the flow rate of H2 + 02 is approximately in the range of isim to 40 slm. And the ratio of ΐνΗ2 + 02 is in the range of about 40%. In some embodiments of the present invention, a carrier gas is passed through the chamber together with a mixed gas of hydrogen and oxygen to improve the uniformity of pressure. The carrier gas is, for example, nitrogen. However, since the carrier gas is not an essential element in the in situ generation process of oxygen radicals, its flow rate can be between 0 slm (if no carrier gas is used) to 50 slm. In the conventional process, the ratio of hydrogen to oxygen used is quite high, for example, 1/67: 1, and the reaction temperature is, for example, 1000 degrees Celsius. Oxides on silicon nitride and oxidation on silicon The ratio (SiN / Si) of the product generation rate is, for example, about 0.26. According to the method of the present invention, the generation rate of the oxide on the nitrided stone and the oxide on the stone can reach a higher ratio, and the oxide can be simultaneously formed on the surface of silicon nitride and silicon. The flowchart shown in FIG. 1 is a conventional process 100 for forming an oxide with a NO structure. Figures 2A to 2G are schematic diagrams showing the structures formed at different stages of the conventional process towel. Please refer to Fig. 1 and Fig. 2A ®, the step 10 of the conventional manufacturing process 10 is to form an isolation structure 204 in the base 202 to define the first area outline = the second area, 208. The substrate 202 is, for example, a Shixi wafer, and the isolation structure is, for example, a trench isolation structure. The first region is used to form a memory I: The first Γ region 208 is used to form a logic element. Then in step 104, a layer 210 is formed on the first region 206 and the second region 208, as shown in FIG. 2B. Then, in step 106, a layer of gas 12367 is deposited, and then in step 108, an oxidation process is performed on the silicon nitride layer 212. A cutting layer 2U is covered on the tunneling oxide layer 210, such as the top oxide layer 214. Since the nitrogen cutting layer 212 is partially consumed during the oxidation process, the thick bismuth layer of the silicon nitride layer 213 that remains is:

On the second region 206 of the minus 202, the ONO structure 22O and the ONV structure 222 'are defined and the surface of the substrate 202 in the second region 208 is exposed. Each of the ONO structures 220 and 222 formed constitutes a ONO stack structure, and sequentially from the substrate 202 upwards are a bottom oxide layer, a nitrogen layer, a layer 226, and a top oxide layer. In this embodiment, the source / inverter region 230 is used to turn off the ONO stack structure. In step U2, an ion implantation process is performed to form a buried diffusion region 232 and form a buried source / and electrode, as shown in FIG. 2E. Then, in step U4, a chemical process is performed to generate an element gate oxide layer on the second region 208, and a source / inverted oxide layer 234 is formed. However, due to a part of the buried expansion process ^ skin loss ', a relatively thin buried 233' is generated as shown in FIG. 2F. The conditions and structures used here have a very small increase in the thickness of the weird layer, which is equivalent. , The number of meanings' is, for example, several Angstroms. In step 116, the polycrystalline silicon layer 238 is deposited to cover the gate oxide layer 236, the ONO structures 22 and μ; however, it is worth noting that removing the layer 210 will make the entire process more complicated and produce an uneven surface. surface. And on the buried source back electrode oxide layer 234, 2 · remove the complex oxide covering the second area, and it will be obliterated on the second area 208, 4 · Li-15 1236¾ twf .doc / 006 FIG. 3 is a flowchart showing the steps of an oxidation process according to an embodiment of the present invention. 4A to 4G are schematic cross-sectional views illustrating structures formed at different stages in the oxidation process 300 of the present invention. Referring to FIG. 3 and FIG. 4A, in step 302 of the process 300, an isolation structure 404 is formed in the substrate 402 to define a first region 406 and a second region 408. The first region 406 is used to form a memory cell, and the second region 408 is used to form a logic element isolation structure. The substrate 402 is, for example, a silicon wafer, and the isolation structure is, for example, a trench isolation structure 404. In step 304, a tunneling oxide layer 410 is formed to cover the first region 406 and the second region 408, as shown in FIG. 4B. In step 306, a silicon nitride layer 412 is deposited on the tunneling oxide layer 410, as shown in FIG. 4C. These steps can be accomplished using conventional techniques. Moreover, please refer to FIG. 4C. The result of completing these steps is to provide a substrate 402 having regions defined by the isolation structure 404, and covering these regions with a tunneling oxide layer 410, and tunneling oxidation. A silicon nitride layer 412 having an exposed surface is formed on the layer 41. According to the present invention, a patterning process is performed by using a mask (not shown) in step 308 to define a portion of the under-oxide layer in the OO structure predetermined to be formed on the first region 406 of the substrate 402. 424 and the silicon nitride layer portion 426 have the structures shown as 42 and 422 in the figure, and expose the surface of the substrate 402 in the second region 408 as shown in FIG. 4D. At this time, the gate oxide layer of the Lai element in the second region 408 and the oxide material emitted by the ONO are not formed. However, in the present embodiment / the defined structure formed by the oxide chalcogenide is between a source / drain, please refer to the source / drain. In step 31, an ion implantation process is performed to form a buried diffusion region in the basal source-level electrode region 1236¾¾twf.doc / 006 to form a buried source / drain 432. As shown in Figure 4E. Then, in accordance with the present invention, in step 312, a rapid thermal oxidation (RTO) process is performed in the presence of an oxygen radical to form a top oxide layer 428 and a buried drain / source at the same time. The electrode oxide layer 434 and the gate oxide layer 436 are as shown in FIG. 4F. And while the top oxide layer 428 is being formed, a portion of the silicon nitride layer 426 is consumed, and a thinner silicon nitride layer 427 remains. Each of the 0N0 structures 421 and 423 formed by the above process constitutes a 0N0 stacked structure, and from the base 402 in sequence, the bottom oxide layer 424, the nitride oxide layer 427, and the top oxide layer 428 are sequentially formed. Thereafter, in step 314, a polycrystalline silicon layer 438 is deposited to cover the gate oxide layer 436, the ONO stack structures 421 and 423, and the buried source / drain oxide layer 434, as shown in FIG. 4G. Please refer to FIG. 5, which illustrates a schematic cross-sectional view of the ONO structure 500 formed in the memory cell area according to a conventional process. The structure 500 is formed on the substrate 502, which includes a 10NO stack structure 522, and the ONO stack structure 522 is a bottom oxide layer 524, a silicon nitride layer 526, and a top layer in order from the base 502. It is composed of an oxide layer 528. The buried & scattered region (source / drain region) 532 is formed on the 5G2 substrate adjacent to the ONO stack structure. Its formation method is, for example, ion implantation / drain oxide layer. It is said by oxidized buried human diffusion area. The polycrystalline silicon layer 538 covers the top oxidation of the ONO stack structure 522 and the source / non-polar oxidation sound adjacent to the ONO stack structure 522. It is worth noting that the conventional oxidizing process is used to form the ^ 17 1236712 〇7672twf.doc / 0〇6 stacking structure 522 and a cleaning process, and this cleaning process requires cycling a cleaning process, the angle of 526, Γ top oxidation Layer 528 and expose the corners or edges of the nitride layer. Please use the stacking method to describe the damage caused by the known method. The edge 529 of the top emulsion layer 538 is deposited by the crystal layer 538 and the edge 527 of the fossil layer. When the extra edge ends 597 !!, the polycrystalline silicon layer 538 overlying the exposed silicon nitride layer Γ π is contacted, and a leakage current path is formed from 6 to polycrystalline silicon layer 528. As a result, the effectiveness of the 500 structure of 0N0 is reduced. Shihuan can avoid the above leakage current problem. FIG. 6 is a schematic cross-sectional view of a kind of ON0 structure formed in accordance with the description. Please refer to FIG. 6. The ONO structure 600 of the present invention is formed on a substrate 602, including a ONO stack structure 622, and the ONO stack structure 2 is a bottom oxide layer sequentially from the base = 02. 624. A nitride nitride layer and a top oxide layer 628. The buried diffusion region (_ / drain region) 632 is formed in the substrate 602 adjacent to the ONO stack structure 622, and a formation method thereof is, for example, an ion implantation method. The source / drain oxide layer 634 is formed by oxidizing the buried diffusion region 632 in the RTO process containing oxygen radicals. The top oxide layer 628 is also formed at the same time as the source / drain oxide layer 634 in this process, as described above with reference to Figures 3 and 4D to 4F. The polycrystalline silicon layer 638 covers the top oxide layer 628 of the ONO stack structure 622 and the source / drain oxide layer 634 adjacent to the ONO stack structure 622. According to the present invention, the top oxide layer 628 of the present invention is formed after the patterned nitride stone layer 626 and the bottom oxide layer 624 are oxidized from the surface exposed by the nitride stone layer 626. In addition, the top layer of this method, 18 1236712 〇7672twf.doc / 0〇6, layer 628 can completely cover the edge of the nitrided layer—and the top oxide layer 628 surrounds the edge of the nitrided dream layer 626❾. 4 near. The P-source / non-electrode oxide layer 634 is in contact. Therefore, the nitride nitride layer 626 can be completely isolated from the polycrystalline silicon pin formed later thereon, and can be further modified. The efficiency and reliability of the ONO structure 600. Example 1 In this example, a patterned nitride nitride (S,) and a nightmare surface are formed on a wafer substrate, and the wafer is placed in a furnace where steam is generated in situ. Then, the wafer is heated in an ISSG chamber to about Celsius and exposed to hydrogen, oxygen, and nitrogen gas for about 300 seconds to form an oxide layer on the surface of silicon and silicon nitride. The flow rate of hydrogen in the ISSG process chamber is 2 slm, and the flow rate of oxygen is 8 slm. The thickness of the oxide layer formed on the silicon surface is about 158 angstroms, and the thickness of the oxide layer formed on the silicon nitride surface is about 128 angstroms. Example 2 This example compares the difference between the actual value of the rate of oxide formation on the zeolite compound (siN) using the ISSG process and the theoretical value derived from the reaction formula. The theoretical value rate can be derived from the following formula:

Si3N4 + 6H20- > 3 S i02 + 4NH3

Si3N4 · (28 · 086χ 3 + 14x 4g / mole) / (3.1g / cm3) = 45.25cm3 / mole

Si02 · (28 + 16x 2g / mole) / (2.21 g / cm3) = 27.18cm3 / mole I236m.d. (27.18χ 3) /45.25=1.8 Right draw the relationship between the thickness of the oxide layer in the experimental data of the ISSG process and the loss thickness of the silicon nitride layer (SiNGen) as a relationship chart, and the resulting slope is 1.6301. The formation of nitrogen-combined oxides (nitrogen oxides) in a thin layer at the interface between the top oxide layer and the nitride layer can be used to illustrate the difference between the theoretical value rate and the measured experimental value rate. Moreover, the precise position of the interface between the oxide layer and the nitride layer, especially the precise position of the interface between the nitrogen oxide layer and the top oxide film in the ONO stack structure, is difficult to determine due to the presence of nitrogen-bound oxides. Example 3 This example will compare the formation rate of the oxide layer on the nitrogen dream compound (Diqiwei 'DCS) in the ISSG process at three different temperatures. The two temperatures are 850 ° C, 900 ° C and 95 ° C. While the wafer at each temperature is exposed to hydrogen and oxygen towels, the flow rate ratio of money gas to oxygen (h2 / h2 + 02) is about 33% (h2 flow rate is 6 slm, and 0 2 flow rate is 12 slm). The time interval for measuring the thickness of the oxide layer is approximately seconds, 60 seconds, 90 seconds, and 120 seconds. In the process of celsius degrees, the oxide layer is oxidized in the process of forming nitride nitride and stone ☆ (SlN / Si) in the range of 0 68:] to 〇75:]. The generation rate ratio of the layer on the nitrided stone and the stone (Si dirty) is within the range of G69: to. The production rate ratio (_) at the temperature of 95G ° C is about. .72: 1 = 20 1236712 07672twf.doc / 006 The conventional method for forming a thin oxide film on a silicon nitride layer is obtained according to the linear growth method. In contrast, the formation of the oxide layer in the ISSG process is obviously obtained by controlling its diffusion. When the square of the value of oxygen 彳 = layer thickness is linearly proportional to the oxidation time, then it is in accordance with the parabolic growth law. Example 4 This example will compare the DCS nitride nitride (DCS) in the ISSG process with different parameters. ) On the formation rate of the oxide layer. The ratios of hydrogen to oxygen (% / ° C + 02) in the process are about 25% and 33%, respectively, and the temperatures are about 850 ° C, 900 ° C, and 950 ° C, respectively. The time interval for measuring the thickness of the oxide layer is about 30 seconds, 60 seconds, 90 seconds, and 120 seconds. A lamp type (XT) single wafer chamber is used to form a silicon nitride film in advance. In general, in higher temperature processes, the oxide layer formed at each time interval will be thicker. That is to say, in the process at a higher temperature, the generation rate of the oxide layer is faster, because the significantly increased kinetic energy in the oxygen radical can make it easier for the valley to overcome the obstacle of active energy. Moreover, at each process temperature, the higher the ratio of% along 2 + 02, the faster the formation rate of the oxide layer. Because at a given process temperature, the higher the hydrogen concentration, the shorter the process time required for the oxide layer to reach a specified f degree. Obviously, the high concentration of hydrogen can accelerate the release of oxygen molecules into neo-oxygen radicals, which in turn enables more oxygen radicals to be able to reach 斑 / 5 窳. Example 5 In this example, the oxide layer is formed on the nitrided layer using 21 1236¾¾: twf.doc / 006 ISSG at 85 ° and 95 ° C. The nitrided layer can be formed in a number of different ways, including a gasification layer (XTlamp type chamber) of dichlorite and sintered base, a sintered nitride generated using a single wafer chamber (XTlamp type), and A single-day-Japanese-yen chamber is a sintered nitride. As expected, the top oxygen generation rate is faster at higher temperatures. At the same temperature, the formation rates of the oxide layers on the three different types of films are similar. The appropriate value of one or more parameters will vary depending on the f value of one or more other parameters. For example, at higher temperatures, P can be reduced ^: the time required for the process. And ^, the ratio of hydrogen to oxygen is high in any-given process Ϊ two-pronged body, the formula is ^ 2 ° These examples are in accordance with the present invention and provide suggestions here to determine the best combination of parameters It is not used to express the specific facts. The disclosure is as above, but it is not used to * 2. / What to expect this artist, without departing from the spirit of the present invention, should make some changes and look around. The attached patent application system is defined as the quasi-issued month. [Simplified illustration of the drawing] Please refer to the flowchart of the steps of the know-how process for the illustration of the 1st drawing. Schematic = A to 2G are marginal diagrams.] The cross-sectional flow at each step in the diagram is a diagram showing the steps of an oxidation process according to an embodiment of the present invention. 22 123674 ^ f.doc / 006 Fig. 4A 4G are schematic cross-sectional views showing each oxidation process step in FIG. 3. FIG. 5 is a schematic cross-sectional view showing an ONO structure formed according to a conventional process. FIG. 6 is a schematic cross-sectional view showing the ONO structure formed according to the process of the present invention. [Description of main component symbols] 100: Known manufacturing process

102 ~ 116, 302 ~ 314: Process steps 202, 402, 502, 602: Substrates 204, 404: Isolation structures 206, 406First area 208, 408: Second area 210, 410: Tunneling oxide layer 212, 213, 226, 412, 426, 427, 526, 626: Nitride layer

214, 228, 428, 528, 628: Top oxide layers 220, 222, 420, 422, 500, 600: ONO structures 224, 424, 524, 624.Bottom oxide layers 230, 430: source /; and polar regions Electrodes) 232, 233, 432, 532, 632: buried diffusion regions (source / not 234, 434, 534, 634: buried source / drain oxide layers 236, 436) · interrogated oxide layer 238, 438, 528, 638: polycrystalline second layer 23 f.doc / 006 300: the process 421, 423, 522, 622 of the present invention: 〇ΝΟ stacked structure 527, 627: the edge of the silicon nitride layer 529 ·· of the top oxide layer edge

twenty four

Claims (1)

1236712 07672twfl .d〇c / 〇〇5 amended date of 94.3.30 X. scope of patent application · L-a method of forming a 0ΝΟ structure, including · providing an oxide-nitride film on the surface of your substrate, the Oxygen-lice compound film includes ... an emulsified layer of pancreatic coin covering the substrate; a layer of nitride stone covering the first oxide layer; the nitride is fine to define a substrate on the substrate And ,,, " a base oxide and a silicon nitride portion, the base oxide The side of the nitrided hair part has a morning glow, and the side wall with a different rain mountain ΛΛ1, a hundred storm road exits, and the silicon nitride part has a hundred storm road exit surface; and > 5 4 : Environment τ with free radical oxidant, so that the exposed surface of the exposed side wall 2 is exposed to-rapid thermal oxidation for money, so that the figure = 2, part and the patterned oxide part of the «surface An oxide layer is formed on the side wall of the storm road. (2) The method for forming a NOO structure as described in item i of the patent application, wherein the free radical oxidant includes an oxygen free radical. 3. The method for forming a NOO structure as described in item 1 of the scope of the patent application, wherein the free radical oxidant includes O ·. 4. The method for forming a ΝΟΟ structure as described in item 1 of the scope of patent application, wherein the process of exposing includes heating the substrate to a specific temperature, and, under a specific action, causing the exposed sidewall and the exposure The surface is blasted in a mixture of an oxygen-containing gas and a hydrogen-containing gas in a specific ratio in the body, and lasts for a specific time, by the reaction of the oxygen-containing gas and the constituents of the hydrogen-containing gas The free radical oxidant is generated near the heated substrate. 25 1236712 07672twfl .doc / 006 Modified acetabular period 94.3.30 5. The method of forming a 0NO structure as described in item 4 of the scope of patent application, wherein heating the substrate includes heating the substrate to about 70 ° C to In the range of 1300 degrees Celsius. 6. The method for forming a 0NO structure as described in item 4 of the scope of the patent application, wherein the step of heating the substrate includes heating the substrate to a range of 900 ° C to 115 ° C. 7. The method for forming an ONO structure as described in item 4 of the scope of the patent application, wherein the step of heating the substrate includes heating the substrate to a range of $ 850 ° to 10,000 ° C. 8. The method for forming a Ν0 structure as described in item 1 of the scope of the patent application, wherein the process of the storm circuit includes heating the substrate to a specific temperature, and subjecting the exposed sidewall and the substrate to a specific pressure. The exposed surface is exposed to a gas mixed with a specific ratio of 02 and Η2 for a specific period of time, and a 0- is generated near the heated substrate by the reaction of the components of 22 and Η2. 9. The method for forming an ONO structure as described in item 8 of the scope of the patent application, wherein the exposure process includes heating the substrate to a range of about 700 ° C to 1300 ° C, and at about 1 Torr. (T〇rr) to 20 Torr, the exposed sidewall and the exposed surface are exposed to a ratio of 10 to H2 (Η2 / Η2 + 02) is about to 40% In the range of the mixed gas, and for a time of about 1 to 1,000 seconds. 10. The method of forming a NOO structure as described in item 9 of the scope of the patent application, wherein the step of heating the substrate includes heating the substrate to a range between about 900 ° C and 1150 ° C. 11. The method of forming the ONO structure as described in item 9 of the scope of patent application 1236712 07672twfl.doc / 006 date of revision 94.3.30 method, wherein the step of heating the substrate includes heating the substrate to about 850 ° C to In the range of 1000 degrees Celsius. 12. The method of forming a 0NO structure as described in item 9 of the scope of the patent application, which = the exposure process includes the flow of 0 2 and the mixed gas of H2 on the substrate, and the ratio (H2 / H2 + 〇2 ) In the range of 5% to 33%. 13. The method of forming a 0NO structure as described in item 9 of the scope of the patent application, wherein the process of exposing includes the flow of 〇2 flowing on the substrate to the mixed gas of 氏 's ratio (¾: 〇2) is about In the range of 1: 19 to 丨: 2. 14. The method for forming a 0NO structure as described in item 9 of the scope of the printed patent, wherein the exposure process includes 0.02% and% of the mixed gas flowing on the substrate for about 10 seconds to 500. Within seconds. 15. The method for forming a qNq structure as described in item 9 of the scope of the patent application, wherein the exposure process includes 02 and% of the time that the mixed gas flows on the substrate in the range of about 30 seconds to 300 seconds. 16. The method for forming a 0NO structure as described in item 1 of the scope of the patent application, wherein the process of exposing includes heating the substrate in a furnace tube, and inducing a predetermined ratio under a specific pressure. A gas mixed with 2% and for a specific time, 0- is generated near the heated substrate by the reaction of the components of 02 and h2. 17. The method for forming a 00n structure described in item 10 of the scope of the patent application, wherein the step of introducing the mixed gas of the person 0ah2 further includes introducing a carrier gas. 18. The formation method of the leg structure described in item 17 of the declared patent scope 27 1236712 Date of revision 94.3.30 07672twfl.doc / 006 Method 'wherein the step of introducing the mixed gas of 02 and H2 further includes introducing a nitrogen gas (N2) as a carrier gas. 19. The method for forming an ONO structure as described in item 16 of the scope of the patent application, wherein the step of introducing a mixed gas of 0 and Η2 at the specific ratio includes introducing 〇2 and Η2 at a specific flow rate ratio. 20. The method for forming an ONO structure as described in item 19 of the scope of the patent application, wherein the step of introducing the mixed gas of 0 and Η2 further includes introducing 乂 as a carrier gas at a specific flow rate. 21. The method for forming an ON0 structure as described in item 19 of the scope of the patent application, wherein the step of introducing 〇2 and η2 includes introducing 〇2 and η2 at an additive flow rate in a range of approximately 1 to 40 slm. 22. The method for forming a Ν0 structure as described in item 20 of the scope of the application for patent, wherein the step of a 0 ′ entering 0 2 and 导入 2 includes the introduction of 0 2 and 1 at a flow rate of approximately 1 to 40 slm. η2, and introduction of ν2 includes introduction at a flow rate greater than 50 slrn. 23. · A method for manufacturing a semiconductor device having an ONO structure, comprising: providing an oxide-nitride film on a surface of a substrate, the substrate having first and second regions defined by an insulator, the The oxide_nitride film includes a first oxide layer on the substrate and a nitride layer on the first silicon oxide layer; patterning the oxide-nitride thin film to The surface of the substrate is exposed in the second region on the substrate, and a portion of a bottom oxide layer and a silicon nitride layer in a 100N stack structure is defined in the first region on the substrate. The bottom Both the oxide layer portion and the silicon nitride layer portion have an exposed side wall of 28 1236712 ° 7672twfl.doc / 006, which amends the date of 94.3.30, and the nitrided layer portion has an exposed surface. When the substrate The temperature is about 700 ° C to 120 ° C. The difficulty of exposure and the exposure of the exposed peaks are exposed to free radical oxidants to pattern the exposed sidewalls of the fossil layer and the exposed core. Form a first An oxide layer, and at the same time, a gate oxide layer is formed on the mouth soil & surface in the second area; and a conductive layer is formed to cover the second oxide layer and the gate layer The half-reading manufacturing method having the 0ν〇 structure described in the scope item 23 'The radical oxidant includes a monooxy radical. ° Half the QNQ structure described in item 23 of the middle material benefit range * 1 piece of manufacturing method, the free radical oxidant includes 0_. Dao Magnetic 2-6 · As described in item 23 of the scope of the patent application, a semi-structured method with an ONO structure, the exposure process of the towel includes adding the substrate to the temperature range and the temperature, and — At a specific pressure, the side walls of the two channels and the exposed surface are exposed to — a mixture of an oxygen-containing rolling body and a hydrogen-containing gas in a specific ratio for a specific time ^ by the The reaction of the oxygen-containing gas with the constituents of the hydrogen-containing gas generates the free radical oxidant near the substrate of π ",. Moban 27. Half of the structure with ONO as described in item 26 of Shen Qing's patent scope = A method for manufacturing an element, wherein the step of heating the substrate includes heating the soil base to a range between about 900 degrees Celsius and 1150 degrees Celsius. Zeng ^ # 28. As described in item 26 of the scope of the patent application, it has ONO. Half of structure = manufacturing method of wide element, wherein the step of heating the substrate includes heating the soil bottom to a range of about 850 ° C to 1000 ° C. 29 1236712 〇7672twfl.doc / 006 Date of amendment 94.3.30, 29. Rushen Patent No. 23 The manufacturing method of the semiconductor element with the 〇N〇 structure is described. The process of manufacturing a red towel includes heating the substrate to a temperature within the temperature range, and exposing the exposed sidewall and the exposure under a specific pressure. The surface of the substrate is exposed to a gas mixed with a specific ratio of 02 and% for a specific period of time, and the reaction between the constituents of thorium and the thorium generates near the heated substrate. According to the method for manufacturing a semiconductor element having a 0N0 ^ structure as described in item 29 of the scope of the patent application, the process of exposing the towel includes heating the substrate to a temperature within the temperature range, and at about Qin Ting) to a pressure in the range of 20 torr, so that the exposed sidewall and the exposed surface are exposed to a ratio of 102 to H2 (H2 / H2 + 〇2) of about 0.1% to 40%. In a mixed gas in the range, and lasting from about 丨 to 1000 seconds. 31. The method for manufacturing a semiconductor device having an OO structure as described in claim 30 of the patent application scope, wherein the substrate is heated The steps include heating the substrate to about The range is from 900 degrees to 1150 degrees Celsius. 32. The method for manufacturing a semiconductor device having a 0N structure as described in item 30 of the patent application scope, wherein the step of heating the substrate includes heating the substrate to about Celsius degrees. The range is from 850 degrees to 1000 degrees Celsius. 33. The method for manufacturing a semiconductor device having a 0N0 structure as described in item 30 of the scope of patent application, wherein the process of exposing includes the flow of 0 2 and The ratio of this mixed gas (η2 / Η2 + 02) is in the range of about 5% to 33%. 34. The method for manufacturing a semiconductor device having an ONO structure as described in item 30 of the scope of patent application, The exposure process includes the mixed gas of 〇2 and Η2 flowing on the substrate, and the ratio (η2: 〇2) is about 30 · 30 1236712 the date of revision is 94.3.30 〇7672twfl.doc / 〇〇6 19 In the range of 1: 2. 35. The method for manufacturing a semiconductor device having an OO structure as described in item 30 of the scope of the patent application, wherein the exposure process includes 〇2 and% of the mixed gas flowing on the substrate for about 丨 0 seconds In the range of 500 seconds. 36. The method for manufacturing a semiconductor device having an ONO structure as described in item 30 of the scope of the patent application, wherein the exposure process includes the time for which the mixed gas of 0 2 and the flow of the mixed gas on the substrate is about 30 seconds to Within 300 seconds. ^ 37. The method for manufacturing a semiconductor device having a structure as described in item 23 of the scope of patent application, wherein the process of exposing includes heating the substrate in a furnace tube, and introducing a specific ratio under a specific pressure. The gas mixed with 而成 2 and ， 2 lasts for a specific time, and generates __ near the heated substrate by the reaction of ο] and the constituent elements of Η2. 38. The method for manufacturing a 7L semiconductor device having an ONO structure as described in item 37 of the scope of the patent application, wherein the step of introducing the mixed gas of 02 and Y2 further includes introducing a carrier gas. 39. The method for manufacturing a semiconductor 7L with an ONO structure as described in item 38 of the scope of the patent application, wherein the step of introducing the mixed gas of 02 and Y2 further includes introducing a nitrogen gas (N2) as a carrier gas. . 40. The method for manufacturing 70 semiconductors having a structure of 0] ^ 〇 as described in item 37 of the scope of the patent application, wherein the step of introducing the mixed gas having the specific ratio of 02 to Η2 further includes a specific Flow rate ratio introduction and Η2 〇41 · Has a half of an ONO structure as described in item 40 of the scope of patent application 31 1236712 Amended date 94.3.30 〇7672twfl.doc / 0〇6 The method of manufacturing a conductive element, where the introduction 〇2 The step of mixing the gas with Η2 further includes introducing% as a carrier gas at a specific flow rate. 42. The method for manufacturing a semiconductor device having an ONO structure as described in item 40 of the scope of the patent application, wherein the step of introducing 〇2 and Η: includes introducing 〇2 and η2 at an additive flow rate in a range of approximately 1 to 40 slm. . 43. The method for manufacturing a semiconductor device having an ONO structure as described in item 41 of the scope of the patent application, wherein the step of introducing 〇2 and Η2 includes introducing 〇2 and η2 at an additive flow rate in the range of approximately 1 to 40 slm And introducing Ns includes introducing% at a flow rate greater than 50 sim. 44. The method for manufacturing a semiconductor device having an ONO structure as described in item 23 of the scope of the patent application, wherein the thickness ratio of the formation of the second oxide layer to the gate oxide layer is approximately 0.6: 1 to 0.8: 1. Within range. 45. The method for manufacturing a semiconductor device having an ONO structure as described in item 23 of the scope of patent application, wherein the exposed process includes heating the substrate in a furnace tube, and when the temperature of the substrate is maintained within one of the temperature ranges When the temperature lasts for about 10 seconds to 500 seconds, the free radical oxidant is generated in the furnace tube. 46. The method for manufacturing a semiconductor device having an ON structure as described in item 23 of the scope of patent application, wherein the exposed process includes heating the substrate in a furnace tube, and when the temperature of the substrate is maintained within one of the temperature ranges When the temperature lasts for about 30 seconds to 300 seconds, the free radical oxidant is generated in the furnace tube. 47 · —A method for manufacturing a memory element having an ONO structure, comprising: providing an oxide-nitride film on the surface of a substrate, the substrate 32 1236712 〇7672twfl.doc / 006 correction date 94.3.30 by A first region defined by the insulator and the oxide-nitride film include a first oxide layer and a nitride layer covered on the substrate and a nitride layer; Forming the oxide-nitride film so that the surface of the substrate is exposed in the second region on the substrate, and defining a bottom oxide layer in the 20N0 stack structure in the first region on the substrate And a portion of a nitride layer, the bottom oxide layer portion and the silicon nitride layer portion each have an exposed sidewall, and the silicon nitride layer portion has an exposed surface; when the temperature of the substrate is approximately Between 700 ° C and 1200 ° C, the exposed sidewalls and the exposed surfaces are exposed to a free radical oxidant to the exposed sidewalls and the exposed portions of the patterned nitrided layer. Exposed On the surface, a second oxide layer is formed, and at the same time, a gate oxide layer is formed on the surface of the substrate in the second region; and a conductive layer is formed to cover the second oxide layer and the gate oxide layer. 4 8 · The method for manufacturing a memory element having a structure of 0 Ν 0 as described in item 47 of the scope of patent application, wherein the radical oxidant includes an oxygen radical. 49. The method for manufacturing a memory element having an ONO structure as described in item 47 of the scope of the patent application, wherein the free radical oxidant includes 0-. 50. The method of manufacturing a memory device having a NO structure as described in item 47 of the scope of the patent application, wherein the process of exposing includes heating the substrate to a temperature within the temperature range and applying a specific pressure Next, the side wall and the exposed surface of the storm road are exposed to a gas mixed with an oxygen-containing gas and a hydrogen-containing gas in a specific ratio for a specific time 'through the milk-containing gas and the The reaction of the constituent elements of the hydrogen-containing gas generates the radical oxidant near the substrate heated at 33 1236712 07672twfl.doc / 006, modified at 94.3.30. 5L The method for manufacturing a memory element with an OO structure as described in item 50 of the scope of patent application, wherein the step of heating the substrate includes heating the substrate to a range between about 900 ° C and 1150 ° C. . 52. The method for manufacturing a mindless body element having an ONO structure as described in item 50 of the scope of application for a patent, wherein the step of heating the substrate includes heating the substrate to a temperature between about 850 ° C and 1,000 ° C. Within range. 53. The method of manufacturing a memory το structure having a NO structure as described in item 47 of the scope of the patent application, wherein the exposure process includes heating the substrate to a temperature within the temperature range, and Under pressure, the side wall of the storm road and the exposed surface are exposed to a gas mixed with a specific ratio of 0 2 and krypton 2 for a specific period of time through the reaction of 0 2 and the constituent elements of India. O- is generated near the heated substrate. 54. The method for manufacturing a memory device having an ONO structure as described in item 53 of the scope of the patent application, wherein the process of exposing includes heating the substrate to a temperature in the range of 0 °, / jnL degrees, and Under a pressure in the range of about 1 torr (torr) to 20 torr (torr), the exposed sidewall and the exposed surface are exposed to a ratio of 102 to H2 (H2 / H2 + 〇2) at about In a mixed gas in the range of 0.00% to 40%, and for a period of about 1 to 10,000 seconds. 55. The method of manufacturing a memory element having an ON structure as described in item 54 of the scope of the patent application, wherein the step of heating the substrate includes heating the substrate to a range between about 900 ° C and 1150 ° C. 56. The method for manufacturing a memory element having an ONO structure as described in item 54 of the scope of patent application, wherein the step of heating the substrate includes heating the substrate to a range between about 850 ° C and 1000 ° C. 34 1236712 Amendment date 94.3.30 07672twfl.doc / 〇〇6 57. The method of manufacturing a memory element with a 0NO structure as described in the 54th scope of the application for a patent, wherein the process of exposing includes the flow on the substrate. 〇2 and Η: the mixed gas, the ratio (Η2 / Η2 + 02) is about 5% to 33%. 58. The method for manufacturing a memory element having an ONO structure as described in item 54 of the scope of application for a patent, wherein the exposure process includes 〇2 and% of the mixed gas flowing on the substrate, and the ratio (Η2: 〇 2) About work: in the range of 19 to 1.2. 59. The method for manufacturing a memory element having a 0NO structure as described in item 54 of the scope of the patent application, wherein the exposure process includes 02 and% of the j / heart & oxygen flow time on the substrate is about 1Q Seconds to $ leap seconds. 60. The method for manufacturing a memory with a 0NO structure as described in Item 54 of the scope of patent application, wherein the exposure process includes 02 and Η2 ^ The time for the mixed gas to flow on the substrate is about 30 seconds to In the range of 300 seconds. Jiang 61. The method of manufacturing a memory and a piece having a structure as described in item 47 of the scope of the patent application, wherein the process of exposing includes heating the substrate in a furnace tube, and inducing a person at a specific pressure- The gas mixed with O2 in a proportion of 0% and for a specific time, O_ is generated near the heated substrate by the reaction of the components of O2 and Y2. 62. As described in item 61 of the scope of the patent application, it is included in the following: a gas ... & 63. As described in item 62 of the scope of the patent application, it has a structure of 〇Ν〇35! 236712 07672twfl.d. c / 〇〇6 Revise the date 94.3.30 manufacturing method of the memory element, wherein the step of introducing the mixed gas of 02 and H2 further includes introducing a nitrogen gas (N2) as a carrier gas. 64. The method for manufacturing a memory element having an ONO structure as described in item 61 of the scope of the patent application, wherein the step of introducing the mixed gas with the specific ratio of 02 and η2 further includes the introduction at a specific flow rate ratio 〇2 and Η2 〇65 · The method for manufacturing a 7L piece of memory with an ONO structure as described in item 64 of the scope of the patent application, wherein the step of introducing the mixed gas of 〇2 and Η2 further includes introducing at a specific flow rate Ν2 acts as a carrier gas. 66. The method for manufacturing a memory element having an ONO structure as described in item 64 of the scope of the patent application, wherein the steps of introducing 0 and 2 include introducing at an added flow rate in a range of approximately 1 to 40 slm. 2 and Η2. 67. The method for manufacturing a memory element having a NO structure as described in item 65 of the scope of application for a patent, wherein the step of introducing 0 and 2 includes introducing at an additive flow rate in a range of approximately 1 to 40 slm. 2 and η2, and introduction% includes introduction of ν2 at a flow rate greater than 50 sim. 68. The method for manufacturing a memory element having an ON structure as described in item 47 of the scope of the patent application, wherein the thickness ratio of the formation of the second oxide layer and the gate oxide layer is about 0.6: 1 to 0.8: 1 Within range. 69. The method for manufacturing a memory device having a NO structure as described in item 47 of the scope of patent application, wherein the exposure process includes heating the substrate in a furnace tube, and when the temperature of the substrate is maintained in the temperature range The free radical oxidant is generated in the furnace tube at an internal temperature for about 10 seconds to 500 seconds. 70. As described in item 47 of the scope of the patent application, a record with a 〇NO structure 36 1236712 07672twfl.doc / 006 amended the date 94.3.30 manufacturing method of memory elements, wherein the exposed heating heats the substrate, and when Mithril temperature ^ ^ endogenous oxidant. Only in. The freeware is produced internally by the Hai furnace, including a semiconductor element with a oxide oxide / nitride / oxidized oxide structure, a first silicon oxide layer, covering a substrate, and a silicon nitride layer, covering On the first silicon oxide layer; a first-oxide layer, completely covering the silicon oxide layer in contact; and "g", and the first interlayer conductive layer covering the second oxygen cutting layer. , Γ includes a memory cell with a structure of oxidized stone / nitrided stone / oxidized stone-a buried drain and a buried human source, which are arranged in the buried drain oxide layer to cover the buried human Qi: and a buried, polar oxide layer, covering the buried source; a first silicon oxide layer, covering an area between the poles on the substrate, and covering a part: the A buried drain layer and a portion of the buried source oxide layer; a second layer, which covers a portion of the first silicon oxide layer, and a second oxygen cut layer that completely covers the nitride ^ Emulsified silicon layer contact; and 1 /, / gate conductive layer covering the second silicon oxide layer. 3 7 73. 1236712 〇7672twfl.doc / 006 Date of revision 94.3.30 Buried drain and a buried source are arranged in the-substrate; _, a buried drain oxide layer covers the buried drain On the pole, and one person's "chemical layer" covers the buried source; the pole fish layer ^ 's chemical conversion layer' covers the buried drain source _ area, which is located on the substrate. A part of the buried / η oxygen, a layer and a part of the buried source oxide layer; a silicon nitride layer covering a part of the first silicon oxide layer; an oxidation IΓ completely covers the nitrogen cut Layer and the first-gate conductive layer, covering the second silicon oxide layer. 38