TWI282066B - Apparatus and method for extending data modes in a microprocessor - Google Patents

Abstract

An apparatus and method are provided for extending a microprocessor instruction set beyond its current capabilities to allow for extended size operands specifiable by programmable instruction in the microprocessor instruction set. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions for execution by the microprocessor. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies an extended operand size for an operand corresponding to a prescribed operation, where the extended operand size cannot be specified by an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instruction and performs the prescribed operation using the operand.

Description

1282066 IX. Description of the invention: [Comparison with the relevant application,] [〇_ ^ The case is as follows: 10/227008 of the following US case, the application date is August 22nd, 2nd.匕 [0002] This application has the same applicant and inventor as the US special account application in the application. Taiwan Application No. DOCKET NUMBER ΜΛΜ 91116957 7/30/02 CNTR: 2176 Apparatus and Method for Extending the Microprocessor Instruction Set 91116958 7/30/02 CNTR: 2186 One------ Apparatus and Method for Executing Conditional Commands 91124008 10/18/02 CNTR: 2187 Apparatus and method for selectively controlling memory attributes 91116956 7/30/02 CNTR: 2188 ---- Selective control of condition code write back splitting and method 91116959 7/30/02 CNTR: 2189 Mechanism for Increasing the Number of Registers of Microprocessors 91124006 10/18/02 CNTR: 2191 —--—— Apparatus and Method for Extending Microprocessor Address Mode CNTR: 2192 —. STOP CNTR for Storage Check: 2193 Prohibition of selective interruption*---

Client's Docket No·: TT5s Docket N〇:0608-A40748TWF1/DEVICHEN/2006-07-05 1282066 91124007 10/18/02 CNTR:2195 Non-temporary memory reference control mechanism 91116672 7/26/02 ___ CNTR:2198 Select TECHNICAL FIELD OF THE INVENTION The present invention relates to the field of microelectronics, and more particularly to a technique capable of controlling the extended data mode to control the microprocessor instruction. . [Prior Art] _ [0004] Since the beginning of the resilience in the early 1970s, the use of microprocessors has grown exponentially. From the earliest applications in science and technology to the consumer sectors that have introduced business from specific areas, such as desktop and laptop (iaptop-) computers, video game controllers, and many other common home and business applications. Devices and other products. With the explosive growth in use, the technology has also undergone a corresponding improvement, characterized by increasing requirements for the following items: faster speed, stronger addressing capability, faster memory Access, larger operations, =, more kinds of general-purpose types of operations (such as floating-point operations, single-instruction multiple-batch (SIMD), conditional movement, etc.) and additional special-purpose operations (such as digital signal processing) Features and other multimedia operations). This has led to the development of the technology in the field 1 has been applied to the design of microprocessors, such as extended pipeline (her nswe Plpelmmg), super-quantity architecture (- (10) · muscle · (four), cache structure, out of order Processing (secret. f is rp ga ga g), explosive access (bum access) mechanism, branch prediction (b na h _icati〇n)

Client’s Docket No.: TT,s Docket N〇:0608-A40748TWFl/DEVICHEN/200M7 〇5 1282066 (speculativeTM1〇n)〇 , tb^30^^ Large energy:’. Today's microprocessors are surprisingly complex and powerful. But unlike four other products, there is another _ non-instrument and the evolution of the microprocessor architecture. Nowadays, the complexity is complicated, and a large part of it is attributed to this factor, that is, the market of the old software is under the test. Many manufacturers choose to incorporate the new architectural features into the ride, but at the same time In these latest products, it is also necessary to ensure that it is compatible with older, legaiy applications. [00〇7] This burden of old software compatibility, nowhere else, will be more apparent than in the history of the development of microprocessors in the X864. Everyone: = The current 32/16 bit virtual mode (virtual_m〇de) χ86 microprocessor, still executable in the 1980s octet real mode (real_m〇de) application. Those skilled in the art also recognize that many related architectures are "stacked" in the x86 architecture just to support compatibility with legacy applications and operating modes. While in the past, developers were able to add newly developed architectural features to existing instruction set architectures, the tools that can be used to implement these features are now quite sparse. More simply, in some important instruction sets, there are no “excess” instructions that allow designers to incorporate newer features into an existing architecture. [0008] For example, in the x86 instruction set architecture, there is no undefined one-byte size of the opcode state that has not been used. In the main one-tuple size x86 opcode, all 256 opcode states are

Client’s Docket No·: TT^ Docket N〇: 0608-A40748TWF1/DEVICHEN/2006-07-05 8 1282066 Has been occupied by the existing instructions. 3 The designer must provide new features and protections. / / The designer now offers a new H-version = body-in-a-phase. If you want to have the existing instruction set architecture & These characteristics. The state of the code must be redefined = two: code, then some of the existing new features, you get -μ # ~,, know and desire. Therefore, in order to provide the text, sacrifice the old software phase. Capacitance. [〇〇〇9] A continuous deterioration is the size of the operand. Early _~^ in the middle of the problem, that is, the problem of the eight yuan, the benefit of the design provides the use of 8-bit computing As the application makes (4) calculate the increasing size and related operations, it is also connected to the type of application. _ for desktop / lap processing crying: processing t ' can provide % bit The operation of the element / operation. Micro md ^ n " ~ the size of the different transport, usually called the data mode (data 〇e ° * this 'in order to retain compatibility with the old application, modern top type / The microprocessor of the laptop f brain can operate in the data mode of 32 bits and ^^ bits. 4k 8 [0010] But even now, due to The processor can't support extended data, such as 64-bit and 128-bit data patterns, and some applications will suffer adversely. However, in order to support these in an architecture with no remaining opcode values. Extended (four) mode, must have both opcode redefinition, which will result in the inability to support legacy applications. [0011] Therefore, what we need is a way to incorporate extended data patterns into existing microprocessor instruction sets. The apparatus and method of the architecture, wherein the instruction set architecture is completely occupied by the deprecated code, and the inclusion of the extended data mode allows an old-compliant microprocessor to retain the ability to execute the legacy application.

Clients Docket No.: TTs Docket N〇:0608-A40748TWFl/DEVICHEN/2006-07-05 1282066 [Summary of the Invention] Yu Jiang: 2] 发明Inventions, as in the other above, are for the above and other technologies. And the shortcomings are overcome. The present invention provides a better technology for expanding the microprocessor's fingertips. You are able to surpass the existing capabilities, providing: "70 w the microprocessor The programmable instruction of the instruction set is carried on it: In the specific embodiment, a type (4) is provided, and the device of the type includes: a conversion unit (t lat should be loglc) = l extension execution unit (extended (four) coffee (10) 1 )). The translation logic # unit translates the extension instruction into the corresponding microinstruction (he (10) gives her on) 'executed by the microprocessor. The extension instruction has an extended preamble (extended prefixmKmmI& (extended prefix tag) 〇 The extended preamble specifies the corresponding--the operation-expanded operation element size of the specified operation', wherein the extended operand size cannot be specified by an existing instruction set. The extended preamble tag is flipped out Observing the preamble, where the extended preamble mark is originally = there is a command to turn over another - according to the operating code specified by the architecture. The extended binding logic is single-read to the translation unit, and (4) receives the micro-instruction of the job, And use the operand to execute [0013] Another object of the present invention is to provide an instruction set extension module that adds an extended data pattern capability to an existing instruction set. The instruction set extension module has an extended instruction tag (escapetag), a Extending the preamble and an extended execution logic το. The extension instruction flag is received by a translation logic unit, and indicates that an accompanying portion of the corresponding instruction specifies that the microprocessor is to perform one of the extensions of the extension The instruction is marked as one of the first operation codes in the existing instruction set, and the extended operation element size specification element is coupled to the extension instruction mark, and is the

Clients Docket No.: TT, s Docket N〇: 0608-A40748TWF1/DEVICHEN/2006-07-05 10 1282066 is used to specify a plurality of data modules corresponding to the extension operation, and the extended execution logic unit is coupled to the translation logic Units, , , and ,, but failed to provide the specified data mode. The re-purpose of the invention was to provide an extension of the existing instruction. The method includes providing an extension instruction, the extension instruction including one and an extended preamble, wherein the extension mark is the same as: the code item; the extension instruction is translated into the micro instruction, the package, the detection_extension Marking and money extension translation and decoding the rest of the extension instruction to replace the lean mode of the extension operation; specifying the extended data mode through the extended preamble and the rest of the extension instruction - The operation is specified, wherein the existing instruction set architecture only provides an instruction for the extended mode (4) of the extended mode; and the specified operation is performed according to the extended data mode. BRIEF DESCRIPTION OF THE DRAWINGS [0015] The foregoing and other objects, features and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Block diagram of the microprocessor instruction format, _7] Figure 2 is the table - its 'interpretation' - the instruction in the instruction set architecture, how to correspond to the bitmap logic in the -8-bit operation code bit in the instruction-instruction format [0018] FIG. 3 is a block diagram of an extended instruction format of the present invention;

Client’s Docket No.: TTs Docket No: 0608-A40748TWF1/DEVICHEN/2006-07-05 11 1282066 Special steam imr four materials—forms’ display according to the present invention, extended architecture

The at least, ~ to 8 bits extend the logic of the bit in the preamble embodiment; one of the data patterns [0020] Figure 5 is a block diagram illustrating the application of the extended microprocessor of the present invention; [0021] The sixth is the block diagram of the extended preamble of the extended data mode in the designated microprocessor - the specific figure of the [0022] ® seven-phase five-fibre internal translation stage logic [0023] FIG. 9 is a block diagram showing the logic of the extended execution phase in the microprocessor of FIG. 5; and FIG. 9 is a diagram for describing the operation of the extended data mode in one of the specified microprocessors. Operational flow of the method of translation and execution [Main component symbol description] 100 Instruction format 101 Preamble 102 Operation code 103 Address specification element 200 8-bit operation code diagram 201 Operation code value 202 Operation code F1H 300 Extension instruction format 301 Preamble 302 Run nose code 303 Address designation element 304 Extension instruction mark 305 Extended preamble 400 8-bit preamble map 401 Architecture feature 500 Pipelined microprocessor 501 Extract logic unit

Client's Docket No.: IT's Docket No:0608-A40748TWFl/DEVICHEN/2006-07-05 12 1282066 Case No. 91124005 96; January 4曰, f ;; ^ Correction Page External Memory 505 Extended Translation Logic Unit 507 Execution Logic 600 extended preamble 700 translation stage logic 702 machine specific register 704 buffer 706 translation controller 708 escape instruction detector 710 instruction decoder 712 microinstruction buffer 714 micro opcode stall 716 source Bit 800 Extension Register Stage Logic 802 Register Logic 804 Source Operation Element Address Field 806 Extended Read Logic 808 Micro Instruction Buffer 810 Operation Element Buffer 812 Result Buffer 814 Operation Element Field 504 Translation Logic Unit 5 〇6 micro-instruction queue 508 extended execution logic unit; 701 start state signal 703 extension feature block 705 translation logic unit 707 disable signal 709 extension decoder 711 control read-only memory 713 opcode extension block 715 destination field 717 shift block 801 micro-instruction buffer 803 extended register file 805 source operand address field 807 extended write back Series 8〇9 operand buffer 813 buffers 8Π complete microinstructions result buffer 815 entry bar extending operand bit instruction register 816 extending 900~924 of extension data designated mode operation of a microprocessor, for

Client's Docket No·: TT^ Docket No: 0608-A40748TWF2/DEVICHEN/2007-0U03 1282066 _ Operational flow of the method of execution [Embodiment] The description of the vein mr is in the specific embodiment and its necessary conditions, A variety of 'can be familiar with this experience can be the invention. However, the modification of the == simplification, for the technologist, his embodiment ί 'and the general principles discussed herein can also be applied to its application, and 9' the invention is not Limited to the specific realities shown and described herein. The largest characterization feature that is consistent with the principles and novel features disclosed herein has been discussed in today's microprocessors, how to expand its architecture to 1, and in the technology of ^, t-target instruction set capabilities, . There are two examples of =&quot;:, which will be discussed - examples of related technologies. The discussion here is a dilemma that the spleen, / w (four) meter has been facing, that is, they want to: i develop the architectural characteristics of the design of the microprocessor, but on the other hand: take the implementation of the old The ability to program. In the example of ®-to two, the full-occupied opcode map has been added to the new operation ==exclude' thus forcing the designer to choose the new feature ^=_ degree of wealth, mixed or not The latest developments - and put it in order to maintain the compatibility of the microprocessor with the old application. A discussion of the present invention will be provided after a discussion of related art. By utilizing i_unused transport heterocode as the pre-extension directive pre-coded token, Ben Schumming allows the microprocessor designer to overcome the limitations of the fully-instructed instruction set architecture, in addition to providing programmers with a ratio Existing long calculations

Clienfs Docket No.: U TT^s Docket N〇:0608-A40748TWFl/DEVICHEN/2006.07-05 14 1282066 «Capability' can also (4) Execute the old recorded record f neighbor 7] Please refer to the figure -, its system _ A block diagram of the micro-form 1 (10) of the phase. The related art instruction 1 has a variable number of items 101-103, and each item is set to a specific value, which is in the vicinity of: micro = ^ specific instruction 1 〇 0. The specific instruction_represents the micro-order=detail-characteristic operation, for example, adding two operands, or moving an operand/memory to the internal register, or moving from the internal register to the record . In general, the opcode item 102 of the instruction 1〇_ specifies the desired bribe operation, and the address (gpti(10)al) address designation iQ3 is located after the transport code is moved to specify additional information about the particular operation. How it is: Take the operation, where the operand is located, and so on. The instruction format is 1〇〇 and allows the programmer to add a preamble item before the - opcode 102. The preamble 1G1 is used to indicate whether a particular architectural feature is used when the specific code is executed by the code ship. In general, these architectural features can be applied to most of the operational differences in any instruction code 1〇2 in the instruction set. For example, today's preamble 1〇1 exists in a processed state that can perform different operations using different sized operands (such as 8-bit, 16-bit, 32-bit). And when many such processors are programmed to a predetermined {-equivalent size (such as 32-bit), the pre-coded 101 provided in its individual instruction set still enables the programmer to follow the instructions. The preset operand size is selectively overridden (eg, to perform a μ bit operation). The choice of operand size is just one example of architectural features. In many modern microprocessors, these architectural features can be applied to many operations (such as addition, subtraction, multiplication, and Boolean logic) that can be specified by the opcode 1〇2. Wait). [0028] The instruction format 100 shown in FIG. 1 has a well-known standard in the industry.

Clients Docket No.: TT5s Docket No: 0608-A40748TWF1/DEVICHEN/2006-07-05 15 1282066 Cry ', χ86 command format (10)' It is used for all modern tear-compatible micro-processing. More specifically, the χ86 instruction format 1〇〇 (also known as X% refers to Yagi Wood Construction 100) uses an 8-bit preamble 1 〇 8 8-bit operation stone horse 1 〇 2 and 8-bit 兀 address designation Yuan 1〇3. Χ86 architecture survey also has several preambles 10^ two of which replace the address/data size preset by the edge microprocessor, code 顚 and 67Η), and the other side indicates that the microprocessor is based on the untranslated rules. To interpret the subsequent operation code bit group move (that is, the pre-exhaustion value coffee, which makes the translation action according to the so-called two-bit operation code rule), and the other front-end ΗΠ ············ Until the repetition condition is satisfied (ie REP opcodes: F〇h, F2H and F3H). Referring now to FIG. 2, a table 2 is shown to describe how an instruction 201 of an instruction set architecture corresponds to an 8-bit code byte 1G2 read value in the instruction format of FIG. The table presents an example of an 8-bit opcode ^ 200 that associates the octet opcode item acid with a maximum of 256^ fixed values to the corresponding microprocessor opcode instruction 2〇1. The table maps the code item 1〇2 to a specific value, such as a coffee, to a corresponding opcode instruction 2〇i (ie, instruction 1〇2 2〇1). In the example of the full operation stone horse diagram, it is well known in the art that the code value 14H is mapped to the With86 Add With Carry (ADC) instruction, which will directly The (immediate) operand is added to the embedded value of the architecture register AL. Those skilled in the art will also find that the X86 preamble 1〇1 (ie 66H, 67H, 0FH, F0H, F2H and F3H) mentioned above is the actual opcode value of 2 in different contexts. 'Specify that a particular schema extension is to be applied to the operation specified by the subsequent operation item 102. For example, at opcode 14H (normally,

Client's Docket No.: TT5s Docket No: 0608-A40748TWF1/DEVICHEN/20〇6-〇7.〇5 16 1282066, not to mention the ADC opcode) plus the preamble (four), will make the processing - the implementation of , % and insert a low-precision single-precision floating-point value" (ah pure - Interleave Low Packed Single-Prec. sion Floating-Point Values), instead of the original ADC operation. Features such as this are partially enabled in modern microprocessors, since the instruction translation/decoding logic within the microprocessor is a sequential interpretation of the project igmg3 of age (8). So in the past, using a specific opcode value as the preamble KH in the instruction set architecture allowed the micro-processing designer to have less advanced architectural features and compatibility with the old software-reading design, without Negative impact on execution without the use of those specific opcode states. For example, a private model that has not been used to transport I 0FH can still be executed on today's χ86 microprocessor. A newer application, by using the χ86 opcode (4) as the preamble 101-', can use many of the newly incorporated features of the 86 architecture, such as single instruction heavy-duty (SIMD) operations, conditional mobile operations, and so on. , meaning [〇〇3〇] although the architecture has been provided in the past by specifying the available/excessive opcode value 201 as the preamble 1G1 (also known as the architectural signature/indicator ΐ() ι or the escape instruction 101). Features, but many instruction set architectures (8) in the provision of functions ^ spoon to strengthen the day-to-day defensive will still be due to a very direct reason, and encountered obstacles / redundant opcode values have been used up, that is, the opcode map · The full H-calculus value in the middle has been singulated. When all the possible (four) values are assigned to the first 21= or the preamble item 1G1, there is no remaining opcode value in the device architecture. A serious problem exists in many of the current micro-processing L designers. You have to choose between adding architectural features and retaining old compatibility. work

Client's Docket No TT'sDocketNo: 0608-A40748TWFl^VICHEN/2006-07-05 17 1282066 [0031] It is worth noting that the instruction 2〇1 shown in Figure 2 is expressed in a general manner (ie, 124, 186), rather than specifically referring to actual operations (such as carry accumulation, subtraction, mutual exclusion or). This is because, in some different microprocessor architectures, the fully occupied opcode map 200 is architecturally excluded from the possibility of incorporating newer developments. Although the example in Figure 2 is an 8-bit opcode entry 102, those skilled in the art will still recognize that the specific size of the opcode 1〇2, except as a special case, discusses the fully occupied opcode structure. In addition to the problems caused by the problem, other aspects are not related to the problem itself. Therefore, a fully occupied 6-bit opcode map will have 64 architectablely specified opcodes/pre-blocks 201' and will not provide usable/excess opcode values for expansion. [0032] Another alternative is not to completely discard the original instruction set, replace it with a new format 1 (10) and the opcode map 200, but only for a part of the existing opcode 2〇1, with a new one. The instruction is intended to be replaced, as shown in the operating code 40H to 4FH of Figure 2. With this hybrid technology, the microprocessor can operate in one of two modes: the old mode uses the opcode 4〇h_4fh, depending on the rules, or in another modified mode ( (3) ^ sister (four) m〇de) Operation, this day's shoud code 4〇Η-4Ρϋ is interpreted according to the strengthened structure rules. This singularity technology does allow designers to incorporate new features into the design. However, when the microprocessors that meet the old specifications operate in enhanced mode, the shortcomings still exist, because the micro-processing does not perform any use of the opcode 4〇H_4FH Application. Therefore, it is still unacceptable to stand on the standpoint of retaining the old software compatibility and compromising the old software/enhancement model. [0033] However, 'the instruction set that is completely occupied by the opcode space』 (8), and the space covers all applications executed on the microprocessor conforming to the old specification.

Client's Docket No · rr, DocketNo: 0608.A40748TWFl/DEVlCHEN/2006-07-05 1β 1282066 The situation of the program 'The inventor of this case has noticed the use status of the operation code 201' and they also observed that although some instructions 202 are Architecturally specified, but not used in applications that can be executed by a microprocessor. The command ΙΠ 202 described in Fig. 2 is an example of this phenomenon. In fact, the same opcode value 202 (i.e., F1H) is mapped to an active instruction 2〇2 that is not used in the 指令86 instruction set architecture. Although the unused Χ86 instruction 202 is a valid χ86 instruction 202 indicating that an architecturally specified operation is to be performed on the χ86 microprocessor, it is not used in any modern x86 microprocessor. application. This special x86 instruction 202 is called In Circuk Emulation φ Breakpoint (ie ICE Β κρτ, opcode value F1H), which was previously used exclusively for a microprocessor simulation that no longer exists. In the device. Ice BKPT 202 1⁄4 is not used in applications other than in-circuit simulators, and in-circuit analog devices that previously used ICEBKPT 202 no longer exist. Thus, in the case of x86, the inventor of the present invention has discovered a tool in a fully occupied instruction set architecture 200 by utilizing an active but unused opcode 202 to allow for inclusion in the design of the microprocessor. Advanced architectural features without sacrificing the compatibility of legacy software. In the "fully occupied instruction set architecture 2"_ the present invention utilizes - an architecturally specified but unused opcode 2 〇 2 as an - indicator flag ' to indicate one of the following n-bit preambles, Therefore, micro-processing is allowed to count up to 2n of the latest developments of the architectural features, and the microprocessors of the microprocessors are completely compatible with all the old software. [0034] The present invention provides a meta-month ij code by providing an n-bit extended operation element size to mark/extend the concept of a preamble, thereby allowing a program to be in the microprocessor. Specify an extended data mode according to each instruction

Clients Docket No.: TT^ Docket No: 0608-A40748TWF1/DEVICHEN/2006-07 〇5 19 4 1282066 • The operation should be. The extended data model system replaces the existing data schema supported by the existing command set architecture of the microprocessor. The invention will now be discussed with reference to IX. ..., U - [0035] Please refer to FIG. 3, which is a block diagram of the extended instruction 柊弋3(10) of the present invention. The format discussed in the figure--is very similar. The extension 2 has a variable number of instruction items 301-305, and each item is set to a value of 7 ' to form one of the microprocessors. Instruction 3 (10). The particular private order 300 instructs the microprocessor to perform a particular operation, such as balancing the two operands or moving the operand from the memory to the temporary storage of the microprocessor. In the case of the instruction 300, the operation of the Shima project 3〇2 specifies the address to be executed and the specified address is specified. The item 3〇3 is located after the operation code 3〇2, and the additional information related to the specific operation , like how to perform the operation, how, where, and so on. The command format also allows the programmer to place the code in the "code" item. The specific operation execution specified in the operation code 3〇2 is used to indicate whether or not to use the existing architectural features. [〇〇36] However, the extension instruction of the present invention is a superset of the above-mentioned FIG. 1 instruction j1〇〇, which has two additional items deleted: can be selected as an extension of the instruction, and threatened— Format extension refers to; the rest of the project is 3〇1-303. The two additional items 304 and 305 are materials; the type 5 is capable of performing an operation according to the extended data mode in the microprocessor of the old specification, wherein the extended mode cannot be performed. In addition, the existing instruction set conforms to the old rule #丄曰令钇U processing state plus ==^ These two additional items 3〇4 and 3〇5 can be larger operands/operations..., Inbound - A microprocessor design with a fully occupied instruction set architecture. selected

Client’s Docket No.: TT s DocketNo: 〇608-A40748TWFl/DEVICHEN/20〇6-〇7.〇5

Client’s Docket N丨 20 « 1 1282066 With items 304 and 305 - Huding; 乂 庄 庄 甲 甲 甲 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才 才In the extension instruction flag, another operation code #, which is specified by the architecture, reads "Order the instruction instruction mark 3G4, or the escape_3G4," which is the 1CEBKPT instruction used earlier. Escape: two '=F1H, The series pointed out that the extended preamble 3〇5 ☆ out of the ^ 304 to the microprocessor behind the logic, 1 towel # ^ said the extension feature specified element 3G5, the system followed by the extension of the preamble 305 specified For the operation unit/operation size or data = in the case of Yun Yun - 3〇4 points out that - corresponding to the extension instruction in the example, the "escape mark determines the microprocessor to perform - the extension of the transport points (10) 3 and 3 〇 5 fingers Dingzhi extends the difference. The extended operation element size specifies the elementary tube or ^extends the preamble 3〇5' to specify the plural number corresponding to a correlation operation&quot;&quot; The unit accesses the operands in the extended size register when the p extension is extended, and processes the accessed operands using the specified operand size or data pattern processing rule. 0037] Here is an overview of the technique of the extended data pattern of the present invention. Configuring to specify an extended φ poor mode in an existing microprocessor instruction set, wherein the extended data mode cannot be specified in accordance with the existing microprocessor instruction set. The extended instruction includes the existing instruction set One of the opcodes/instructions 304 and an n-bit extended feature preamble 3〇5. The selected opcode/instruction is used as an indicator 304 to indicate that the instruction 300 is an extended feature instruction 300 (ie, its An extension of the microprocessor architecture is specified, and the η-bit feature preamble 305 indicates the extended data pattern. In a specific embodiment, the extended preamble 305 has octets and can specify up to 250 Different capital

Clients Docket No.: TT5s Docket No: 0608-A40748TWFl/DEVICHEN/2006-07-05 21 1282066. For the embodiment of Fu Shi Shima, you can specify up to 2n different types of characters: right stroke: in the embodiment, provide 64-bit data mode to replace the default data mode in a microprocessor. (For example, 32-bit or 16-bit two-ports, when the corresponding traffic is executed, the execution logic is 64-bit operations (such as addition, subtraction, logic operations, etc.). In another case, 'more allows the programmer to specify 64-bit or 128-bit data modulo ^, , . . . [Caf] Please refer to Figure 4, a table 4 〇〇 shows according to the present invention, temporarily How to store the sub-thresholds to the bit-robin state of an S-bit extended preamble embodiment. Similar to the opcode diagram discussed in Figure 2, Table 4 of Figure 4 presents an 8-bit number. An example of an extended data pattern preamble map 400 that associates up to 256 values of an 8-bit extended preamble item 305 to a corresponding extended data pattern 401 of a microprocessor that conforms to the old specification (eg, 34) , E4D, etc.) In the specific embodiment of the -6, the 8-bit extension feature preamble 3 of the present invention is still Supply data mode 4〇1 (also known as e〇〇_eff), which is not provided by the current x86 instruction set architecture. [0039] Figure 4 does not extend the feature 4〇1 In a general manner, the table does not specifically refer to actual features, as the techniques of the present invention are applicable to a variety of different architecture extensions 40i and specific instruction set architectures. Those skilled in the art will recognize that many Different architectural features 4〇1, some of which have been mentioned above, can be incorporated into the existing instruction set according to the escape tag 3〇4/extension preamble 3〇5 technique described here. The four-octet preamble embodiment provides up to 256 different features 4 (U' and the n-bit preamble embodiment has a stylized selection of up to two different features 401.

Client's Docket No.: TT?s Docket N〇: 0608-A40748TWF1/DEVICHEN/20〇6-〇7_〇5 1282066 Factory 4 [0040] Please refer to Figure 5 for illustrating the present invention for performing extended data杈A block diagram of a conventional microprocessor 500. The microprocessor 500 has months, types, pages, types, extractions, translations, and executions. The extraction phase has a logic = unit 501, and the command can be extracted from the instruction cache 5〇2 or the external memory 5〇2. The fetched instructions are sent to the translation phase via command queue 503. Turning to ^=4, there is a translation logic unit 504 coupled to a microinstruction queue 506. The conversion unit 5Q4 includes an extended translation logic unit 505. The execution phase has execution logic 507 with an extended execution logic unit 5〇8. According to the present invention, in operation, the extraction logic unit 5〇1 extracts formatting instructions from the pointing 2 cache memory/external memory 502, and places the fingerprints in the order in which they are executed. Queue 5〇3. The instruction is then fetched from the instruction queue 5〇3 and sent to the translation logic unit 5〇4. The translation logic unit 5〇4 translates/decodes each of the incoming instructions into a corresponding microinstruction sequence to instruct the microprocessor 500 to perform the operations specified by the instructions. In accordance with the present invention, the extended translation logic detects 70 505 instructions having extended preamble markers for translation/decoding of the specified meta preamble corresponding to the extended poor mode. In an implementation of x86, the extended translation logic unit 505 is configured to detect an extension of the F1H _ pre-code flag, which is an ICE Β κρτ opcode of x86. The extended microinstruction block is provided in the microinstruction queue 5〇6 to allow the extension of the data mode to be specified in the microprocessor 5(8). [0042] The microinstruction is sent from the microinstructor column 5〇6 to the execution logic, wherein the L extension execution logic unit 508 is configured to access the internal microprocessor temporary storage as specified by the extended microinstruction block. Device. A plurality of source transport elements that are designated to be used to perform the transfer are extracted from the source operand extension register.

Client's Docket No.: TT s Docket No: 〇 608-A40748TWF1/DEVICHEN/2006-07. 〇 5 23 1282066 The extended execution logic unit 508 performs the operation specified by the microinstruction and produces a corresponding result. As the result is generated, the extended execution logic unit 508 writes back the corresponding result to the destination operand extension register specified by the extended microinstruction block. Those skilled in the art will recognize that the micro-processing crying 500 series modern pipelined microprocessor 50 shown in FIG. 5 has a simplified result. In fact, modern pipelined microprocessors 500 can contain up to 20 to 30 different pipeline stages. However, these stages can be broadly classified into the three stages shown in the block diagram, and therefore, the block diagram 500 of Fig. 5 can be used to clarify the necessary elements required for the foregoing embodiments of the present invention. For the sake of brevity, the unrelated components of the microprocessor 5 are not shown. [0044] Reference is now made to FIG. 6, which is a block diagram of one embodiment of an extended preamble 600 for designating a microprocessor extension/transport. The extended operand/operation specifies the meta preamble of 600 with an 8-bit size. In one embodiment, the value of the 8-bit preamble 600 specifies an extended data pattern for a corresponding operation, wherein the corresponding operation is specified by the remainder of the extended instructions of the present invention, as described herein. In an x86 embodiment, the extended data pattern (e.g., a 64-bit operand/operation) is designated to replace a predetermined data call mode (e.g., a 32-bit operand/operation). [0045] In the embodiment of the present invention extending the preamble 6〇〇 of FIG. 6, the entire preamble 600 is used to designate an extended data mode. However, those skilled in the art will recognize that the number of bits required to designate one of the plurality of extended data patterns depends on the number of extended data patterns. Thus, an embodiment capable of specifying a 64-bit or 128-bit data pattern requires only one bit of preamble 6 (10) to distinguish between the two modes. So, the rest of the preamble 6〇〇

Client's Docket No.: TT5s Docket No:0608-A40748TWF1/DEVICHEN/2006-07-05 24 1282066 ^Can be used to specify - other extended special logic chains that are not available in the existing instruction set architecture [7〇Γ6] The job seven's is the block diagram of the detail of Figure 5. The translation stage logic 700 has a one-to-one instruction, which provides an extension instruction to the translation logic unit. Turn 70 7G5 system turn - machine with an extended feature block 703 cry 2 special register Ua object e sp touch c 7. 2. The translation logic is long: 2 = controller 7 〇 6 ’ which provides a divisor signal 7〇7 to the escape command to extend the decoder 7〇9. The escape command detector 708 is transferred to the delay decoder 709 and the -instruction decoder 71A. The extended decoder 7〇9 and the instruction decode logic 710 access a control read-ahead memory (ROM) 711 in which pairs of template microinstructions to some extended instructions are stored. The translation logic element 705 also includes a microinstruction buffer 712 having an opcode extension block 713, a microcode block 714, a destination block 715, a source block 71, and a displacement field 717. . [0047] In operation, during the power-on startup of the microprocessor, the state of the extended block 703 in the machine-specific temporary storage 702 is determined by the signal activation state _ power-upstate 701 to indicate the particular microprocessor. Whether it is possible to translate and execute the extended instructions of the present invention for providing an extended data mode of the microprocessor. In one embodiment, the signal 701 is derived from a feature control register (not shown) that reads a fusearray that has been assembled at the time of manufacture (not display). The machine specific register 7〇2 sends the status of the extended feature block 703 to the translation controller 706. The translation control logic 7〇6 controls the instructions fetched from the instruction buffer 704 in accordance with the extended translation rules.

Client’s Docket No.: TT5s Docket N〇: 0608-A40748TWF1/DEVICHEN/2006-07-05 25 1282066 Or use the translation rules for interpretation. Providing such a control feature, the application program (such as the extended execution feature of the class calling enable/disable microprocessor) is de-energized, and is marked by the &amp; 'right ^, page is extended The b of the computational code bear will be translated according to the translation rules. In:, select the operation code state F1H as Sll + h, the body yoke example, and (4) c1Um η as pure 5, then under the customary translation rules, Encountering the leg will result in an illegal command exception (exeeptiQn). If the extension is disabled, the instruction decoder 71G will translate/decode all the given instructions and configure all of the intercepts 713 to 717 of the microinstruction 7i2. However, under the extension rule, if the flag is marked, the instruction will be detected. The escape command detector 708 thus causes the instruction decoder 71 to translate/decode the rest of the extension instruction, and The micro-opcode block Μ 位移 位移 位移 位移 微 微 微 微 微 微 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 712 The shelf 713 is configured. Some specific instructions will lead The access to the control R〇M 711 is obtained to obtain a corresponding microinstruction sequence template. The configured microinstruction 7i2 is sent to a microinstruction queue (not shown) for subsequent execution by the processor. [0048] Referring now to Figure 8, a block diagram of the extended temporary stage phase logic 800 in the microprocessor of Figure 5. The extended register stage logic 8 - register logic 802' extracts the extended microinstruction of the present invention from a microinstruction buffer 8〇1 or ^instruction queue 801. The register logic 8〇2 has two extended register files containing a plurality of extended registers 816 8〇 3. Each extension register 816 has a predetermined operand block 814 and an operand extension block 815. In an X86 embodiment, the preset operand block 814 is 32 bits. Yuankuan' to support the storage and extraction of 32-bit operands with x86.

Clients Docket No.: TT5s Docket No: 0608-A40748TWF1/DEVICHEN/2006-07-05 26 1282066 II; 延伸 The extension block δί5 is 32 bits wide to allow S t64 bits. - 128-bit wheel _ (four) bit: fruit = source, and by extension back to write logic 8.7 access,; : transport 4. The extended read_806 will source the operands (10), (10) to the two operand buffers 809, 810. Result = Two result buffers are committed, sent to the extended write logic 8, and the delay instruction is synchronized with the -f_ pulse (not shown), and the microinstruction queue 801 is sent to the scratchpad logic. 802. In the -clock cycle ^ delay: read the logical transfer decoding extended micro-instruction source operand address location 5 to determine which register 816 contains to be used - specify the transport: ^ yuan two extended micro-instructions The operation code extension of 801 is blocked (the value is not shown, and the item 8G6 is accessed in the access register 8). Following the data mode, only the addressed register 8i6 = Han Yun's different pain position 8M is accessed. In view of the f _ type, the bit 814 is accessed with the operation of the distraction item (4) 5 - isometric part, to take the source county 7C. Therefore, the source operation unit (10), W2 8〇3 is extracted and sent to the source operand register 8〇9, δι〇. And:= The microinstruction is sent to the pipeline to the buffer 8〇8 for the subsequent pipeline stage of the microprocessor (not Display) Execution. During the same clock cycle, the most recent execution of the management RS RS2 is written back to the buffer (c〇mpleted) by the complete (c〇mpleted) micro-instruction; the destination register of the Chuanzhong (not shown) The specified destination register is δΐ6. The value of the operation code extension block (not shown) in the complete microinstruction buffer m determines whether the result is back. To the destination operand of register 816 extends items resting position, to

Client’s Docket No·: TT?s Docket No: 0608-A40748TWF1/DEVICHEN/2006-07-05 27 1282066. The corresponding result operand and which part of the extension field 815 is written back to the RS 102 is sent to the buffers 812, 813. [0050] The register stage logic shown in [0050] provides an effort to access the two source registers and the two result registers in a single day cycle. In addition, the implementation outline provides two source operands and a single-purpose destination operand. In order to ensure that the temporary H 816's -> extension register logic 8Q2 is before the execution of the result RS b RS2 write back, the source operation element 〇ρι, beating is accessed. [0051] Referring now to Figure IX, a flowchart showing the operation of the present invention for a method of translating and executing an instruction that allows a programmer to specify an extended data mode of a microprocessor. The flow begins at block 902' where a program configured with extended feature instructions is sent to the microprocessor. The flow then proceeds to block 9〇4. [0052] In block 904, the next instruction is extracted from the cache memory/external memory. The flow then proceeds to decision block 9〇6. [0053] In decision block 906, the next instruction fetched in block 904 is checked to determine if an extended escape code of the present invention is included. In an embodiment of 86, the check is used to detect an opcode value F1 (ice BKPT). If the extended escape code is detected, the flow proceeds to block 9-8. If not &quot;[the extended escape code is detected, the flow proceeds to block 912. [0054] In block 908, the extended preamble portion of the extension instruction is decoded/translated to determine an extended data pattern designated to perform the current operation. Flow then proceeds to block 910. [0055] In block 910, the extended data pattern used by the current operation is assigned to an extension field of a corresponding microinstruction sequence. The flow then proceeds to block 912.

Client's Docket No.: TT^ Docket N〇:0608-A40748TWF1/DEVICHEN/2006-07-05 28 1282066 [0=6] at block 912, 'All the rest of the instruction is decoded/turned = to determine the designation The operation, the bit (4) of the operand of the operation, and the = microprocessor instruction set architecture 'use of the existing architectural features of the preamble. Flow then proceeds to block 914. ...[=057] at block 914 t '-the microinstruction sequence is configured to specify the specified operation and its corresponding opcode extension. Flow then proceeds to block 916. [0058] At block 916, the sequence of microinstructions is sent to a microinstruction queue, which is executed by the microprocessor. The flow then proceeds to _方方, the micro-finger = thorn one extension · the register logic to extract. The extension register logic extracts an operand corresponding to the specified operation from the specified scratchpad. The operand is sized according to the data mode (ie, preset or extended) specified in the second instruction sequence. Flow then proceeds to block 920. [0060] In block 920, the extended execution logic unit applies the specified data pattern, and the specified operation is performed using the operand accessed in block 918 to produce the resulting operand. Flow then proceeds to block 922. [0061] In block 922, the result operand is sent to the extended scratchpad logic and written back to the extended register in the data pattern specified by the sequence of microinstructions. Flow then proceeds to block 924. [0062] In block 924, the method is completed. [0063] While the invention and its objects, features and advantages have been described in detail, other embodiments may be included within the scope of the invention. For example, the present invention has been described in the context of a single _, unused code state in a fully occupied instruction set architecture as a flag to indicate the subsequent extended feature front

Client's Docket No.: TVs Docket No: 0608-A40748TWF1/DEVICHEN/2006-07-05 29 1282066 =: However, the scope of the present invention is not limited to the fully occupied architecture of the command set or not. The instruction used, or single-mark. Conversely, the present month covers an embodiment of an instruction set that is not fully mapped, an embodiment with a used opcode, and more than one private tag. For example, consider a private order architecture that is not used and is sloppy. One embodiment of the present invention includes the selection of =, = the state of the opcode of the escape token, wherein the selection criteria are determined by market factors. Another embodiment includes the use of a particular combination of opcodes as a signature, such as the sequential occurrence of opcode state 7FH. Therefore, the essence of the present invention is to use a --mark sequence, followed by an n-bit extended preamble, which allows the well-programmer to specify an extended data pattern in the -extension instruction, and the benefit method is additionally processed by micro processing. The instruction set of the device is provided by an instruction. -^, , , , , , _64 In addition, the present invention is mainly described in the extended bit mode of 64 bits and 128 bits. However, these modes are merely illustrative of the various aspects of the present invention in the context of the data patterns exhibited by modern desktop/laptop microprocessors. Therefore, those skilled in the art will appreciate that the scope of the present invention can be extended to applications that require very large or small operands/operations, or applications that have variable-sized operands/operations, where a particular operand/ The size of the operation is specified according to each instruction. # _5] Further, the present invention and its objects, features and advantages are exemplified by those skilled in the art. Those skilled in the art will still be aware that the scope of the invention is not limited to the architecture of the microprocessor. It can cover all forms: device, such as signal processor, workmanship ^ Wang + η, earth to use industrial controller (industrial controller), array processor and other similar devices. In summary, the above is only a preferred embodiment of the present invention, when not

Clienfs Docket No.: TTs Docket No: 0608-A40748TWF1/DEVICHEN/2006-07-05 30 1282066 \ % The scope of the invention can be limited thereto. The equal changes and modifications made by Dafan in accordance with the scope of patent application of the present invention should still fall within the scope covered by the patent of the present invention. I would like to appoint the reviewer for the examination and pray for the best. wind

Client’s Docket No·: TT5s Docket N〇:0608-A40748TWF1/DEVICHEN/2006-07-05

Claims (1)

1282066 Amendment No. 91124005 January 4, 1996 10, the scope of application for patents: Order, executed by micro-processing, which is transferred to the corresponding micro-finger one extension preamble, used for the second day 7 · &gt; extends the operand size, where the extended gentleman-operator is specified; and the size b is extended by the existing instruction set extension preamble, where the delay code; and 曰7 within - according to the architecture specified by the corresponding to: the translation logic unit 'to access the translation logic unit contains: μ to perform the specified operation, two of which are used to detect the extended preamble tag; Knowing that the heart decides that the material is to be executed, and that it is used to transfer the output command side and the instruction decoding: the size is different, and the corresponding two instructions are specified in the corresponding micro-instruction. The setting of the item/1, wherein the extension instruction further includes an instruction item of the existing instruction set. 3. The device described in item 2 of the U-profit range, the operation of the instruction item is straightforward and the operation of the operation is performed on the operation of the operation, wherein the register is based on a plurality of different sizes. The extraction/storage of the transportation. 4. The device of claim 3, wherein the operand sizes comprise a 64-bit operand size. 5. The device of claim 3, wherein the operand sizes further comprise a 128-bit operand size. ^ Client's Docket No.: TT^ Docket No: 0608-A40748TWF2/DEVICHEN/20〇7-〇i.〇3 32 1282066 Set the operation size.仃 邮 邮 载 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' For example, the size of the φ 兀 是 是 是 〇 〇 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 φ φ φ φ φ φ φ , , , , , , , , This extension pre-sets the operation code F1 (ICEBKPT). The set extension module package i has both the instruction set and the extension (four) mode capability of the instruction finger ^ 'by the translation logic unit pure, and indicates that the corresponding tube ^ is specified to execute one extension of the microprocessor = and its boat The extension instruction is marked as the first operation in the existing instruction set; the bucket is in the range = the code is connected to the extension instruction mark, and is the accompanying part 2. One to specify the plural corresponding to the extension operation The data row mode is coupled to the translation logic unit, and the extension operation is performed by using the two modes, wherein the existing instruction set only provides: jϋ' and fails to provide the specified data mode The translation logic 7L includes: /, an escape command detector for detecting the extension instruction indicating that the translation operation of the attachment (four) points is based on the extended translation convention; and ^-extending decoding n, secret to the escape The instruction (4) is configured to execute the translation operation according to the Client's Docket No.: Tr.DocketNo: 0608-A40748TWF2/DEVICHEN/2007^ 33 1282066, and translate the extension according to the extension; Yiyi According to the specified data schema, the instruction set extension module described in the section 11 of the Haili Range f11, the address refers to the second operation code and the selected plurality of operation element system. In the μ ^ *, the 1st 5th-above instruction set extension module 'its code F1) 〇匕3 86 is the ICE BKPT opcode in the wood (ie, 11) The micro-finger (4)^ part is translated into pairs to take/store an extended operation unit. π, 廿甲θ廿口17· The data pattern specified in item n of the patent application scope contains -6 4 bits ^ day: : Extending the core group, 18. The data pattern specified in the patent application scope u ϋ 二 2 includes a 128-bit extension module, 19. A method for expanding an existing instruction set architecture ^&amp; Specifying an extended data pattern, the method comprising: providing an extended instruction in the four places, wherein the extended mark is the extended instruction mark, and the extended instruction instruction is to translate the extended instruction into a micro instruction. The microinstruction indicates an extension to execute Client's Docket No.: TT^ Docket N〇:0608-A 40748TWF2/DEVICHEN/2007-01-〇3 34 1282066 Logic single ί f ^ 伸 资料 资料 资料 资料 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该The reading order of the observation instruction D is different from the default data mode. The rest of the age of the data mode specifies that the extension has both the formula and the second, and the extension (four) mode performs the calculation. The method described in item 19 of the data pattern is to specify a delay operation, wherein the first specified action includes using the second instruction code item in the existing instruction set architecture.仏 吏 或 或 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 〇 8-bit size item, the method described in the extension of the pre-extension to the nm-range range, item 19, wherein the provisioning includes selecting the first-transport range from the χ86 microprocessor instruction set architecture* The method of claim 22, wherein the selection of the first code includes the selection of the x86 ice bkpt operation horse (ie, the operation of the method: the method described in item 19) wherein the data pattern of the specified extension is 64 bits, as the Extended data mode. Client's Docket No:: TT s DocketNo-°608-A40748TWF2/DEVICHEN/2007-01-03 12820铋91124005 July 6, 1995 using extended data mode microprocessor 500 501 502 Extract Logic Unit Instruction Cache Memory / External Memory Extract Command Queue 503 1282066 Case No. 91124005 January 4, 1996 P-year-old t-day repair three / correction page Microprocessor using extended data mode 700 701 Figure 7 1282066 VII. Designated representative map: (1) The representative representative of the case is: Figure 5. (b) A brief description of the component symbols of the representative diagram: 500 pipelined microprocessor 501 extraction logic unit 502 instruction cache memory / external memory 503 instruction queue 504 translation logic unit 505 extension translation logic unit 506 micro-instruction queue 507 Execution logic 508 extends the execution logic unit. 8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention: Slightly Client's Docket No.: TT5s Docket N〇: 0608-A40748TWF1/DEVICHEN/2006-07-05