TWI223773B - Suppression of store checking - Google Patents

Abstract

An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies that store checking be suppressed for the extended instruction. The extended prefix tag is an otherwise architectural opcode within an existing instruction set. The fetch logic precludes store checking for pending store events associated with the extended instruction. The translation logic is coupled to the fetch logic. The translation logic translates the extended instruction into a micro instruction sequence that sequence directs the microprocessor to exclude store checking during execution of a prescribed operation.

Description

1223773 V. Description of the invention (1) Contrast with related applications [0001] This application claims the priority of the following US applications: Case No. 10/283, 397, the application date is October 29, 2002. [0 0 0 2] This application is related to the following U.S. patent applications, which are also in the same application, and all have the same applicant and inventor. Applicant's case number for reading Taiwan's application number DOCKET NUMBER Patent name 91116957 7/30/02 CNTR: 2176 Device and method for extending microprocessor instruction set 91116958 7 / 3Q / 02 CNTR: 2186 Execution # instruction instruction and method 91124008 10/18/02 CNTR: 21g7 Selective control method and method for remembering and dismantling the nature of 91911956 7/30/02 asm 2188 Device and method for selectively controlling the write-back of bar code 91116959 7/30/02 CNTR : 2189 Mechanism for increasing the number of registers in the microprocessor 91124005 10/18/02 CNTR: 2190 Farming method and method for extending microprocessor data mode 91124006 10/18/02 CNTR: 2191 Extended microprocessor address mode Device and method CNTR: 2193 Prohibition of selective interruption 91124007 10/18/02 GNTR: 2195 Reference control mechanism for non-temporary shame ships 91116672 7/26/02 CNTR: 2198 Device for selectively controlling the write-back of results and Method [Technical field to which the invention belongs] [0 0 0 3] The present invention relates to the field of microelectronics, and more particularly to a method that can selectively prohibit store checking at the instruction level.

1223773 V. Description of the invention (2) Technology incorporating features of an existing microprocessor instruction set architecture [Previous Technology] [0004] Since the early 1970s, microprocessing has grown exponentially. From the earliest application to the official use of 1 ?; some special areas 5: enter the commercial consumer; the leading :: Mita of the above) computers, video game controllers and many other common use and commercial devices and other products . Xiba he sang to see that [0 0 0 5] with the explosive growth in the use of t, which is characterized by having the following items: faster speed, stronger addressing ability, faster; More; ί yuan, more general-purpose types of operations (such as floating-point operations, early instruction multiple data (SIMD), conditional movement, etc.), and special-purpose operations with ^ (such as digital signal processing functions and other Multimedia computing). This has created amazing technological progress in this field and has been applied to the design of microprocessors, such as extensive ~ pipelining, SUper — scaiar architecture, cache structure, and out-of-order processing. (〇ut — 〇f — 〇rder processing), burst 1: access mechanism, branch predication, and speculative execution. To put it bluntly, today's microprocessors-show a tremendous amount of complexity and powerful capabilities compared to when they first appeared 30 years ago. [0006] But unlike many other products, there is another very important

Page 7 Page 1223773 i. Description of the invention (3) ---- The important factors have limited ′ and continue to limit the microprocessor rack ^ Today microprocessors will be so complicated that a large part of them must be evolved ^^ ^. That is the compatibility of old software. In consideration of the market, all manufacturers ^ =, new architecture features are incorporated into the latest microprocessor design, make 5: ^ choose to incorporate the latest products, and retain all to ensure compatibility === in these It is said that the capabilities necessary for "1 egacy" applications, that is, the burden of compatibility of the old software [0007], is 1% more than that in x86-compatible microprocessors. See the history of development in Canada, ^^. Everyone knows that 'virtual 32 / 16-bit virtual mode', VirtUal-m86 x86 microprocessor 'can still implement 19-bit 8-bit real-mode applications Technologists in the field written by Cheng Gezhen also acknowledge that there are many related architectures "outsourcing; in this architecture, U is used to support the old applications and operability. Although in the past, 'developers can use the newly developed architecture' :::: ms' But now using the tools that these features rely on, you can incorporate the updated features into an existing architecture, so that ... you can use undefined [definition 00 ::] bits such as // x86 instruction set architecture, Already, the size of one of my blocks is running in the main-byte size x86vm; ^ unused. The code status has been shown in the existing code of the household registration agency 1, and all 256 operators are now set to # — 现. As a result, the X 8 6 microprocessor makes a choice. If you want to provide a new dagger that can be used :: The software has two J% formulas and special features, you must assign the shipment. 5. Description of the invention (4) The state of the code gives these characteristics. If the state of the code is calculated, then some existing transport code = set architectures have no extra transport supplies and new features. Therefore, it is necessary to re-define the two states to improve the compatibility of the software. /, New features, you have to sacrifice the old [0 0 0 9] features in modern microprocessors, but before that, some programmers in m77 wanted to include people, which is impossible to achieve at the command level. . One of the items [0 0 1 0] since almost ^^ 疋 more than storage check. The pipeline architecture uses multi-stage instructions that are extracted to the pipeline (the probability is very high), an operation target, and the storage and pending storage have not yet been completed. That is to say; the stage behind the second pipeline, but in many different situations: memory or internal cache memory. This line to-an unused write-storage instruction may be progressing-the appropriate time to write = :: =; the buffer is waiting to leave the pipeline. Familiar with the technology in this field; the designer is allowed to pose various challenges. The two-tiered architecture is related to micro-processing, but these instructions have one. 1. Synchronize the execution of the private order. [0011] An instruction to be executed by a programmer. I ’m worried, it ’s really a kind of device and tool, in order to show that there are paused storage events in the microprocessor pipeline that provide each I and have not been written into memory. 1223773 V. Description of the invention (5) Check all The purpose of step-by-step control instructions to enter the pipeline: Address: II: Save instruction,? C fast; = pause storage event, the destination address corresponding to the corresponding ’then the pipeline will suspend operation, and U: the bit of the instruction to enter the pipeline. When the pipeline is suspended, the pieces are allowed to be written to the memory location and the pipeline is written again. After the writer is written from the original -storage instruction, if: = :, t is allowed to pass through the pipeline. At the time, and its position (that is, its instruction ":, a; the previous pipeline stage was measured IP)) corresponds to the storage instruction Pinter, the step logic will suspend the pipeline operation 'all the same in the microprocessor The pipeline phase. The pipeline before the 2 empty = the previous pipeline phase. After the command is written, it will be refilled. _? 0l2j M check is a very heavy operation, the required hardware and micro processing The storage purpose of the pipeline stage iR from the rainbow ω 丄 corpse is compared with the command position. This is why 'It is very complicated in nature, and it is achieved by replacing the physical address with the address. ★ Check uu virtual address instead of entity [ [0 013] At present, the programmer cannot control the storage inspection feature of the microprocessor. If the programmer chooses the technology of self-modif (Second Memory Check Code), he / she must make sure that the follow-up of the storage target "'is really Corresponding application = Differences on page 10 5. Invention description (6) Need. At the source code level, although such a programming technique is not reasonable. Qiu Jiu / Achieved Does not execute the source code. Automated compiler slave :: instruction stream required by the processor and the parallel. The generated command code generates a micro-alignment alignment feature, and the code and data that are wrong in the same-bian learning. Therefore, even if the tools used to ensure the consistency of the source code are used to ensure the self-chapter, Ch-inon) events are still possible: the process line type = ground. 7 八 码 的 编 #, which is unfavorable [0014] The programmer based on various changes-insert before the instruction-storage operation, _ 1 test 1, you may want to perform the position repair 2 2 position in the desired execution sequence 'but the : Because of the current storage check ... just this =: in the order of :: check [: two reasons: one, ::: / rational method, where the instruction set 4 ==: 2 structured devices and methods include the prohibition feature to allow —Fun Renyun ’s different code is completely occupied, and the ability of the old application is the same as ^ = 2. The processor retains the execution programmer and / or the compiler number to suppress, a '; special instructions can be provided, and it should also be provided as a control. The ability to perform storage checks. [Summary of the Invention] [0016] The present invention is the same as the aforementioned other + other conventional techniques. The problem # 3 is to overcome the above-mentioned problems and disadvantages. The invention of this invention 1223773 (7) Good technology is used to expand the microprocessor's instruction set, beyond the existing capabilities, to provide instruction-level storage check prohibition feature. In a specific embodiment, a device is provided that can perform instruction-level storage check control within a microprocessor. The device includes a fetch logic and a translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended preamble specifies that the storage check of the extended instruction is prohibited. The extended preamble flag is another architecture operation code in an existing instruction set. The fetch logic excludes the storage check for the suspended storage event related to the extended instruction. The translation logic is coupled to the extraction logic, and the extended finger is transformed into a microinstruction sequence (micror instruction sequence), except for a memory check to instruct the microprocessor to execute a specified operation when it is [0017] the present invention An objective of the present invention is to propose a processor mechanism that expands both sets to selectively disable storage checks within a microprocessor pipeline. The microprocessor mechanism has an extended instruction.

Cara's two instructions specify its related storage core: only, where the extension only contains one selected from the existing instruction set, followed by the -n bit extension preamble. The selected operation :: point to the extended instruction "❿ The extended preamble of the n-bit indicates that more than one storage check is required. The translator receives the extended instruction, ^ order sequence, to instruct the microprocessor to perform a specified storage check operation when a microfinger operation is performed ... Exclude the designation 1223773 V. Description of the invention (8) [0018] 本Another object of the invention is to add a module for storing the inspection feature of the prohibition instruction in the reminder set. A ▲ is an existing reference escape tag, a storage check, and the group includes a (store check SUppressiori specifTr does not refer to a certain element and an extended execution logic. The escape tag is extracted by an 'a translation The accompanying part of a corresponding instruction logically specifies the operation to be performed, and refers to the operation that the escape flag is one of the first instruction in the existing instruction set. The query prohibits the specified element from being coupled to the operation. The escape flag is the η; ::: check one, which is prohibited when the operation is executed: turn :: is coupled to the extraction logic, and is used to generate a microfinger ^ the turn-ze logic processor Execute the operation and specify in the microinstruction sequence to be checked. The extended execution logic is coupled to the translation logic, and the sequence is executed without storing and checking. Retry again after the trial and error A purpose 'is to provide a method of expanding the existing finger set wood structure to prohibit storage checking at the instruction level. The method includes providing an extension instruction, which includes an extension & record = an extension preamble, Wherein the extension mark is There is one of the first opcode items in the instruction set structure; the extended preamble is used to specify that the extended instruction is forbidden and stored when it is executed. The rest of the extended instruction specifies the operation to be performed, and the extended instruction is prohibited. [Storage implementation] [Embodiment] [0 0 3 1] The following description is provided in the context of a specific example and its necessary conditions, so that those skilled in the art can use this

Page 13 1223773 V. Description of Invention (9) Invention. = = &Amp; ", and 'various modifications to the preferred embodiment are obvious to those skilled in the art, and the general principles discussed herein can be applied to other embodiments Therefore, the present invention is not limited to the specific embodiments described here in Bayi, but has the widest scope consistent with the principles and novel features disclosed herein. Mu Quan has previously described how to expand the microprocessors in today :. Ancient convergence, technology beyond the ability of the relevant instruction set, the background is discussed: 1 here, in Figures 1 and 2, the limitations of an example set of related technologies will be discussed: the microprocessor design is adjusted The “face” of the instruction microprocessor has been facing. They want to incorporate the newly developed architecture features into the application. On the other hand, they have to keep the old code diagrams. In the example, the possibility of a completely occupied operation thus forcing a new operator to the example architecture is ruled out, and the old softness = ΓΓ 生生 ί chooses to incorporate new features and sacrifice a certain process in order to maintain it The latest in architecture Discuss the compatibility of the post-processing technology with the old application program. The use of an existing Diffuse f 2 to 11 will provide a discussion of the present invention. By marking, the operation code of the present invention can be used. As an extension of the pre-set instruction set architecture limitation, except that the processor designer overcomes the storage check of the instruction instruction group that has been fully used, the programmer can selectively disable a single instruction or all of its features.—, and also Can keep the old applications needed to execute [0 0 3 3] Please order y to make the format 100 the same as β one, which is a related art microprocessor chart. The related technology instruction 100 has a quantity variable

Page 14 1223773

The data items 1 01 -1 0 3, each item is set to a specific value, which together constitutes a specific instruction of the microprocessor 丨 〇 〇. The specific instruction 100 instructs the microprocessor to perform a specific operation, such as adding two operands, or moving an operand from memory to an internal register, or from the internal register to § Ji Yi body. Generally speaking, the operation code item 102 in the instruction 100 specifies the specific operation to be performed, and when the address of the (〇pti〇nal) selected is specified, it is specified before. An example of a location that is not provided by an operation instead of a bit. In most cases, logic can be used. The fixed element item 103 is located after the operation code 丨 02 to specify additional information about the operation, such as how to perform the operation. Located etc. The instruction format is 100 and allows the programmer to encode the item 101 before an operation code 102. A specific operation specified in operation code 1 02 is performed. A code 1 0 1 is used to indicate whether to use a specific architectural feature. Generally these wooden features can be applied to most of the calculations of any operation code 102 in the instruction set. For example, today's preamble 01 exists in processors that can perform operations of the same size (such as 8-bit, 16-bit, 32-bit). When many such processors are programmed to a budget size (such as 32-bit), the prefix 101 in their individual instruction set still allows programmers to selectively override the preset based on each instruction. Set the operand size (for example, to produce 16 operations 70). The selectable operand size is only one of the architectural features. In many modern microprocessors, these architectural features can be applied to the operations specified by the operand 102 (such as the example of addition, subtraction, multiplication, and this is the X86 instruction format). 100, which is what =

1223773 V. Description of the invention (11) Microprocessor | More specifically, the χ 8 6 instruction format i 〇〇 (also known as the x86 instruction set architecture 100) uses an 8-bit preamble 101, an 8-bit opcode 102, and an 8-bit address specification. Yuan 1 〇3. X 8 6 architecture 1 〇〇 also has several preambles 101, two of which replace the preset address / data size of the x86 microprocessor (that is, opcode states 66H and 67H), and the other indicates The microprocessor interprets the following operation code bytes according to different translation rules (that is, the preamble value 0 F Η, which makes the translation action based on the so-called two-byte operation code rules) , The other preambles 丨 〇1 makes special operations repeated until the repetition conditions are met (ie REP operation codes: F〇 [I, F2H and F3H) 〇 [0035] Please refer to Figure 2 for a table 2000 is used to describe how the instruction 211 of the instruction set architecture corresponds to the bit value of an 8-bit operation code byte 102 in the instruction format of FIG. Table 200 presents an example of an 8-bit opcode in Figure 200, which associates up to 256 values of an 8-bit opcode item 1 02 with the corresponding microprocessor opcode instruction 2 〇1. Table 200 maps a specific value of the different code item 1Q2, such as Q2H, to a corresponding operation code instruction 2101 (that is, instruction 1022 1). In the example of the χ86 opcode diagram, as is well known in the art, the opcode value 丨 4 is mapped to the χ86 Add With Carry (ADC) instruction. This instruction directly converts an 8-bit The (immediate) operand is added to the embedded value in the architecture register AL. Those skilled in this field will also find that the above-mentioned x86 preamble 101 (ie, 66H, 67H, 0FH, F0H, F2H, and F3H) is only the value of the operation code 2 0, which is in different contexts , Specifies that a particular schema extension is to be applied to the operation specified by the subsequent opcode item 丨 0 2.

Page 16 1237773 V. Description of the invention (12) For example, adding the preamble OFH before the opcode 14H (normally, the aforementioned ADC opcode) will cause the x86 processor to perform a "decompression and insertion low" Compressed single-precision floating-point value "(Unpack and Interleave

Low Packed Single-Precision Floating-Point

Values) operation instead of the original ADC operation. Such features as described in the example 6 are partially enabled in modern microprocessors. The instruction translation logic in the microprocessing benefit is to sequentially interpret an item 100 of an instruction 101 to 103. Therefore, in the past, the use of specific opcode values as the preamble 101 in the instruction set architecture allowed microprocessor designers to incorporate many advanced architectural features into the design of microprocessors compatible with legacy software without It will bring negative execution to old programs that do not use those specific opcode states. For example, an old program that has not used the χ86 opcode 0FH can still be processed on today's X 8 6 micro processor 5 |; Product ^ ^ With the new application of / k, with the prefix 101, you can use many new calculations, conditional move operations, and more. Qixi Beibei (SIMD) operation code [): 6 ", regardless of the past, by specifying the available (ie redundant-Geweiyupai) operation code value 2 001 as Yu 丨 Xiyu: ¾ Hecai Diary / index 1 0 1 or escape into Shanghai, 入 i ”,, (also known as architecture characteristics, instruction set architecture 100 has been provided for V straight 2 architecture characteristics, but many when all available values are assigned as P military transport The code value should be specified in a structured manner. At this time, there is no remaining code I code entry item 1 0 2 or preamble item j 0 code difference value can be used to incorporate new features. 1223773 V. Description of the invention (13 ) = Heavy problems exist in many of today's microprocessor architectures, thus forcing programmers to choose between adding architectural features and retaining compatibility with legacy programs. [0037] It is worth noting that The instruction 201 shown in Figure 2 is generalized * (that is, 124, 186), rather than specifically referring to actual differences (such as carry accumulation, subtraction, mutual exclusion, or). This is because, In some different mystery processing architectures, the fully occupied operation code diagram 2000 has been incorporated into the possibility of newer progress in architecture. Excluded. Although the = in the example in Figure 2 refers to the 8-bit opcode item 102, those skilled in the art will still ship the specific size of the different code 1G2 'except as a special case to discuss the operation of occupancy. The problem caused by the code structure 200 is not related to other aspects. Therefore, a fully occupied 6-bit opcode map will have 64 opcodes / preambles that can be architecturally specified. It will not be able to provide usable / excessive opcode values for expansion. [0 0 3 8] Another alternative is not to completely discard the original instruction set, and use a new format 丨 00 and opcode figure 2〇 〇 instead, but only a part of the existing operation code 20 1, replaced by a new instruction meaning, such as. With this mixed technology, the microprocessor can be alone and early,】 of the two modes κ at first: The old code 40H-4FH in Langzhong still has rules to interpret, or operates in another improved operating mode (enhanced mode). At this time, the operation code 40h_4fh is based on the enhanced architecture: To interpret. This technology does allow designers to Shortcomings still exist, because the microprocessor can not perform any page = in the first 181,223,773

V. Description of the invention (14) Application code for 40H-4FH. Therefore, from the standpoint of preserving legacy software compatibility, technologies that are compatible with legacy software / enhancement models are not the best choice. [0 0 39] However, for the instruction set 20, where the opcode space is completely occupied, and the space covers all applications that run on microprocessors that meet the old specifications, the inventor of this case has noticed that the operations The use of code 2 01 'and they also observed that although some instructions 2 02 are architecturally specified, they are not used in applications that can be executed by a microprocessor. The instruction I F 1 2 0 2 described in FIG. 2 is an example of this phenomenon. In fact, the same opcode value 20 2 (ie F1H) is mapped to a valid instruction 202 that is not used in the 乂 86 instruction set architecture. Although the unused χ86 instruction 202 is a valid χ86 instruction 202 'which instructs a architecturally specified operation to be performed on a χ86 microprocessor, it is not used on any modern χ86 microprocessor. Running applications. This special χ86 instruction 202 is called the In Circuit Emulation Break Point (that is, the ICE BKPT 'opcode value is F1H). It was previously used exclusively for a type that no longer exists. Microprocessor simulation device. ICE Βκρτ 202 has never been used in applications other than in-circuit simulators. The in-circuit analog devices that used ICE BKPT 202 are gone. Therefore, in the case of x86, 'the inventor of the present case has found a sample-like tool within a completely occupied instruction set architecture 200,' by using a valid but unused computing horse 202 to allow the processor to be in the microprocessor at noon. The design incorporates advanced architecture features without sacrificing the compatibility of legacy software. In a fully occupied instruction / architecture 200 ’, the present invention utilizes an architecturally specified but unused

Page 19, 1237773 V. Description of the invention (15) The calculation code 2 0 2 is used as an index mark to indicate the following ~ code, so the microprocessor designer is allowed to designate up to 11 bits of haiku features. Incorporated into the design of the microprocessor, while ensuring the complete compatibility of the latest development of the frame. /, 4 and all the old software [0040] The present invention allows a programmer to allow an extended instruction by providing an η-bit extended fixed element preamble to use the preamble mark / extended preamble to check forbidden fingers. From the concept of extracting codes, because of this process, it is specified that the corresponding storage check should be prohibited. In the case of the second embodiment, the extended instruction and the specific number thereafter refer to the person's other physical microprocessor's storage inspection mechanism. This invention is now discussed. ^ ", Figures 2 to 10 [004 1] Please refer to Figure 3, which is a block diagram of the extended instruction grid 300 of the present invention. It is very similar to the formula 100 discussed in Figure 1 / the extended instruction The format 300 has a variable number of command items 30-305, and each item is set to a specific value, which together constitutes a specific instruction 300 of the microprocessor. The specific instruction 300 instructs the microprocessor to execute a Specific operations, such as ^ adding two operands, or moving an operand from memory to a temporary register of a microprocessor. Generally speaking, the operation code item 30 of the instruction 300 specifies the desired The execution of the special transport nose 'and the selected address designation meta-item 3 03 is located after the operation code 3 002' to specify additional information related to the specific operation, such as how to perform the operation, temporary storage of the operand Device, direct and indirect data for calculating the memory address of the source / result operand, etc. The instruction format 300 also allows the programmer to add a preamble item 301 before an operation code 302. In operation code 30 2 Prefix items when the specified specific operation is executed

V. Description of the invention (16) 3 0 1 is used to indicate whether or not | 00421 Miao Z ΐ has some architectural features. L 0 042] However, the extension of the present invention refers to a superset of format 100, and In the figure on the right, the instructions 304 and 305 can be selectively used as instruction extension items. There are two additional items, and all the remaining items in the extension instruction 300 are juxtaposed. A format and 305 are extension instructions 300. Two. The two additional items determine whether to prohibit or exclude the extended instruction. Let the clerk refer to 304 and 305 as an extended instruction_ Ercun check. Select item code 305. The extended instruction = 1 before the extended storage check is prohibited According to the operation code specified by the architecture. In another episode, another instruction mark 304 ′, or escape mark 304, is indicated by the extended logic. The extended preamble 304 follows the microprocessor, and is falsely called. The extended feature designation element 305, 300, M ^ / 〇 / Λ ^ 〇; ^ ^ ^ ^ ^ A corresponding part of the extended instruction 300 3001_3〇3 and out = 3 ^ 04 indicate the operation to be performed by the processor. The storage inspection prohibits pointing to the pre-code 305 if it is slightly extended, then it is designated to be executed. Operation " Storage inspection of 70, or extension 300. The microprocessor 'two strength Z = performs extended instruction calculation, but the operation is to exclude any internal extension: the order logic executes the operation [... called here The storage selection check of the invention 7 is summarized. An extended instruction is transmitted monthly: the operation that can be performed by the instruction set of the selector, the ψ and j centers are deducted—based on the existing microprocessing check. The The extended instruction includes the existing finger 1: Excluded storage and inspection of the 7 episodes of the operation code / instruction 304 of which 1223773 5. One of the invention description (17) and an η-bit extension before the order as an index 304, To indicate the finger j 5: the selected operation code / finger (that is, it specifies the microprocessor frame 7 〇 1 extended feature instruction 300 characteristic preamble 30 5 indicates the extension to be stopped), and In the n-bit embodiment, the storage check of the preamble 305 and two is extended. In a specific implementation of the size of a single instruction and a maximum of 255 subsequent instructions, you can specify that the storage of this instruction and n subsequent instructions is prohibited. Check 'or specify that the remaining bits of the prefix code 30 5 are referred to ^ ^ plus the eight-bit extension In the embodiment of the present invention, at most, it can be used to refer to the characteristics of the cup; the extension feature. There must be more than 2η storage inspections before the η bit, and the formula is "11 various combinations of other inspection features-only storage 9 Now referring to FIG. 4 ', a table 400 shows how, according to the present invention, more than the storage check button is mapped to the 8-bit extended logical state of the bit. Similar to the figure = only the table 400 in FIG. 4 presents an 8-bit丄 ::!: An example of the difference code map 20, JL gland ^^ 4, and an example of the extension code map 400, which has a maximum of 6 values for an 8-bit extension preamble item 305. ]: It is sold by Lti. In the microprocessor with specifications, the storage check corresponding to some instructions = 401 (such as E34, E4D, etc.). The specific implementation of the one-to-one = check J Mao Ming's 8-bit extended feature preamble 3005 is provided for the storage of the check level = 401 (ie, E00-EFF) for the instruction level control, these storage bans 401 The current x86 instruction set architecture cannot be specified separately. Huanyi [0 0 4 5] The extended feature 4 〇1 shown in FIG. 4 is expressed in a general way, and does not specifically refer to the actual feature. This is because the technology of the present invention can be used for various different architecture extensions. Item 401 is related to a specific instruction set architecture. Those skilled in the art will find that there are many different architectural features 401, of which one is on page 22 1223773. V. Description of the invention (18) These are mentioned above, and can be escaped as described here. 3 〇4 / extended preamble 305 technology incorporates it into an existing instruction set. The eight-bit preamble embodiment of FIG. 4 provides a maximum of 256 different features 401, and an n-bit preamble embodiment has a stylized selection of up to 2n different features 401. [0046] Please refer to FIG. 5, which is a block diagram illustrating a pipelined microprocessor 500 for performing selective storage check prohibition operation according to the present invention. Microprocessor 5 0 0 has three distinct types of stages: fetch, fetch logic 5G1, fetch from external memory M3 k, so the fetched instructions are sent to the extended prefetch logic pre fetch loglc 5) 2. The extended prefetch logic 502 is sent to the storage check, and is configured to detect whether it has the instructions as shown in Figure 3 ^ 2 to synchronize in the foregoing manner; the heart cache memory 504 is sent Enter an instruction and take it from the deduction 7 queue) 505 'for-access logic 506 access. This transfer === is connected to a micro-instruction queue 508, and its package and series 506 are coupled at the stage-the execution logic-the second; = [0047] According to the present invention, logic 51. . The memory 503 fetches the formatting instructions and edits them from the external logic 502. The extended prefetch logic 502 executes 7k into the extended prefetch instruction. The instruction is subject to a suspended storage event at the back of the pipeline and f is sent to the input action. If an extension of the present invention is detected, a synchronization is initiated 5.2. The extension instruction is allowed to prefetch logic 504 and the instruction queue 505 without going through the material inspection. —That is, the instructions sent to the instruction fetch are executed in the order

Page 23, 1237773 V. Explanation of the invention (19) Send "Lingzi 5005". Then from the instruction symbol 5 to the transfer logic 506. The translation logic 50 sends the corresponding micro-instruction sequence without any instructions,-♦ The instruction entered by t is translated into a specified operation. Mind; the micro processor 501 to execute these instructions has an extension of the preamble mark ^ 8, and the extension logic 507 detects those translations with only the preamble. Action :: 4: The 2nd extended storage check forbidden series 507 is configured as _ and its value is F1H only: Medium, extended translation logic of ICE: βΚΡΤ opcode. Extended J is set up, which is χ8θ 50 In 6, it is designated to remove the% extension; ^^ booths are provided in the micro-instruction queue to check the inventory. Other extended translation logic chest: two fixed number of instructions 4: ί: stop the present invention-the first-instruction and Follow-up-⑽ [〇 乂 8] micro-instruction from micro-instruction queue 5 08 is sent to the execution logic scheduling logic 510 configured to execute all the instructions in the front section of the micro-finger official line 1P position to check if it is different Project address: If the destination address of a suspended storage operation matches the IP position of a previous stage, and the previous stage of the instruction The micro instruction block did not specify that the storage check should be prohibited, and the extended execution logic 510 empties the pipeline up to the previous stage and allows the suspended storage operation to be written into its negative material. After the storage event is completed, it is refilled Pipeline. However, 'if the extended microinstruction field of the previous stage of the instruction specifies that storage checking is prohibited, the extended execution logic 5 1 0 will exclude the pipeline's emptying action. Therefore, tagged instructions are allowed to execute through the pipeline' Does not cause the same pipeline due to a subsequent storage event

Page 24 1223773 V. Description of the invention (20) It is emptied and refilled in steps. [0 0 4 9] Those skilled in the art will find that the microprocessor 500 shown in FIG. 5 is a simplified result of a modern pipelined microprocessor 50. In fact, modern pipelined microprocessor 500 may contain up to 20 to 30 different pipeline stages. However, these stages can be broadly classified into the three stages shown in the block diagram. Therefore, the block diagram 500 of FIG. 5 can be used to point out the necessary elements required for the embodiment of the present invention. For brevity, extraneous components in the microprocessor 500 are not shown and are not discussed. [0 0 5 0] Please refer to FIG. 6, which is an exemplary embodiment of an extended preamble 6 0 0 used in a microprocessor to designate that the related storage check of an extended instruction is to be prohibited. Illustration. The storage check prohibits the prefix code of 6 octets in size, and includes a banned stop of 601. In a specific embodiment, prohibition of blocking 601 specifies that related storage checks of the extended instruction are to be excluded. Another specific embodiment includes a prohibited stop that can specify that the extended instruction and subsequent storage checks of up to 255 instructions are to be excluded. The number of inspection prohibitions is indicated by the prohibition of stops. [οογ1] Please refer to FIG. 7, which is a detailed block diagram of the extraction of slave logic 700 in the microprocessor of FIG. 5. The extraction stage logic 700 includes a prefetch buffer 704 coupled to the external § memory 705. The prefetch buffer 704 = prefetch instruction to-extended prefetch logic 7Q6. The extended prefetch logic 706 has an extraction controller 709, which is coupled to a su_ss detector 707 via a disable signal 708. The extraction controller 709 is also coupled to a machine-specific register with an extension field 703 (niachine

1223773

specific register) 702. The forbidden sequence detector 707 provides a control signal SUPP to a pending store evaluation logic 710. The suspended storage evaluation logic 710 accesses a plurality of registers 7 1 including the destination address of the suspended storage event. In one embodiment, the registers 711 are referred to as a lower linear instruction pointer (LIP) chain. The register 711 is a storage address in the pipeline (such as a composite write buffer (wri te ^ combine buffer), write back buffer (write back buffer, etc.)) through the destination address provided by the bus 71 5 To update. Suspend the health evaluation logic 7 1 0 coupled to a pipeline 1ine synchronization logic 712 via the SMC Η IT signal. The pipeline synchronization logic 71 2 k provides a control signal ST ALL 71 3 to the pipeline control logic (not shown in the figure). The extended prefetch logic 706 sends the fetched instruction to a fill buffer (fi 1 1 buffer) 714, which is coupled to an instruction memory 716. f. Fetching Stone [0052] In actual operation, when the cache line is fetched from the memory 705, it is sent to the prefetch buffer 704. Extend the prefetch logic 706 to extract the contents of the cache, and check the destination address of the sent instruction against the lower Llp chain of the register 711 to suspend the storage operation. If the ^ evaluation logic 710 determines that the IP address of a prefetch instruction matches the pause storage target in the temporary register 7m ^, the SMC Η IT signal is set to true: therefore, the pipeline synchronization logic signal 713 is set to true, And start a tube to synchronize events. Therefore, the pipeline is suspended until the temporary storage of the data is written into the memory, and then the prefetch instruction re- =

1223773 V. Description of the invention (22) Take and allow execution into the pipeline. If the IP address of the prefetch instruction does not match any storage target, the extended prefetch logic 706 sends the prefetch instruction to the fill buffer Is 71 4 ′ and finally to the instruction cache memory 7 丨 6. [0053] Forbidden sequence debt tester 707 also from the prefetch buffer? The content of the cache line of 〇4 is evaluated to detect whether it contains an escape tag / extended preamble sequence indicating that the storage check is to be stopped. If this sequence is detected, the supp signal is set to true to indicate that the evaluation logic is temporarily suspended? 10 Do not evaluate the lower LIP key register 711, and allow the corresponding instruction to be fed into the fill buffer 714. [0054] During the start-up of the microprocessor, the state of the extended bit 703 in the machine specific temporary 702 is determined by the signal power-up state) 701 to indicate that the specific microprocessor can handle the invention. Delay order to prohibit microprocessor storage inspection. In the specific embodiment, the signal 701 is derived from a feature control register s (not shown in the figure), and the feature control register reads — the fuse array that has been configured at that time. (Not shown = The specific register 702 sends the status of the extended feature block 703 = 709 and other logic described below. The extraction control logic 709 determines whether to obtain the cache line from the prefetch buffer 704 The data is evaluated to detect and store the inspection prohibition sequence. Providing such a control feature allows to supervise the "application (such as BIOS) enabling / disabling the extension execution of the microprocessor. If the extension feature is disabled, it has the The finger selected as the ^ state of the extended feature mark will be checked like any other command: Extraction controller 7Q9 u ^ Store event 9 Day sequence detector 707 is not forbidden to borrow

1223773 V. Description of the Invention (23) The detection of the extended sequence is disabled by setting the disabling signal 708 to true. [0 0 5 5] Now refer to FIG. 8, which is a translation of the microprocessor in FIG. A detailed block diagram of the logic 8GO. The logic stage of the translation stage has an instruction buffer 804. According to the present invention, it provides extended instructions to the beep logic, and the logic / 805 system is easily connected to a machine with an extended feature shelf 803. This is described in the previous section of Figure 7. The translation logic 805 has a translation controller 806, which provides a disabling signal 807 to an escape instruction detector 808 and an extended preamble translator 809. The escape finger 808 is coupled to the extended translator 809 and an instruction translator 810. The extended translation logic 809 and the instruction translation logic 810 access a control read-only memory (ROM) 811, which stores a model sequence of Ganwei instructions corresponding to some extended instructions. Translation logic 805 also includes a "microinstruction" rush state 812, which has an opcode extension block 813, a microcode block 814, a destination block 815, a source block 816, and a displacement field 8 1 7 〇 [0056] In actual operation, during the start-up of the microprocessor, the state of the extended field m in the machine 802 is activated by a signal = 809 to determine whether the particular microprocessor can Translating blood executes the extended instruction of m, as described in the previous section of Figure 8. The machine-specific register 802 sends the state of the extended feature stop 803 to the translation controller 806. The translation control logic 806 decides whether to obtain the extended translation rule obtained from the instruction buffer 804 or use the translation rule to perform translation. ^ 二 ^ If the feature is disabled, the code with the operation code selected as the extended feature mark can be translated according to the conventional translation rules. In —χ86's 1223773 V. Invention Description (24), the opcode state F 1 选取 is selected as a flag. Under the conventional translation rule, encountering F1H will cause an illegal instruction exception (exceptioon). If extended translation is disabled, the instruction translator 8 10 will translate all incoming instructions' and configure all the stops 8 13 to 817 of the micro instruction 812. However, under the extended translation rule, if a tag is encountered, it will be detected by the escape instruction detector 8 0 8. The escape instruction detector 8 08 will instruct the extended preamble translator 80 9 to translate the extended preamble portion of the extended instruction according to the extended translation rule, and configure the operation code extension field 8 丨 3. It is instructed to prohibit the storage check of the micro instruction sequence corresponding to the extended instruction. The instruction translator 81 0 will translate the rest of the extended instruction, and perform operations on the micro-operation code field 8 1 2 of the micro instruction 8 j 2, the source stop 8 1 6, the destination stop 8 1 5 and the displacement stop 817. configuration. Certain specific instructions will cause access to control ROM 811 to obtain the corresponding microinstruction sequence template. The configured micro-instruction 8 1 2 is sent to a micro-instruction queue (not shown in the figure) for subsequent execution by the processor. ° [0 0 57] Please refer to FIG. 9, which is a block diagram of the execution stage logic 900 in the microprocessor of FIG. 5. The execution stage logic 900 has an extended store logic 908, which is coupled to a data cache memory 9 11 and a bus unit 9 1 2. The bus unit 9 1 2 is used for the memory access operation on the memory bus 6 (not shown) of the memory bus 1 (not shown). According to the present invention, the extended storage logic 908 extends the microinstruction buffer g 〇1 from one of the previous stages of the microprocessor to receive microinstructions, receives a data operand from the data buffer 90 2, and from the address buffer 903 Receives a destination address operand. Extended storage logic 908 contains a storage

Page 29 1223773 V. Description of the invention (25) " Memory check logic 90 9 which is respectively coupled to a plurality of linear IP registers 905 ′ -pipeline synchronization logic 914 (via Ιρ Ηΐτ signal) and a plurality of storage buffers 9 1 0. These linear registers ρ0 are also referred to as higher Lj ρ chains, and each buffer 905 has an IP block 906 and a storage check prohibition = 1 bit 9 0 7 . The content of the lower IP chain 905 includes the virtual address of Cai 7 located in the previous pipeline stage. These contents are sequentially sent from the previous pipeline stage to the higher lip chain 905 via the bus 904. ☆ [0 0 58] In actual operation, according to the instruction of the extended micro-finger = buffer 9 1 micro instruction in the extended storage logic 809, the operation π is written into the cache memory 9 through the bus unit g 丨 2. 11 or external memory. As far as the write / store operation shown in the extended microinstruction is concerned, the storage check logic 909 receives the destination address information required for the operation from the address buffer 903, and receives the user's stored information from the buffer 902. Operand. The storage check logic 109 then enters the address and data into the storage buffer 910, and simultaneously evaluates the contents of the higher LIp chain 905 to determine whether there is an instruction in the pipeline, its virtual 1? Address and the storage suspension event. The destination address matches. If a matching virtual IP address 906 is found in the higher up chain 905, the storage check logic 109 checks the related storage check forbidden field 907. If the contents of the relevant stop 907 indicate that storage inspections are to be prohibited, the storage inspection logic 9 0 9 allows the pipeline to continue to operate without interruption. The content of the storage buffer 9 10 is in accordance with the memory characteristics assigned to the storage event, and is written into the cache memory 911 or the external memory through the bus unit 912, wherein the memory characteristics are determined by a specific processor. (Pr〇cess〇r 一 ~ speciflc) The architecture is generally specified. However, if the storage check logic 909 decides not to prohibit a storage check for a matching virtual IP address 906, then

1223773 V. Description of the invention (26) Η IT signal will be set to true, in order to recite the event of m μ emptying / refilling, ^ Event: =! Logic 914 starts-pipeline stage of the pipeline IP address until After the detection of the coincident virtual FLUSH signal 915, the pipeline n = step logic 914, and then through the extended micro-instruction, a tube event is generated. As the instructions are processed, the register 913 is ordered. ,, "脉 (not shown) is the same as #, sent to Weiqiu Qiu Til5 9)]: the important technical features of the present invention (as shown in Figures 3 to 9 = Si is specified by the use, but the actual Supply-a kind of programmable mark;: ννΛ person can be in one, the preamble is used to indicate the combination of a person / person code. In the specific embodiment, the storage check of the extended instruction .: 2 Yes The specification of the microprocessor only prohibits the amount of the microprocessor from prohibiting the extended instruction and the follow-up: ί: 2 check. When the extended instruction is fetched, this extended instruction is sent to this place; "Code combination" and allows to suspend the private cache memory stored in Sedu, * one place, instead of comparing with the madness of the invention Φ 1: m / ding any storage check. Extended translation logic is extended through this extension The operation code extension field in the ΐίΐ order indicates that the storage check of the internal UTF order sequence of the bit is to be prohibited. The operation code extension prevents the storage check of the spring-grade fairy in the higher lip chain, such as storage d : "When storing events, the synchronization will not be started for the double _ and extended instructions that have been specified. Event 2: Compilation 60: Because of / b, the present invention gives programmers and / or automated code code (Automated code compiUti〇n heart) (⑶) a

1223773 V. Description of the invention (27) The mechanism can be used to instruct a microprocessor that conforms to the old specifications to prohibit the storage check of a single instruction or instruction group, thereby overcoming the errors caused by the father of the code and data in the same cache line. The pipeline synchronizes the emptying problem and provides a more flexible tool to implement an algorithm containing a self-correcting code. [0 0 6 1] Now refer to FIG. The operation flow chart of the method for extracting, translating, and executing the instruction of the staff to replace the instructions of the storage inspection process in the microprocessor at the instruction level. The flow starts at block 1 0 2 ', where one of the programs configured with extended feature instructions is sent to the microprocessor. The flow then proceeds to block 104. [0062] In block 1004, the next instruction is fetched to enter the pipeline of the microprocessing mushroom. The flow then proceeds to decision block 1 Q 08. [0063] In decision block 1008, the instructions extracted in block 1004 are evaluated to determine whether an extended escape code-extended preamble sequence is included. In an embodiment of X86, the evaluation is used to detect an operation code value Fl (ice BKPT) of a specified meta-item for a storage prohibition check thereafter. If the extended escape code and subsequent items are detected, the flow proceeds to block 1010. You Weizhen measured the far-extended escape code and the extended designation element, and the flow proceeds to block 106. [0 064] In block 1006, the instruction fetched in block 1004 is synchronized with the pause storage event. The target of the storage suspend event is evaluated to determine whether it matches the virtual address of the fetch instruction. If they match, the pipeline is suspended 'and allows those suspended storage events to complete the action. Then, the fetch instruction is re-fetched from the external memory, and the flow

Page 32 1223773

5. Description of the invention (28) proceeds to block 102. [0 0 6 5] In block ι010, the extended preamble portion of the extended instruction is decoded to specify that when a corresponding microinstruction sequence passes the pipeline, the storage check of the microinstruction sequence is prohibited. The prohibition of the storage check is specified by the extended micro-operation code field of the present invention. The flow then proceeds to 1012. Ghost [0 066] In block 1012, all the rest of the instruction is translated to determine a specified operation, the location of the register operand, the memory position ^ the specified element, and according to the existing microprocessor instruction set, Use of pre-existing architectural features specified by the preamble. The flow then proceeds to block 104. [0067] In block 1 ο 14, an extended microinstruction sequence is grouped to specify the specified operation and its corresponding operation code extension term. The process then proceeds to block 1 0 1 6. # [0 068] In block 1016, a plurality of microinstruction sequences, the first of which includes the extended microinstruction sequence configured in block 1014, is sent to a microinstruction queue according to the order of the translation device, and is processed by the micro器 Executive. The flow proceeds to decision block 1018. [0 069] In decision block 1018, the next microinstruction sequence is extracted by one of the extended execution logics of the present invention. The extended execution logic evaluates the next microinstruction sequence to determine if a storage event is specified. If,, and μ exist, the flow proceeds to block 1 028. If so, the process proceeds to [0070] In block 1020, since a storage event has been specified, the storage check logic queries one of the higher L IP chains of the present invention. The process continues

1223773 V. Description of the invention (29) to decision block 1 022. [0 071] An evaluation is performed in judgment block 1022 to determine whether the destination address of the storage event matches any virtual IP address of the instruction in the pipeline after the storage event. If a matching virtual IP address is found in the LIP chain, the flow proceeds to decision block 1 024. If not found, the process proceeds to block 1 028. '[0 0 7 2] In judgment block 1 0 24, evaluate the relevant storage inspection prohibition stop of the corresponding virtual IP address to determine whether to prohibit the storage inspection of the relevant instruction. If yes, the flow proceeds to block 028, if not, the flow proceeds to block 1 026. '[0 073] In block 1026, the extended execution logic states that the related instruction requires a pipeline synchronization event. The flow then proceeds to block 1028. "[00 74] In block 1 0 28, the operation specified by the next microinstruction sequence is executed. The flow then proceeds to block 1 030. [0075] In block 1030, the method is completed .... [0076] Although the present invention and its objects, features, and advantages have been described in detail, other embodiments may also be included within the scope of the present invention. For example, the present invention has been described in terms of the following techniques: using a fully occupied instruction set The status of unused opcodes is used as a banner to indicate the extended feature preamble of ^. However, the scope of the present invention is not limited to the fully occupied instruction set architecture or unused instructions in any aspect. , Or a single tag. Conversely, the present invention encompasses an incompletely mapped instruction set, an embodiment with used opcodes, and the use of more than one reference ^^^

1223773 V. Description of the Invention (30)-Examples. For example, consider an unused operating system. A specific embodiment of the present invention includes the state of the operation code of the instruction set selected by the two daggers, and the selection criteria is based on market factors; the output embodiment includes the use of one of the operation codes, such as the following, , 疋 Continuous appearance of another code state 7FH. Therefore, if a mark is used as a mark, then a sequence of marks followed by an n-bit ^^^^ quality is to allow the programmer / compiler to use an existing microprocessor instruction = code [= allow Only check the storage of individual instructions or instruction groups. / 、 彳 日 疋 要 禁 [0077] In addition, although the above is the use of the present invention and its objectives, features, and advantages, familiar with this field " dry ,,, and f solutions, the scope of the present invention is not limited to Microprocessor frame :::: Programmable devices with a form, such as signal processors, industrial controllers, arrays, etc. Pinghuan and other similar equipment • No = two: the one who is only the preferred embodiment of the present invention, the equivalent changes made in the scope of the patent :: within the scope of the application of the present invention 'I would like to blame the reviewer , And pray for the accuracy, it is for the benefit. Page 35 1223773 Simple illustration of the diagram [Simplified illustration of the diagram [0020] I have the following to say [0 02 1] Block diagram; [0022] Refers to how the bit logic [0023] [0024] Architectural features such as logical state; [0025] Control one tube [0026] To exclude storage [0027] block diagram [00〇28] block diagram [00〇29] block diagram [0030] The foregoing and other objects, features, and advantages of the present invention related to the decree will be better understood after clearing and accompanying drawings: Figure 1 is a microprocessing of a related technology Figure 1 of the device instruction format is a table describing the state of an instruction set structure corresponding to an 8-bit opcode byte in the instruction format of Figure 1. Figure 2 is a block of the extended instruction format of the present invention. Figure 4 is a table showing how the extension corresponds to Figure 5 of an embodiment of an 8-bit extended preamble is a block diagram of the use of the selective storage checking of the present invention to detect a dry-line microprocessor; Figure 6 is a microprocessor of the present invention. The extended preamble used to check-specific embodiment block diagram; 疋; Figure 7 is the details of the extraction stage logic in the ® five microprocessor; Figure 8 is the details of the translation stage logic in the five microprocessor ; Figure 9 and Figure 5 is a detailed flowchart of the execution stage logic in the microprocessor as a flowchart of the method used in the microprocessor for storage inspection in the present invention. More than

Page 36 1237773 Simple illustration of the drawing Description of the drawing number: 100-instruction format 1 0 1 -preamble 1 0 2 -opcode 1 0 3 -address designator 2 0 0-8-bit opcode picture 2 0 1 -Operation code value 20 2-Operation code F1H 3 0 0 -Extended instruction format 3 0 1 -Preamble 3 0 2 -Operation code 3 0 3 -Address designation element 3 0 4 -Extended instruction mark 3 0 5 -Extended Preamble 4 0 0-8-bit preamble diagram 401-Architecture characteristics 5 0 0-Pipelined microprocessor 501-Fetch logic 502-Extended prefetch logic 5 0 3-External memory 504-Instruction cache memory Body 50 5-instruction queue 506-translation logic 507-extended translation logic 508-microinstruction queue 509-execution logic 510-extended execution logic 6 0 0-extended preamble 601-prohibited field 7 0 0-extraction stage Logic 7 0 1-Enable status signal 702-Machine specific register 7 0 3-Extended feature field 704-Prefetch buffer 70 5- External memory 706-Extended prefetch logic 70 7-Disable sequence detector 7 0 8-Disable signal 70 9-Extraction controller 710-Suspend storage evaluation logic 7 11-Register 712-Pipeline synchronization logic 713-STALL · Signal

Page 37 1223773 Brief description of the diagram 714-Fill the buffer 715-Bus 716-Instruction cache memory 8 0 0-Translation stage logic 801-Start status signal 802-Machine-specific register 803-Extended feature field 804 -Instruction buffer 80 5-Translation logic 80 6-Translation controller 807-Disable signal 808-Escape command detector 80 9-Extended preamble translator 810-Instruction translator 811-Control read-only memory 812 -Micro-instruction buffer 813- Opcode extension entry bad bit 814-Micro-op code field 815- Destination bad bit 816-Source field 817- Offset field 9 0 0-Run-time logic 901- Data cache memory 9 0 2-Data buffer 90 3-Address buffer 904-Bus 9 0 5-Linear IP register 9 0 6-IP field 90 7-Storage check prohibited shelf 908-Extended storage logic 9 0 9- Storage check logic 910- Storage buffer 911- Data cache memory 912-Bus unit 913-Micro-instruction register 914-Pipeline synchronization logic 915-FLUSH signal 1000 ~ 1 0 3 0-Method for disabling storage check in the microprocessor Operation process

Page 38

Claims (1)

1 Real page change, year 1 jeLI · L # No. 92innQ49_—year—month Yuexiu__ VI. Patent application scope 1 A device that can perform instruction-level storage inspection control in a microprocessor, including: an extraction logic To receive an extended instruction, where the extended instruction includes: • an extended preamble, which is used to specify that the storage check of the extended instruction is prohibited; and an extended preamble tag, which is another in the existing instruction set Architecture opcode The fetch logic excludes the storage check of the suspended storage event related to the extended instruction; and a translation logic coupled to the fetch logic for translating the extended instruction into a micro-instruction sequence to instruct the microprocessor on a specified When the calculation is executed, the storage check is excluded. 2. The device according to item 1 of the scope of patent application, wherein the extended instruction further includes an instruction item of the existing instruction set. 3. The device as described in item 2 of the scope of patent application, wherein the instruction item specifies the specified operation to be performed by the microprocessor, and when the specified operation is performed, a storage check will be performed separately. 4. The device according to item 3 of the scope of patent application, wherein if a storage event is detected before a specific instruction is completed and executed, and a destination address of the storage event matches the position of the specific instruction, a The storage check logic will additionally clear the specific instruction and all subsequent & fetched instructions from the microprocessor, and after the storage event is completed, re-fetch the instruction from the specific instruction I position. 丄 W73 = The device described in the scope of the patent application, wherein the extraction logic includes eleven pre-fetch logic, and is configured to detect the extended preamble and the extended small two code mark, and enable the extended instruction in You do not need to check this: ^ guilty guilty / two 孖 | 6 f month, proceed to the translation logic. The device described in item 5 of the patent scope, one of which temporarily suspends the storage of the judges and evaluates the previous instructions in the microprocessor pipeline to detect the second temporary storage event, and if it is found Head 2 = the address matches the location of an fetched instruction, the storage check logic ^ The fetch instruction is executed to allow the destination address to be updated. • The device described in claim 1 of the patent scope, wherein the extension includes 8 bits. Code The device as described in item 1 of Shenyan's patent scope, wherein the extension pre-contains: Qiao Yi prohibition of stop, used to specify that related inspection of the extension instruction is prohibited. = 9 · The device according to item 1 of the scope of the patent application, wherein the extension includes a prohibition stop to specify that the related storage inspection of the extension instruction and a specified number of subsequent instructions is to be prohibited. I 〇 The device described in item 1 of the scope of patent application, wherein the existing instruction set includes an x86 instruction set. II. The device according to item 1 of the scope of patent application, wherein the extended preamble mark includes the operation code FI (ICE ΒΚΡΤ) of the X86 instruction set. Page 40 1223773 _Case No. 92100942 July ^ _iii_ VI. Patent application scope 1 2. The device described in item 1 of the patent application scope, wherein the translation logic includes: an escape instruction detection logic for Detect the extended preamble label I; an instruction translation logic to determine the specified operation and specify the specified operation in the microinstruction sequence; and an extended translation logic coupled to the escape instruction detection The logic and the instruction translation logic are used to specify within the microinstruction sequence, and the storage check is excluded when the specified operation is performed. 1 3. A microprocessor that expands an existing instruction set to selectively disable storage checks in a microprocessor pipeline, including: An extended instruction 'set of complaints specifying that related storage checks for the extended instruction are to be disabled , Where the extended instruction includes one selected operation code of the existing instruction set, followed by an n-bit extended preamble, the selected operation code indicates the extended instruction, and the n-bit extended before A code indicates that storage inspections are prohibited; and A translator is configured to receive the extended instruction, generate a micro-instruction sequence to instruct a microprocessor to perform a specified operation, and exclude the related storage check when the specified operation is performed. 14. The microprocessor according to item 13 of the scope of patent application, wherein the extended instruction further includes: the remaining instruction items, configured to specify the specified operation. 1 5. The microprocessor according to item 13 of the scope of patent application, wherein the pre-n-bit code includes: Page 41 1223773 _Case No. 92100942_July ^ Amendment_ VI. Patent Application Scope A prohibition field is configured to specify that the storage inspection of the extended instruction is prohibited. 16. The microprocessor according to item 13 of the scope of the patent application, wherein the pre-n-bit code includes: a prohibition stop configured to specify that the extended instruction and a specified number of subsequent performance instructions are to be prohibited Storage check. 1 7. The microprocessor according to item 13 of the scope of patent application, wherein the extended preamble of the n-bits includes 8 bits. 1 8. The microprocessor according to item 13 of the scope of patent application, wherein the existing instruction set is a x86 microprocessor instruction set. 19. The microprocessor according to item 13 of the scope of the patent application, wherein the selected operation code includes the ICE ΒΚΡΤ operation code (that is, operation code F1) in the instruction set of the x86 microprocessor. 20. The microprocessor according to item 13 of the scope of patent application, wherein the translator comprises: an escape instruction detector for detecting the selected operation code in the extended instruction; An instruction translator for translating the rest of the extended instruction to determine the designated operation nose, and an extended preamble translator coupled to the escape instruction detector and the instruction translator for translation The n-bit extended preamble designates that the micro-instruction sequence prohibits the storage check. 2 1. The microprocessor described in item 13 of the scope of patent application, further comprising: Page 42 1237773 _Case No. 92100942, July, Amendment_ VI. Scope of patent application-Extended prefetch logic, used to receive the extended instruction from the memory, detect the selected opcode and the n-bit extended before Set the code and allow the extended instruction to be sent to the translator without checking whether the suspended storage event matches the location of the extended instruction. 2 2. —A module for adding storage inspection features of prohibited instructions to an existing instruction set, including: An escape flag, received by an extraction logic, and indicating that the accompanying part of a corresponding instruction specifies what is to be executed An operation, wherein the escape flag is a first operation code in the existing instruction set; A storage check prohibition designated element, coupled to the escape tag, and being one of the accompanying parts, used to specify that storage check is prohibited when the operation is performed; a translation logic, coupled to the extraction logic, For generating a micro-instruction sequence to instruct a microprocessor to perform the operation, and specifying that the storage check is prohibited in the micro-instruction sequence; and an extended execution logic coupled to the translation logic to receive the micro-instruction sequence, This operation is performed without a storage check. 2 3. The module according to item 22 of the scope of patent application, wherein the rest of the accompanying part includes a second operation code for specifying the operation. 2 4. The module according to item 22 of the scope of patent application, wherein the storage inspection prohibition designation element contains 8 bits. 2 5. The module according to item 22 of the scope of patent application, wherein the existing instruction set is the x86 instruction set. 2 6. The module according to item 22 of the scope of patent application, wherein the first operation Page 12 1223773 The code contains the ICE BKPT operation code in the χ86 instruction set (that is, operation code F1). … 2 7 · The module described in item 22 of the scope of patent application, wherein the translation logic includes: an escape mark detection logic 'for detecting the escape mark and instructing the translation action of the accompanying part Need to be based on extended translation conventions; and a decoding logic coupled to the escape tag detection logic to perform instruction translation actions based on the existing instruction set conventions, and execute according to the extended translation conventions The translation of the corresponding instruction enables the operation to be performed in a manner that does not perform a storage check. • A method of expanding an existing instruction set architecture to disable health check at the instruction level, the method includes:-providing an extended instruction, the extended instruction includes an extension mark and:, extending the preamble, wherein the extension mark Is a first opcode item in the Existing Instruction Set Architecture; using the extended preamble to specify that when the extended instruction is executed, the rest of the extended instruction in the jailer storage check specifies one of the operations to be performed; and Relevant storage inspection of the extended instruction is prohibited. 29. The method described in item 28 of the scope of patent application, wherein the specified action includes: ^ using a second opcode item of the existing instruction set architecture to indicate 1223773 --- Cliff No. 92100M2 ------ Six 'Applicable patent scope 30. The method described in item 28 of the patent application scope' wherein the action of providing extended instructions includes using an 8-bit size item to Configure the extended preamble. 3 1 · The method as described in item 28 of the scope of patent application, wherein the action of providing an extended instruction includes taking the first opcode item from the X 8 6 microprocessor ^ command set. 3 2 · The method described in item 28 of the scope of patent application, wherein the action of providing an extended instruction includes selecting an x86 ICE BKPT operation code (that is, operation code F 1) as the extension mark. 3 3 The method as described in item 28 of the scope of patent application, further comprising: translating the extended instruction into a micro instruction sequence, the micro instruction sequence instructs an extended execution logic to perform the operation without performing a storage check. Method 34. The method described in item 33 of the scope of patent application, wherein the action of the transfer instruction includes:; and the code and the extension refer to a translation logic, detecting the extension mark to decode the extension preamble according to the extension translation rule Order the rest to generate the microinstruction sequence. Page 45 1223773 (Patent No. 0921 0094 Patent Amendment Sheet) 801 Ichihachi