TWI247241B - Microprocessor apparatus and method for performing block cipher cryptographic functions - Google Patents

Abstract

The present invention provides an apparatus and method for performing cryptographic operation on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction and execution logic. The cryptographic instruction is received by logic within a processor, wherein said cryptographic instruction prescribes one of the cryptographic operations. The execution logic is coupled to said logic. The execution logic is coupled to said logic. The execution logic performs the one of the cryptographic operations.

Description

1247241

[Description of the Invention] [0001] The present invention filed a provisional case in the United States on April 18, 2003, file number 60/464394 (Docket CNTR.2222), and filed a formal US application on September 29, 2003. No. 10/674057. [Technical field to which the invention pertains] [00 02] The present invention relates to the field of microelectronics, and more particularly to an apparatus and method for encryption in a microprocessor. "[Prior Art] [0003] Running a system of internal or post-production or a computer is unified by the next use or storage interface, which is used in the same way. The operation of the input data program between the stores [0004] is written into the magnetic file in white paper. This execution is the same as the encrypted ones that are compatible with the protection sensitive password compilation license. The software program is the same as the file part of the software. If this can be used as a system for the early years, the system needs to be stored in the system. , Free of the file on the 'use' is the tape that is input when the built-in is black, the application of the printed output is a soft computer application. Or the decryption is now working in the early stage. The printed disc or the file program is connected to the system by the internal movement of the system. The line presents, for the other part of the application can then store the Edict of cognitive input #-acting type. Developed code to compile soft square multiple computers

V. Description of the invention (2) This advantage of sharing information through t. Therefore, the network administration and the data transmission protocol are also relative to each other. Therefore, the network architecture and the operating system share the information provided by them. So far, in addition to the users who can support the data, the function is also very important. For example, there is another network server that is used to get another workbench or his data, and hundreds of other cases, through the Internet to get news and computer software provided by the computer system of its business. Mail, connecting restaurants, airports and other public cards or bank information to buy items, is already used to it: it is important to do the above through the wireless network. The uselessness of i users to protect the transmission of sensitive data has also increased. = : The data that needs to be protected needs to be protected, the identity is stolen, and the long-term disclosure is sent to the public to spam emails. This Lu Yu ρ position bullying and credit card fraud and other electricity is purely unintentional: ^ The motivation behind the Q privacy action is sometimes action. When the relevant units use ~%, it is a well-thought-out cyber-terrorism attack screen and other actions to the H law. Strict implementation of the norms and education of the infringement of computer data. These actions are still unable to successfully eliminate the worry of the intelligence unit::=Government , financial institutions, the military and the use of online banking services turned into a mother to check e-mail at home, [_5] information security most worried about the problem. Provide a specific 2 solution; one of the domain's data is encrypted, and the only Thunder-style protection technique is cryptography. In the type of identification. (^ said nose ~plaintest, cleartext) can not be called 岔文, Clphertext). Convert this article to 1247241

The private sequence of the text is called "encryption" and the procedure for transferring the ciphertext back to the text is called "decrypti". · [0006] In the field of cryptographic compilation, several methods and protocols are opened. If the user does not need to have too many cryptographic compilation knowledge or spend too much effort, the data can be sent out in encrypted form. For different users. In addition to the power of the user, the user usually provides the recipient with a cryptographic key for decryption. The cryptographic key allows the recipient to recover the encrypted data or sometimes provide a conduit for the recipient to obtain unencrypted data. The steps described above are often used to encrypt and decrypt bit-sensitive data through password protection, mathematical algorithms, and encryption and decryption applications. _ [ 0007 ] There are currently many types of algorithms that are applied to the =^ secret of the data. A special algorithm in a certain type (public key plus wide method, one of the RSA Rivest-Shamir-Adelman algorithm classes) uses two keys (〇1^1)1:〇§1^1 )}^(31^7). A public key (Pu^l ic Key) and a private key (private key) are used to encrypt or f secret. According to some public auction algorithms, the recipient's public key is used by the sender to encrypt the data for delivery to the recipient. Because there is a certain mathematical relationship between the public and private keys of ^f, the recipient will use the private record to unlock the received data and restore the original data. Although such encryption algorithms are widely used, they handle encryption and are very slow. Even processing small amounts of data is very slow. There is also a kind of algorithm, called symmetric encryption algorithm, which not only has the confidentiality of the data of the level of the f-class algorithm, but also the speed of execution. The reason why such a different method is called a symmetric encryption algorithm is that it is use

Page 8 1247241 V. INSTRUCTIONS (4) The same set of encryption compiler keys are used for encryption and decryption. At present, the two main types of data encryption algorithms (Single-key cryptographic algorithms: Data Encryption Standard (DES), Triple Data Encryption Standard (Triple Data Encryption Standard, Triple DES) and high-order encryption algorithms are used in public organizations. Advanced Encryption Standard (AES). Because of the protection strength of these shoulder algorithms, the relevant units of the US government now use these three algorithms to keep confidential information. I believe that one or more of these will become in the near future. Standards used in commercial and private transactions. According to these symmetric encryption algorithms, both the text and the ciphertext are cut into segments of certain size for encryption and decryption. For example, the High-Level Encryption Standard (AES) encrypts 128-bit large segments. And use 128_, 192 and 256-b 11s size encryption compiler keys. [〇〇〇8] All symmetric key encryption algorithms (symmetric key will be encrypted in this sub-〇Peration step:: : two f according to the more commonly used symmetric encryption algorithm, key program table, key sche = expansion to the upper number The key '(that is, the compilation of B's knee π 士士 dUle) 'Mother key will be used in the password compilation, the Japanese syllabus will encrypt this paragraph / rrnnnH,. Chu ^ one of the rounds of the operation The result becomes the first-input text. The stem-doorman and the rich-spoken brother take a bite. Enter the two keys to do the operation, and the #^-5 operation uses the first few rounds in the key program table. Became the two,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

Haim Page 9 1247241 V. Invention Description (5) It is called SubByte (or S-box), ShiftRows, MixColums, and round key join (AddRoundKey) ). The step of decoding a ciphertext is actually very similar to encryption. It is to treat the ciphertext as the input value, and the output of the reverse zebu code and the reverse nose 'last*-round is straight every turn. This article. [00 0 9 ] The secondary operations of the Data Encryption Standard (DES) and the Triple Data Encryption Standard (Tr ip 1 e-DES) applications are not the same in small details but they are basically similar to the AES algorithm because They convert the fragment of this article into a ciphertext of a segment in a similar manner. [0 0 1 0 ] All symmetric encryption algorithms encrypt the pattern of multiple consecutive fragment data. These include cipher block chaining mode (CBC), eiectronic code book 'ECB' cipher feedback mode (CFB) and output feedback (0UtpUt feedback mode, OFB). Some of the models require an additional initialization vector to perform the secondary operation, and some add the first set of encrypted ciphertexts to the second set of encrypted operations. If you delve into each cryptographic compilation Each of the sub-term operations in the algorithm and the current symmetric encryption algorithm is beyond the scope of the application of the present invention. For a detailed discussion of the data encryption standard DES and the three-dimensional data encryption standard Triple des, the reader can refer to the Federal Information Processing Standards Publication 46-3 (FI PS-46-3) on January 25, 1999. Federal, November 26, 2001

I round

Page 10 1247241 V. Description of invention (6)

In the Information Processing Standards Publication 197 (F IP S - 1 9 7), there is a discussion of A E S. The above publications are compiled by the National Institute of Standards and Technology (NIST) and are hereby incorporated by reference. In addition to these publications, NIST's Computer Security

The Resource Center (CSRC) website http://csrc.nist· gov/ also provides unit teaching, white papers, toolkits and related articles. [0 0 1 1] Readers of this technology should be aware that there are many software on the computer system that can be used to perform cryptographic compilation (ie, encryption and decryption). In fact, some operating systems (such as Microsoft Windows ,ρ,

Linux) provides direct encryption/decryption services through cryptographic primitives, cryptographic application program interfaces and other similar interfaces. The inventors of the present have discovered that there are many drawbacks in many aspects of computer compiling cryptography. Readers are now looking at Figure 1, which shows these shortcomings, which are discussed below. [0 0 1 2] Figure 1 is a block diagram of the current computer password compilation application. Figure 1 0 0 shows that the first computer 1 0 1 is connected to the local area network 1 〇 5. In addition, there is a second computer connected to the network 105, a network file storage device, a first router 107 or other interface connected to a wide area network (WAN), such as a network. And a wireless router 108, such as a wireless router compliant with the IEEE 802.11 specification. Connected to the other end of the wide area network 110 is a second router 111 for providing an interface to the third computer.

Page 11 1247241 V. INSTRUCTIONS (7) [0013] As mentioned earlier, today's users will need to keep their computer data more and more frequently when using a computer. For example, a user of Computer 1 〇 1 under Jobs" System Control may perform multiple tasks at the same time, and each job requires a password compilation job. The computer 1 (the user of the user needs to perform encryption/decryption (through the operating system service or the operating system) to store a file in the network storage device 106. While the file is being stored, the user may also encrypt the file. The information is passed to the user of the second computer ,2, and this action will also require the application 112 to perform encryption and decryption work. The information transmitted may be instant (eg, instant message) or not instantaneous. (e.g., email). In addition, the user may be accessing personal financial information (eg, credit card number, financial transaction, etc.) or other important materials on the computer 103 via the wireless local area network. The computer 103 can also be a home office or a remote computer 103, wherein the computer user 101 is not in the office, but uses the network to access the area network 105 on the 1,102,1,6, 1〇7, 1〇8, and 1〇9 internal body. The behavior described above requires calling application 丨丨2 to perform related encryption and decryption actions. In addition, wireless network 109 has been widely used. The layout is in public places such as cafes, airports, schools, etc., so the users of the laptop 104 must pass the wireless network 1〇9 to the wireless router in addition to encrypting or decrypting the data received or transmitted to other users. The data of 1〇8 must also be encrypted/decrypted. [0 0 1 4] Those skilled in the art can understand that when the computer 1 〇 1 〇 1 needs to perform cryptographic compilation, the application 112 will be affected. Call, then encrypt or decrypt the action. So the future computer 1〇1_1〇4 has

Page 12 1247241

V. Description of invention (8) It is necessary to perform hundreds of cryptographic operations at the same time.

[0015] The inventors have found that computer systems 1 - 1 - 4 simultaneously calling one or more encryption or decryption applications 112 have the following disadvantages. For example, if you can use a special hardware to handle these functions, hard processing will be faster than using software. Every time the application 11 2 needs to perform the decryption decryption, the work that the computer 101-1 04 is performing must be #1 pause %^ to transfer the parameters required for the password compilation action (this article, ciphertext, mode, gold record) to the computer. The operating system, and then the computer operating system passes these resources to the application 112 to complete the cryptographic compilation action. Since the application software 112 needs to perform a number of rounds of sub-operations when editing and translating a piece of data, the number of instructions to be executed by the computer is large and the processing speed of the entire operating system is significantly reduced. Those skilled in the art can understand why the transmission time required to send an encrypted e-mail in the Microsoft Outl〇〇'k environment is five times that of the unfilled [0016] delays in intervening in the computer operating system. It will also affect the use of this technology now. At present, most of the application software does not have complete key generation or encryption/decryption functions, so it depends on the operating system or plug-in software.

Lug-in software) to complete these tasks. To obtain operating system resources, an interrupt is issued to the operating system or the operating system is requested by the executing application software. [0017] The inventors have also found that the computer system ^ 丨〇 4 cipher compilation operation mode is very similar to the processing unit of the floating point operation in the earlier microprocessor. Early floating-point operations were handled by software, so execution was slow. The speed of password compilation through software processing is also reported

Page 13 .1247241 V Description of invention (9) 忮. With the technology of floating-point arithmetic ^ — the auxiliary processor of the central processor. : * The operation command is being re-introduced into the whole system. The price of the whole system rises θ = the number of ports into the ocean point auxiliary processor makes many. The speed of the pure float is faster than the software. Most of them are processed by the parallel processor to process the hardware, and the plug-in or plug-in bus interface (such as the universal serial bus processor can shorten the computer). The auxiliary processor of class f increases the price and power consumption of the system. But in addition to the low, data security becomes a consideration: the stability of the system is reduced by eavesdropping. On the chip, the connection between them may be necessary. I. The password compilation hardware built into the microprocessor is the beginning of C €: each hardware should let the application software only need to send one instruction to complete $ 4", . Learn. Inventor It is believed that this kind of hardware can reduce the interoperability of the computer operation system. This invention can provide the application software to perform the password compilation: the first right 1 needs to be more common with the current market, and the support is better. Old operating system and application software. It is more important to stop eavesdropping. This hardware should support a variety of different cryptographic compilation algorithms and be able to authenticate and test cryptographic compilation algorithms on hardware. The mode of operation, for example, allows the user to choose to provide their own key or choose to issue the key by hardware and support the switching of different sizes of data fragments and key sizes. Finally, the encryption/decryption mode used by this hardware should be Choose, for example, whether to use an e-book code

(ECB), edit block chain (CBC), code feedback (CFB) or output feedback

Page 14 1247241

(〇 F B) Do password compilation. [Summary of the Invention] [0 0 1 9] The invention of New Zealand, the name of the name seems to account for solving the problems faced by the prior art, and an excellent microprocessor built-in cryptographic compilation technology. One real two is too much for the invention. The invention is a microprocessor-embedded and customary U-translated logic and execution logic. The device contains the cipher compilation command to transfer, tf;: the steps that will be received after the translation command. Execute the logic and transfer the microcomputer instructions on the second pair to indicate that the operation is connected from the translation logic to the micro-#logical operation, and the logic is executed. After the computer refers to 7 and steps, the processor device can be started. The device has a micro-processing device for processing the cipher. The microprocessor device J has a translation command and a translation logic. The cryptographic instructions are provided to the microprocessing: = code compile instructions and translation logic. In the instruction flow. This password "J J will convert the received command into the password compile command into a two-two button without processor operation. The translation logic will take the step. 'Microcomputer command, instruct the processor to execute [002 1] Invented from a certain order of the device. This device scoop people have no need to deal with a password compile program. The logic inside the microprocessor ^ you 3 ... a password compile instruction and execution logic need to execute which password is compiled ^ After the code compile instruction, the instruction is interpreted as a connection, so the execution logic W ^, the execution logic and the processor are the translation operations. The specific password is executed 1272441

[0022] The invention can also be viewed as a method of performing cryptographic compilation in a microprocessor. This method includes how to receive and execute cryptographic instructions. [Embodiment] [0036] The following is only the preferred embodiment of the present invention, and is intended to limit the scope of the present invention. That is, the equivalent changes and modifications made by the scope of the application of the present invention are covered by the scope of the invention.

[ 0 037 ] The following will refer to Figure 2 for a discussion of the technical background and its shortcomings of the previous cryptographic compilation operations. Next, please refer to FIG. 3 - 11: - The present invention provides an apparatus and method with superior performance and mechanism to perform cryptographic compilation operations. This invention reduces the need for an interventional system. In addition to this, the invention also meets other requirements, such as independent integrity, and

Old architecture compatibility, algorithm and mode switching, hacking, ^ and testability. — A

[0 0 3 8 ] Now look at Figure 2, which depicts a block diagram of the current computer system password compilation. Block 2 contains a microprocessor. The microprocessor 2 is responsible for accessing application-related instructions/access-related data from the system memory. f : The software control and data access mechanism in the ί5 memory area 2〇3 is usually processed by the operating system 202 in memory. The operating system 2〇2 is stored in the protected area. As described in the previous section, an application needs to do the decoding and compiling action during execution (for example, an electric ^

Page 16 1247241 V. Invention Description (12) ---- Mail program or software for storing files), must notify the microprocessor, and then the microprocessor 201 completes a series of huge instructions: code: translation. Some of these instructions are in the implementation of this type of application: two sub-programs 'some are software plug-ins connected to the executable program or there are: can be made "the service provided by the system 202. No matter these refers to; from where" It is located in a specific area of the memory. For convenience, the fragment maps of these different areas in the memory are enclosed in the ^ : 9 memory area 203. The application memory area 203 also contains a ^ The firmware 204 is generated. The key generation software usually pays for the work of generating and accepting the gold balance, and also expands the key into the key program table 205. If the encryption mode used is required, the encrypted software 206 will read The initialization vector 2〇8. After the software executes the internal instruction to complete the encryption operation, and finally outputs the ciphertext 211. The decryption process is substantially the same, and when the ciphertext needs to be interpreted, the decryption software 207 is called. 2〇7 executes a specific instruction to obtain ciphertext 211, key program table 205 and cryptographic compilation parameters. The cryptographic compilation parameter can provide detailed details of cryptographic compilation. If the decryption mode used is needed, the decryption software 2〇7 will read the initialization vector 2〇8 and execute the instructions there to complete the ciphertext decryption operation, outputting this 210. [0 0 39 ] Encryption, decryption and generation The action of the key should be completed with fewer instructions. It was previously proposed that the specifications published by FIps provide several different virtual codes to estimate the need to perform a simple cryptographic compilation. The number of instructions. The number of instructions used to process compiled passwords is now more than one hundred. In addition,

Page 17 1247241 V. Invention Description (13) & The implementation software (file management, newsletter, f-end:: access, credit card) software perspective: Password compilation is neither the main use of the software itself , < 2 ~ 叩 and very tedious and even make the user of the software illusion that the application software is not efficient enough. = Three software 206, decryption software 207 is the software plug-in architecture, then the brothers are f The system's work items have added support calls; the 206 '207 software. The operating system must support interrupts, exceptions, etc. In addition, every simultaneous compilation on the computer system will need to be arranged in memory 203. Some space is given to the software 2〇4, 2〇6 and 207. And the password compiler that the microprocessor 202 needs to process in the future.

The amount will only increase. P I

[0040] The inventors have in view of the fact that today's computer systems handle cryptographic compilation, and the drawbacks would require a built-in microprocessor and the need for improved means and methods for cryptographically compiling speeds. This unit starts the compiler with a single = code compile command. With regard to this invention, we will make a more in-depth explanation with reference to Figures 2 - 12. Field (10) Referring now to Figure 3, Figure 3 is a block diagram of a micro-f 岔 code compilation operation device in accordance with the principles of the present invention. Diagram 300 shows microprocessor 301 if memory bus 319 is combined with system memory 321. The microprocessor 3〇1 ^, Ze logic 303. The translation logic 3〇3 receives the instruction from the instruction register 3()2. The composition of the password translation logic 3〇3 can be a logic, a circuit, a device, a micro-decryption code (that is, a micro-instruction or a native instruction), or a logic, a 指令 ϊ : micro-instruction code or other components that can achieve the same function. The junction is the component of the microinstruction code. Compose password compilation

1247241 V. INSTRUCTIONS (14) The components of logic 303 can be shared with the components of the microprocessor 3〇1, such as their execution, microinstruction code, and the like. According to the scope of this application, refers to: 5 multiple? Means, Micro-instructions (can also be referred to as native instructions; refer to the cryptographic compilation unit level can be tens of thousands of households 隹 瞀 揷 拙 拙 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The processor, such as the processor of the Χ86 phase, first translates the instruction into a micro-instruction, and then executes it by one or more internal units. The translation logic 303 and the fingerprint array 304 are coupled. The command queue 3〇4 There are a plurality of microinstructions 3〇5, 3〇6, which are handed over to the scratchpad stage logic by the microinstruction queue 3〇4, wherein the scratchpad stage logic contains the scratchpad file 3〇7 The microinstruction moves from the instruction queue to the temporary storage logic area. The temporary storage logic includes a temporary archive Μ7, and the temporary archive 307 has a plurality of temporary registers 3〇8-313. These registers are compiled and encoded. Before the operation, the data required for the operation is carried in. Each of the registers points to the memory 321 323-327 which contains the data required for compiling the password. The temporary storage area logic is coupled to the loading logic 314. ^ Logic and cache memory data 3 1 3 coupled, from cache memory Material 3 1 3 reads the data required for the cryptographic compilation operation. The data cache memory is coupled to the memory through the memory bus 3 1 9 and executes the received instructions. The execution logic 3 2 8 can be a logic, A circuit, device, microinstruction code (that is, a microinstruction or a native instruction) or a logic, circuit, device, microinstruction code or a combination of components that can achieve the same function, and the execution instruction indicates the operation logic 3 The 〇3 component can be shared with other functions in the microprocessor 3 。 1. The execution logic 328 includes a cryptographic compilation unit 316. The gift code compilation unit 3 1 6 receives the cryptographic compilation operation from the loading logic 3 1 4 Required capital

Page 19 1247241 V. INSTRUCTIONS (15) Materials. The microinstruction instructs the cryptographic compilation unit 316 to perform a code compilation on a plurality of inputs 3 2 6 and output a corresponding plurality of rounds of texts & 327. The cryptographic compiling unit 316 can be composed of a logic, a device, a microinstruction code (that is, a microinstruction or a native instruction) or a circuit, an I f, a microinstruction code or the like to achieve the same function, and to handle cipher compilation. The cryptographic compiling logic 303 component can perform other functions in the microprocessor 301. The cipher compiling unit 316 is executed in parallel with the execution unit such as the execution logic unit and the integer unit. The embodiment of the unit may be a logic, a Ray 7-three micro-instruction code (that is, a micro-instruction or a native instruction) or a t-set, a device, a micro-instruction code or the like that can achieve the same effect. The unit component can be shared with the π B in the microprocessor 3〇1. The circuit, the microinstruction code, and the like are shared. A f γ 彳 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 1, in the integer unit instruction or native instruction) or a logic, "^ circuit, 曰 码 code (that is, micro or other can achieve the same function of the element of the girl set, micro-instruction code a floating point stand Is a 纟 ^ ^ integer instruction. The code (that is, micro-instruction or native instruction) or device, micro-finger, micro-instruction code or other can reach k series, circuit, floating point instruction. In-bit execution I $ mortal component combination, execution and floating-point arithmetic unit processing floating-point operations means that the person's components can be shared by code, etc. One is compatible with χ8β architecture, 〃 component line, micro finger unit 3 1 6 and an X 8 6 integer unit, an XR Α : In the example, 'password compilation is earlier than 86 ocean point units, -χ86 ΜΜΧ single I

Βϋ Page 20 1247241 V. Description of invention (16) = Parallel operation with an X86SSE unit. In accordance with the scope of the present invention, an embodiment of a fish x86 compatible structure can support most of the χ86 processors. The method of judging whether the software is correctly executed is to check whether the line is soft, ', and whether the correct result is obtained. Other implementations that are compatible with χ86 code compilation units are considered to be a subunit of χ86 execution unit ten. The fee unit 316 is coupled to the storage logic 317 and provides an output of a plurality of corresponding characters, segment 327. The storage logic is coupled to the data cache memory 315. The data memory 315 sends the output text data 327 to the memory 321 for storage. The memory logic 317 is coupled to the write back logic 318. The cryptographic compilation operation is completed, and the playback logic 318 is updated. The register file 3〇7 is the contents of the temporary register 3〇8_313. In the embodiment, the microinstruction cooperates with the clock signal (not shown) to flow to the aforementioned logic stages 302, 303, 304, 307, 317, this operation can perform multiple operations simultaneously as a production line job. [0 042] In the system memory 321, an application may issue a cryptographic operation instruction 322 to the microprocessor 301 if it is necessary to perform a cryptographic operation. Hereinafter, the XCRYPT instruction 322 is referred to. In an enhanced instruction set operation embodiment, the XCRYPT instruction 322 includes a microinstruction that indicates a cryptographic compilation operation. In the reduced instruction set operation embodiment, the XCRYPT instruction 322 includes a microinstruction that indicates a cryptographic compilation operation. In one embodiment, the XCRYPT instruction 3 22 uses an instruction code that is either extra or used in an existing instruction set. In an x86-compatible embodiment, the XCRYPT instruction 322 is a 4-bit instruction that includes an x86 prefix (ie, 0xF3), and is used within a set of 2-bit operands (ie, x) 〇FA7), and - bit block decryption mode. In one embodiment, the XCRYPT instruction 32 2 is allowed in accordance with the application software.

1247241 V. INSTRUCTIONS (17) = - Person, the XCRYPT instruction 322 can be directly programmed into the microprocessor 301 or written by the operating system 320. Because only the software or job f ^ only needs the next instruction 322 to complete the password compilation, the password, and the details of the job are transparent to the operating system. /0043] The operating mode of the computer system is determined by the operating system 3〇2 to subscribe to the application software 320. The application software orders the execution of the XCRYpT instruction 322, and the deduction is obtained in the logic 302. Of course, there will be other private extensions in the software: the microprocessor 3〇1 first cryptographic characters 323 of 323-327 in the memory 321, the initial cryptographic control key 324 or the key program t vector 325 ( If needed). Waiting for the processed input = sub-326 and output 327 will be copied to the corresponding register 323 - π?. The actions of this initial buffer 308-31 2 must be performed. Because all the data in the temporary L is used when executing the KRYPT322 instruction. In addition, there is a temporary register, a negative alpha shell directory input text has several segments and needs to be encrypted/decrypted temporary storage ^ 5 / 303 from the extraction logic 302 to obtain instructions, translated into corresponding two two,: the first buckle 7 Will not be able to compile the unit 31 6 to the data from the two people, and then start the specified number of password compilation. The execution will be stored in the text area of the memory buckle 317 through the data cache 315. 327 ° The second group of multiple fingers: the second structure of the year; the other execution units in the processor 301 (not shown). ^ child °, hang contains temporary results and counter update input and output

1247241 V. INSTRUCTIONS (18) Indicator registers 311-312. If there is an update to the initial vector register. One of the embodiments is that the scratchpad 3 08-3 1 3 is an architectural register. [0044] In the embodiment, the cipher compilation unit 316 is divided into a plurality of stages, allowing the continuously input text segments 32 6 to be pipelined. [0 0 4 5 ] The elements shown in Figure 3 are necessary elements for explaining the present invention. The logic inside many of today's microprocessors 301 is not shown in Figure 3A. Those skilled in the art will recognize that the logic contained within many of the microprocessors 301 is simplified in the diagram 300 in order to clearly illustrate the invention. This is for the convenience of the narrative. The load logic 314 can include an address generation step followed by a cache memory interface stage. Then there is a cache memory alignment phase. However, it is important that the present invention cryptographically compiles a plurality of input text segments 326, and the operating system can be completed by a single instruction. The details of the initial password compiling operation of the present invention are completely transparent, and are simultaneously operated with other execution logics in the microprocessor 3.1. The cryptographic compilation unit 316 and associated XCRYPT instructions 322 operate completely compatible with today's older operating system operations. [0 046] Please refer to Figure 4, this is the block compile instruction. The block cipher command 400 contains a pre-block 4〇ι, a re-blocking block 4 〇2, and an opcode field 4 〇3. A block decryption mode j bit 404. In one embodiment, the contents of the block 40 404 are compatible with the x86 instructions. [0047] When computing, many instruction set structures have been joined with an optional pre-column 4〇1. This field is used to instruct the processor to turn on and turn off some computing functions. For example, directly for 16-bit or 2-bit operations

Page 23

1247241 V. INSTRUCTIONS (19) 2 The function of directly processing or accessing a specific segment, etc. The content of the repeated preamble 402 represents the number of times the cipher compilation operation needs to be repeatedly executed. [0048] The opcode intercept 403 refers to the microprocessor executing the control character to indicate the f code, operation, and the actual control character. The upper is stored in the memory, and a control word indicator points to the position of the control word in the memory. The value of the opcode will be set to a value that is rarely used in an existing instruction set. In this way, the old operating system and application software can be used. For example, an x86-compatible system can set this value to 〇x〇FA7. Block decryption mode block 404 indicates which cryptographic operation needs to be performed. Please see Figure 5. [0 049] Figure 5 is an example of a block password field value and a microprocessor operation. As shown in the figure, if the value in the block password field is 0x08, the microprocessor will use the electronic book code (ECB) mode to complete the password compiling action. When the value in the field is OxDO, the microprocessor will edit the block chain (CBC) mode. ΟχΕΟ indicates that the microprocessor should use the code feedback (CFB) mode, and 0χΕ8 indicates that the output feedback (〇fb) mode is used. The various modes described above are described in detail in the F I PS literature. [0050] Please see Figure 6. Figure 6 shows an embodiment of the invention of a cryptographic compilation unit 161 in a microprocessor 60 compatible with Χ86. There is an instruction fetch logic 601 within the microprocessor 600. The instruction fetch logic 6〇1 fetches the instruction from the memory (not shown). The translation logic 602 is set by a logic, a circuit, a microcode (that is, a micro instruction or a native instruction).

1247241 V. INSTRUCTIONS (20) are other components of a microinstruction code that can be converted into a control. The translation elements within translation logic 602 can be shared with other functional elements within microprocessor 600. As shown, translation logic 602 includes a translator 603 and microinstruction code read memory 604 that are interfacing. Interrupt logic 626 is coupled to translation logic 602 via bus 633. The interrupt request signal 627 from the soft/hardware is processed by the interrupt logic 626. Interrupt logic 626 relays instruction translation logic 602 to an interrupt. As shown in Figure 6, the instruction translation logic is coupled to the following series of stages. Including register stage 605, address stage 606, load stage 607, execution stage 608, save stage 618, and write back stage 619. An execution logic 632 is included in the execution phase 6 08 depicted in FIG. Execution logic 632 has multiple execution units for simultaneous operations, units 61 〇, 612 '614, 616, and 617. The integer unit 610 is responsible for executing the integer microinstruction in the microinstruction queue 609, the floating point unit 612 is responsible for executing the floating point microinstruction in the microinstruction array 6 11 , and the μ Μ X unit 61 4 is responsible for executing the instruction queue 6 1 3 The SE microinstruction, SSE unit 616 is responsible for executing the SS Ε microinstruction in the microinstruction array 61 5 . S S Ε unit 61 6 and password compilation unit 6 1 7 face to side. There is a load bus 620, an idle signal 621 and a storage bus 622 in between the two units. The cryptographic compilation unit 61 7 and the SSE unit share the same command queue 6 1 5 . Another embodiment is to set the cipher compilation unit 617 to a completely separate unit such as units 610, 612 and 614. The integer unit 610 and the x86 EFLAGS register are coupled. The EFLAGS register contains an X bit 625. The value in this X-bit is currently whether there is a cryptographic compilation operation in progress. One of the X-bit 6 2 5 embodiments is the 30th bit in the x8 6 EFLAGS register 624. another

Page 25 1247241 V. Invention Description (21) In addition, the whole "6:0" will read the data in the register m to analyze the value in the HE bit 継 of the 継 疋 疋 629 indicating whether the cryptographic coding unit 61 7 exists in Micro-f (4) 。. 1 unit 610 will also read a " 立元631. This bit το is located in the feature control temporary # 63〇@, used to open and close the secret, edit, unit 617.% Figure 3 The microprocessor implements the micro-processing 600 of the sixth diagram in order to clearly express the characteristics of the invention, and some microprocessors are constructed in the figure, and other parts are put together or have been omitted. The person skilled in the art can understand the components, such as the interface of the data cache (not shown), the bus interface unit (not shown), and other microprocessor units such as the clock generator and the decentralized logic are omitted. During the calculation process, the instruction fetch logic cooperates with the clock signal (not before) to extract the deduction from the memory (not shown) to the translation logic 6〇2. The translation logic 602 transcodes the instruction into a (4) microinstruction and then cooperates with the clock signal. Transfer to the microprocessor 600 6 Units 05-608, 618, and 619. Each of the two pairs of micro-instructions instructs the microprocessor to perform a sub-action to complete the = item, such as an address generation instruction performed by the address stage 606. I includes the two registers specified first from the register stage 605 (two operands are not displayed in the ==^, and then two integer units 61 〇 are added to all execution units 610, 612, 614 The /9/fruit produced by 616 and 617 are stored in the memory by the storage logic 618. The translation logic will judge the type of the instruction and the instruction will directly generate a conjunction or translation using the translator 6〇3. The logic 602 extracts a coherent microinstruction from the microinstruction code read only memory. Or the translation logic 602 generates the microinstruction of the 1247241 V invention description (22), and the remaining rewrite memory from the microinstruction code. The microinstruction is executed in the order of clock speeds in the microprocessor 600 following the stages 605 - 608, 6 1 8 and 61. When the microinstruction moves to the execution stage 608, the execution logic 632 sends the microinstruction. To the execution units 61〇, 612, 614, 616, and 617 The result of the execution of the operation then proceeds to the storage phase 618. In one embodiment, the microinstruction includes instructions that indicate the range, whether or not it can be performed concurrently with other operations. [0052] After the translation logic 602 receives the XCRYPT instruction, The corresponding instruction is generated, and the other logic 605-608, 618, 61 9 in the microprocessor 6 is commanded to execute the cryptographic operation instruction. The first plurality of micro instructions are directly assigned to the cryptographic unit 61. 7Incoming Command Unit 61 7 Load the required data from the loading queue. Or load a fragment of the data, start the password compilation round of the indicated number. It is also possible to transfer a portion of the output stream to the storage logic 61 through the storage stream 622 and then store it in the memory. Next, the second set of multiple instructions will be divided into =^ to execute the units 61 〇, 612, 614 and 6 1Θ to perform other necessary sub-segments. For example, test E bit 629, set D bit 631, and set bit 625 to indicate that the cipher compilation operation is being executed, and set χ bit 625 = value: to display the cryptographic operation is being executed. Update the temporary storage J temporary storage:, the number 2 device, input the text indicator register, • the text refers to the work in the range of 6〇5, and handle the interrupt request sent by the interrupt logic bZb 62?, ^ ^ The work of Zhai π and so on. In order to achieve the most efficient integer--) private order, the order of the micro-instructions will be specially arranged to intersperse the micro-instructions into the cryptographic-compilation micro-instructions, and the integer arithmetic has been achieved.

Page 27 1247241 V. Invention Description (23) "" ' 'One' --- Calculation and password compilation operation in parallel. The microinstructions contain the microinstructions needed to recover from the pause 627. All indicators pointing to cryptographic parameters and data are located in χ86 scratchpads. When an interrupt request is received, the indicator will be stored. After interrupt 2, the data meter parameters will be restored. When replying from an interrupt, the group is responsible for testing the state of the X bit and determining if a cryptographic operation is in progress. If so, the microprocessor will begin processing the incoming data that is being processed halfway through the interrupt request. The order of the microinstructions will allow the indicator register and the incomplete result of the ongoing code compilation to be updated to the scratchpad before the interrupt 627 is processed, and then the interrupt is 0.

= 053 ] Now look at Figure 7. Figure 7 is an example of a microinstruction structure. The attack microinstruction 700 is used to instruct the microprocessor as shown in Figure 6 to perform cryptographic compilation operations. The microinstruction 7〇〇 contains a microcode field 701, a data register field 7〇2, and a scratchpad block 703^. The micro-opcode block 701 provides the microprocessor 6() to execute those sub-operations, and the logic to be used at each stage. In the present invention, a particular value is assigned to the microinstruction for use by the decoding unit. The first value (XL0AD) indicates the data in the location pointed to by the data scratchpad block 7〇2 in the memory. This information should be loaded into the scratchpad field 7〇3 only in the location of the password compilation unit. This proposed material (such as password code #key data, control word, input text data, initialization vector) is provided to the cryptographic unit. The second micro-opcode blocks the value of 7〇 1 (XST0R), indicating that the result of the cryptographic unit operation should be stored in the record.

Page 28 1247241 V. Description of invention (24) " ' ' ' " I. The position in the hidden register field γ 〇 2. For the = code compilation unit of the multi-level structure, the contents of the scratchpad block 7〇3 indicate that the one of the plurality of output beaker segments should be stored in the memory. The rounded data piece is placed in the data field 7〇4 and is stored in the storage logic. Next, the table and Figure VIII and Figure 9 will further explore the execution flow of XL〇AD and XST0R in the cipher code; HENG [0054] Referring now to Figure 8, Table 8 is a set of instructions for translating xcmT instructions as previously described. The first group of micro-instructions of the micro-grain is directly executed by the cipher-compilation unit, and the plurality of micro-instructions of the m-group of the m-th group are one or more other new instructions. The actions performed include the state-of-the-art register, the structure register, the test and the setting of the bit state of the device. The micro-instructions of the group are ΪΞί;: two passwords? Parameters, and input data to the password file file in the 4 ί body, record, store the output text data. A ... or solution unit loaded secret link 丨 - second earth, 丨, XL0AD micro & 々 4th day to show the password compilation table, ^ ^ sub-negative, loading the password compilation key or key program ίι start who planted Initialization vector data, loading input text data and pointing - column rushing code editing and shipping. When the micro-instruction micro XLOAD, temporary storage of the word ΓΛ: the value 0_0 indicates that the exhausted compilation unit loads the control wordΛ ...19 means that this instruction controls the memory control word indicator of the scratchpad in the pipeline. ii 浐^/, the control word is paid. Paraplegia, blush k and kh to the memory load logic from the cache memory This control is proposed in the bodyΗ

瞧

Page 29 1247241 V. Description of the invention (25) Word, placed in the data field 704. The same 'scratchpad field value (10) 1 indicates that the cryptographic unit loads the input text in the data block 7 0 4 . Then perform the password compilation operation. Just as the control character 'input data is presented through an indicator in the existing structure register. [0055] In the embodiment, the register fields 〇b 100 and OblOl can be regarded as a two-stage cryptographic unit. Continuous input text data can be pipelined. The first XL0AD microinstruction puts the first input text into IN-1, the second XL0AD microinstruction puts the second input text into ΙΝ-0, and the second XL 0 AD microinstruction also starts the cipher compilation unit. Perform a password compilation operation. [0 0 5 6 ] If the cryptographic compilation operation uses a user-generated key schedule, the number of XL0AD microinstructions corresponds to the number of gold inputs in the user-generated key schedule. The user-generated key program table will be distributed to the cryptographic compilation unit. This unit will load the gold balance used for the round from the gold output program table according to the status of the yam code compilation. [0057] The other values in the XL0AD microinstruction register stall 7〇3 are reserved. -" [0058] Please refer to Figure 9. The table in Figure 9 shows the comparison table of the XST〇R micro-instruction register field 703. The XST〇RE instruction instructs the password-compiled bit to process the output text segment (encrypted). The position in the memory indicated by the storage field 702 is over or decrypted. According to the present invention, two XL0AD micro-instructions are first generated to load an input text 'and then XST0R is issued to output the corresponding input of the input text. Text storage. Temporary storage

Page 30 1247241 V. Invention Description (26) ------- The value of the field 70 3 〇 bl 〇〇 indicates that the cryptographic unit provides internal temporary storage = output-〇, 0UT output text segment Supply storage logic to do = save. The content of OUT-0 is the correspondence of the input text segment in IN-〇. The internal temporary register of the phase of the temporary storage block Obi 01, which corresponds to the input data in the I N-1. After loading the key and control word data, the next XL0AD.IN-1, a plurality of input text segments can be pipelined into the cipher compilation unit. The XLOAD.IN-0 microinstruction (xload.IN-0 also starts the cryptographic compilation operation in the cipher compilation unit), 疋9 XST0R.0UTPUT-1, XSTOR.OUT-O, XLOAD.IN-1, XLOAD.IN- 0 (starts to operate on the next input text segment), and so on.

[0059] Now look at Figure 10 'Figure 10 is an example of the format of a control character 1〇〇〇. The control character contains the cryptographic parameters used to indicate the cryptographic compilation operation. Control character 1 〇 〇 〇 is programmed into the memory by the user: The indicator pointing to the control character in the input code is located in a faculty register. Therefore, in a set of micro-instructions corresponding to the XCRYPT instruction, the LOAD micro-instruction instructs the microprocessor to read the architecture register containing the indicator, and converts the indicator into a physical address, and takes control from the memory (cache memory). Word 1 0 0 0 ' Put the control word register inside the cipher compilation unit. Control Word 1 000 contains a reserved RSVD block 1001, a KSIZE field 2002 representing the size of the key, an encryption/decryption E/D field 1003, an intermediate result IRSLT field 1 004, and a key generation KGEN Field 1 005, an algorithm ALG field 1 006 and a round count RCNT field 1 00 7. [ 0060 ] All values of reserved field 1001 are to be retained. KSIZE column

Page 31 1247241

The value of bit 1 002 indicates the size of the key used for encryption or decryption. In a real example, the KSIZE block 1 002 indicates whether the key is 128 bits, and the 19^ bit is still 256 bits. The ε/D field 1〇〇3 indicates that this cipher is compiled with 70 ciphers or decrypted operations. The KGEN field 1 005 indicates the gold in the memory: the user generated key program table is still a single key. If there is a single key in the memory, the micro-instruction will expand the password compilation key, and the root ALG field 1 0 06 content specifies the password compilation algorithm into a key sequence. In one embodiment, the ALG block 1 006 specifies the AES algorithm, so so far our 'discussions are for Tripie-j) Eg and Mg calculus. Other embodiments that apply different cryptographic compilation algorithms, such as

Rijndael Cipher, Twofish Ciper, et al. The contents of RCNT Block 1〇〇7 indicate the number of rounds that the password is compiled to follow for the repeated compilation of the ciphers required for each text segment. Although the specification of the cryptographic comprehension algorithm described above indicates a cryptographic compilation of a fixed number of rounds of different input text segments, the RCNT interception 1〇〇7 allows the programmer to set the value of the RCNT block 1 007 to Change according to the algorithm used. In one embodiment, the programmer specifies that each piece of text is to be comcoded to 15 rounds of cryptography. Finally, the IRSLT field 1 〇〇 4 indicates whether the number of rounds for encryption/decryption of the input text refers to the RCNT block 1〇〇7 and the ALG field 1 0 0 6 to indicate the nose method or according to the ALG shelf 1 The algorithm described in 〇〇6, the number of calculations done in the RCNT field of 1 0 0 7 produces only an intermediate result, not the final result. Those skilled in the art will appreciate that many cryptographic algorithms will repeat the same sub-operation, and will do different things in the last round. So I R S L T field 1 〇 〇 4 is provided in one

1247241 V. The results of the invention (28), and the programmer can confirm the intermediate result before proceeding to the next step. For example, if the final result is to add value to the intermediate result, you can first encrypt the text for one round, then compile the same text fragment for two rounds, and then perform three rounds. This configurable password compile round setting function and intermediate result function enable users to evaluate the performance of password compilation, solve problems, and also a tool for studying different key structures and rounds. [0 0 6 1 ] Now look at Figure XI, a block diagram of a cryptographic compilation unit 丨丨〇 。. The cryptographic unit contains a microcode register 丨丨〇3. The microprogram code register 11 0 3 receives the microinstruction through the microinstruction bus bar 11丨4. (such as XLOAD and XSTOR micro-instructions) cryptographic unit 11〇〇 also contains a control character register 1104, an inpUt one register, an input-1 register 1106, a key-0 temporary storage The device 11〇7, and a key-one register 1108. The load bus 1111 loads the data into the memory 11〇4-11〇8 in accordance with the contents of the XL〇AD microinstruction in the microinstruction register 1103. The cryptographic unit 11〇〇 also includes a block decryption logic 11〇1 coupled to all of the registers 11〇3-11〇8 and the key random access memory 1102. The block decryption logic provides a stop signal 1113 and a block result to 1:1111:1) 111: - 〇 register 1109 and ouput-l register 111 〇. The output registers 11〇9111〇 will internally send the internal content to the microprocessor through the storage bus 1111. In one embodiment, the microinstruction register 1103 is 32 bits large, while the other registers 1104-1110 are 128 bits large. ^ [0 0 6 2 ] In the case of the difference, the cipher-compilation micro-instruction is sent to the scratchpad 1103 in sequence, in addition, the control word register 11〇4 and the input register

1247241

One of the 1105-1106 or one of the key registers 11 〇 7 - 11 〇 8 is also sent to the microinstruction register. In the embodiment discussed in connection with Figures 8 and 9, the control word is first loaded into the control character register 1 1 04 in the XL 〇 AD micro-instruction. The cryptographic key or key program is then loaded under the command of the next XLOAD microinstruction. If you are loading a 128-bit cryptographic key, the 彳 彳 〇 AD microinstruction will arrange KEY-〇 1107 to store the key. If the key size is greater than 128 bits, XLOAD will arrange KEY-〇 1107 and KEY-1 1108 to store.

This key. If a user generates a key, the next XLOAD microinstruction will arrange KEY-〇 1107. The keys in each of the golden program tables are sequentially arranged in the key random read memory 丨丨0 2 for use in each cipher compilation round. The next input text (if no initialization vector is required) will be loaded into the IN-1 register 1106. A microinstruction in XLOAD will instruct the IN-〇 register 11〇5 to load the input data and apply it to the IN-1 register or to the two inputs based on the contents of the control word register 1104. The initialization vector in the 1105-11〇6 starts the cryptographic compilation of the data in the scratchpad. (If the input data is pipelined) After the XLOAD microinstruction specifies the in- scratchpad 1 0 0 5, the block decryption logic begins the cryptographic compilation following the contents of the control word. If a single cryptographic key needs to be expanded, the block decryption logic will generate each key in the key program table and store them in the random read memory 1102. Regardless of whether the block decryption logic needs to generate a key program table or the key program table has been loaded from the memory, the key used for the first round of password decryption must be fast in the block decryption logic 11 〇 1 Take memory

Page 34 1247241

The cryptographic interpretation round of the first block in the body can be directly performed, and the memory 丨丨02 is randomly read from the key. Once the block decryption logic starts to operate, one or more pieces of input text are cryptographically compiled, and the gold used in the key random memory is successively extracted. The password compiling unit 11 0 进行 performs specific and cryptographic operations on the specified input fragment text. The XL〇AD and XST〇R microinstructions are issued to encrypt or decrypt the rounded text. When the XST〇R micro-command is executed, if the output data (OUT-0 or OUT-1) is not ready, the block decryption logic sets a stop signal 111 3 . Once the output data has been generated and stored in the corresponding scratchpad 1109-1110, the contents of the scratchpad are transferred to the storage bus 111 2 . [0063] Please see Figure 12. Figure 12 is a block diagram of an AES algorithm block decryption logic 1200. The block decryption logic 12〇〇 contains a round-counting engine (roun(j engine)i22〇, one round-calculated engine engine controller 1 2 1 0. The round calculation engine 1 22 0 passes through the bus bar 1 2 11 -1 2 1 4 and bus bar 121 6-1 218 are coupled to the round calculation engine controller 121. The round calculation engine controller can access the microinstruction register 12〇1, and the KWH register 1 2 0 4 to read Key data, microinstructions, and passwords compile arithmetic parameters.

The contents of the registers 1205 - 1206 are supplied to the round calculation engine 1220, and the round calculation engine 1 220 then passes the corresponding output text to the output registers 1 207-1 208. The output registers 12 〇 7 - 12 〇 8 are coupled to the round calculation engine controller 121 through the bus bars 1216 - 1217. Such a round calculation engine controller can read the result of each cipher compilation round and supply it to the round calculation engine 1 220 to allow the round calculation engine 122 to pass through the bus program.

Page 35 1247241 V. INSTRUCTIONS (31) NEXT IN1 218 performs the cryptographic compilation operation for the next round. The cryptographic key is extracted from the random read memory (not shown) through the bus 1 2 1 5 . The ENC/DEC 1211 signal indicates that the round calculation engine performs encryption (s - Box) or decryption (reverse S-Box). The RNDCON bus 1212 instructs the round calculation engine to perform the first AES round or the intermediate AES round or the last round of AES. When the GENKEY signal 1214 is set, it represents that the round calculation engine 1 220 needs to expand the key obtained from the bus 1 1 1 3 into a key schedule. The key bus 1213 is also used to provide the gold balance, and she will provide the key required for each round to the round calculation engine 1220. [0064] The round calculation engine 1220 is coupled to the first register reG-0 1224 and includes a first x〇R logical key 1221. The first register 1222 is coupled to the S-Box logic 1223. S-Box logic 1223 is coupled to Shift Row logic. The shift logic 1 224 is coupled to the second register REG -1 1 225. The second register REG-1 1 225 is coupled to the Mix Column logic 1226. The mix logic is coupled to the third register REG-2 1 227. The first key logic 1221, the S-Box logic 1 2 2 3 'shift logic 1 2 2 4 and the hash logic 1 2 2 6 are used as the execution name phase subroutine operation. The mix logic 1 226 is used to perform an AES X0R operation on the data added during the intermediate cryptographic operation round, using the return alloy record provided by the key exchange 1213. The first key logic 1221, the S-Box logic 1 223, the shift logic 1224, and the hash logic 1 226 are also used to perform the corresponding inverse AES subroutine operations when the ENC/DNC status indicates decryption. Those skilled in the art will appreciate that the data will be fed back to the block decryption mode indicated by the contents of the control character register 1202 during the intermediate round.

Page 36 1247241 V. INSTRUCTIONS (32) Round calculation engine 1 220. If the vector data needs to be initialized, the initial vector is transmitted back to the round calculation through the queue NEXTIN1 218. [0 0 6 5] Figure 12 is an embodiment. The round meter* is divided into two phases as shown: the engine phase between REG-0 1 222 and REG-1 1 225 and the second phase between REG-1 1 225 and REG-2 1 227. The data of the first round is placed in two stages, in conjunction with the clock signal (in the middle of the bit. When the cipher compile operation completes an input data, the output data is not), the corresponding output register 1 207-1 208 is moved. Executing the XSTOR micro-instruction memory 1207-1208 to transfer the embedded data to the storage bus (not shown) [0066] although the present invention has been disclosed above in the preferred embodiment. τ. The present embodiment of the present invention The x86 architecture is used as the benchmark. Because of the architecture of 86 people, the architecture is more convenient. The invention can also be applied to other architectures, such as p〇werp(:, MIPS, or The other instruction set architecture is completely different on the system. ^ [ 〇 0 6 7 ] The present invention can be applied to a computer system other than a microprocessor, and the instruction mode used in the present invention can be easily used for 2 conversion. On other computer processing systems other than microprocessors, this can be included in the peripheral chipset of the microprocessor, such as North Bridge, South:) Paper\ is made into a microprocessor, #门处理The secret, translated password compiles the microprocessor. When the microprocessor sees the password compilation target = action, it will give the security to the password to compile the microprocessor. This array;:: embedded controller, I industry control Signal The processor, the array processor, and other processors for processing data. The invention 1247241 V. The invention description (33) can be implemented as a necessary original only for implementing the cryptographic operation, and becomes a low cost and low A power-competing cryptographic comprehension executor, such as a processor that handles encryption/decryption in a communication system. For the sake of clarity, other processing elements are covered by a microprocessor. [0068] In addition, the present invention has been Blocks of 128-bit size are considered 'but other blocks of different sizes can also be applied. As long as the input data 'output data, the size of the gold gun and control character register can be adjusted 0 [0 0 6 9 Although the current application range of the present invention belongs to the widely used DES, Triple-DES and AES algorithms, it is a little-known block cipher mode, such as MARS Cipher, Rijndeal cipher, Twofish cipher ^ Blowfish Cipher ^ Serpant Cipher and RC6 cipher 〇[0 0 7 0 ] Although the current discussion scope uses the block cipher compilation algorithm and its algorithm to describe the cryptographic work of the present invention. It is to be noted here that the present invention can be fully applied to other cryptographic compilation algorithms, as long as it is capable of performing a cryptographic compilation operation, encryption or decryption, and the microprocessor contains a password specifically for receiving the cryptographic compilation command. In addition, for the round calculation engine discussed above, the inventor states that the stage of pipelined processing of input segments in the round calculation engine is not limited to the two phases described above. The engine can be at the current stage of two or more. [0 0 7 2 ] Finally 'Although the current discussion of the present invention is currently limited to 12247241. 5. Description of the invention (34) A single cryptographic unit handles a plurality of block cipher compilation algorithms, and it is stated herein that the present invention can include multiple A parallel cipher compilation unit that is coupled to other execution units in a microprocessor. Among them, a plurality of cipher coding units can separately process different block algorithms. For example, the first unit is responsible for processing the high-order encryption standard AES algorithm, the second unit is processing the data encryption standard DES algorithm, and so on.

[ 0 073 ] Persons who need to be identified, the above are the specific examples of the creation and the technical principles used. If the function of the creation is beyond the spirit of the illustrated book, it should be Within the scope of this creation, it is given to Chen Ming.

Page 39 1247241

[Simple description of the illustration] [〇〇23] The following explanations and pictures can help to understand the other objects, features and advantages of the present invention: [0 0 2 4] Figure 1 depicts a block diagram of a conventional cryptographic compilation application. . [0 0 2 5 ] Figure _ depicts a block diagram of a technique for compiling cryptographic operations. [0 0 2 6 ] Figure 3 is a block diagram of a microprocessor device for processing ciphers in accordance with the present invention. σ [〇 0 2 7 ] Figure 4 is a block diagram of an independent cipher compilation instruction set in accordance with the present invention. ^ [0028] Figure 5 is an example of a block decryption mode block according to the present invention. Unicode in the microprocessor [0029] Figure 6 is a block diagram of the 相86 translation unit in accordance with the present invention. Code Compilation Related to Fields Contained [0 0 3 0] FIG. 7 is an exemplary diagram of a cryptographic compile instruction according to the present invention, which instructs the microprocessor of FIG. 6 to perform a sub-term operation. [0031] FIG. 8 is a comparison table of register values and operation actions in several (^)) microinstructions according to the present invention. The format of the XL0AD microinstruction is as shown in the figure. [0032] FIG. 9 is an XST0R according to the present invention. The comparison table of the micro-instruction median value and the operation action, the format of the XST0R micro-instruction is as shown in the figure; Figure 10 is a cryptographic compilation parameter indicating a cryptographic compilation operation for a control character cell control sub-dimension in accordance with the present invention. n thousand 1 1247241 Schematic description of the figure [0 034] Figure 11 is a block diagram of a cryptographic unit according to the present invention. [0035] Figure 12 is a block diagram of the AES block decryption logic in accordance with the present invention. [Illustration number] 1 0 0 computer password compilation application block diagram 1 0 1 computer workstation 1 0 2 computer workstation 1 0 3 computer workstation 104 notebook computer 1 0 5 area network 106 storage device 1 0 7 first router 1 0 8 wireless router 1 0 9 wireless network 11 0 wide area network 111 second router 112 encryption / decryption software 2 0 0 computer system execution password compilation block diagram 2 0 1 microprocessor 202 operating system 2 0 3 memory 204 generate gold Key software 205 metal file program table

Page 41 1247241 Simple description of the schema 2 0 6 encryption software 207 decryption software 2 0 8 initialization vector 2 0 9 cryptographic compilation parameters 210 211 ciphertext 30 0 microprocessor cryptography computing device block diagram microprocessor 301XCRYPT instruction 3 0 2 translation logic 303 micro-instruction array 304 micro-instruction 305 micro-instruction 306 register file 3 〇 7 register 308 register 309 register ❿ 310 register 311 register 312 register 313 load logic 3 1 4 data cache memory 3 1 5 password compilation unit

Page 42 1247241 Schematic description 3 1 6 Storage logic 317 Write back logic 3 1 8 Memory bus 3 1 9 Operating system 3 2 0 System memory 321XCRYPT instruction 322 Control character 3 23 Initialization key/key program table

3 2 4 initialization vector 325 input text 326 output text 4 0 0 password compile instruction block diagram 401 selective pre-field 402 repeat pre-field 403 opcode field 4 0 4 block decryption mode field

500 block password field value and microprocessor operation action table 6 0 0 code compilation unit invention embodiment 601 instruction acquisition logic 6 0 2 translation logic 6 0 3 translator 604 micro instruction code read only memory 6 0 5 Register stage 6 0 6 address stage

Page 43 1247241 Schematic description of the schema 607 loading phase 608 execution phase 60 9 microinstruction queue 6 1 0 integer unit 6 11 microinstruction queue 6 1 2 floating point unit 61 3 microinstruction array 614MMX unit

6 1 5 micro-instruction queue 616SSE unit 6 1 7 password compilation unit 6 1 8 storage phase 6 1 9 write back phase 6 2 0 load bus 621 idle signal 6 2 2 storage bus 624EFLAGS register 625X bit 626 Interrupt logic 627 microinstruction 628MSR register 629E bit 630FCR register 6 3 1 D bit

Page 44 1247241 Simple illustration of the diagram 6 3 2 Execution logic 6 3 3 Bus 700 Example of micro-instruction structure 7 0 1 micro-code field 7 0 2 poor material temporary storage 1 § shed 7 〇 3 register column Bit 703 800XLOAD value comparison table 900XSTOR value comparison table 1 0 0 0 control character format 1001RSVD field 1 0 02 key size KSIZE field 1 003 encryption/decryption E/D field 1 004 intermediate result IRSLT field 1 005 Key generation KGEN field 1 00 6 algorithm ALG field I 007 round number count RCNT field II 0 0 cryptographic unit block diagram 11 0 1 block decryption logic 11 0 2 key random access memory 11 0 3 Microprogram code register 1104 control character register 1105input-0 register 11 0 6 i npu t - 1 register 1107key-0 register page 45

1247241 Schematic description of the 1108key-l register 1109output-0 register 1110ouput-l register II 11 load bus III 2 storage bus II 1 3 stop signal III 4 micro-command bus 1 20 0AES algorithm Block Decryption Logic Block Diagram 1201 Microinstruction Scratchpad 1 202CW Scratchpad 1 203KEY-0 Scratchpad 1 204KEY-1 Scratchpad 1 205 IN-0 Scratchpad 1 206 IN-1 Scratchpad 1207OUT-0 1208OUT-1 1210 round calculation engine duty controller 1 2 11 encryption/decryption sink signal 1212RNDCON busbar 1 2 1 3 key busbar 1 2 1 4 key generation signal 1 2 1 5 busbar 1 2 1 6 busbar 1 2 1 7 bus

Page 46 12472241 Schematic description 1218NEXTIN bus 1 220 round calculation engine 1221 first XOR logic key 1 222 register REG-0 1 223S-Box logic 1 224 shift logic 1225 register REG-1 1 2 2 6 Mixed logic 1 227 register REG-2第47页

Claims (1)

1247241 VI. Application Patent Range 1 · A device for processing cryptographic operations in a microprocessor, comprising: translation logic for accepting a cryptographic compile instruction, the instruction indicating a cryptographic compile operation to be performed. Turn # is a set of microinstructions indicating the sub-operations to be performed; and execution logic, coupled with the translation logic, responsible for receiving the microinstructions and performing sub-operations. 2· ^ The device described in claim 1 of the patent scope, wherein a cryptographic compilation system has system privileges to hold the application. 3. The apparatus of claim 1, wherein the cryptographic operation comprises: a fee-adding operation s encrypting the snippet of the plural snippet into a ciphertext fragment of a plurality. 4. The apparatus of claim 1, wherein the cryptographic operation includes a decryption operation to decrypt the ciphertext of the plurality of slices into a plurality of slices. 5. The apparatus of claim 1, wherein the cryptographic compilation uses a high-order encryption standard algorithm. 6. The apparatus of claim 1, wherein the cryptographic compile instruction indicates a fragment compile mode used in the cipher compilation operation. 7. The apparatus of claim 6, wherein the fragment compilation mode comprises an electronic code book (ECB) mode. 8. The device of claim 6, wherein the fragment compilation mode includes a cipher block chaining mode ( Page 48 1247241 VI. Patent application scope CBC) mode. 9. The apparatus of claim 6, wherein the fragment compilation mode includes a cipher feedback mode (CFB) mode. 10. The apparatus of claim 6, wherein the fragment compilation mode includes an output feedback mode (0FB) mode. 11. The apparatus of claim 1, wherein the cryptographic compile instruction instructs one of a plurality of cryptographic operations on a plurality of text segments. 1 2 The apparatus of claim 1, wherein the cryptographic compile instruction is an X 8 6 instruction format. 1 3 The apparatus of claim 1, wherein the cryptographic compile instruction indirectly points to a plurality of registers in the microprocessor. The device of claim 13, wherein the plurality of registers comprise: a first register, wherein the first indicator points to the first memory location, the first A memory location is the location of the first text segment of a plurality of input text segments. The apparatus of claim 13, wherein the plurality of registers comprise: a second register, wherein the second indicator points to a second memory location, the first The two memory locations are locations in the memory in which a plurality of rounded text segments are stored. These output text segments are the result of the cipher compilation operation of the input text segments. 1 6 · The device of claim 13, wherein the plurality of devices Page 49 1247241 Patent application scope register winter sentence *Γ· , 乂了 · From, 十,仏X 4 The total number of pieces worn by a 0 is a second temporary at 5 §, straight is the escape input text AA 17^ In the arm storage device, the plurality of devices described in the 酤 酤 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • The content == indicator, pointing to the third record location, this memory location is the location of the code compilation key in the memory ship. 1 8 · If the patent application scope is the 17th item玛编#金余资料 contains a password for gold. 1 9 · If you apply for the patent scope of the 17th item, the cryptographic key data contains a key program table. 20·If you apply for a patent 13 devices, wherein the plurality of registers include: a fifth register, wherein the fifth register contains a fourth indicator 'pointing to the fourth memory location, the memory location Is the position of the initialization vector in the memory. 21·If you apply for a patent The device of claim 13, wherein the plurality of registers comprise: a sixth register, wherein the sixth register includes a fifth target, pointing to a fifth memory location, and a memory location 曰The position of the word 疋, the control word 70 is a cryptographic compilation table control 22, as described in claim 21 of the scope of the patent application, the batch: including: 11 sub-package encryption/decryption block, configuration Added to indicate the password translation operation Page 50 1247241 VI. Patent application scope Confidential or decryption action. 23.:; Please refer to the section "Performance logic package one unit" described in the third paragraph of the patent scope to receive the first group of multiple microinstructions, and ^ round the text segment to perform the complex round of the cipher 'Generate a plurality of output text segments, in which a plurality of Mima, and Bianze rounds are controlled by control characters in the cipher compilation unit. 24. The method of claim 23, wherein the cipher is compiled into a single block cipher logic, configured to complex a plurality of input text segments, and a round cryptographic operation to generate a plurality of corresponding output text segments. And the key random access memory, coupled with the block cipher logic operation, configured to store a key program table, the golden remainder program table includes a plurality of round keys, and a plurality of ciphers respectively Round correspondence, configured to provide block cipher logic multiple keys have completed multiple comma compilation rounds. 25. The apparatus of claim 23, wherein the block cipher logic is divided into two or more stages, and two or more plural character input segments are cryptographically compiled. The device of claim 23, wherein the execution logic further comprises: an integer unit coupled in parallel with the cryptographic unit, configured to receive the second plurality of microinstructions, and perform cryptographic compilation The integer number of integer operations required to perform the operation. Painting No. 51 1247241 VI. Application No. 27 The apparatus described in claim 23, wherein the microinstruction comprises: a first set of microinstructions, configured as soil is a secret array unit respectively loaded into the plural The rounded text and the multiple passwords are edited. 28·- A microprocessor device for implementing a secret compilation operation, comprising: a cryptographic compilation instruction, belonging to a microprocessor execution: a step in the process, wherein the password instruction instructs the microprocessor to enter &amp; A specific cryptographic compilation operation, a translation logic, configured to translate the grammar compilation instructions into relative microinstruction codes indicating the secondary operations that need to be performed. 29. The device of claim 28, wherein the cryptographic compilation operation comprises: a corresponding plurality of ciphers, wherein the cipher is compiled into a cryptographic operation, and the plurality of snippet segments are converted into snippet segments. 30. As claimed in claim 28, the apparatus comprises: a decryption operation, converting a plurality of ciphertext segments into corresponding plurality of text segments. 31. The apparatus of claim 28, wherein a cryptographic operation is performed in accordance with a high-order encryption standard AES algorithm. 3 2 The apparatus of claim 28, wherein the cryptographic compile instruction instructs completion of the cryptographic operation in the block cipher mode. 3 3 · The device described in claim 3, wherein the zone fast password mode includes an eleCtr〇nic code book (ECB) mode. stomach Page 52 1247241 34. The device of claim 3, wherein the zone fast cipher mode comprises a cipher block chaining (C B C) mode. 3 5 . The device of claim 3, wherein the zone fast cipher mode comprises a cipher feedback mode (CFB) mode. 3 6 · The device described in claim 3, wherein the zone fast password mode includes an output feedback (0FB) mode. 3 7. The apparatus of claim 28, wherein the cryptographic compile instruction instructs a cryptographic operation on a plurality of text segments. 38. The device of claim 28, wherein the cryptographic compilation command format is an x86 instruction format. 3 9. The device of claim 28, wherein the cryptographic compilation instruction is directed to a plurality of registers in the microprocessor. 40. The device of claim 39, wherein the plurality of registers comprises: a first register having a first indicator pointing to a first memory location, the first memory location being The position of the first piece of text in the input text segment. 41. The device of claim 39, wherein the plurality of registers comprise: a second register having a second indicator pointing to a second memory location, the second memory location Is the location where a plurality of output text segments are stored in the memory, and the output text segments are input texts. 1247241 VI. Scope of application for patents Fragment of the word 4 2 · If applying for a patent, the result of the translation of the 39th cryptographic code. The device, wherein the plurality of registers comprises: a third register, wherein the content is a total number of the input text segments. 4 3 · The device described in claim 39, wherein the plurality of registers include: a fourth temporary indicator, the code compilation refers to the secret 4 4 · If the patent application contains a 4 5 · such as Applying for a patented yoga contains a 46. If the application package is a standard starting 47. If the patent application package is a standard, please include the patent: The fifth temporary 'pointing vector, please include: the sixth temporary 'pointing to the character's deposit The cryptographic key of the 43rd item in the memory range to the third record key. The 43rd item of the range 43th gold program table range, wherein the fourth memory is in the memory of the 39th item, the fifth memory position, the content of the fourth register contains the first The position of the memory of the three memory is the position in the body. The device described in the device of the cryptographic compilation method, wherein the device described in the weight compilation file is in which a plurality of temporary storage fifth registers contain a fourth finger position. The body position is the initial position. The device </ RTI> wherein the plurality of temporary storage sixth registers contain a fifth location, and the memory location is one of the cryptographic parameters of the control character. 1247241 Among them, the control character package is six. The scope of patent application 48. The device described in item 47 of the patent application includes an encryption/decryption block, which is configured to instruct the cryptographic operation to perform a force-to-peer or decryption operation. The device of claim 28, further comprising: execution logic coupled to the translation logic in the operation, configured to receive the microinstruction and perform the subroutine operation. 50. The device of claim 49, wherein the execution logic comprises: t a cryptographic unit configured to receive the first plurality of microinstructions, and to perform a complex round of the plurality of input text segments respectively. The instruction is compiled to generate a plurality of output text segments, wherein the plurality of password compilation rounds are controlled by control characters in the cryptographic unit. 5 1 · The device according to claim 50, wherein the cryptographic unit includes: block cipher logic configured to perform a complex round cryptographic operation on a plurality of input text segments, respectively, to generate a plurality of corresponding The output text segment, and the key random access memory, are logically connected with the block cipher logic, and configured to store a key program table, the key program table includes a plurality of round keys, and a plurality of passwords respectively Compile round correspondence, configured to provide block cipher logic multiple keys have completed multiple comma compile rounds. 5 2 · The device described in claim 51, wherein the block cipher logic 1247241 6. The scope of the patent application is divided into two or more stages, and at the same time, two or more plural text input segments are subjected to the secret editing. 53. The device described in claim 5 The execution logic further includes: an integer unit, parallel to the cryptographic unit, configured to receive the second plurality of microinstructions, and to perform a plurality of integer operations required to perform the cryptographic operation. 54. The device of claim 5, wherein the execution logic further comprises: a first set of microinstructions configured to load a plurality of input words and perform plural numbers The password is compiled round. 55. The device of claim 28, wherein the application swivel has system privileges to hold the application. 5 6 · The device for performing cryptographic compilation operations, comprising a cryptographic compile instruction, is a step in the flow of instructions executed by the microprocessor, wherein the cryptographic instruction instructs the microprocessor to perform a specific cryptographic operation, a translation logic , configured to translate the cryptographic compilation instructions into relative microinstruction codes indicating the secondary operations that need to be performed. 5 7. The apparatus of claim 56, wherein the cryptographic operation comprises: an encryption operation to convert the plurality of fragments into a corresponding plurality of ciphertext fragments. 58. The device of claim 56, wherein the password is compiled and shipped Page 56 1247241 Scope of application for patents A package of explanations 59. If the application is 6 0. If the application is 6 1 · If the application is packaged. 62. For example, the application package mode 63· is as the application package. 64·If the application is packaged. 65. If the application refers to 66. If the application is 67. If the secret operation is performed, the ciphertext segment is converted into a corresponding plurality of segments. Please refer to the device described in the 56th patent, in which the cryptographic compilation is performed according to the high-level encryption standard AES. The device of claim 56, wherein the cryptographic compilation indicates that the microprocessor completes the cryptographic operation in block cipher mode. The device described in Item 60 of the patent scope, wherein the block cipher module includes the device described in the electronic ic code book (ECB) model patent range No. 60, wherein the block cipher module contains Edit the cipher block chaining 'CBC' mode. The device described in claim 60, wherein the block cipher module includes a device as described in item 60 of the cipher feedback mode (CFB), wherein the block cipher module includes an output. The output feedback mode (0FB) is a device described in claim 60, wherein the cryptographic compilation instruction performs a cryptographic operation on a plurality of text segments. The device described in claim 60, wherein the cryptographic compilation mode is the x86 instruction format. Please refer to the device described in claim 56, wherein the code compiling instruction Page 57 1247241 Sixth, the scope of application for patents Indirect pointing to a plurality of registers in the microprocessor. 68. The device of claim 67, wherein the plurality of registers comprise: a first register, wherein the first indicator points to a first memory location, the first memory location Is the position of the first text segment of the plurality of input text segments. 69. The device of claim 67, wherein the plurality of registers comprise: a second register, wherein the second file contains a second The indicator points to a second memory location, which is a location in the memory in which a plurality of output text segments are stored. These output text segments are the result of the cryptographic compilation operation of the input text segment. 70. The apparatus of claim 67, wherein the plurality of registers comprises: a third register, wherein the total number of input text segments is recited. 71. The device of claim 6, wherein the plurality of registers comprise: a fourth register, wherein the content of the fourth register includes a third indicator, pointing to the third memory Body position, this memory location is the location of the cryptographic key in memory. 7 2 . The device of claim 7, wherein the cryptographic keying material contains a cryptographic key. 73. The device of claim 71, wherein the cryptographic keying material comprises a key schedule. Page 58 1247241 VI. Application for Patent Range 74. For example, the device of claim 67, wherein a plurality of registers contain: a fifth register, wherein the fifth register contains The fourth indicator points to the fourth memory vessel position, which is the position of the initialization vector in the memory. 75. The device of claim 67, wherein the plurality of registers comprise: a sixth register, wherein the sixth register includes a fifth indicator, pointing to the fifth memory Position, this memory location is the location of the control character, which is one of the password compilation parameters. 76. The apparatus of claim 1, wherein the control character comprises: an encryption/decryption block configured to instruct the cryptographic operation to perform an encryption or decryption operation. 7 7. The apparatus of claim 56, further comprising: a translation logic configured to translate the cryptographic compilation instructions into relative micro-instructions, indicating sub-operations to be performed. 78. The device of claim 77, wherein the execution logic further comprises: - a cryptographic compilation unit configured to receive the first plurality of copies; and the input text segments respectively perform a plurality of rounds of secrets: , generate a plurality of output text fragments, the code compilation round is compiled by the cipher unit ^ ' 79. As claimed in the 78th item of the patent scope: control Xi Bu Yi 罝 密码 编译 编译 第 第 第 59 page 247241 ----- Enemy contains: block cipher logic, configured to perform complex round cipher compilation operations on a plurality of input text segments, generate a plurality of corresponding output text segments, and key random access memory, and block cipher logic The operation is coupled and configured to store a key sequence table. The gold program table includes a plurality of round keys, corresponding to a plurality of password compilation rounds, configured to provide block cryptography logic plurals. Complete multiple password compilation rounds. • The apparatus of claim 7, wherein the block cipher mode logic is divided into at least two stages, and at least two character input segments are simultaneously cryptographically compiled. 81. The device of claim 78, wherein the execution logic further comprises: an integer unit coupled in parallel with the cryptographic unit, configured to receive the second plurality of microinstructions, and the I cryptographic compiling operation A number of integer operations to be performed. 82. The device of claim 78, wherein the microinstruction comprises: a first set of microinstructions configured to be a cryptographic compilation unit to load a plurality of input words and to perform a plurality of cipher compilation rounds. . 83. The device of claim 56, wherein the cryptographic compilation system has system privileges to hold the application. 84· A method for performing a mega-compilation operation in a microprocessor, comprising: receiving a cryptographic compile instruction, wherein the cryptographic compile instruction specifies at least Page 6 1247241 VI. Scope of Patent Application The cryptographic compilation operation and the execution of the specified password compilation operation. 85. The method of claim 84, wherein the receiving further comprises: designating an encrypted cryptographic code operation, wherein the encrypting operation comprises encrypting the plurality of text segments to generate a plurality of encrypted text segments. 8. The method of claim 84, wherein the receiving further comprises: specifying a cryptographic compilation operation that is decrypted in a first direction, wherein the decrypting operation includes decrypting the plurality of encrypted segments to generate a plurality of text segments. 87. The method of claim 84, wherein the performing comprises: performing a cryptographic compilation operation in accordance with an AES (Advanced Encry Pti〇n Standard) algorithm. 88. The method of claim 84, wherein the receiving further comprises: specifying a block decryption mode used by the cryptographic operation in the cryptographic compile instruction. 8. The method of claim 8, wherein the block decryption mode comprises an electronic code book (ECB) mode. The method of claim 8 wherein the block decryption mode includes a cipher block chaining mode (CBC) mode. 9. The method of claim 88, wherein the block decryption mode includes a cipher feedback mode (CFB) mode. 1247241 ττ, Ψ-guided range --- Type. 92. The method of claim 88, wherein the block decryption mode 匕 3 has an output feedback mode (OFB) mode. 9. The method of claim 8 of the patent application scope, wherein the receiving comprises an escape horse, a flat ##曰令, a password compiling operation for a plurality of text segments. 94. The method of claim 84, wherein the receiving comprises indicating a block cipher mode in an x86 command mode. 95. The method of claim 84, wherein the receiving further comprises indirectly reading a plurality of registers in the microprocessor. 96. The method of claim 95, wherein the indirect reading further comprises: a position of the sub-segment. The indirect reading is further as described in claim 95. The method of claim 95 includes: reading a first register, wherein the content of the first register contains the first indicator to point to the first memory location The first memory location is the position of the first text segment in the plurality of input text segments. Reading a second register, wherein the content of the second register includes a second indicator pointing to a second memory location, where the second memory location is a location in the memory storing a plurality of output text segments. The output text segment is the result of the input text segment undergoing a cryptographic compilation operation. 98. The method of claim 95, wherein the indirect reading is further 1247241 6. The scope of application for patents includes: reading a third register, wherein the content of the third register contains the total number of input text segments. 9. The method of claim 95, wherein the indirect reading further comprises: reading a fourth register, wherein the content of the fourth register includes a third indicator, pointing to the third memory Body position, this memory location is the location of the cryptographic key in memory. Among them, the password compile gold, which is the password compile gold, and the indirect read is more 1 0 0. The method described in the ninth item of the patent application scope contains a cryptographic key. 1 0 1. The method described in item 99 of the patent application scope contains a key program table. The method of claim 95 includes: reading a fifth register, wherein the content of the fifth register includes a fourth indicator, pointing to the fourth memory location, This memory location is the location of the initialization vector in the memory. The method of claim 95, wherein the indirect reading further comprises: reading a sixth register, wherein the content of the sixth register includes a fifth indicator, pointing to the fifth Memory location, which is the location of the control character, which is one of the cryptographic parameters, where the control character can be used to specify at least one of the at least one of the cryptographic operations used A password compilation parameter. Page 63 1247241 VI. Patent Application Scope '~ -- 1 0 4 · The method described in the first paragraph of the patent application, in which the parameter value of the cryptographic operation is indicated by the guard character. The control encryption operation in the control element encryption/decryption block is encrypted b ^ ^ operation. The method described in claim 84 of the patent application, which further comprises: translating the cryptographic compile instruction into a coherent microinstruction, which refers to the subroutine operation that is executed by ^^^. And the method of claim 84, wherein the executing further comprises: ^ distributing the first plurality of consecutive microinstructions to the cryptographic unit; and then in the cryptographic interpretation unit, the plurality of Enter the text segment to 'do' the complex round of the password compilation, and generate the corresponding complex commission output text segment. The multiple password compilation rounds are controlled by the control character in the password compilation unit. The method of claim 106, wherein the step of compiling the plurality of input text segments in a plurality of rounds further comprises: storing a key program table in the cryptographic unit, wherein the key The program table contains the keys of the complex rounds, corresponding to a plurality of comma compilation rounds; the use of a plurality of rounds of gold is required to complete the complex cipher compilation rounds for the block cipher logic. 1〇8· The method described in the first and sixth paragraphs of the patent application, wherein the execution further includes: 1247241 VI. Application for Patent Range The second set of multiple consecutive micro-instructions are distributed to the integer units coupled in parallel with the cipher compilation unit, and then the complex integer operations to be performed by the cryptographic operation are performed. The method of claim 1, wherein the translating comprises: generating a first microinstruction, instructing the cryptographic unit to load a plurality of input text segments and start a cipher compilation round. II. The method of claim 18, wherein a cryptographic compilation system has system privileges to hold an application. Page 65