TW200417926A - Selective interrupt suppression - Google Patents

Abstract

An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies that interrupt processing be suppressed until execution of the extended instruction is completed. The extended prefix tag is an otherwise architecturally specified opcode within an existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and completes execution of the corresponding micro instructions prior to processing a pending interrupt.

Description

200417926 V. Description of the invention (1) Contrast with related applications [0001] This application claims the priority of the following US applications: Case No. 10/384, 390, the filing date is March 10, 2003. '[0 0 0 2] This application is related to the following U.S. patent applications which are also in the same application and all have the same applicant and inventor. Taiwan Application No. 91116957 Application No. 7/30/02

DOCKETNUMBER Patent name CNTR: 2176 Device and method for extending microprocessor instruction set 91116958 7/30/02 CNTR: 2186 Device and method for executing conditional instructions CNTR: 2187 91124008 10/18/02 Device and device for selectively controlling memory attributes and Device and method for selectively controlling condition code write-back 91911956 7/30/02 CNTR: 2188

Page 7 200417926 V. Description of the invention (2) 91116959 7/30/02 CNTR: 2189 Mechanism for increasing the number of registers of the microprocessor 91124005 10/18/02 CNTR: 2190 Device and method for extending the data mode of the microprocessor 91124006 10/18/02 CNTR: 2191 Device and method for extending microprocessor address mode 92100942 1/17/03 CiNTR: 2192 Prohibition of storage inspection 91124007 10/18/02 CNTR: 2195 Reference control of non-temporary memory 91116672 7/26/02 CNTR: 2198 Device and method for selectively controlling result write-back

Page 8 200417926

[Technical field to which the invention belongs] [0 0 0 3] The present invention relates to microelectronics, which selectively suppresses interrupts at the instruction level, and particularly relates to a technology that can construct an instruction set. , 1 ,, 'Into an existing microprocessor [Prior technology] [0 0 04] Since the early 1970s, it has grown exponentially. From the earliest applications to science and 'use of state', that is, consumers who have introduced business from those special fields:: f 'to today = (—) computers, video games; and; =: household and commercial devices and other products. Cang Xi's other comments [0 0 0 5] With the explosiveness in use. A knowledge _ 々 tan said ^ ^ Lai Bu Zhuang grows up technically also through the corresponding ", and is characterized by the following requirements: Faster speed, stronger location of enemies, warriors, review of the force, faster memory storage management, protection: more general-purpose types of operations (such as floating point Distortion, early order = SIMD, conditional movement, etc.) and additional special-purpose transportation (such as digital signal processing functions and other multimedia operations). This has created 'amazing technology in this field' Progress, and has been applied to the design of microprocessors, such as extended ~ pipelining, super_scaUr architecture, cache structure, out-of-order processing (〇ut_〇f_〇rder processing) , Burst access mechanism, branch predication, and hypothetical execution 200417926

5. Description of the Invention (4) (speculative execution). To put it bluntly, today's microprocessors are more complex and powerful than they were just 30 years ago. [0006] But unlike many other products, there is another very important factor that has limited and continues to limit the net advancement of microprocessor architectures. Today's microprocessors can be so complex, a large part of which is due to the compatibility of legacy software. In consideration of the market, many manufacturers have chosen to incorporate new architectural features into the latest microprocessor designs, but at the same time, in this latest product, all of them have been retained to ensure compatibility with the older, so-called " Required for an "egacy" application. [0 0 0 7] This old software compatibility burden, nowhere else, will be more visible and visible than in the history of the development of x86-compatible microprocessors. Everyone knows that the current 32 / 16-bit virtual-mode x86 microprocessor can still be written in the 1980s.

Write 8-bit real mode application. And those skilled in this field also acknowledge that there are many related architectures “coated” stacked in the χ86 architecture ’just to support compatibility with legacy applications and operating models. Although in the past, developers could add newly developed architectural features to the existing instruction set architecture, but now the tools that can be used to use these features can be programmed into instructions, but it is quite rare. To put it simply, there are no “redundant” instructions in some important instruction sets, allowing designers to incorporate newer features into an existing architecture. [0008] For example, in the x86 instruction set architecture, there is no any—undefined one-tuple-size opcode state, which is not yet used.

Page 10 200417926 V. Description of the invention (5) = x 丄 opcode map of tuple size, all 256 opcodes have been occupied by existing instructions. Designers must now provide new features. ; JJ has a choice between x86 microprocessors. If you want to receive the new software, you can sell the software with two phases of code. This is: If both; the feature ', you must assign a code I, the target U: There is no redundant instruction set structure. If this is the case, some existing opcode states must provide new features. Therefore, in order to improve the compatibility of the software. 4 扪 Features, hopefulness, sacrificing and selling [纳 Γ] Λ Some features of modern microprocessors are programmers who have not been able to achieve it for the reasons mentioned above. Among them-the characteristics of members is the interruption suppression control at the level of private order. [0010] At the present time, the micro processing device is transferred to the relevant time mtime: 处理: processing Qiu Zi strike a machine iLlcai) interface requirements ^ ^ ^ ^ σ, the application is in the uninterrupted micro Handle on the piano. When the "external device" is like a disk: 2 η service, the external device will send 2 directly or indirectly to the server; the reason is to point out that an event that needs a timely response has been:. Therefore, most microprocessors include interrupts to normal programs to service these external devices. After the processing is interrupted, it returns to the point where the program originally executed was interrupted. [0011] Most microprocessors have one or more external pins, which can be referred to as α, and _ connected to several externals = it is sufficient to install the following facts: Typical interrupt control is small;

1ΙΙΗ

Page 11 200417926 V. Description of the invention (6) ---- The interrupt signal pin connects a large number of external devices to the microprocessor, and communicates with the main microprocessor in this way. Example # 'Through a typical interrupt controller that communicates with a known microprocessor with two interrupt signal pins, more than two hundred external devices can issue interrupts to this microprocessor $, and the microprocessor can Identify and process.

[0012] Interrupt processing is a very complicated task. When an interrupt is issued, the running application must be suspended at a certain point, and the execution status of the & point can be stored during interrupt processing for subsequent recovery before the program can continue to execute. The status of a running program is usually reflected in the execution point or instruction address. At this point, execution is temporarily suspended, and all general registers and system status values associated with the program are also stopped from updating. Therefore, when an interruption occurs, the program will finish the running instruction first, then suspend the operation of the program, and set the value of the general register and the system state register related to the process = and the value of the running instruction. The next instruction address is stored. After these parameters are stored, the program control in the microprocessor usually branches to an interrupt handler (called an exception handler), which is a part of the operating system program. The interrupt handler starts the operation of the microprocessor (usually through the system bus) to determine which external device is the interrupt signal pin. As soon as it is determined, the program flow is shifted to the feature 中断 = interrupt service application to perform the f required to "service" the external device. Serving the external device involves almost any type of operation, such as = < the device reads or writes data, updates special temporary storage inside the microprocessor, and moves a large amount of data from / to memory. When interrupt processing is complete,

200417926 V. Description of the invention (7) The control right is returned to the operating system to restore the state of the stored interrupted application mode and transfer program control to the address of the next instruction.

[0013] The foregoing description of interrupt processing is to let the reader understand that in a typical pipelined microprocessor, the operations required to process a typical interrupt. Those familiar with the technology in this field will understand that the differences between individual microprocessor architectures are the number of interrupt signal pins provided, the way in which interrupt signals are enabled, how the device transmits interrupts, the level of interrupts, and the applications being interrupted. The method of saving and restoring the state of the program, the point at which the application is suspended after an interruption occurs, and the special operation details of the interruption handler provided by each microprocessor architecture. [0014] Because interruption processing is so complicated, the current Microprocessors provide mechanisms that limit interrupt processing to the operating system level.

For example, many microprocessors have a programmable register that allows the interrupts generated to be ignored. In a χ86-compatible microprocessor, this programmable temporary storage state: The form used is the X86 flag in the χ86-compatible microprocessor. Register = interrupt enable flag bit. When this bit is set to true, then: break is processed. When this bit is not set to true, the interrupt is ignored. Programmable control at this level allows the programmer to ensure that certain operations (ie, specific instruction sequences) can be completed without interruption. For example, when a specific interrupt occurs and the handler in the operating system is processed in this specific interrupt, the interrupt handler is usually disabled (= flags are not passed). After the processing of this particular interrupt is completed, the interruption location is again enabled, and any pending interrupts are allowed to be accessed. To avoid disabling and enabling interruption of non-operating system programs ^ The processor architecture also provides a mechanism to prevent application programs from running

Page 13 200417926 V. Description of the invention (8) ______________ Instructions that will affect whether the interrupt is enabled or disabled. The χ86 phase container allows programmers to specify four privilege levels (priviUge $ handles one to all programs running on the microprocessor. It is pre-fetched in e, and the application is given the lowest special screen. An application that is executed at a lower privilege level is attempting to perform the disabling two, and. If it is ordered, the x86 processor will detect this event and avoid executing this instruction. Other microprocessor architectures use different Mechanism, 9 control is only given to the program responsible for this part of the work. Here only two or two reasons in modern microprocessors, due to the complexity of interrupt processing, the use of programmers to determine whether and when their programs need Pause 'reason. &Amp; 1 Dingjia break [0015] However, there are a lot of calculations performed by applications, + more than one program instruction is executed without interruption. For example, / Yes. Share memory with other devices In the system configuration, for an item that reads a value from the ^ = position, modifies this value, and writes the modified value back to memory:: This value Before being returned to the memory, the execution was interrupted. It can be imagined that this multi-instruction job will fail. This operation is called read-modify-write operation. Read-modify-write operation must be performed "continuously" That is, it is not interrupted to ensure that the program can be executed properly. Some microprocessor architectures provide limited instructions to complete general continuous operations. In the x86 instruction set, a compare and exchange instruction (CMPXCHG) is provided. Allows the programmer to instruct the microprocessor to continuously compare the first operand (read from a memory location) with a register operand, and write the first operand or register operand according to the comparison result

Page 14 200417926 V. Description of the invention (9) Return to the memory location. Another continuous instruction, XADD, allows the programmer to instruct the microprocessor to read the first operand from a memory location and exchange the embedded values of the first operand and a register operand. And write back to that memory location. … [0 0 1 6] Therefore, in a particular microprocessor instruction set, continuous instructions provide some of the more general continuous operations required by applications. However, there are still many other operations performed at the application level that fail due to interruptions. These operations need to be performed without interruption-a series of operations or instructions, but the application programmer cannot ensure that in this series There will be no interruption during the execution of Yun Zeng or 4th Command. The application programmer is more limited by the specific 'f-continuous' instructions described above, and these instructions may not be able to perform other continuous operations effectively, because these continuous instructions are only used to perform more continuous operations. Ding Wen-like [0017] Therefore, what we need is a device and method that can incorporate the features in suppression into an existing microprocessor instruction set architecture. The instruction set architecture is already defined. The opcode is completely occupied, and its interrupt suppression feature allows a microprocessor that meets the old specifications to be retained = ^, with the ability to apply programs, and at the same time provide any known instruction sequence to the old programmer and / or The compiler controls whether to perform interrupt processing. [Summary of the Invention] [0 0 1 8] The present invention, like the other applications mentioned above, overcomes the problems and disadvantages of other conventional technologies. The hair, the above, and the enemy's confession

Page 15 200417926 V. Description of Invention (ίο) Good technology is used to expand the instruction set of micro-processing, beyond the existing capabilities, and to provide interrupt suppression features at the instruction level. In a specific embodiment, a device capable of performing instruction level interrupt suppression control in a microprocessor is provided. The device includes a translation logic (translation '10 g i c) and an extended execution logic. The translation logic translates an extended instruction into a corresponding micro instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended preamble specifies that the interrupt processing is to be suspended until the execution of the extended instruction is completed. The extended preamble mark is an operation code originally specified by the architecture in the existing instruction set. The extended execution logic consumes translation logic, receives the corresponding microinstruction, and completes the execution of the corresponding microinstruction before processing a pending interrupt. [0019] An object of the present invention is to provide a microprocessor mechanism for expanding an existing instruction set 'to selectively suppress interrupts. The microprocessor 2 has an extended instruction and a translator. The second extension order specifies that interruption-related interruption processing should be suppressed until the extension order is completed. The extended instruction includes one of the selected alien codes of the existing instruction set, followed by an n-bit extended preamble. The selection should be: 2 i f ΐ extended instruction, and the n-bit extended preamble,] designation / processing. The translator receives the extended instruction and generates a micro ^ ^ ^ Λ before the microprocessor inhibits processing interruption until the micro instruction sequence is completed. And Yu / [0020] Another object of the present invention is to collect modules that add interrupt suppression features. The module includes an escape-out tag

Page 16 200417926 V. Description of the invention (11) (escape tag), an interrupt suppression specifler (interr ^ t suppression Specifler), a translation logic and an extended editor. A escaping flag indicates that the accompanying part of a corresponding instruction specifies the operation to be performed, wherein the escaping flag is an operation code in the existing instruction set. The interruption suppression designation element is lightly connected to the escape flag, and is-'of the Ik part, and it specifies that interruption processing is to be suppressed until the operation is completed. The translation logic receives the escape flag and the interrupt suppression finger = 7L, and generates a micro-instruction sequence to instruct the microprocessor to execute the operation of the translation logic and instructs to suppress interrupt processing until the operation is completed: extended execution logic Coupling to the translation logic, receiving the microinstruction sequence, = completing the execution of the operation before processing a pending interrupt. [0 02 1] Another object of the present invention is to provide a method for expanding an existing instruction set architecture to suppress interrupt processing at the instruction level. The package 2 provides-extension finger ♦, the extension instruction includes an extension mark 'an extension code 2 code, where the extension mark is one of the different code items of the existing instruction set architecture; specified by the extension prefix The extension refers to time-suppression: break processing, in which the rest of the extension instruction is designated = the difference in the light, and when the extension instruction is executed, a break is suppressed. τ [Embodiment] [0 032] The following description is based on a specific embodiment and its necessary information, so that those skilled in the art can use this " ... Modifications to the preferred embodiment will be apparent to those skilled in the art, and 'discussed here: =

Page 17 200417926 V. Description of the invention (12) 3 Xianyi: Application to other embodiments. Therefore, the present invention is not limited to the specific embodiments described here: f, but has the maximum scope consistent with the principles and novel features disclosed herein. [0030] The previous article has discussed the background of the technology in the microprocessor today, how to expand its structure to exceed the relevant instruction set capabilities; Yu Erjian: In Figure-and Figure 2 'will discuss-examples of related technologies i here the sleeves emphasize the instructions that microprocessor designers have been facing, that is, on the one hand' they want to incorporate the latest developed architectural features , But on the other hand, they want to keep the old V s. 1¾ ^. In the example of Figures 1-2, a completely occupied operation: the code map has excluded the possibility of adding new opcodes to the example architecture. The design "does not choose to incorporate new features, but sacrifices some process to sell software Let ’s combine the latest developments in architecture together to maintain the compatibility of the microprocessor with the legacy applications. After discussion of the related techniques, we will provide the Discussion of the invention. By using an existing but unused operation code as an extension instruction before the code: α, this invention allows the microprocessor designer to overcome the limitation of the instruction, j, which has been fully used, in addition to using The application programmer can instruct the microprocessor to suppress the interrupt processing of a single private order or instruction group, and at the same time can retain all the features required to execute the legacy application. Person [0034] Please refer to Figure 1, which is a related technology The microprocessor refers to a block diagram of 7 format 1 0 0. The instructions of the related technology 丨 0 0 has a variable number of data items 1 (H -1 0 3, each item is set to a specific value, and it is composed at the beginning. Microprocessor specific instruction Billion billion. This particular instruction means Shu billion billion

Page 18 200417926 V. Description of the invention (13) shows that the microprocessor performs specific operations, such as moving two operands from memory to an internal 4 plus, or moving registers to memory. Generally speaking, it refers to 2 'or the specific operation to be performed specified from the internal project 102. The address designation meta-item 103 of the transport code item is located in the operation ^ 1〇2 ^ (optional) in addition to the specific operation. Information, such as where the second counts and so on. The command format is 100 and the programmer is allowed to prefix the item with ^ and 101. When the operation code 102 and the horse 102 are not added, the preamble 1 101 is used to indicate whether M is to be executed, and the operation ^ L ★ uses the special architectural features. As a whole, these architectural features can be applied to most of any specified operations in the instruction set. For example, the preamble 01 is stored and stored in the current day; :: Different sizes of operands (such as 8-bit, 16-bit, 32-bit) are executed in different micro-processing states. And when many such processors are programmed with a set operand size (such as 32-bit), they can be coded 1 (H before they are provided by the individual Chinese, still allowing the programmer to choose the H location based on each instruction. Override the default operand size (eg, to generate a bit operand). The operand size that can be selected is just one example of an architectural feature. In many modern microprocessors, these architectural features can be applied In most cases, the operation code 102 can be used to specify operations (such as addition, subtraction, multiplication, human logic, etc.). Lin [0 035] The instruction format shown in Figure 1 is 00. There is a well-known example in the industry. This is the x86 instruction format 100, which is used by all modern x86 microprocessors. More specifically, the X86 instruction format 10q (also the x86 instruction set architecture 100) uses 8 bits. Prefix 101, 8-bit transport

200417926

= 102 and 8-bit address designation element 103. The χ86 architecture 100 also has several ^ setting codes 101, two of which replace the preset address / size of the χ86 microprocessor (that is, the opcode states 66Η and 67Η), and the other indicates the microprocessor j According to different translation rules, interpret the following operation code byte 102 (that is, the f code value is 0FH, which makes the translation action based on the so-called two-byte operation code rule). Setting the code 丨 〇1 makes the special operation repeated until the repetition condition is satisfied (that is, the REp operation code: f〇h, F2H, and F3H). [0 0 3 6] Please refer to FIG. 2, which shows a table 200, which is used to describe how the instruction 2 of the set = architecture corresponds to an 8-bit = opcode byte in the instruction format of FIG. 1 Bit value of 102. Table 袼 200 shows an example of the 8-bit operation figure 2000, which associates up to 256 values of an 8-bit opcode item 102 to the corresponding microprocessor opcode instruction 2 〇1. Table 20 maps a specific value of the operation code item 102, such as 〇2H, to a corresponding operation code instruction 2101 (that is, instruction 1202 2101). In the example of the χ86 opcode diagram, it is well known in the art that the opcode value 14 ^ is an Add With Carry (ADC) instruction to χ86. This command will make an 8-bit direct ( The immediate) operand is added to the embedded value of the temporary storage state AL ^. Those skilled in this field will also notice that the above-mentioned Ke code 101 (ie, 66H, 67H, 0FH, F0H, F2H, and F3H) is a different code value of 001, which is in a different context. , Specifies that a specific ', ^ structure extension is to be applied to the operation specified by the subsequent opcode item 丨 〇2. = For example, in the operation code 14h (normally, the aforementioned ADC operation code) 刖 plus W setting code 0FH, will make the χ86 processor perform a "decompression and interpolation

Page 20 200417926 V. Description of the invention (15) Low-precision single-precision floating-point value "(Unpack and interleave

Low Packed Single-Precisi〇n Floating-Point

Values) operation 'instead of the original ADC operation. Such characteristics as described in the example 6 are partially enabled in modern microprocessors. This is because the instruction translation logic in the microprocessor is to sequentially interpret an item 100 of an instruction 1 (H-1 , 0 3 ^ So in the past, the use of specific opcode values as the preamble 101 in the instruction set architecture allowed microprocessor designers to incorporate many advanced architectural features into the design of microprocessors compatible with legacy software Without causing a negative impact on the execution of the old programs that are not in the specific state of ::: For example, an old program that did not use the x86 opcode 0FU can still cry on today's x86 microprocessing上 博 荇 品 荖! Field ^ π _ w. And a newer application, by using the nose code 0FH as the preamble 101, can use many new construction features' such as a single command multiple data, Different, conditional movement operations, etc. Mind [0037] Although it has been used in the past, the operation code value 2 is made 4 =: available; V: redundant or unreferenced / indicator 101 or escape instruction 101): : ,,, architectural features Instruction set architecture 100 has been-very 5; soil features, but Multi # Enhancement on this: all available / excessive opcode values have been used: y, ik for power, all opcodes in opcode map 200 are used, that is, when all available values are assigned as op v2 Value = structurally specified. Shi Yi '^ Shima Project 1 〇 2 or Lunba r Zhuang π 重 2 There are remaining operating values can be used to incorporate new features 101 exist in many microprocessor architectures today, and = juice The scholars added architectural features and retained the old program: Rong m

Page 21

200417926 V. Description of Invention (16) Make a choice. [0 0 3 8] It is worth noting that the instruction 2 shown in Figure 2 is expressed in a general way (ie, 24, 186), and does not specifically refer to the actual operation (such as carry accumulation, subtraction, mutual Scold or). This is because, in some different microprocessor architectures, the fully occupied operation code figure 200 has already excluded the possibility of incorporating newer progress in the architecture. Although mentioned in the example of Figure 2, the 8-bit opcode item 丨 〇2, those skilled in the art will still notice that the specific size of the opcode 102, except as a special case, discusses the completely occupied code. Apart from the problems caused by the structure 2000, other aspects have nothing to do with the problem itself. Therefore, a fully occupied 6-bit opcode map will have 64 opcodes / preambles 201 that can be architecturally specified, and will not provide usable / excessive opcode values for expansion. [0 0 3 9] Another alternative is not to completely abandon the original instruction set and replace it with a new format 100 and operation code figure 20 (), but only for one existing operation. The code 201 is replaced with a new instruction meaning, as shown in the operation codes 40H to 4FH in Figure 2. With this hybrid technology, the microprocessor can operate independently in one of two modes: the old mode uses the opcodes 40H-4FH, which still has rules to interpret, or an improved mode (enhanced mode) operation. At this time, the operation code 40H_4FH is interpreted according to the enhanced architecture rules. This technology does allow designers to incorporate new features into their designs. However, when a microprocessor that conforms to the old specifications operates in enhanced mode, the disadvantages still exist because the microprocessor cannot perform any application that uses the opcodes 40H-4FH. Program. Therefore, from the standpoint of retaining legacy software compatibility, technologies that are compatible with legacy software / enhancement models are not the best choice

Page 22 200417926 V. Description of Invention (π) Choice. [0 0 4 0] However, for the instruction set 2 0, where the opcode space has been fully occupied, and the space covers all applications running on microprocessors that conform to the old specifications, the inventor of this case has noticed Among them, the use of the operation code 201, and they also observed that although some instructions 202 are specified architecturally, they are not used in applications that can be executed by the microprocessor. The instruction I F 1 2 0 2 described in FIG. 2 is an example of this phenomenon. In fact, the same opcode value 2 0 2 (ie F 1 Η) is mapped to a valid instruction 2 02 that is not used in the χ 8 6 instruction set architecture. Although the unused 6 instruction 202 is a valid x86 instruction 202, which instructs to perform a structurally specified operation on a x86 microprocessor, it is not used in any that can be executed on a modern x86 microprocessor. Application. This special χ86 instruction 202 is called the In Circuit Emulatlion Breakpoint (ie ICE BKPT, and the opcode value is F1H), which were previously used exclusively

In a microprocessor analog device that no longer exists. ICE 202 has never been used in applications other than in-circuit simulators, and the previous in-circuit simulation devices that used ICE ΒΚΡΤ 202 are no longer x86. The inventor of the present invention—a person who knows that The same work was found within the occupant structure 200. The sakura field seven L / x ^ The eight hunters used a valid but unused opcode 2 0 2 to allow the micro-processing of the crying grappler's sigh. Included in the advanced hibiscus 牿 ΐ-II: Need to sacrifice Λ software compatibility. In the "completely occupied instruction" in the wooden structure 200, the present invention uses a structured calculation code 202 as an index mark: "ren unused transport code" therefore allows the microprocessor designer to make it; Up to 2n latest development frameworks 200417926 V. Description of the invention (18) The structural features are incorporated into the design of the microprocessor while retaining full compatibility with all old software. [0 0 4 1] The present invention provides an n-bit extended interrupt suppression designated meta-preamble to use the concept of preamble mark-extended preamble, thus allowing programmers to perform the entire execution of an extended instruction Procedure, specifying the corresponding interrupt processing to be suppressed. In another embodiment of the present invention, execution of the extended instruction and a specific number of instructions thereafter is excluded from the interrupt processing mechanism of the microprocessor. The invention will now be discussed with reference to Figs.

[0 0 4 2] Now referring to FIG. 3 ', it is a block diagram of the extended instruction format 3 0 0 of the present invention. It is very similar to the format 100 discussed in Figure 1. The extended instruction format 300 has a variable number of instruction items 301-305. Each item is not combined with ^ special values to form a microprocessor ^ * Specific instructions 3 0 0. The specific instruction 3 0 means that the microprocessor does not perform a specific operation, such as adding two operands or moving an operand from a memory to a register of a microprocessor. Generally speaking, the operation code item 3202 of the instruction 3 0 0 specifies the special operation to be executed, and the selected address designation meta item 3 0 3 is located after the operation code 3 0 2 to specify the specific operation. Related additional information, such as how to perform the operation, the register in which the operand is located, the direct and indirect data of the memory address used to calculate the source / result operand, and so on. The instruction format 300 also allows the programmer to add a preamble item 301 before an operation code 3 02. When a specific operation specified by the operation code 3 02 is performed, the preamble item 3 0 1 is used to indicate whether to use an existing architectural feature. [0 043] However, the extended instruction 300 of the present invention is a superset of one of the instruction formats 100 of the foregoing FIG. 1 and has two additional items

200417926 V. Description of the invention (19) 3 0 4 and 3 0-5 can be selectively used as instruction extensions, and placed in a box extension instruction 30. All remaining items in 30 ". 3 Dagger 乂 _5 ’which is an extension instruction 30. Part of y; y; decide whether to suppress or eliminate interrupt processing of the extended instruction. ^ 304 and 305 series-extended instruction mark 304 and an extended set of 305. The extended instruction mark 30 is another set in a microprocessor instruction set:; the designated operation code is constructed. In the 186 embodiment order, the extension refers to the human data 304, or the escape tag 3 () 4, which is cut with the state of the operation code, and the ICE Μρτ instruction previously used but not abandoned. The escape mark 304 will be treated as a logical finger it} 'The extended preamble 3Q5, or extended feature finger 3 0 5' is followed, in which the extended preamble 3 05 specifies whether to suppress ; Broad :: Let 3 to 00 interrupt processing. In a specific embodiment, the escape tag Chuan-yu-e ', a companion part of the extension instruction 300, 30b 303 and 3505—the operations to be performed by the microprocessor. Interrupt suppression designation element 305, extended preamble 3 05, specifies that the operation needs to be performed continuously, that is, the effect of pending interrupts is not ^, and a microprocessor that meets the old = specification is in In other cases, pending interrupts are allowed. As the operation is completed, interrupt processing is re-enabled. In another implementation, the extended preamble 30 5 indicates that the operation covers a plurality of instructions, where delay = instruction 3 0 0 is the first instruction, and the operation specified by these instructions must not be changed during execution. Suspended due to interrupt processing. [0 0 4 4] Here, the instruction-level interrupt suppression technology of the present invention =. An extended instruction 300 is configured to specify that an operation is to be executed according to two microprocessor instruction sets. The execution of the extended instruction 300 is 200417926.

, =-Completed before pending interrupt. The extension instruction 300 includes one of the operation codes 3G4 of the existing set—and the day 3 before the extension of m. The selected operation code 304 is used as an index 304 to refer to the two :: extended feature instruction 30 ", that is, it specifies the microprocessor structure, = term 丄 ', and the feature code of the n "Liyuan 3 05 indicates that suppression is required ^ In a specific embodiment, a woman with an extended preamble of 305 octets can specify the interruption of the -instruction and a maximum of 25 5 subsequent instructions. Interrupt processing of a small number of instructions, other two specified by the remaining bits of the preamble 3G5 extension f :, the embodiment of the preamble 'can specify a maximum of 2n] 7. Interrupt processing 'Or various combinations of suppression interrupt processing as described above and others. [0045] Referring now to FIG. 4, a table 400 shows how the designation of interruption suppression is mapped to the bit π logic state of an 8-bit extended preamble embodiment according to the present invention. Similar to the operation code discussed in FIG. 2, the table 40 in FIG. 4 and the table 40 in FIG. 4 show an example of an 8-bit extended preamble figure 400, and an 8-bit extended preamble item 3 is straightforward. A maximum of 256 values of 5 are related to the two-character σ old specification microprocessor, and some instructions 401 (such as E34, etc.) interrupt interruption corresponding. In a specific embodiment of χ86, the 8-bit extended feature preamble 3005 of the present invention is provided to the order-level control of interruption suppression 401 (ie, ε〇〇_ EFF). These interrupt suppressions are not specified by the current X 8 6 instruction set architecture. [0046] The extended feature 401 shown in FIG. 4 is expressed in a general manner rather than specifically referring to actual features. This is because the technology of the present invention is applicable

Page 26 200417926 V. Description of the invention (21) In various architecture extensions 401 and specific instruction set architecture. Those skilled in the art will find that there are many different architectural features 401, some of which have been incorporated in the above k and 'can be used in accordance with the escape tag 304 / extended preamble 3 0 5 technology described herein An existing instruction set. The 8-bit preamble embodiment of FIG. 4 provides a maximum of 256 different features 401, while an η-bit preamble embodiment has a stylized selection of up to 2 η different features 401. . [0 0 4 7] Please refer to FIG. 5, which is a block diagram illustrating a pipelined microprocessor 500 for performing selective interrupt suppression according to the present invention. The microprocessor 500 has three distinct types of stages: extraction, translation, and execution. The fetch stage has fetch logic 501, which is coupled to the bus unit 516 to fetch instructions or macro instructions from a memory 5 1 5 which is usually located outside the microprocessor 500. The bus unit 5 1 6 is coupled to the memory 51 5 through a system bus 51 9. The fetch logic 501 sends the fetched giant instruction to a giant instruction queue 503, which is read by a translation logic 505. The translation logic 505 is coupled to a micro-instruction queue 508. The translation logic 505 includes an extended translation logic 506. The execution stage has an execution logic 509, which contains an extended execution logic 510. [0 0 4 8] According to the present invention, during operation, the translation logic 505 sends the index or address (N I P) of the next instruction to the fetch logic 501 via the N I P bus. The fetch logic 501 sends the address of the next fetch instruction to the bus unit 5 1 6 through the command bus 502. The bus unit 5 1 6 communicates with the memory 5 1 5 through the system bus 5 1 9 to fetch huge instructions, and sends these instructions to the fetch logic 501 through the command bus 5 2. Those skilled in the art will find that Figure 5 is simplified for clarity, so it does not include this

IHII Circle Page 27 200417926

Domains commonly use the mechanism of cache giant instructions, such as internal instruction cache memory (not shown in the figure). According to the present invention, the fetch logic 501 then sends the formatted instructions to the instruction queue 503 in the execution order. These instructions are fetched from instruction queue 503 and sent to translation logic 505. The translation logic 505 translates each incoming instruction into a corresponding microinstruction sequence to instruct the microprocessor 500 to perform the operation specified by the giant instruction. According to the present invention, the extended translation logic 506 detects those instructions with extended preamble flags to perform translation of the corresponding extended interruption suppression preamble. In a χ86 embodiment, the extended translation logic 506 is configured to detect an extended preamble flag whose value is ηΗ, which is an ICE BKPT operation code of x86. The extended microinstruction bit is provided in the microinstruction queue 508 to specify that the interrupt processing of the operation specified by the instruction accompanying section is to be suppressed. Other embodiments of extended translation logic 506 'may specify in the extended microinstruction field that interrupt processing of one of the first giant instruction of the present invention and a certain number of subsequent giant instructions is to be suppressed.

[0 0 4 9] The microinstruction is sent from the microinstruction column 5 08 to the execution logic 5 9 ', where the extended execution logic 5 1 0 is configured to execute a specific operation designated by the micro instruction. For a micro instruction corresponding to a translated giant instruction, if an interrupt is enabled during its execution, the interrupt control logic 5 1 8 in the microprocessor 5000 will have one or more interrupt pins 5 1 7 The enable of this interrupt was detected. The interrupt control logic 5 1 8 informs the logic in the microprocessor via a signal I N T that an interrupt is waiting to be processed. Without the extended instruction of the present invention, the translation logic 505 sends the address of the interrupt handler to the fetch logic via the bus 504 to initiate a series of interrupt processing events. At the same time, the execution logic 509 completes the execution of the current microinstruction and clears the pipeline. because

Page 28 200417926 V. Description of the invention (23) Therefore, the microprocessor 500 starts fetching, translating, and executing instructions to confirm the pending interruption 'and to determine which device has enabled L I N τ 51 7. When these instructions are executed, the execution logic sends a request to interrupt the bus cycle via the INTACK bus 513 to the bus unit 5 丨 6. The bus unit 5 1 6 uses a programmable interrupt controller 5 14 located in the system bus 5 1 9 to process this interrupt and confirm the bus cycle to determine the device that enables [I n τ 5 1 7. At this time, the address of one of the specific interrupt service routines (also known as interrupt vectors) of the operating system is usually received from L I NT 5 1 7 and is assigned to service the interrupt-enabled device. The bus unit 5 16 extracts the interrupt vector and sends it to the execution logic 509 through the I N T A C K bus 5 1 3. The execution logic 509 is then routed to the translation logic 505 by the I N T A D D R bus 5 1 1. The translation logic 505 sends the interrupt vector to the extraction logic 501 through the extraction bus 504, and the extraction logic 501 starts to extract the instruction corresponding to this interrupt vector to process the confirmed interrupt. For the sake of brevity, the previous description of the middle processing has omitted specific details on how the status of the interrupted application is stored and restored. Those skilled in the art will recognize that these details depend on the microprocessor architecture to which the invention is applied. [0 0 5 0] When the extended instruction of the present invention is fetched and executed, the extended translation logic 5 in the translation logic 5 0 will block the delayed micro-instructions in the corresponding 澂 instruction sequence (not shown in the figure) It is configured to indicate that interrupt processing will be suppressed until the corresponding microinstruction sequence is completed. Therefore, the execution logic 5 10 in execution logic 509 will ensure that these micro instructions complete execution without interruption. When an interrupt is enabled via LINT 51 7 ^ As mentioned above, the translation logic 505 will wait until the microinstruction is executed before starting a middle school. 200417926 V. Description of the invention (24) Interrupt handler. The execution logic 5 0 9 indicates that the micro instruction has been executed by enabling the c MP signal 5 1 2. The interrupt control logic 518 informs the translation logic 505 that the execution is completed by enabling the GOINT signal 507. When ⑶ 丨 NT 507 is enabled, the translation logic 505 will start the interrupt handler, as described earlier. [0051] Therefore, the extended execution logic 510 indicates to the translation logic 50 5 via the GO NT signal 507 that the interrupt processing is started by setting the CMP signal 512. In the absence of the extended instructions of the present invention, when an interrupt

When L INT 5 1 7 is generated, CMP signal 51 2 is set after the current micro instruction is executed. If there is an extended instruction that indicates that interruption is to be suppressed, the extended execution logic 5 10 delays the setting of the C MP signal 5 12 until all corresponding micro instructions are executed. [0052] As mentioned earlier, most microprocessor architectures have interrupt processing enabled and disabled, and usually only operate at privileged levels that are not assigned to applications / applications. In an X 86 compatible microprocessor, the deer program cannot set and clear the energy bit (not shown) in the χ86 flag register (not shown). However, the present invention provides a mechanism that allows an application programmer to drive the microprocessor 500 to disable interrupts at the instruction level, so that "at mic" operations can be performed without interruption. In addition, * 1 The invention's designation of interrupt suppression can also replace interrupt processing by other architecture functions ^

Disable the assignment. In an X86 embodiment, the infringement caused by the invention and the slave slave %% refers to the current screen level suppression interrupt, which will replace the designation of the interrupt enable bit in the flag register, ie, 疋. π [0 0 5 3] Those skilled in the art will find that Fig. 5_ processor 500 is a simplified processing result of modern pipelined microprocessor 50. thing

Page 30 200417926 V. Description of the invention (25) In fact, the modern pipelined microprocessor 500 can order up to 30 different pipeline stages. However, these stages can be generally classified into three stages shown in the block diagram. Therefore, the block diagram 500 of FIG. 5 can be used to clearly describe the necessary elements required for the embodiment of the present invention. For the sake of brevity, unrelated components in the fWay's 500 are not shown and are not discussed. [00 54] Please refer to FIG. 6, which is a block diagram of an exemplary embodiment of an extension code 600 in the microprocessor 500, which is used to specify that the corresponding interrupt processing of an extended instruction is to be suppressed. The interrupt suppression preamble 600 has an 8-bit size and includes an interrupt suppression field 601. In a specific embodiment, the suppression stop 601 specifies that when the extended instruction is executed, the corresponding interrupt processing is to be excluded. Another specific embodiment includes an interrupt suppression stop 601 that can specify that the extended instruction and the interrupt processing of the subsequent maximum of 255 instructions are to be excluded. The number of instructions executed during interrupt suppression is displayed by the suppression bit 601. [0055] Please refer to FIG. 7, which is a detailed block diagram of the logic 700 of the transformation stage of the microprocessor 500 in FIG. 5. The translation stage logic 7000 has a finger = buffer 704, which provides an extended instruction to the translation logic 705. Translation logic 705 is coupled to a machine-specific temporary

Memory (machine specific register) 70 2. The translation logic 705 has a translation controller 706, which provides a DISABLE signal 707 to an escape command detector 708 and an extended preamble translator 708 g. The escape instruction debt tester 708 is coupled to the extended preamble translator 709 and an instruction translator 710 ° extended preamble translator 709 and instruction translation logic 7 10 access to a control read-only memory ( ROM) 711, which stores corresponding extension instructions

Page 31 200417926 V. Template micro instruction sequence of invention description (26). Translation logic 705 also includes a microinstruction buffer 712, which has an opcode extension field 713, a microop field 714, a project field 715, and a source block? 16 and-Shift the field 7 1 7. [0 0 5 6] In operation, during the start-up of the microprocessor, the state of the extension field 703 in the specific register 70 2 of the machine cry is determined by the signal power-up state 701 To indicate whether the particular microprocessor can translate and execute the extended instructions of the present invention. The machine-specific temporary cry 70 2 sends the status of the extended feature field 7 03 to the translation controller 7 06. The translation control logic 70 6 controls the instruction fetched from the instruction buffer 704 to be translated according to the user, the extension translation rule, or the conventional translation rule. If the extended feature is divided into ', the finger with the opcode status selected as the extended feature mark will be translated using translation rules according to practice. In an x86 specific implementation example 7, 7, ’selects the opcode state F 1 Η as a mark, and then encounters it under the conventional translation rules? 111 will cause an illegal instruction exception (^ (: 61) 1: 1〇11). In the case where the extended translation function is disabled, the instruction translator 7 10 translates all the sent instructions 704, and administers all the fields 713-717 of the micro instruction 712. 'However, under the extended translation rule, if a tag is encountered, it will be escaped. The escape instruction detector 708 will refer to the μ μ, 9: the 4th day does not extend the code translator 7 0 9 to translate the extension 1 preamble part of the extended instruction according to the extended translation rule, and configure the operation code The extension field 7 1 3 is interrupt processing of a micro instruction sequence corresponding to an a-type extension instruction. In the embodiment of Ganai, the extended preamble translator 709 interprets the extended preamble part of the extended instruction according to the extended translation rule, and applies all relevant micro-codes to nine of a series of giant instructions.

Page 32 200417926 V. Description of the invention (27) The operation code extension field of the instruction 7 1 3 is configured, and the extended instruction is the first instruction of this series of giant instructions, and the preamble translator 7 0 is extended. 9 It has been learned from an extended preamble that the extended instruction and subsequent subsequent giant instructions are to be executed continuously. The instruction translator 7 1 0 translates the rest of the extended instruction, and configures a micro-op code field 714, a source block 71 6 'destination field 71 5 and a displacement field 71 7 of the micro instruction 712. Certain specific instructions will cause access to the control ROM 1 0 1 1 to obtain the corresponding microinstruction sequence template. The configured micro-instruction 7 1 2 is sent to a micro-instruction queue (not shown in the figure) for subsequent execution by the processor. [0057] When the translation logic 705 is informed via IMT signal 718 that there is an interrupt waiting to be processed, 'the translation action will continue until G〇 丨 NT signal 7 丨 9 is set', that is, a continuous micro-instruction sequence now executed Until execution is complete. When G0INT 719 is set, the translation logic 705 starts the interrupt handler as described above. In all embodiments, the translation logic 705 is to translate all the giant instructions to be executed without interruption before starting the $ break handler. y 〇〇58] Please refer to FIG. 8, which is a block diagram of the stage logic 800 in the microprocessor 500 of FIG. 5. The execution stage logic 800 has a suppression count logic 806 that generates a CMP signal 809, and an interrupt confirmation logic = 7 ', which starts an interrupt confirmation cycle via the lNTACK bus 800. According to: Row Logic 8 ° 5 receives data operands from an extended microinstruction buffer 801, 1'7, and 1 'data buffers 802-804. In the exemplary embodiment shown in FIG. 8, the logic 0805 flag register 811-interrupt enable bit 2 is extended to determine the operating system software temporarily.

Page 33 200417926 V. Description of the invention (28) Interrupt processing has been enabled

[0 0 5 9] In the inter-operation, the micro-instruction and its related operands are executed by extending the micro-instruction buffer 801 and the operand buffer 802-804. During the execution of the microinstruction corresponding to the conventional giant instruction, according to the conventional interrupt processing rules, the suppression counting logic 806 must ensure that the Cmp signal 809 remains set to show that interrupt processing may occur. In a specific embodiment, if I E 8 1 2 is not set, it means that the interrupt is disabled, and αρ 8 0 9 is not set. When the microinstruction to be interrupted is inhibited from being sent during execution, the inhibit count logic 806 will wait until all extended microinstructions have been executed before setting the CMP signal 809. In one embodiment, an extended field (not shown in the figure) of the first microinstruction of a continuous microinstruction sequence indicates that a certain number of microinstructions are to be executed continuously without interruption. In this embodiment, before the CMP 80 9 is set, the suppression counting logic 80β is also counted when the subsequent microinstructions are executed to ensure uninterrupted execution. As mentioned earlier, the extended microinstruction to specify the suppression interrupt will replace the state of the flag register 8u, the work of E 8 1 2. When an interrupt is processed, the interrupt confirmation logic 807 will start an interrupt confirmation bus program via the I NTACK bus 808 to determine the vector of pending interrupts. This vector is sent to the translation logic via the INT ADDR bus 810 (not shown in the figure).

[0 0 6 0] The important technical features of the present invention (as described in Sections 3 to 8) are collated here. The present invention can provide a programmable mark-preamble combination in an extended instruction by using an operation code that is specified according to the architecture but not actually used as a mark. In a specific embodiment, the uranium coding is used to indicate that a microprocessor that meets the old specifications only suppresses

Page 34 200417926 V. Description of the invention (29) Interrupt processing of the extended instruction. On the other hand, it indicates that the microprocessor which conforms to the old specification =, the preamble interrupts the processing of a certain number of instructions. When the extended finger instruction and subsequent inventions extend the micro-finger through extended finger instructions, according to the content of the bit, the corresponding ^ code extension item 该 of the extended instruction should be suppressed. In another embodiment, the interrupt processing of the first two = columns should be extended and followed by a certain number of instructions: 疋 To be suppressed-the opposite is to determine the subsequent instructions to be continuously executed = 1, ', extended translation logic extension Micro-instruction blocking to ensure uninterrupted execution #: 亚 依此 Configure extension [006 1] Therefore, the invention's compiler (aut （ated eQde and / or automated code mechanism can be used to indicate compliance with the old # P1: 1011 device) A kind of interruption of order or instruction group; sale; processor to suppress single-finger system, these existing architectures mostly use this service as the limit of processor architecture. Here the application programmers are given a routine go mechanism, because they are not limited to special-purpose giant instructions that can only write continuous operations. Use-or two to ensure continuity [0062] Please refer to Figure 9, ii ^ ^ ^ ^ ^ ^ ^ 4 .1! ^ 'Λ # V „^ ^ The operation of the method of extraction, translation and execution = rational Said 'enter the block 902, one of which is configured with a 1-way open-end processor. The process then proceeds to the block's program, which is sent to the micro-test 〇06 in Fanggu Block! 〇 04' The next instruction is fetched to enter the pipeline of the microprocessing state. The flow then proceeds to the judgment block. 200417926 V. Description of the invention (30) [0 0 6 4] The judgment block g 〇6 is evaluated to determine whether the packet Sequence. In an x86 embodiment, the operation of suppressing the specified meta-item is interrupted to the extended escape code and subsequent items do not detect the extended escape code and delay 908. ', [0 0 65] in block 9 In 〇8,-the extended item corresponding to the microinstruction sequence suppresses the interruption point 91 when the sequence is executed. ^ [0066] In block 910, to determine a specified operation, temporarily = specified element and according to the existing micro [00 6 7] In block 912, ,, 'to specify the specified operation and its Proceed to block 914. [0068] In block 914,, send to a microfinger in the order of execution. The process then proceeds to the judge [0 069] at judge block 9 16 = interruption of reason. If not, then The flow process proceeds to block 918. In the finger extracted in block 904, an extended escape code-extended preamble is included, and the evaluation is used to detect a code value FI (ICE BKPT). If the detection ', the flow proceeds to block 910. If the finger is extended, the flow proceeds to the extended translation logic in the block microprocessor. In the field,' specify the corresponding micro-numerology. The flow then proceeds to the block. All other parts of the instruction are transferred to the position of the operand of the dump register and the instruction set of the memory bit processor, and the flow indicated by the preamble proceeds to block 91 2. The translation logic generates an extension of the operation code corresponding to the extended microinstruction sequence. The sequence of micro-instructions is listed in the processing order of the translation device and executed by the microprocessor in block 916. The evaluation is performed to determine whether there is a process to proceed to block 926. If so, then

Page 36 200417926 V. Description of the invention (31) [0 070] In block 918, the execution of an existing micro instruction is completed. The flow then proceeds to decision block 920. [0071] In decision block 920, the delay suppression field of a subsequent microinstruction is evaluated to determine whether it is to be executed without interruption. If so, the process proceeds to block 9 2 2. If not, the flow proceeds to block 9 2 4. [0 0 72] In block 922, because continuous operation has been detected in decision block 92, the execution of the next microinstruction is started, and the flow also proceeds to block 9 1 8 where the next microinstruction becomes Micro-instruction currently executed. [0 073] In block 924, because the interrupt has been detected in block 916 'and the extension field of the next microinstruction is not designated to suppress interrupt processing, the translation logic in the microprocessor before processing the pending interrupt, Transfer control to the microcode of the interrupt handler to save the current execution: ^ Use private state. The flow then proceeds to block 9 2 6. [0074] In block 926, the method is completed. [0107] Although the present invention and its objects, features, and advantages have been described in detail ^ 'other embodiments may also be included in the scope of the present invention β. For example, Ming has described the following technology: Use the state of the operator-single-single, unused operation code that has completely occupied the person 2 as the standard: :: shelf = extension feature preamble. However, the scope of the present invention is "[after not limited to the instruction set architecture that has been fully occupied. From the f side, it is a sub-single tag. On the contrary, the present invention covers non-, instructions, or embodiments with used opcodes." And = = order set, implement the example. For example, consider-there is no unused Yuncai: marked structure. The invention-the specific embodiment includes 200417926 V. Description of the invention (32) The state of the operation code, which is selected It is determined by market factors. Another embodiment includes the use of a special combination of operation codes as a mark, such as the continuous appearance of 7FH with a% code status. Therefore, the essence of the present invention is to use a mark sequence, and thereafter It is an n-bit extended preamble, which allows ^ program / compilation in an existing microprocessor's command set to 'specify the interrupt processing of individual instructions or instruction groups. [0 0 7 6] In addition, although the microprocessor is used as an example to explain the present invention and its objects, features, and advantages, those skilled in the art can still perceive that the scope of the present invention is not limited to the architecture of the microprocessor, but can be Cover other forms of programmable devices, such as signal processors, industrial controllers, array processors, and other similar devices. In short, the above is only a preferred embodiment of the present invention, When it is not possible to limit the scope of implementation of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application for the present invention should still fall within the scope of the patent of the present invention. It is all prayer.

200417926 Schematic description [Schematic simple [0022] Cooperate with the following [0023] block diagram; [0024] instructions, how to bit logic [0025] [0026] architecture characteristics such as logic state; [0027] pipelined micro [0028] Interruption [0029] Block Diagram [0030] Block Diagram [0 03 1] Instructions Related Instructions] The foregoing and other objects, features, and advantages of the present invention will be described and illustrated. A better understanding will be obtained: Figure 1 is a prior art microprocessor instruction format, Figure 2 is a table describing the pairs in an instruction set architecture, and 8 bits in the instruction format of Figure 1 Meta operation code byte state; Figure 2 is a block diagram of the extended instruction format of the present invention; Figure 4 is a table showing how the extension corresponds to an 8-bit extended preamble embodiment according to the present invention Figure 5 of the bit is a block diagram of the selective interrupt suppression control processor using the present invention; Figure 6 is a block diagram of a specific embodiment of the extended preamble used in a microprocessor of the present invention to specify processing Picture; The translation stage logic within the processor thin. FIG eight lines of the execution stage logic within the microprocessor of FIG fine five, nine, and FIG operating system the interrupt processing flowchart of a method of the present invention is used in the description of the microprocessor. , 200417926

Schematic description on page 40 100 Instruction format 101 Preamble 102 Opcode 103 Address designator 200 8-bit opcode figure 201 Opcode value 202 Opcode F 1 Η 300 Extended instruction format 301 Prefix 302 Opcode 303 address designator 304 extended instruction mark 305 extended preamble 400 8-bit preamble figure 401 architecture features 500 pipelined microprocessor 501 extraction logic 502 instruction bus 503 giant instruction queue 504 bus 505 translation logic 506 Extended translation logic 507 G 0 I ΝΤ signal 508 microinstruction queue 509 execution logic 510 extended execution logic 511 INT ADDR bus 512 CMP signal 513 INTACK bus 514 programmable interrupt controller 515 memory 516 bus unit 517 interrupt connection Pin 518 interrupt control logic 519 system bus 600 extended front stone horse 601 interrupt suppression bad bit 700 translation stage logic 701 start status signal 702 Machine-specific register 703 Extended feature field 704 Instruction buffer 705 Translation logic 706 Translation controller 707 Disabling signal 708 Escape instruction detector 709 Extended preamble translator 200417926 Schematic description 710 Instruction translator 711 Control read-only memory 712 Microinstruction buffer 713 Opcode extension field 714 Microcode field 715 Destination field 716 Source field 717 Offset field 718 INT signal 719 G 0 INT signal 800 Run-time logic 801 Extend micro Instruction buffer 802 Data buffer 803 Data buffer 804 Data buffer 805 Extended execution logic 806 Suppression count logic 807 Interrupt confirmation logic 808 INTACK bus 809 CMP signal 810 812 INT ADDR bus interrupt enable bit 811 Flag temporarily Register 9 0 0 ~ 92 6 operation of the method for suppressing interrupt processing in the microprocessor flow

Page 41

Claims (1)

200417926 VI. Scope of patent application 1. A micro-device, including: a translation logic, used to extend an extended instruction including: ^ «— instruction extended interrupt control in the processor for instruction level interrupt suppression control # 成 corresponding microinstructions, where the extended instruction includes: an extended preamble, used to specify that interrupt processing is to be suspended until the execution of the extended instruction is completed; and an extended preamble tag, which is an original instruction set in the existing instruction set According to the operation specified by the architecture; an extended execution logic, coupled to the translation logic, to receive the corresponding microinstruction and complete the execution of the corresponding microinstruction before processing or pending interruption. 2. The device according to item 1 of the scope of patent application, wherein the extended instruction further includes the instruction items in the existing instruction set of the 5th. 3. The device as described in item 2 of the scope of patent application, wherein the instruction item refers to the operation to be performed by the microprocessor, and the pending interrupt should have been processed before the corresponding micro instruction completes execution. 4. The device described in item 3 of the scope of patent application, further comprising: a flag, a register, coupled to the extension execution logic, configured to specify the interrupt processing of the BJ microprocessor, where the extension The prefix 5 refers to the designation that replaces the flag register. The series contains devices such as ·· 4, where the extension performs logic-suppression counting logic and configures A into. Complete the execution of the corresponding microinstruction for Hungary Page 42 mm 200417926 6. Scope of patent application 6. The device described in item 1 of the scope of patent application, wherein the translation logic judges the completion of the execution of the extended instruction, and the translation logic excludes the processing of the pending interrupt. 7. The device according to item 1 of the scope of patent application, wherein the extended preamble includes 8 bits. 8. The device according to item 1 of the scope of patent application, wherein the extended preamble includes: An interrupt suppression field is used to specify that interrupt processing is to be suppressed until the execution of a plurality of giant instructions, wherein the extended instruction is a first giant instruction of the giant instructions. 9. The device according to item 1 of the scope of patent application, wherein the existing instruction set includes an x86 instruction set. 10. The device as described in item 1 of the scope of patent application, wherein the extended preamble mark includes an operation code FI (ICE BKPT) of the x86 instruction set. 11. The device according to item 1 of the scope of patent application, wherein the translation logic includes: an escape instruction detection logic for detecting the extended preamble mark; An instruction translation logic for determining an operation to be executed by the microprocessor and specifying the operation in the corresponding microinstruction; and an extended translation logic coupled to the escape instruction detection logic and the instruction translation logic, It is used to specify that interrupt processing is to be suppressed in the corresponding microinstruction. 1 2. A microprocessor mechanism that extends an existing instruction set to selectively suppress interrupts, including: Page 43 200417926 6. Scope of Patent Application-An extended instruction configured to specify that interrupt processing related to the interrupt is to be suppressed until the execution of the extended instruction is completed, where the extended instruction includes one of the existing instruction set selections An operation code followed by an n-bit extended preamble, the selected operation code indicates the extended instruction, and the extended n-bit extended preamble specifies that interrupt processing should be suppressed; and a translator, It is configured to receive the extended instruction and generate a microinstruction sequence to instruct a microprocessor to suppress processing of the interrupt until the execution of the microinstruction sequence is completed. 1 3. The microprocessor mechanism as described in item 2 of the patent application scope, wherein the extended instruction further includes: the remaining instruction items are configured to specify the operations to be performed by the microprocessor. 14. The microprocessor mechanism as described in item 12 of the scope of the patent application, wherein the pre-code of 004 yuan includes: an interrupt suppression field configured to specify that interrupt processing is to be suppressed until a plurality of The execution of the instruction is completed, wherein the extended instruction is the first one of the giant instructions. 1 5. The microprocessor mechanism as described in item 2 of the patent application scope, wherein the extended instruction instructs the microprocessor to replace the interrupt enable instruction provided by a flag register. 16 The microprocessor mechanism as described in item 12 of the scope of the patent application, wherein the extended preamble of the n-bit bit includes 8 bits. 1 7 · The microprocessor mechanism described in item 12 of the patent application scope, wherein 200417926 VI. Patent Application Existing instruction set is x86 microprocessor instruction set. 1 8. The microprocessor mechanism described in item 12 of the scope of patent application, wherein the selected operation code includes the ICE BKPT operation code (ie operation code F1) in the instruction set of the x86 microprocessor. 19. The microprocessor mechanism according to item 12 of the scope of patent application, wherein the translator includes: an escape instruction detector for detecting the selected operation code in the extended instruction; an instruction A translator for translating the rest of the extended instruction to determine the operation to be performed by the microprocessor; and an extended preamble translator coupled to the escape instruction detector and the instruction translator, Translating the n-bit extended preamble and specifying that interrupt processing is to be suppressed until the microinstruction sequence is completed. 20. The microprocessor mechanism as described in item 12 of the scope of patent application, further comprising: an extended execution logic coupled to the translator to receive the micro instruction sequence, execute the operation, and indicate the micro Completion of instruction sequence execution. 2 1. The microprocessor mechanism according to item 20 of the scope of patent application, wherein the extended execution logic includes: / a suppression counting logic configured to judge completion of execution of the corresponding microinstruction. 2 2. The microprocessor mechanism according to item 12 of the scope of patent application, wherein the translator judges the completion of execution of the extended instruction, and the translator excludes 417926 VI 'Application for Specialist®®--~ --_ ° Mysterious interrupted processing. 23. Eight types of modules that add interrupt suppression features to an existing instruction set, including escape flags, indicate that the accompanying part of a corresponding instruction specifies an operation to be performed, where the escape flag is the existing instruction One of the first opcodes in the set; one interrupt suppression designator, coupled to the escape tag, and one of the accompanying parts, which specifies that interrupt processing should be suppressed until the calculation is completed; a translation logic, For receiving the exit flag and the interrupt suppression designation, and generating a micro-instruction sequence 'to instruct a microprocessor to perform the operation, and the translation logic is used to instruct the interrupt processing to be suppressed until the operation is completed; and The extended execution logic is coupled to the translation logic to receive the microinstruction sequence and complete the execution of the operation before processing the pending interrupt. 2 4 · The handle set described in item 23 of the scope of patent application, wherein the rest of the accompanying part contains a second service code to specify the operation. 2 5 · The module as described in item 23 of the scope of patent application, wherein the interrupt suppression designation element includes 8 bits. 26. The module according to item 23 of the scope of application for a patent, wherein the existing reference set is the x86 instruction set. 7 27. The module as described in item 23 of the scope of patent application, wherein the first code includes the ICE BKPT operation code in the χ86 instruction set, (that is, the operation code is different Page 46 200417926 VI. Patent application scope F1) ° 2 8 · The module described in item 23 of the patent application scope, wherein the translation logic includes: an escape mark detection logic to detect the escape Mark, and indicate that the translation action of the accompanying part should be based on extended translation conventions (convent i 0ns); and a translation logic, which is consumed by the escape mark detection logic to follow the convention of the existing instruction set, The translation operation of the instruction is executed, and the translation of the corresponding instruction is executed according to the extended translation routine, so as to eliminate interrupt processing until the operation is completed. 2 9 · —A method for expanding an existing instruction set architecture to suppress interrupt processing at the instruction level. The method includes: providing an extended instruction, the extended instruction includes an extension mark and an extension prefix, wherein the extension mark It is one of the first operation code items in the existing instruction set architecture; the extension preamble is used to suppress interrupt processing when the extension instruction is executed, and the rest of the extension instruction specifies an operation to be performed; and When an extended instruction is executed, an interrupt is suppressed. 3 〇 The method described in item 2g of the scope of patent application, wherein the specified action includes: using the second operation code item of the existing instruction set architecture to specify the operation. 7 ^ ”31 · The method as described in item 2 of Shenyan ’s patent scope’, where the extension is provided 200417926 The scope of the 4th patent application includes the use of an 8-bit item to configure the extended preamble. 32. The method as described in item 29 of the scope of patent application, wherein the action of providing an extended instruction includes selecting the first opcode item from the x86 microprocessor instruction set architecture. 3 3 · The method as described in item 29 of the scope of patent application, wherein the action of providing an extension instruction includes selecting an x86 ICE ΒΚΡΤ transport code (that is, an operation code F 1) as the extension mark. 3 4 · The method described in item 29 of the scope of patent application, further comprising: translating the extended instruction into a micro instruction sequence j 'The micro instruction sequence instructs an extended execution logic to execute the vehicle' and suppresses interrupt processing until The operation is completed. 3,5. The method described in item 34 of the scope of patent application, wherein the action of the translation extension instruction includes: detecting the extension in a translation logic and translating the extension preamble and The rest 'to generate the microinstruction sequence. _