1281247 九、發明說明： 【發明所屬之技術領域】 一種防靜電之電路板結構及其製造方法，尤指一種電 路板上至少一面形成有防護層，俾可藉由該防護層防止靜 電所產生的放電效應而對接置在電路板上的晶片造成損 * 壞。 【先前技術】 隨著半導體封裝技術不斷進步，該封裝電路板之厚度 ® 由以往之0.13 // m到90nm，再演進至60nm，而未來則可 能進步至45nm以下。又晶片之工作電壓愈來愈低，相對 於晶片來說，其直接忍受靜電衝擊的能力也越低，使得晶 片之品質要求愈嚴苛。為避免晶片受靜電之影響，靜電保 護成為半導體封裝之重要的課題，良好的電路設計必須使 用保護電路以避免靜電累積而放電，造成半導體裝置被靜 電破壞。 • 而積體電路之工作電壓通常為5伏特、3.3伏特或更 小，當積體電路承受較高之電壓時即會損壞積體電路。而 對於摩擦、感應、接觸等所產生之靜電，目前習用之晶片 中，僅有少數會在電路中加入靜電保護電路的設計，以藉 由靜電保護電路以防止靜電對晶片放電而造成損壞。另在 晶片封裝或封膠過程中，若因介質磨擦、感應、接觸而產 生靜電，則在靜電累積至一定量而產生放電現象，則可能 破壞晶片而造成封裝失敗。故在封裝電路板製程中避免靜 電之放電效應損害半導體晶片，而在電路板上形成保護裝 6 18177 1281247 置藉以保護半導體裝置，如本國專利第5G4813號、第 5〇8769號及第519748號等所揭示。1281247 IX. Description of the invention: [Technical field of the invention] An anti-static circuit board structure and a manufacturing method thereof, in particular, a protective layer is formed on at least one side of a circuit board, and the protective layer can prevent static electricity from being generated by the protective layer The discharge effect causes damage to the wafers attached to the board. [Prior Art] As semiconductor packaging technology continues to advance, the thickness of the packaged board ® has evolved from 0.13 // m to 90 nm to 60 nm, and may progress to below 45 nm in the future. Moreover, the operating voltage of the wafer is getting lower and lower, and the lower the ability to directly withstand electrostatic shock than the wafer, the more stringent the quality requirements of the wafer. In order to prevent the wafer from being affected by static electricity, electrostatic protection has become an important issue in semiconductor packaging. A good circuit design must use a protection circuit to avoid electrostatic discharge and discharge, causing the semiconductor device to be electrostatically destroyed. • The integrated circuit typically operates at 5 volts, 3.3 volts or less, and can damage the integrated circuit when the integrated circuit is subjected to higher voltages. For the static electricity generated by friction, induction, contact, etc., only a few of the conventional wafers are designed to incorporate an electrostatic protection circuit in the circuit to prevent electrostatic discharge from being damaged by the electrostatic discharge circuit. In the process of chip packaging or encapsulation, if static electricity is generated due to friction, induction, and contact of the medium, the static electricity accumulates to a certain amount to cause a discharge phenomenon, which may damage the wafer and cause package failure. Therefore, in the process of packaging the circuit board, the discharge effect of the static electricity is prevented from damaging the semiconductor wafer, and the protective device 6 18177 1281247 is formed on the circuit board to protect the semiconductor device, such as national patents 5G4813, 5〇8769 and 519748. Revealed.
/月麥閱第1圖及第2A圖，係為本國專利第5〇4813號 及第508769號之具有靜電放電防護之封裝電路板，係在— 封裒电路板π上設有一晶片區11〇，該晶片區係供接 置一晶片（圖式中未表示），於該封裝電路板u之上下表面 的周邊分別環設有-第-銅網層12及第二銅網層13，而 在該第一銅網層12及第二銅網層13之間則形成一介質層 14，並在底層之第二銅網層13底部形成有一金屬墊16。^ 由於該第一銅網層12及第二銅網層13係呈一電容結構， 2得藉由該第一銅網層12及第二銅網層13以電容的方式 术、〜靜电，並藉由設在第二銅網層丨3底部的金屬墊16靠 在丞屬衣成的載具上以將靜電導除，如此即可避免靜電累 積造成放電效應而損害晶片。 ” 上斤睛麥閱第2B圖，係為上述習知構造之另一實施，於 居第一銅網層12及第二銅網層13形成一貫穿的導通孔 17(Plating thr〇Ugh h〇le)，使該第-銅網層12及第二銅網 a 3連接‘通，如此即可直接由第一銅網層12及第二銅 罔層13 Θβ守集結靜電，並使該金屬塾16靠在載具上，而 可直接將靜電導引至載具，如此即可在製程中避免靜電產 生之放電效應而損壞晶片。 但忒用以集結靜電的第一銅網層12及第二銅網層13 僅環狀繞設在封裝電路板η的周邊上，而靜電產生的效應 非僅有接觸及磨擦，對於非接觸之感應同樣會產生靜電， 7 18177 1281247 f此在封衣$路板之中間部位則無任何的防護，因此容 易造成漏洞，仍有可和、生4、y 曰y 、曾 此&成好電之放電效應而損壞封裝的 二不:致產生封裝失敗的產品，因此對於降低不良率的 生，言長使用時間’以及降低熱量產 之貧聲曰。曰曰电屋越來越低’相對即降低其防止靜電 1 。…防止晶片在封裝過程中受到靜電衝擊損i申&_ 況發生，而在封穿雷敗如一』“衡#知壞的情 雖可防侧:ί 咖峨的結構， 電則無任何的防護，此在㈣』接觸之感應式靜 成晶片損壞。在封穿作孝=過私中仍有可能因靜電而造 已成為封裝製程中重要的課題。威阳片知 【發明内容】 =於前述習知技術之缺失，本發明之 七、-種防靜電之電路板結構及並穿』造 的係在提 擊接置在其上之半導體元件。、’方止靜電衝 本發明之又一目的，係 構及其製造方法之防護層，係 提高防靜電衝擊之效果。、 电路板上，俾以 板其它目的’本發明揭露-種防靜電之電路 八'、、°構主要係包括：一電路板，其上且 之电路 層，且該線路層呈右# I 乂 一線路 忠,千办 層具有複數個電性連接塾；一絕❹ 成在電路板之至少一表面，並 ^層’係形 層具有複數個相對㈣電:一“層’且該絕緣 對於。亥电性連接墊的第—開〇,使該電性 18177 8 1281247 連接墊外露；-防護層係形成在絕緣層上，且該防護層且 有複數個相對於該電性連接塾的第二開口，使該電性連接 墊外路，以及- p方焊層，係形成在防護層及絕緣層上，而 /防4層上具有複數個第二開σ，該第三開口相對於電路 板的電性連接塾，使該電性連接墊外露，又在該防焊層上 形成至少-第四開口，以外露出部份防護層，以提供該防 遠層連接至外部結構作接地。得藉由該防護層吸收靜電， 並將靜電導引至外部結構，俾以消除靜電，以避免對接置 在電路板上的半導體元件造成損壞。 又該電路板上形成錢數個承餘，於 以接置半導體元件。 上用 其中該防護層係為金屬、合今 材料與金屬之混合物等，而得二』=電材料'有機 防止層係全面成形在電路板表面，而得以全面 電饮；板’以避免累積在電路板的靜電產生放 电效應知及爰置在電路板的半導體元件。 本發明進一步提供上述結構之製造方法 一具有複數個電性連接墊的 括· 表面上形成—料层的"路板，於該電路板之至少一 層上形成相對於該電性連接在心緣 墊得以外露1使該電性連接 護層上相絕緣層上形成-防護層，而在該防 上相對於各個電性連接墊上方形成—第 電性連接墊外霞·田 一開口，使该 該防焊層上相：:::該防護層上形成-防焊層’而在 相對方：各個電性連接塾上方形成一第三開口， 18177 9 1281247 使及电陡連接墊外露，並於該防焊層上形成至 口’以外露出部份防護層，使該 ：四開 作接地，以消除靜電對半導雜元件之危=接至外部結構 【實施方式】 σ 、下係藉由4寸定的具體實施例說明 t:熟習此技藝之人士可由本說明書所揭示之::::二 I、％本發明之其他優點與功效。本發明亦可 _ 的具體實施例加以施行或應用，本 ^項=同 可基於不同觀點盥痺 曰中的。項細郎亦 種修飾與變更。 在不恃離本發明之精神下進行各 非以實施例係進—步詳細說明本發明之觀點，但並 非> 以任何觀點限制本發明之範疇。 [第一實施例] 凊參閱第3Α圖至第3D FI及或士 a 靜電之為本發明所揭露—種防 之二路板的製造方法剖面示意圖。 上具Γ ί Γ—圖所示’提供—電路板21，於該電路板2〗 接墊^、線路層211，且該線路層具有複數個電性連 電性傳導a之Γ與電子元件如半導體晶片或其他電路板作 电r生傳導之連接端。 t 3B圖所不’接著於該電路板21之至少—表面上 ::絕緣層22’並覆蓋該該線路層叫。再於該絕緣層 ^成相對於該電性連接塾2山的第一開口 述之電性連接墊2山得以外露。 凊麥閱第3C圖，然後於該絕緣層22上形成一防護層 18177 】0 1281247 23，而該防護層23係為金屬、合金或有機 為有機材料與金屬之混合物，並於該防護層’幻上 個電性連接塾211a上方形成—第二開口 兩性^ 接墊21U外露。 使”玄i性連 ，'請參閱第3D圖，最後於該防護層幻及絕緣層^上 形成一防焊層24，再於該防焊層24上相 接墊^ 相對於各個電性連 ^ 、，形成一弟二開口 241 ’使該電性連接墊2lla外 亚於該防焊層24上方形成至少―第四開π 242,以外 :出部份防護層23。於該第四開口扣則可形成如凸塊 :P)之導電結構（圖式中未表示），而可藉由該導電結構 連接至外部，如此即可將防護層23上之靜電傳導至外部。 主此外，該電路板21上形成有複數個承载區（圖式中未 表不），於該承載區上則用以接置如晶片（chip)之半導體元 件（圖式中未表不;I ’或該半導體元件係嵌埋在多層結構之 電路板21内。1st and 2nd drawings of U.S. Patent No. 5,4813 and No. 508,769, which have electrostatic discharge protection package boards, are provided with a wafer area 11 on the sealing circuit board π. The wafer area is connected to a wafer (not shown), and a - copper mesh layer 12 and a second copper mesh layer 13 are respectively arranged around the periphery of the lower surface of the package circuit board u. A dielectric layer 14 is formed between the first copper mesh layer 12 and the second copper mesh layer 13, and a metal pad 16 is formed on the bottom of the second copper mesh layer 13 of the bottom layer. Since the first copper mesh layer 12 and the second copper mesh layer 13 have a capacitor structure, 2 is capacitively operated by the first copper mesh layer 12 and the second copper mesh layer 13, and is electrostatically charged. The metal pad 16 provided at the bottom of the second copper mesh layer 3 is placed on the carrier of the enamel to guide the static electricity, thereby preventing the static electricity from causing a discharge effect and damaging the wafer. FIG. 2B is another embodiment of the above-mentioned conventional structure, and a through-hole 17 is formed in the first copper mesh layer 12 and the second copper mesh layer 13 (Plating thr〇Ugh h〇). Le), the first copper mesh layer 12 and the second copper mesh a 3 are connected to each other, so that the first copper mesh layer 12 and the second copper germanium layer 13 Θβ can be directly connected to the static electricity, and the metal germanium is adhered 16 is placed on the carrier, and the static electricity can be directly guided to the carrier, so that the discharge effect of the static electricity can be avoided in the process to damage the wafer. However, the first copper mesh layer 12 and the second layer for collecting static electricity are used. The copper mesh layer 13 is only annularly wound around the periphery of the package circuit board η, and the effect of static electricity is not only contact and friction, but also static electricity is generated for non-contact induction, 7 18177 1281247 f. The middle part of the board does not have any protection, so it is easy to cause loopholes. There are still the same, and the 4, y 曰y, and the electric discharge effect of the electric power and the damage of the package are not caused: the product that causes the package failure Therefore, for the purpose of reducing the rate of non-performing, the term "use time" and reduce the poverty of calorie production曰.曰曰Electric house is getting lower and lower 'relatively lowering its anti-static 1.... Preventing the wafer from being subjected to electrostatic shock damage during the encapsulation process, The bad feelings can prevent the side: ί The structure of the curry, the electricity does not have any protection, this is damaged in the (4)" contact inductive static wafer. In the case of cloaking and filial piety, it is still possible to create electricity due to static electricity. It has become an important issue in the packaging process.威阳片知 [Summary of the Invention] = In the absence of the prior art, the seventh embodiment of the present invention, the structure of the anti-static circuit board and the structure of the board are attached to the semiconductor component mounted thereon. Further, another object of the present invention, the protective layer of the system and the method of manufacturing the same, is to improve the effect of antistatic impact. On the circuit board, the board is used for other purposes. The invention discloses an anti-static circuit VIII. The structure mainly includes: a circuit board, a circuit layer thereon, and the circuit layer is right # I 乂A line of loyalty, the thousand layers have a plurality of electrical connections; one is formed on at least one surface of the circuit board, and the layer has a plurality of relative (four) electricity: a "layer" and the insulation is. The first opening of the electrical connection pad causes the electrical 18177 8 1281247 connection pad to be exposed; the protective layer is formed on the insulating layer, and the protective layer has a plurality of second portions relative to the electrical connection Opening, the electrical connection pad externally, and the -p square solder layer are formed on the protective layer and the insulating layer, and the /4 layer has a plurality of second openings σ, the third opening is opposite to the circuit board The electrical connection port exposes the electrical connection pad, and at least a fourth opening is formed on the solder resist layer, and a portion of the protective layer is exposed to provide the remote layer connection to the external structure for grounding. The protective layer absorbs static electricity and directs the static electricity to the external structure. In addition to static electricity, to avoid damage to the semiconductor components attached to the circuit board. The circuit board also forms a surplus of money to connect the semiconductor components. The protective layer is made of metal, and the material is a mixture of metals, etc., and the second "= electrical material" organic prevention layer is fully formed on the surface of the circuit board, and can be fully electricized; the board 'to avoid the static electricity generated on the circuit board to discharge the effect and know that it is placed on the circuit board The present invention further provides a method for fabricating the above structure, wherein a plurality of electrical connection pads are formed on the surface of the substrate, and the circuit board is formed on at least one layer of the circuit board relative to the electrical property. The connection is formed on the edge of the core pad to form a protective layer on the insulating layer on the electrical connection layer, and the upper layer is formed on the protection layer with respect to the respective electrical connection pads. So that the upper layer of the solder resist layer:::: a protective layer is formed on the protective layer and a third opening is formed on the opposite side: each of the electrical connections, 18177 9 1281247 The connection pad is exposed, and a part of the protective layer is formed on the solder resist layer to the outside of the port, so that the four layers are grounded to eliminate the danger of static electricity to the semi-conductive component to the external structure. [Embodiment] σ The following description is by way of a specific embodiment of 4 inches: t: Those skilled in the art can disclose the following description:::: II, % Other advantages and effects of the invention. The invention can also be embodied For example, if the application is implemented or applied, the item can be based on different opinions. The item is also modified and changed. The embodiment is not deviated from the spirit of the present invention. The present invention is described, but it is not intended to limit the scope of the invention in any way. [First Embodiment] 第 Refer to Figure 3 to 3D FI and or a static electricity as disclosed in the present invention - Schematic diagram of the manufacturing method of the road board.上 ί Γ Γ 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' A semiconductor wafer or other circuit board is used as a connection for electrical conduction. The t3B diagram does not follow at least the surface of the circuit board 21: the insulating layer 22' and covers the circuit layer. Further, the insulating layer is exposed to the electrical connection pad 2 of the first opening of the electrical connection 塾2 mountain. The buckwheat is read in FIG. 3C, and then a protective layer 18177] 0 1281247 23 is formed on the insulating layer 22, and the protective layer 23 is made of a metal, an alloy or an organic mixture of an organic material and a metal, and the protective layer is The upper second electrical contact pad 21U is exposed. "Xuanyilianlian," please refer to the 3D figure, and finally form a solder resist layer 24 on the protective layer and the insulating layer ^, and then connect the pad on the solder resist layer 24 relative to each electrical connection And forming a second opening 241' such that the electrical connection pad 2lla forms at least a fourth opening π 242 outside the solder resist layer 24, and a portion of the protective layer 23 is removed. Then, a conductive structure such as a bump (P) can be formed (not shown in the drawing), and the conductive structure can be connected to the outside, so that the static electricity on the protective layer 23 can be conducted to the outside. Mainly, the circuit A plurality of load-bearing regions (not shown in the figure) are formed on the board 21, and the semiconductor component (such as a chip) is connected to the semiconductor device (I' or the semiconductor component is not shown in the drawing). It is embedded in the circuit board 21 of the multilayer structure.
由於該電路板21表面之絕緣層22全面形成防護層 23,而可藉由該防護層23吸收靜電，並藉由形成在第四開 口 242之導電結構以連接至外部結構，如金屬製成之載 具’如此即可在製造過財將可能產生的靜f加以導除， 如制式或非接觸式之摩擦、感應所產生之靜電，以避免 牙貝畜的’ $產生放電效應而造成半導體元件損壞的情況。 *然本發明亦可如第4圖所示，可將該防護層23導接 I線路層211 ’使該防護層23上之靜電得傳導至線路層 211 ’而由線路層211將靜電傳導至其它非電路部位，並與 18177 1281247 而為另種排導靜電的 外。卩接地，俾以將靜電傳導至外部 實施結構。 •路製造方法所製成之結構，係包括:-Since the insulating layer 22 on the surface of the circuit board 21 integrally forms the protective layer 23, the protective layer 23 can absorb static electricity and is connected to the external structure, such as metal, by the conductive structure formed in the fourth opening 242. The vehicle 'can be used to eliminate the static electricity that may be generated in the production of wealth, such as the friction generated by the standard or non-contact type, the static electricity generated by the induction, to avoid the 'discharge effect of the teeth and the semiconductor element Damaged condition. * The present invention may also be as shown in FIG. 4, the protective layer 23 may be connected to the I line layer 211' to conduct static electricity on the protective layer 23 to the circuit layer 211', and the circuit layer 211 conducts static electricity to Other non-circuit parts, and with 18177 1281247, the other is to discharge static electricity.卩 Grounding, 俾 to conduct static electricity to the external implementation structure. • The structure made by the road manufacturing method includes:-
In广上具有至少一線路層211，且該線路層2U 有複數個電性連接塾211a; 一形成在該電路板2 =仏且該絕緣層22具有複數個相對於該電性連接 la的弟一開口 221，使該電性連接墊2na 一 ::_係形成在絕緣層22上，且該防護層23具有· Μ目對於邊電性連接塾2Ua的第二開口 23ι，使該電性 2接:2lla外露;一防焊層⑷系形成在防護層η二緣層 ，而该防焊層24上具有複數個相對於電 =第三開口冰，使該電性連接墊211a外露，又該防焊;& 形成至少一第四開口 24卜以外露出部份防護層23, 口 242形成導電結構以將防護層23上之靜電 參[第二實施例] 1參閱第4圖’係為本發明之又—實施結構剖面示意 圖，與别述貫施例不同處在於該電路板21中形成至少一導 通孔25(plating thr0Ugh hole, ΡΤΗ)，且該導通孔25連接防 護層23,使該防護層23可藉由導通孔乃作接地，同樣得 以達到前述之目的。 一或由該導通孔25將電路板21另面的防護層（圖式中未 表不）導接至該線路層211，而由形成於該防護層23表面 之防瘦層23的第四開口 242以連接至外部，如此即可連通 12 18177 1281247 電路板21兩面的防護層23，並由形成於第四開口 242上 的導電結構以將靜電接引至外部。 [第三實施例] &請參閱» 5A_至第5Β_，係為本發明之又—實施製 ^方去纠面不思圖’與前述實施例不同處在於該靜電防 層26係具有抗靜電及防焊之功能。 如第5A圖所示’提供一電路板21，於該電路板2ι 性ίΐί少—線路層2U，且該線路層211具有複數個電 性連接墊2 11 a。 如帛5B圖所不，接著於該電路板之至少 靜電防護層26，並覆蓋該電性連接墊2na，再於 護層26上形成相對於該電性連接墊2山的第― 二護声6 3述之電性連接墊仙得以外露，而該靜電 4層26具有抗焊及抗靜電之作用。 •藉由：Γ:靜Γ護層26具有抗焊及抗靜電之作用，而可 ·=心電防護層26吸收或阻撞製造過程中可能產生的 本卷明依上述之製造方法製 結構不同處則在於該靜電防護層^有%與:一貫施 之功能。主要係包括：一電路板焊 層扣，且該線路層2„具有複數個電連乂一線路 靜電防婼Β Κ〆 叉双⑽电注運接墊211a ; — 电防叹層26’係形成在電路板2 該靜電防護層26且右递叙七， 表面上，且 第一開口 261，使二該電性連接塾川3的 使“性連接㈣la外露，以提供電路板 18177 13 1281247 _ 21上之靜電得以連接外部電路或電器。 〃由於該睜电防濩層26係具有抗靜電及防焊之功能，而 Μ化製程及結構，俾可降低製造成本，並可提高良品率。 、綜上所述’以上僅為本發明之較佳實施例而已，並非 用=限疋本發明之實質技術内容範圍，本發明之實質技術 3 4係廣義地疋我於下述之中請專利範圍中，任何他人完 去，技術只脰或方法’若是與下述之申請專利範圍所定義 m相同’亦或為同一等效變更，均將被視為涵蓋於 此申請專利範圍中。 【圖式簡單說明】 f 1圖係為本國專利公告第508769號之上視圖； 第A圖及帛2B圖係為本國專利公告 剖視圖； 盆制、m圖至第3E圖係為本發明防靜電之電路板結構及 八衣Xe方法的剖面示意圖； 第係為本發日緖靜電之電路板結構及其製造方法 的另一貫施剖面示意圖；以及 苴制圖至第化圖係為本發明防靜電之電路板結構及 >、衣以方法的另一實施剖面示意圖。 【主要元件符號說明】 11 封裝電路板 110 晶片區 12 第一銅網層 13 弟二銅網層 18177 14 1281247 14 * 16 17 21 211 211a 22 221 、 261 拳23 231 24 241 242 25 26 介質層 金屬墊 導通孔 電路板 線路層 電性連接墊 絕緣層 第一開口 保護層 第二開口 防焊層 第三開口 第四開口 導通孔 靜電防護層In has at least one circuit layer 211, and the circuit layer 2U has a plurality of electrical connections 211a; one formed on the circuit board 2 = 仏 and the insulating layer 22 has a plurality of brothers relative to the electrical connection la An opening 221 is formed on the insulating layer 22, and the protective layer 23 has a second opening 23ι for the electrical connection 塾2Ua, so that the electrical property 2 Connected: 2lla exposed; a solder resist layer (4) is formed on the protective layer η two-edge layer, and the solder resist layer 24 has a plurality of ice relative to the electric=third opening, so that the electrical connection pad 211a is exposed, and Solder masking; & forming at least a fourth opening 24 to expose a portion of the protective layer 23, the opening 242 forming a conductive structure to electrostatically deposit the protective layer 23 [second embodiment] 1 see Fig. 4 In addition, the present invention is different from the other embodiments in that the at least one via hole 25 is formed in the circuit board 21, and the via hole 25 is connected to the protective layer 23 to make the protection. The layer 23 can be grounded by the via hole, and the same purpose can be achieved. Or a conductive layer (not shown in the drawing) of the circuit board 21 is further connected to the circuit layer 211 by the via hole 25, and the fourth opening of the anti-skin layer 23 formed on the surface of the protective layer 23 242 is connected to the outside, so that the protective layer 23 on both sides of the 12 18177 1281247 circuit board 21 can be connected, and the conductive structure formed on the fourth opening 242 is used to conduct static electricity to the outside. [Third Embodiment] &<>>><5>> to 5A_ to 5th _, which is a further embodiment of the present invention - the implementation of the system is not to be corrected. The difference from the foregoing embodiment is that the electrostatic protection layer 26 is resistant. Static and solderproof functions. As shown in Fig. 5A, a circuit board 21 is provided, the circuit board 2 is less than the circuit layer 2U, and the circuit layer 211 has a plurality of electrical connection pads 2 11 a. As shown in FIG. 5B, at least the electrostatic protection layer 26 of the circuit board is covered, and the electrical connection pad 2na is covered, and then the second protection sound is formed on the cover layer 26 with respect to the electrical connection pad 2 6 3 The electrical connection pad is exposed, and the electrostatic 4 layer 26 has anti-welding and anti-static effects. • By: Γ: The static protective layer 26 has the function of anti-welding and anti-static, and the 心·= ECG protective layer 26 absorbs or blocks the manufacturing process, which may be produced according to the manufacturing method described above. The point is that the electrostatic protection layer has a % and a consistent function. The main system includes: a circuit board welding layer buckle, and the circuit layer 2 „ has a plurality of electrical connection 乂 a line of static anti-mite Κ〆 双 double (10) electric injection pad 211a; — electric sigh layer 26 ′ formation On the circuit board 2, the static protection layer 26 and the right reciprocating seventh, the surface, and the first opening 261, the two of the electrical connections of the Sasakawa 3 are exposed, so as to provide the circuit board 18177 13 1281247 _ 21 The static electricity on it can be connected to an external circuit or an appliance. 〃Because the anti-static and anti-welding function of the anti-static layer 26, the deuteration process and structure can reduce the manufacturing cost and improve the yield. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the technical contents of the present invention. The essential technology of the present invention is generally in the following patents. To the extent that any other person finishes, the technology only or the method 'is the same as defined in the scope of the patent application below' or the same equivalent change will be considered to be covered by this patent application. [Simple description of the schema] The f 1 diagram is a top view of the National Patent Publication No. 508769; the diagrams A and B2B are cross-sectional views of the national patent publication; the basin system, the m diagram to the 3E diagram are the anti-static of the invention. The schematic diagram of the circuit board structure and the Xe method of the eight clothes; the first is a cross-sectional view of the circuit board structure and the manufacturing method thereof; and the drawing to the first drawing is the antistatic of the invention A schematic diagram of another embodiment of the circuit board structure and the method of coating. [Main component symbol description] 11 package circuit board 110 wafer area 12 first copper mesh layer 13 two copper mesh layer 18177 14 1281247 14 * 16 17 21 211 211a 22 221 , 261 punch 23 231 24 241 242 25 26 dielectric layer metal Pad conductive via circuit board circuit layer electrical connection pad insulation layer first opening protection layer second opening solder resist layer third opening fourth opening via hole electrostatic protection layer