I279^649twf.d〇c/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種多晶矽薄膜電晶體及其製造方 法，且特別是有關於一種利用金屬誘發側向結晶製程所製 作的多晶矽薄膜電晶體及其製造方法。 【先前技術】 近年末’多aa^薄膜電晶體因具有極高的載子移動 率’所以廣泛地應用在主動式液晶顯示器(AMLCD)、有機 發光顯示器(OLED)以及靜態隨機存取記憶體(SRAM)、動 態隨機存取記憶體(DRAM)、可電除可程式唯讀記憶體 (EEPROM)等元件中。 “ 在多晶矽薄膜電晶體的製程中，多晶矽薄膜的製造必 須考量的重點是製造成本與薄膜品質。在各種多晶石夕薄膜 的製造技術中，金屬誘發側向結晶(Metal Induced Latemi Crystallization，MILC)製程具有較低的生產成本，且可以 製作品質優良的薄膜。然而，金屬誘發側向結晶製程需要 在多晶石夕薄膜電晶體的製程之中增加一次微影钮刻製程， 因此增加了製造成本，而且降低了產品良率。 此外，上述電晶體的通道區是由多晶矽薄膜構成。由 於在多晶矽薄膜的晶粒邊界上，有許多的缺陷(Traps)存 在。這些缺陷會造成元件的載子遷移率降低，以及臨界電 壓飄移(Threshold Voltage Shift)等問題。 【發明内容】 有鑑於此’本發明的目的就疋在提供 >—種多晶秒薄膜 Ι27984Ό 16991twf.doc/g 電晶體的製造方法’以減少-次微影_製程，進而降低 生產成本。 ，發明的再—目的是提供—種多晶销膜電晶體，以 減>、夕晶石夕邊界缺陷所造成的問題。 本發明提出-種多晶石夕薄膜電晶體的製造方法，包括 先提供基板，再於基板上形成一層非晶矽層。铁後，利用 第一光罩’對此非晶糾進行微影_製程，蚊義主動 區。此主動區可以包括數個通道區。接著，於基板上形成 =緣層’覆蓋非奸層。之後，於絕緣層上形成一層 =層’再_第二光罩’對導體層與絕緣層進行微雜 衣私卩於主動區上疋義閘極。閘極兩側的主動區分別 ，源極區歧極區。繼之，於基板上形成—層隔離層，覆 盖閘極與主動區。之後，第三光罩，對隔離層進行微 影侧製程，以於隔離射形成—個結晶製程關口以及 數個接觸®開口。其中，結晶製刻開口暴露出部份非晶 ^層而接觸囱開口則分別暴露出閘極、源極區與汲極區。 隨，進行-個金屬誘發側向結晶製程，以使非晶梦層轉變 為多晶矽層。接著，進行離子佈植製程，以於閘極、源極 區與汲極區内植入離子。之後，於基板上形成一層第一金 屬層，覆盍隔離層並填滿此些接觸窗開口以及結晶製程用 =口。然後，利用第四光罩，對第一金屬層進行微影蝕刻 ，程，以定義數個金屬接點。其中這些金屬接點經由接觸 固開口分別與閘極、源極區與汲極區電性相連。 在上述製造方法中，非晶矽層的形成方法例如為低壓 1279840 16991twf.doc/g 化學氣相沉積法(LPCVD)。而於基板上形成非晶石夕層之步 驟前可於基板上先形成一層緩衝層。此外，絕緣層與隔離 層的形成方法例如為利用TEOS作為反應氣體沉積二氧 化矽。另外，導體層的形成方法例如為低壓化學氣相沉積 法。而第一金屬層的形成方法例如物理氣相沉積法。另」 方面，在形成金屬接點後，更可進行一次合金化製程，例 如是在氮氣環境中以溫度400°C進行30分鐘退火。 而前述金屬誘發侧向結晶製程例如先利用物理氣相沉 積(PVD)於基板上沉積一層如鎳(Ni)、钻(c〇)或鉛(pd)的第 二金屬層，然後進行退火製程，以便造成金屬誘發侧向結 晶。接著，去除未反應之第二金屬層，而去除溶液例如是 硫酸溶液。 此外，前述微影蝕刻製程例如是先進行電子束微影製 程，再進行反應性離子蝕刻製程。 本發明再提出一種多晶矽薄膜電晶體，其是由基板、 至屬誘叙側向結晶多晶石夕層、閘極、隔離層以及金屬接點 所構成。金屬誘發侧向結晶多晶矽層位於此基板玉，此層 是由源極區、汲極區以及數個通道區構成。其中通道區位 於源極區與汲極區之間。此外，閘極位於通道區上。另外， 隔離層覆盍於金屬誘發側向結晶多晶矽層與閘極上。隔離 層包括一個結晶製程用開口以及數個接觸窗開口。結晶製 程用開口暴露出部份金屬誘發侧向結晶多晶矽層，而接觸 囪開口 S別暴露出閘極、源極區與没極區。金屬接點通過 接觸窗開口分別與閘極'源極區與汲極區電性相連。 1279840 16991twf.doc/g 上述夕晶碎薄膜電晶體的源極區與没極區可推雜有磷 離子。此外，閘極包括絕緣層以及導體層，其中絕緣層位 於導體層與金屬誘發側向結晶多晶矽層之間、絕緣層的材 ，包括氧化矽(SiOx)、氮化矽(SiNx)、氮氧化矽(SiQxNy)、 氧化组(Ta〇x)或氧化紹(Α1〇χ)。而導體層的材質包括摻雜 多晶矽。另外，隔離層的材質例如是以TE〇s作為反應氣 體沉積的二氧切。此外，金屬無之材質例如為紹Γ另 一方面，此多晶矽薄膜電晶體更包括一層緩衝層，位於基 板與金屬誘發側向結晶多晶硬層之間。此緩衝層的材質例 如是氧化梦。 本發明的優點是把接觸窗開口與結晶製程用開口在同 -次微影製財完成’因崎低製作的成本。此外，由於 本發明藉由縮減通道區的通道寬度以及閘極長度，以及利 用金屬誘發側向結晶製麵減少通道的多料晶粒邊界的 =，並_適當通道數目的聊’明賴子遷移率並 準確控制臨界電壓的範圍。 目的、特徵和優點能更明顯 並配合所附圖式，作詳細說 為讓本發明之上述和其他 易懂’下文特舉較佳實施例， 明如下。 【實施方式】 -的：w JH5 Α Ϊ t發明較佳實施例之多晶石夕薄膜電 版的衣把/仙私圖。為方便以另—角度解說，圖 在同一位置均有剖面線1 _ I，，圖1B至圖5B分別為沿 1A至圖5八的剖面線卜1，所繪示之剖面圖。 1279840 16991twf.doc/g 首先，請參照圖1A與圖iB。提供基板1〇〇。基板loo 之材質例如是(100)方向之六吋單晶p型矽晶片。接著，在 基板100上形成一層緩衝層(Buffer Layer)i〇2。緩衝層1〇2 之材質例如為二氧化矽，其厚度約為4〇〇奈米。緩衝層1〇2 之作用在於增進基板100與後續形成之多晶矽層的附著 性，以及防止基板100中的金屬離子污染此多晶矽層。然 後在基板1 〇〇的表面上形成一層非晶石夕(Amorphous Silicon ’ A-Si)層。非晶矽層之厚度例如為5〇奈米，其形 成方法例如為低壓化學氣相沉積法(LPCVD)。之後，利用 一光罩10對非晶矽層進行微影蝕刻製程，以定義一主動區 104 ’主動區1〇4包括源極區1〇4a、汲極區與通道區 l〇4c，且可如圖ία呈現數條的通道區1〇4c，以於後續結 曰曰‘私減少其中多晶石夕晶粒邊界的缺陷；此外，也可以選 擇一整個的通道區，而不限於本實施例所述。前述微影蝕 刻製程例如先進行電子束微影製程，再進行反應性離子蝕 刻。 接著，請參照圖2A與圖2B。於基板1〇〇上形成一層 絕緣層106，此絕緣層106覆蓋主動區1〇4。此絕緣層1〇6 之材質例如為氧化矽(Si0x)，其厚度約為25奈米，而形成 方法例如以四乙氧基矽烷(TEOS)為反應氣體進行化學氣 相’冗積。此外，此絕緣層106之材質也可以是氮化矽 (SiNx)、氮氧化矽（si〇xNy)、氧化钽（Ta〇x)或氧化鋁 (Al〇x)。然後，於此絕緣層ι〇6上形成一層導體層ι〇8。 此導體層108之材質例如為多晶矽，其厚度約為150奈米， 1279840 16991twf.doc/g 而形成方法例如以低壓化學氣相沉積法⑽㈣)在約 620度沉積而成。接著，利用—光罩％對此導體層_ 此絕緣層H)6進行微職刻製程，以於主動區购 ς 區104c上疋義構成一個閉極u〇的絕緣層應與= 108。此微純刻製程例如先進行電子束微影製程 ^ 一反應性離子蝕刻製程。 1罨订I279^649twf.d〇c/g IX. Description of the Invention: [Technical Field] The present invention relates to a polycrystalline germanium thin film transistor and a method of manufacturing the same, and more particularly to a metal induced lateral crystallization process A polycrystalline germanium film transistor and a method of manufacturing the same. [Prior Art] At the end of the year, 'multi-aa film transistors have a very high carrier mobility', so they are widely used in active liquid crystal displays (AMLCDs), organic light-emitting displays (OLEDs), and static random access memories ( SRAM), dynamic random access memory (DRAM), and electrically erasable programmable read only memory (EEPROM). "In the process of polycrystalline germanium film transistors, the fabrication of polycrystalline germanium films must focus on manufacturing costs and film quality. Metal Induced Latemi Crystallization (MILC) is used in various polycrystalline film manufacturing techniques. The process has a low production cost and can produce a good quality film. However, the metal induced lateral crystallization process requires a lithography button process in the process of the polycrystalline film transistor, thereby increasing the manufacturing cost. Moreover, the yield of the product is lowered. In addition, the channel region of the above transistor is composed of a polycrystalline germanium film. Since there are many defects (Traps) at the grain boundary of the polycrystalline germanium film, these defects cause carrier migration of the device. The rate is lowered, and the threshold voltage shift (Threshold Voltage Shift) and the like. [Invention] In view of the above, the object of the present invention is to provide a polycrystalline second film Ι27984Ό 16991 twf.doc/g transistor manufacturing method. 'To reduce - lithography _ process, thereby reducing production costs., the re-invention of the purpose is Providing a polycrystalline pin film transistor to reduce the problems caused by >, the cerevisiae boundary defect. The present invention proposes a method for manufacturing a polycrystalline slab thin film transistor, which comprises providing a substrate first, and then a substrate A layer of amorphous germanium is formed on the layer. After the iron is used, the first mask is used to perform a lithography process, and the mosquito active region. The active region may include a plurality of channel regions. Then, formation on the substrate = The edge layer covers the non-small layer. After that, a layer = layer is formed on the insulating layer, and then a second mask is used to smear the conductor layer and the insulating layer on the active region. The active regions on the side are respectively separated from the source regions, and then a layer isolation layer is formed on the substrate to cover the gate and the active region. Thereafter, the third mask performs a lithography process on the isolation layer. The isolation shot forms a crystallization process gate and a plurality of contact openings, wherein the crystallization opening exposes a portion of the amorphous layer and the contact opening openings expose the gate, the source region and the drain region, respectively. Perform a metal induced lateral crystallization process to make amorphous The layer is transformed into a polycrystalline germanium layer. Next, an ion implantation process is performed to implant ions in the gate, source and drain regions, and then a first metal layer is formed on the substrate to cover the isolation layer and fill up. The contact window opening and the crystallization process are used for the port. Then, the first metal layer is etched by a fourth photomask to define a plurality of metal contacts, wherein the metal contacts are respectively connected via the contact opening The gate electrode, the source region and the drain region are electrically connected. In the above manufacturing method, the method for forming the amorphous germanium layer is, for example, a low voltage 1279840 16991 twf.doc/g chemical vapor deposition (LPCVD). A buffer layer may be formed on the substrate before the step of forming the amorphous layer. Further, the method of forming the insulating layer and the spacer layer is, for example, depositing ruthenium dioxide using TEOS as a reaction gas. Further, the method of forming the conductor layer is, for example, a low pressure chemical vapor deposition method. The method of forming the first metal layer is, for example, physical vapor deposition. On the other hand, after the metal contacts are formed, an alloying process can be performed, for example, annealing at a temperature of 400 ° C for 30 minutes in a nitrogen atmosphere. The metal induced lateral crystallization process, for example, first deposits a second metal layer such as nickel (Ni), drill (c) or lead (pd) on the substrate by physical vapor deposition (PVD), and then performs an annealing process. In order to cause the metal to induce lateral crystallization. Next, the unreacted second metal layer is removed, and the removal solution is, for example, a sulfuric acid solution. Further, the aforementioned photolithography etching process is performed, for example, by performing an electron beam lithography process and then performing a reactive ion etching process. The present invention further provides a polycrystalline germanium thin film transistor which is composed of a substrate, a tempering lateral crystallized polycrystalline layer, a gate, an isolation layer, and a metal contact. The metal-induced lateral crystalline polycrystalline germanium layer is located on the substrate jade, and the layer is composed of a source region, a drain region, and a plurality of channel regions. The channel area is located between the source area and the drain area. In addition, the gate is located on the channel area. In addition, the isolation layer is coated on the metal-induced lateral crystalline polysilicon layer and the gate. The spacer layer includes a crystallization process opening and a plurality of contact window openings. The opening of the crystallization process exposes a portion of the metal-induced lateral crystalline polysilicon layer, while the contact opening S exposes the gate, source and immersion regions. The metal contacts are electrically connected to the gate 'source region and the drain region respectively through the contact window opening. 1279840 16991twf.doc/g The source and the non-polar regions of the above-mentioned crystalline crystal film can be mixed with phosphorus ions. In addition, the gate includes an insulating layer and a conductor layer, wherein the insulating layer is located between the conductor layer and the metal-induced lateral crystalline polysilicon layer, and the insulating layer comprises yttrium oxide (SiOx), tantalum nitride (SiNx), yttrium oxynitride. (SiQxNy), oxidation group (Ta〇x) or oxidation (Α1〇χ). The material of the conductor layer includes doped polysilicon. Further, the material of the separator is, for example, a dioxode deposited by using TE〇s as a reaction gas. In addition, the metal-free material is, for example, in addition, the polycrystalline germanium film transistor further includes a buffer layer between the substrate and the metal-induced lateral crystalline polycrystalline hard layer. The material of this buffer layer is, for example, an oxidative dream. The present invention has the advantage of making the cost of the production of the contact window opening and the opening for the crystallization process in the same lithography. In addition, since the present invention reduces the channel grain boundary of the channel by reducing the channel width and the gate length of the channel region, and by using the metal induced lateral crystal plane, and the number of appropriate channels, the mobility of the channel And accurately control the range of the threshold voltage. The above, and other preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. [Embodiment] - w JH5 Α Ϊ t The preferred embodiment of the polycrystalline stone film electronic version of the garment / fairy chart. For the convenience of the other angle explanation, the figure has a section line 1 _ I at the same position, and FIG. 1B to FIG. 5B are cross-sectional views taken along line 1 of FIG. 1A to FIG. 1279840 16991twf.doc/g First, please refer to FIG. 1A and FIG. A substrate 1 is provided. The material of the substrate loo is, for example, a six-inch single crystal p-type germanium wafer in the (100) direction. Next, a buffer layer i 〇 2 is formed on the substrate 100. The material of the buffer layer 1〇2 is, for example, cerium oxide, and has a thickness of about 4 Å. The buffer layer 1 〇 2 serves to enhance the adhesion of the substrate 100 to the subsequently formed polysilicon layer and to prevent metal ions in the substrate 100 from contaminating the polysilicon layer. An amorphous A'Si layer is then formed on the surface of the substrate 1 . The thickness of the amorphous germanium layer is, for example, 5 Å, and the forming method is, for example, low pressure chemical vapor deposition (LPCVD). Thereafter, a photolithography process is performed on the amorphous germanium layer by using a mask 10 to define an active region 104' active region 1〇4 including a source region 1〇4a, a drain region and a channel region l〇4c, and A plurality of channel regions 1 〇 4c are present as shown in FIG. ία, so as to reduce the defect of the polycrystal ridge grain boundary in the subsequent sufficiency; in addition, an entire channel region may be selected, and is not limited to the embodiment. Said. The aforementioned microetching process is performed, for example, by an electron beam lithography process followed by reactive ion etching. Next, please refer to FIG. 2A and FIG. 2B. An insulating layer 106 is formed on the substrate 1 , and the insulating layer 106 covers the active region 1〇4. The material of the insulating layer 1 〇 6 is, for example, yttrium oxide (Si0x) having a thickness of about 25 nm, and the formation method is, for example, chemical gas phase redundancy using tetraethoxy decane (TEOS) as a reaction gas. In addition, the material of the insulating layer 106 may also be tantalum nitride (SiNx), bismuth oxynitride (si〇xNy), tantalum oxide (Ta〇x) or aluminum oxide (Al〇x). Then, a conductor layer ι 8 is formed on the insulating layer ι6. The material of the conductor layer 108 is, for example, polycrystalline germanium having a thickness of about 150 nm, 1279840 16991 twf.doc/g, and a forming method such as low pressure chemical vapor deposition (10) (4) is deposited at about 620 degrees. Then, the conductive layer _ the insulating layer H) 6 is subjected to a micro-in-situ process using the mask % to form a closed-electrode insulating layer on the active-area-purchasing region 104c. The micro-pure engraving process, for example, first performs an electron beam lithography process - a reactive ion etching process. 1罨
然後，請參照圖3A與圖3B。在基板1〇〇上形成 隔離層112’隔離層112覆蓋閘極11〇與主動區ι〇4 ^ 層112之材質例如為二氧化石夕，其厚度約為剛奈米 離層112之形成方法例如以TE〇s為反應氣體進行—化= 氣相沉積。接著’利用一光罩3〇對隔離層112進行： 侧製程，以於隔離層112中形成—個結晶製程關口^ 以及接觸窗開口 116。結晶製程用開口 114暴露出部分滿 極區104a，而接觸窗開口 116暴露出部分閘極ιΐ2、部乂 源極區104a與部分没極區i〇4b。 77 之後’請參照圖4A與圖4B。進行一金屬誘發側向結 晶(metal-induced lateral crystallization，MILC)製程，以^ 主動區HH由非晶石夕層轉變為多晶秒層。金屬誘發側向結 晶製程例如先以物理氣相沉積(PVD)於基板1〇〇上沉積: 層金屬層（未繪示），金屬層之厚度約為1〇奈米，其材質 如為鎳(Ni)、鈷(Co)或鉛(pd)，然後，於一實驗例中，可在 氮軋環境下以溫度550°C進行歷經48小時的退火製程， 以造成金屬透過結晶製程用開口丨14進行金屬誘發側^結 晶製程。接著，去除未反應的此金屬層。去除此金屬層^ 1279^,〇c/g 溶液例如為硫酸溶液。接著，進行離子植入製程ii7，以 於閘極110、源極區1〇4a、沒極區腿内植入離子。而前 述離子植人製程117的方㈣如為制—離子佈植機台 ^會不），將離子劑量為5嗜IS⑽·2的鱗離子植入間極 〇、源極區104a、汲_娜，再進行—快速熱退火。 因為經過了離子植入製程，所以閘極11〇、源極區购盘 汲極區104b之材質均成為摻雜多晶矽。 〃 接著’請參照圖5A與圖5B。於基板1〇〇上形成一# 此金屬層覆蓋隔離層112並填滿接“ L甘結砂程射扣114。此金屬層之材質例如 為紹，其厚度約為奈米，而形成方法例如為物理氣相 ^積法—光罩仙對此金屬層進行微影钱刻製 二個金屬接點118。此微影賴製程例如先 :丁电子束微影製程’再進行一反應性離子侧製程。金 =點118經由這些接觸窗開σ 116分別與間極110、源 1 與汲，祕電性相連。之後，將元件置於 以二"1=1環境下’進行30分鐘退火的合金化製程， 體用，發側向結晶製程的多晶石夕薄膜電晶 % i /而要五次微影侧製程，以完成整個製程。 二虫=明：多晶石夕薄膜電晶體製程中，這僅需四個 衣長用開π與接觸㈣口的製作，因此大幅降低製作的時 Ι27984Ό 16991twf.doc/g 間與成本。 以下說明本發明另一較佳實施例的多晶矽薄膜電晶體 結構。請參照圖6A，而圖6B為沿圖6A的剖面線Π - Π， 的剖面圖。此多晶矽薄膜電晶體是由基板2〇〇、金屬誘發 侧向結晶多晶石夕層204、閘極210、隔離層212以及金屬接 點218所構成，其中基板200之材質例如是玻璃基板、石 英基板或石夕晶片。此外，金屬誘發側向結晶多晶矽層2〇4 是配置於基板200上。金屬誘發側向結晶多晶石夕層204包 括源極區204a、汲極區204b以及多數個通道區2〇4c。源 極區204a與波極區204b的材質例如為摻雜多晶石夕。此摻 雜多晶矽之摻質例如為磷離子。通道區2〇4c位於源極區 204a與汲極區204b之間。通道區2〇4c之材質為多晶矽。 值得庄思的疋，以金屬誘發側向結晶製程所製作的通道區 204c可以經由縮減通道寬度w與調整通道數目以減少通 道區204c的多晶矽晶粒邊界的缺陷。因為晶粒邊界缺陷的 減少，所以載子遷移率隨之增加，辅以適當的通道數目選 擇，可以準確地控制元件的臨界電壓。另外，基板2⑽上 配置有緩衝層观。緩衝層2G2之材質例如為^化石夕，其 厚度約為400奈米，其位於基板2〇〇與主動區2〇4之間了 問極210位於通道區204c上。閘極21()包括絕緣層 206與位於絕緣層206上的導體層208。絕緣層2〇6之材所 例如是氧化石夕(SiOx)、氮化石夕(SiNx)、氮氧化秒_ 貝、 氧化组(Ta〇x)或氧化銘(A10x)，其厚度約為乃夺米卿 層細之材質例如是摻雜多晶石夕。值得注意的是:、縮減ς 12 1279840 16991twf.doc/g 道覓度W可以減少通道區2〇4c的多晶矽晶粒邊界的缺 陷二而增進载子遷移率，並準確地控制所製成元件的臨界 電壓值。此外，因為閘極21〇所覆蓋的部分通道區2〇4c 是貫質上構成通道(Channel)的部分，所以若閘極長度l愈 紐，通道長度愈短，而載子遷移率也隨之增高。Then, please refer to FIG. 3A and FIG. 3B. Forming the isolation layer 112 ′ on the substrate 1 隔离 the isolation layer 112 covering the gate 11 〇 and the active region ι 4 4 layer 112 is made of, for example, a dioxide dioxide, and the thickness thereof is about the formation method of the nano-layer 112 For example, TE〇s is used as a reaction gas for gasification. Next, the spacer layer 112 is subjected to a side process by using a mask 3 to form a crystallization process gate and a contact window opening 116 in the spacer layer 112. The crystallization process opening 114 exposes a portion of the gate region 104a, and the contact window opening 116 exposes a portion of the gate electrode ΐ2, the portion 乂 source region 104a and the portion of the gate region i〇4b. 77 After that, please refer to FIG. 4A and FIG. 4B. A metal-induced lateral crystallization (MILC) process is performed to convert the active region HH from an amorphous layer to a polycrystalline layer. The metal induced lateral crystallization process is first deposited on the substrate 1 by physical vapor deposition (PVD): a layer of metal (not shown) having a thickness of about 1 nanometer and a material such as nickel ( Ni), cobalt (Co) or lead (pd), and then, in an experimental example, a 48-hour annealing process can be carried out at a temperature of 550 ° C in a nitrogen rolling environment to cause a metal permeation process opening 丨 14 Conduct a metal induced side crystallization process. Next, the unreacted metal layer is removed. The metal layer is removed, and the 〇c/g solution is, for example, a sulfuric acid solution. Next, an ion implantation process ii7 is performed to implant ions in the gate 110, the source region 1〇4a, and the leg of the electrodeless region. The above-mentioned ion implantation process 117 (4), if the system is a plasma ion implantation machine, the ion dose is 5 IS (10)·2 scale ion implantation interpolarization, source region 104a, 汲_娜, then proceed - rapid thermal annealing. Because of the ion implantation process, the material of the gate 11 〇 and the source region of the drain region 104b becomes doped polysilicon. 〃 Next, please refer to FIG. 5A and FIG. 5B. Forming a metal layer covering the isolation layer 112 on the substrate 1 and filling the "L Gan sanding shot button 114. The material of the metal layer is, for example, a thickness of about nanometer, and the forming method is, for example, For the physical vapor deposition method, the reticle is etched into the metal layer by two kinds of metal contacts 118. The lithography process, for example, first: D-electron beam lithography process, and then a reactive ion side Process: Gold = point 118 via these contact window opening σ 116 is connected to the interpole 110, source 1 and 汲, respectively, and then the component is placed in a two "1 = 1 environment for 30 minutes annealing The alloying process, the body, and the side of the crystallizing process of the polycrystalline celestial thin film electro-crystal % i / and five times the lithography side process to complete the entire process. Second insect = Ming: polycrystalline lithene thin film transistor process In this case, only four garment lengths are required for the opening of the opening π and the contact (four) opening, thereby greatly reducing the time and cost of the production of 27984 Ό 16991 twf.doc/g. The following describes a polycrystalline germanium thin film transistor according to another preferred embodiment of the present invention. Please refer to FIG. 6A, and FIG. 6B is a cross-sectional line Π - 沿 along FIG. 6A. The polycrystalline germanium thin film transistor is composed of a substrate 2, a metal-induced lateral crystalline polycrystalline layer 204, a gate 210, an isolation layer 212, and a metal contact 218, wherein the material of the substrate 200 is, for example, a glass substrate, a quartz substrate, or a slab wafer. Further, the metal-induced lateral crystalline polysilicon layer 2〇4 is disposed on the substrate 200. The metal-induced lateral crystalline polycrystalline layer 204 includes a source region 204a and a drain region 204b. And a plurality of channel regions 2〇4c. The material of the source region 204a and the wave region 204b is, for example, doped polysilicon. The doping of the doped polysilicon is, for example, phosphorus ions. The channel region 2〇4c is located in the source region. Between 204a and the drain region 204b. The material of the channel region 2〇4c is polycrystalline germanium. It is worthwhile to think that the channel region 204c made by the metal induced lateral crystallization process can be reduced by reducing the channel width w and adjusting the number of channels. Defects in the polycrystalline germanium grain boundary of the channel region 204c. Since the grain boundary defects are reduced, the carrier mobility is increased, and the threshold voltage is accurately controlled by the appropriate channel number selection. In addition, a buffer layer is disposed on the substrate 2 (10). The material of the buffer layer 2G2 is, for example, a fossil, which has a thickness of about 400 nm, and is located between the substrate 2 and the active region 2〇4. The gate 21() includes an insulating layer 206 and a conductor layer 208 on the insulating layer 206. The insulating layer 2〇6 is made of, for example, SiOx, SiNx, oxynitride. Seconds_Bei, Oxidation Group (Ta〇x) or Oxidation Inscription (A10x), the thickness of which is about the material of the layer of melon, such as doped polycrystalline stone. It is worth noting that: 缩 12 1279840 16991twf The .doc/g degree of turn W can reduce the defect of the polycrystalline germanium grain boundary in the channel region 2〇4c to enhance the carrier mobility and accurately control the threshold voltage of the fabricated component. In addition, since part of the channel region 2〇4c covered by the gate 21〇 is a portion that constitutes a channel on the channel, if the gate length l is longer, the channel length is shorter, and the carrier mobility is also followed. Increase.
隔離層212位於金屬誘發侧向結晶多晶矽層2〇4與閘 極210上。隔離層212之材質例如是以TE〇s作為反應氣 體沉積的二氧化矽，其厚度約為1〇〇奈米。隔離層212中 配置了-個結晶製程用開σ 214以及多數個接觸窗開口 2丄6。其中，結晶製程用開口 214暴露出部分源極區2〇4a， 而接觸自開口 216恭露出部分閘極21〇、部分源極區2〇4a 與部分汲極區l〇4b。 另外，夕數個金屬接點218通過接觸窗開口 216分別 與閘極210、源極區204a與汲極區204b電性相連。金屬 接點的材質例如為鋁。The isolation layer 212 is on the metal induced lateral crystalline polysilicon layer 2〇4 and the gate 210. The material of the spacer layer 212 is, for example, ruthenium dioxide deposited by using TE〇s as a reaction gas, and has a thickness of about 1 nm. In the separation layer 212, a crystallization process opening σ 214 and a plurality of contact window openings 2 丄 6 are disposed. The crystallization process opening 214 exposes a portion of the source region 2〇4a, and the contact opening 216 exposes a portion of the gate 21〇, a portion of the source region 2〇4a, and a portion of the drain region 〇4b. In addition, the plurality of metal contacts 218 are electrically connected to the gate 210, the source region 204a and the drain region 204b through the contact opening 216, respectively. The material of the metal contact is, for example, aluminum.
本發明以金屬誘發側向結晶製程來將主動區之材質由 非晶矽轉換為多晶矽，並以後續的微影蝕刻製程來定義通 道區。藉由縮減以此方式所製作之通道區的通道寬度，而 減少通道❹晶⑪晶粒邊界的缺陷，並辅以適當通道數目 的選擇，以增進载子遷移率並準確控制臨界電壓的範圍。 而且，縮減閘極長度也可以達到相同的效果。 雖然本發明已以較佳實施例揭露如上，然其並非用r 限定本發明，任何熟習此滅者，在不麟本糾 ζ 和範圍内，當可作些許之更動與潤飾，因此本發明之 13 1279840 16991twf.doc/g 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖5A為本發明較佳實施例的多晶矽薄膜電晶 體的製造流程圖。 _ 圖1B至圖5B為沿圖1A至圖5A之剖面線I - I，之剖 - 面圖。 圖6A為本發明較佳實施例的多晶矽薄膜電晶體。 圖6B為沿圖6A之剖面線Π-Π’之剖面圖。 ® 【主要元件符號說明】 10、20、30、40 :光罩 100、200 :基板 102、202 :缓衝層 104 ·主動區 104a、204a :源極區 104b、204b :汲極區 104c、204c :通道區 • 106、206 :絕緣層 108、208 :導體層 110、210 :閘極 * 112、212 :隔離層 114、214 :結晶製程用開口 116 :接觸窗開口 117 :離子植入製程 118、218 :金屬接點 14 Ι27984Ό 16991twf.doc/g 204 ··金屬誘發側向結晶多晶矽層 W:通道寬度 L :閘極長度The invention converts the material of the active region from amorphous germanium to polycrystalline germanium by a metal induced lateral crystallization process, and defines a channel region by a subsequent photolithography etching process. By reducing the channel width of the channel region produced in this manner, the defect of the grain boundary of the channel twin 11 is reduced, and the number of appropriate channels is selected to enhance the carrier mobility and accurately control the range of the threshold voltage. Moreover, the same effect can be achieved by reducing the gate length. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any one skilled in the art can make some modifications and retouchings within the scope of the present invention. 13 1279840 16991twf.doc/g Scope is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 5A are flowcharts showing the manufacture of a polycrystalline germanium thin film transistor according to a preferred embodiment of the present invention. 1B to 5B are cross-sectional views taken along line I - I of Figs. 1A to 5A. 6A is a polycrystalline germanium thin film transistor in accordance with a preferred embodiment of the present invention. Fig. 6B is a cross-sectional view taken along line Π-Π' of Fig. 6A. ® [Main component symbol description] 10, 20, 30, 40: reticle 100, 200: substrate 102, 202: buffer layer 104 · active region 104a, 204a: source region 104b, 204b: drain region 104c, 204c : channel region • 106, 206: insulating layer 108, 208: conductor layer 110, 210: gate * 112, 212: isolation layer 114, 214: opening process 116 for crystallization process: contact window opening 117: ion implantation process 118, 218: Metal contact 14 Ι27984Ό 16991twf.doc/g 204 ··Metal induced lateral crystalline polycrystalline layer W: channel width L: gate length
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