TWI279551B - Voltage measurement apparatus for filter module with adjustable planarity - Google Patents

Voltage measurement apparatus for filter module with adjustable planarity Download PDF

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TWI279551B
TWI279551B TW94115027A TW94115027A TWI279551B TW I279551 B TWI279551 B TW I279551B TW 94115027 A TW94115027 A TW 94115027A TW 94115027 A TW94115027 A TW 94115027A TW I279551 B TWI279551 B TW I279551B
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Taiwan
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voltage
resistor
switch
signal
electrically connected
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TW94115027A
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Chinese (zh)
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TW200639415A (en
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Shr-Chau Li
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Picotest Corp
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Abstract

A voltage measurement apparatus includes a filter module, an AC-DC converter module, and a digital signal processing module. The filter module can accept an AC voltage being measured from a first input terminal, then going through the first output end by attenuating and filtering the signal from said AC voltage. The AC-DC converter module can accept the AC voltage of the first output terminal, and transforming AC voltage into DC voltage in which the RMS value is the equivalent DC value of the AC voltage being measured. The digital signal processing module accepts the DC voltage which output form AC-DC converter, and said DC voltage can be transformed into a corresponding digital signal. Moreover, the digital signal processing module can put out a pulse width modulated signal and a control signal to the AC filter module.

Description

J279551 、九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種量測裝置,特別是指一種電壓量 測裝置。 【先前技術】 參閱圖1,習知電壓量測裝置包括一交流濾波模組6、 一交流轉直流電壓模組7、一數位信號處理模組8及一微處 ^ 理器9。該交流濾波模組6與該微處理器9及該交流轉直流 電壓模組7電性連接,且該數位信號處理模組8與該交流轉 直流電壓模組7電性連接。 該交流濾波模組6由一第一輸入端AC_IN接收該待測 交流電壓,且須將該待測交流電壓中頻率在3〇〇KHz以上的 成分加以衰減濾除,同時將該待量測之交流電壓中頻率在 300KHZ以下的成分適當地衰減後再予以放大成為均方根值 (root mean square)在2V以内之交流電壓,經由一第一輸出 • 端AC 一 OUT輸出至該交流轉直流電壓模組7,以符合該交 流轉直流電壓模組7的最大解析度2V。該直流轉交流電壓 模組7接收到該第一輸出端AC—〇UT之交流電壓後,可將 其轉換為一等於該待測交流電壓之均方根值的直流電壓。 該數位信號處理模組8接收該直流電壓,且輸出相對於該直 流電壓值之畺測值至一顯示器(圖未示)顯示該待測交流電壓 之值。 泫父流濾波模組6包含一交流濾波電路6丨、一第一放 大電路62及一第二放大電路63。該交流濾波電路61包括 1279551 複數電容Cp2〜Cp6、複數電阻r2、r4〜r6、r9〜rlO、H2〜rl3 、一運算放大器(〇P Amplifier) OP1及複數類比開關(Analog Switch) Kl、U1。該第一放大電路62包括一電阻r8、一十 倍放大單元621及複數類比開關U2〜U5。該十倍放大單元 621具有一運算放大器〇P2、一電阻rl及一可變電阻r3。 該第二放大電路63包括一運算放大器0P3、一電阻r7、一 可變電阻rll及一電容Cpl。該等類比開關Kl、U1〜U5由 該微處理器9所控制,且能於一關閉及一開啟位置之間切 換,且該等電阻rl〜r13是精密電阻。 該交流濾波電路61可將該待量測之交流電壓中頻率在 3OOKHz以下的成分適當地衰減後再予以放大,並送至該第 一放大電路62。該第一放大電路62之十倍放大單元可將由 该類比開關U2接收之電壓予以放大十倍。該第二放大電路 63可將由該等類比開關U3〜U5接收之電壓予以放大二倍送 至該第一輸出端AC_OUT。 當該待量測之交流電壓的範圍為均方根值在lv〜1〇v的 父流電壓時,該微處理器9設定該等類比開關K1、及 U5關閉,且該等類比開關U2〜U4開啟,使該運算放大器 0P1之反相輸入端與其輸出端電性連接,且該運算放大器 0P1之輸入阻抗值極高,該運算放大器〇ρι作為一缓衝器 使用,因此該交流濾波電路61之增益值(gai…為丨,該待測 乂:電C等於4運异放大器QP1之輸出電壓送至該第一放 大電路62而為了得到最大解析度,該微處理器9設定該 類比開關U5關閉’該第—放大電路62將均方根值訓以 1279551 下的該待測交流電壓經由該電阻r8衰減1〇倍後成為均方根 2 IV以下之電壓,並饋人該第二放大電路M。該第二放大 電路Μ接著予以放大2倍後成為均方根值範圍在2v以内 之電壓,送入該交流轉直流電壓模組7中。 而當量測均方根值(UV〜1V的待測交流電壓時,同樣 地,該微處理ϋ 9設定料類比_ Ki、m、u4關閉, =:等類比開關U2、U3、U5設定為開啟。該交流渡波 電路Q之運算放大器〇P1仍然作為緩衝器使用該運算放 “ 0P1之輸出電壓等於該待測交流電壓,並送人該第— =大電路62。該第-放大電路62直接將該待測交流送入該 弟1放大電路63放大2倍’成為均方根值範圍在2V以下 的父流電壓’再進入該交流轉直流電麼電路7中。 :當量測均方根值〇·1ν以下的交流電壓範圍時 衫該等類比_mU3關閉,且將 = 開關U4、U5衫為開啟。該交流黯電路61之 ==〇P1同樣地作為緩衝器使用,該運算放大器 輸出μ等於該待測交流電屋,並送人該第一放大 二T:第一放大電路62之十倍放大單元將由該類比開 接收之電麼放大10倍後送入該第二放大電路63再放 一丄均方根值範圍在…以下的交流電壓,送入該 父 >瓜轉直流電壓電路7中。 ::以上三種量測範圍的情形,該交流濾波電路μ之 =异放大器〇P1皆作為緩衝器使用,所以該交流據波電路 有頻率之交流電壓增益值皆為卜無法對任何頻率 1279551 的父流電壓做信號衰減,因此該交流濾波電路61對均方根 值10V以下的該待測交流電壓完全沒有濾波效果。 當置測均方根值10V〜100V以及100V〜750V的待測交 流電壓時’此時該等類比開關K1及U1開啟。該待測交流 電壓由該交流濾波電路61之運算放大器0P1的反相輸入端 輸入’因此該運算放大器〇P1做反相放大器使用,且該交 流濾波電路61之增益值為_ri〇/(ri2+rl3)=-0.01,所以該待 測交流電壓將被衰減100倍,由該運算放大器0P1之輸出 端送至該第一放大電路62及第二放大電路63,並由該微處 理器9適當地設定該等類比開關U2〜U5,使該第一輸出端 AC一OUT之電壓能達到該交流轉直流電壓模組7的最大解 析度。 但因該交流濾波電路61具有增益頻寬比之特性,即增 盈變大則頻寬(Bandwidth)變小的影響,使頻率越高的交流 電壓的衰減幅度將大於100倍(-40db)。圖2之波德圖(Bode) 顯示該交流濾波電路61對3OOKHz頻率範圍内之交流電壓 的頻率與增益值之關係,該交流濾波電路61之頻率響應圖 呈現頻率愈高則增益值下降的曲線。對於頻率在300KHZ以 内的交流電壓皆是被衰減-40db ;但m2點顯示該頻率響應 曲線的增益值於300KHz時卻已衰減成-40.478db,且於頻寬 達10MHz時,增益值衰減幅度為_61db。 習知電壓量測裝置之交流濾波模組6對於頻率在 300KHz的交流電壓衰減了 _40.478db,損失頻寬3〇〇khz内 的平坦度,使其頻寬無法達到300KHz。若要改善頻寬 .1279551 -300ΚΗζ _平坦度,則須調整電阻r6及電容cp4變小才 能增加頻寬,且為使每台電壓量測裝置於量產時都能維持 一致性’則須要相當準確的電阻值及電容值,才能增加頻 寬且符合遽波效果又能維持每台一致性。而目前於市面上 高準確度的電阻及電容,價格相當昂貴。 由上所述,習知電壓量測裝置内之交流渡波模組6於 量測均方根值H)V以下的交流電壓時,完全沒有遽波效果 • ’❿於量測均方根值100V及75〇v的交流電料,受該交 流據波電路61具有增益頻寬比之特性影響,使頻寬降低= 足300KHz,濾波效果不佳。 再者,為了增加頻寬且使濾波效果維持一致性,須相 當準確地調整電阻值及電容值才能增加頻寬,須要高^確 度的電阻值及電容值,才能增加頻寬且使滤波效果維持_ 致性。而高準確度的電阻及電容,其價袼昂貴,實用上 足。 | 【發明内容】 因此,本發明之目的,即在提供—種電壓量測裝置, 該電塵量測裝置之頻寬可達3G()KHz,且不須高準確度的電 阻值及電容值,即可符合頻寬内增益值之平坦度又^維持 每台電壓量測裝置之一致性。 、 於是,本發明之電麼量測裝置,包含一可調整平扭度 的交流濾波模組、-交流轉直流電_組及一數位信號二 理模組。 儿处 該可調整平坦度的交流遽波模組具有—可接收待測交流 1279551 電壓之弟一輸入端及一第一輸出端,並可針對該待測電壓予 以適當地做信號衰減並渡波後,經由該第—輸出端輸出。 該交流轉直流電壓模組與該交流濾波模組電性連接,並 可接收該第一輪出媸夕六、、☆ +抗、 又机電£,且可將該交流電壓轉換為 -電壓值與該第-輸出端之交流電壓之均方根值相等之直流 電壓。 該^位信號處理模組可接收該交流轉直流電壓模組輸 出之直流電壓’且將該直流電壓依據其所在的量測範 換成一與該待測交流電壓相對應之量測值,並可輪出一脈 衝寬度調變信號及-控制信號至該交流濾、波模組。該脈衝 寬度調變信號之脈衝寬度與該量測值及該待測交流電麗之 均值兩者之誤差值成正此,以供該交流渡波模組調整 -亥第輸出翊之輸出電壓。該控制信號可控制該交流濾波 杈組在不同之電壓量測範圍時,將該待測交 做衰減後由該第-輸出端輸出。 適田地 【實施方式】 有關本發明之前述及其他技術内容、特點與功效,在 以下配曰參考圖式之較佳實施例的詳細說明中,將可清楚 的呈現。 參閱圖3及圖4,本發明電壓量測裝置之較佳實施例包 含一可調整平坦度的交流濾波模組1、一數位信號處理模組 3及一父流轉直流電壓模組2。該數位信號處理模組3與該 交流濾、波模組1及該交流轉直流電壓模組2電性連接,該 叮凋整平垣度的交流濾波模組1具有一可接收待測交流電 10 1279551 壓之第一輸入端ac_in,並可針對該待測電壓予以適當地 做L號哀減並且滤波後,經由一第一輸出端Ac_〇xjt送至 該交流轉直流電壓模組2,使該第一輸出端AC—〇UT之電 壓在該交流轉直流電壓模組2之最大解析度以内: 該交流轉直流電壓模組2可接收該第一輸出端 AC_OUT《交流電壓’且可將該交流電壓轉換為一電壓值 與該第-輸出端AC_〇UT之交流電壓之均方根值(酬t咖扣 square)相等之直流電壓,且送至該數位信號處理模組3。該 數位信號處理模組3可接收該交流轉直流電壓模組2輸出 之直流電Μ,且將該直流電|依據該量測範圍轉換成一與J279551, IX. Description of the Invention: [Technical Field] The present invention relates to a measuring device, and more particularly to a voltage measuring device. [Prior Art] Referring to FIG. 1, a conventional voltage measuring device includes an AC filter module 6, an AC to DC voltage module 7, a digital signal processing module 8, and a microprocessor 9. The AC filter module 6 is electrically connected to the microprocessor 9 and the AC-DC voltage module 7, and the digital signal processing module 8 is electrically connected to the AC-DC voltage module 7. The AC filter module 6 receives the AC voltage to be tested by a first input terminal AC_IN, and attenuates the component of the AC voltage to be tested whose frequency is above 3〇〇KHz, and simultaneously measures the to be measured. The component of the AC voltage whose frequency is below 300KHZ is appropriately attenuated and then amplified to become an AC voltage with a root mean square of 2V or less, and is output to the AC to DC voltage via a first output terminal AC to OUT. The module 7 is adapted to meet the maximum resolution of the AC to DC voltage module 7 of 2V. After receiving the AC voltage of the first output terminal AC_〇UT, the DC-to-AC voltage module 7 can convert it into a DC voltage equal to the rms value of the AC voltage to be tested. The digital signal processing module 8 receives the DC voltage and outputs a measured value relative to the DC voltage value to a display (not shown) to display the value of the AC voltage to be tested. The parent-child filter module 6 includes an AC filter circuit 6A, a first amplification circuit 62, and a second amplification circuit 63. The AC filter circuit 61 includes 1279551 complex capacitors Cp2 to Cp6, complex resistors r2, r4 to r6, r9 to rlO, H2 to rl3, an operational amplifier (〇P Amplifier) OP1, and a complex analog switch (Kn1, U1). The first amplifying circuit 62 includes a resistor r8, a ten-fold amplification unit 621, and a plurality of analog switches U2 to U5. The ten-fold amplification unit 621 has an operational amplifier 〇P2, a resistor rl and a variable resistor r3. The second amplifying circuit 63 includes an operational amplifier OP3, a resistor r7, a variable resistor r11 and a capacitor Cpl. The analog switches K1, U1~U5 are controlled by the microprocessor 9, and are switchable between a closed and an open position, and the resistors rl~r13 are precision resistors. The AC filter circuit 61 can appropriately attenuate the component of the AC voltage to be measured having a frequency below 3OOKHz, and then amplify it and send it to the first amplifier circuit 62. The ten-fold amplification unit of the first amplifying circuit 62 can amplify the voltage received by the analog switch U2 by a factor of ten. The second amplifying circuit 63 can amplify the voltage received by the analog switches U3 to U5 by a factor of two to the first output terminal AC_OUT. When the range of the AC voltage to be measured is the parent voltage of the rms value lv~1〇v, the microprocessor 9 sets the analog switches K1 and U5 to be turned off, and the analog switches U2~ U4 is turned on, so that the inverting input terminal of the operational amplifier OP1 is electrically connected to the output end thereof, and the input impedance value of the operational amplifier OP1 is extremely high, and the operational amplifier 〇ρι is used as a buffer, so the alternating current filter circuit 61 The gain value (gai... is 丨, the test 乂: the electric C is equal to the output voltage of the 4-transistor amplifier QP1 is sent to the first amplifying circuit 62. To obtain the maximum resolution, the microprocessor 9 sets the analog switch U5. Turning off the first-amplifying circuit 62, the rms value of the rms value is controlled by 1279551, and the voltage to be tested is attenuated by the voltage r8 by a factor of 1 to become a voltage of the root mean square of 2 IV or less, and is fed to the second amplifying circuit. M. The second amplifying circuit is then amplified by a factor of 2 and becomes a voltage having a root mean square value within 2v, which is sent to the AC to DC voltage module 7. The equivalent rms value (UV~1V) When the AC voltage to be tested is the same, the micro Reason 9 Set the material analog ratio _ Ki, m, u4 off, =: and other analog switches U2, U3, U5 are set to ON. The operational amplifier 〇P1 of the AC wave circuit Q is still used as a buffer to use the output of the operation "0P1" The voltage is equal to the AC voltage to be tested, and is sent to the first-=large circuit 62. The first-amplifier circuit 62 directly sends the AC to be tested to the amplifying circuit 63 of the brother 1 to amplify 2 times to become a root mean square value range. The parental voltage below 2V is re-entered into the AC-DC circuit 7. In the AC voltage range below the rms 1·1ν, the analogy _mU3 is turned off and the switch U4, U5 The shirt is turned on. The ==〇P1 of the AC circuit 61 is similarly used as a buffer. The output of the operational amplifier is equal to the AC house to be tested, and the first amplification is performed. The multiplying unit amplifies the electric power received by the analogy by 10 times and then sends it to the second amplifying circuit 63 and then puts an alternating voltage having a root mean square value below ... and sends it to the parent> 7. In the case of the above three measurement ranges, The AC filter circuit μ=the different amplifier 〇P1 is used as a buffer, so the AC voltage gain value of the AC data circuit has a frequency attenuation of the parent current voltage of any frequency 1279551, so the AC filter circuit 61 The AC voltage to be tested with a rms value of 10 V or less has no filtering effect at all. When the rms value of 10 V to 100 V and the AC voltage to be tested of 100 V to 750 V are measured, 'the analog switches K1 and U1 are turned on at this time. The AC voltage to be tested is input from the inverting input terminal of the operational amplifier OP1 of the AC filter circuit 61. Therefore, the operational amplifier 〇P1 is used as an inverting amplifier, and the gain value of the AC filter circuit 61 is _ri〇/( Ri2+rl3)=-0.01, so the AC voltage to be tested will be attenuated by 100 times, and the output terminal of the operational amplifier OP1 is sent to the first amplifying circuit 62 and the second amplifying circuit 63, and the microprocessor 9 is The analog switches U2 to U5 are appropriately set so that the voltage of the first output terminal AC_OUT can reach the maximum resolution of the AC-DC voltage module 7. However, since the AC filter circuit 61 has a characteristic of a gain-to-gain ratio, that is, when the gain is increased, the bandwidth is reduced, and the attenuation of the AC voltage having a higher frequency is greater than 100 times (-40 db). The Bode diagram of FIG. 2 shows the relationship between the frequency and the gain value of the AC voltage in the frequency range of 3OOKHz by the AC filter circuit 61. The frequency response diagram of the AC filter circuit 61 shows that the higher the frequency, the curve of the gain value decreases. . For the AC voltage with the frequency below 300KHZ, it is attenuated by -40db; but the m2 point shows that the gain value of the frequency response curve is attenuated to -40.478db at 300KHz, and the attenuation value is attenuated when the bandwidth is 10MHz. _61db. The AC filter module 6 of the conventional voltage measuring device attenuates the _40.478 db for the AC voltage having a frequency of 300 kHz, and the flatness of the loss bandwidth within 3 〇〇khz, so that the bandwidth cannot reach 300 kHz. To improve the bandwidth of 1279551 -300 ΚΗζ _ flatness, the resistor r6 and capacitor cp4 must be adjusted to increase the bandwidth, and the consistency of each voltage measuring device can be maintained in mass production. Accurate resistance and capacitance values increase the bandwidth and match the chopping effect while maintaining consistency. At present, high-accuracy resistors and capacitors on the market are quite expensive. As described above, when the AC wave module 6 in the conventional voltage measuring device measures the AC voltage below the root mean square value H)V, there is no chopping effect at all. '❿Measure the root mean square value of 100V. And the AC material of 75 〇v is affected by the characteristics of the gain bandwidth ratio of the AC wave circuit 61, so that the bandwidth is reduced to 300 KHz, and the filtering effect is not good. Furthermore, in order to increase the bandwidth and maintain the consistency of the filtering effect, it is necessary to adjust the resistance value and the capacitance value quite accurately in order to increase the bandwidth, and it is necessary to have a high resistance value and a capacitance value in order to increase the bandwidth and maintain the filtering effect. _ To the sex. Highly accurate resistors and capacitors are expensive and practical. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a voltage measuring device that has a bandwidth of up to 3 G (KHz) and does not require high-accuracy resistance values and capacitance values. It can meet the flatness of the gain value in the bandwidth and maintain the consistency of each voltage measuring device. Therefore, the electrical measuring device of the present invention comprises an AC filter module capable of adjusting a flat twist, an AC to DC_group and a digital signal secondary module. The AC chopper module with adjustable flatness has a first input end and a first output end for receiving the voltage of the 1279551 to be tested, and the signal can be appropriately attenuated and waved after the wave to be tested. , output through the first output. The AC-to-DC voltage module is electrically connected to the AC filter module, and can receive the first round of the hexagram, the ☆+, and the electromechanical £, and can convert the AC voltage into a voltage value. A DC voltage equal to the rms value of the AC voltage at the first output terminal. The signal processing module can receive the DC voltage 'outputted by the AC to DC voltage module' and change the DC voltage according to the measurement range in which it is located to a measured value corresponding to the AC voltage to be tested, and A pulse width modulation signal and a control signal can be rotated to the AC filter and wave module. The pulse width of the pulse width modulation signal is equal to the error value of the measured value and the average value of the AC voltage to be tested, so that the AC wave module can adjust the output voltage of the output terminal. The control signal can control the AC filter group to be attenuated by the first output terminal when the voltage is measured in different voltage measurement ranges. The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Referring to Figures 3 and 4, a preferred embodiment of the voltage measuring device of the present invention comprises an AC filter module 1 having an adjustable flatness, a digital signal processing module 3 and a parent DC DC voltage module 2. The digital signal processing module 3 is electrically connected to the alternating current filter, the wave module 1 and the alternating current to direct current voltage module 2, and the alternating current filter module 1 has a receiving AC power to be tested 10 1279551 The first input terminal ac_in is pressed, and the voltage to be tested is appropriately L-shaped and filtered, and then sent to the AC-DC voltage module 2 via a first output terminal Ac_〇xjt, so that the The voltage of the first output terminal AC_〇UT is within the maximum resolution of the AC to DC voltage module 2: the AC to DC voltage module 2 can receive the first output AC_OUT “AC voltage” and can exchange the AC The voltage is converted into a DC voltage having a voltage value equal to the rms value of the AC voltage of the first output terminal AC_〇UT, and is sent to the digital signal processing module 3. The digital signal processing module 3 can receive the DC power output of the AC to DC voltage module 2, and convert the DC power according to the measurement range into a

該待測交流電壓相對應之量測值,且輸出至一顯示器(圖未 示)顯示出來’並可輸出一脈衝寬度調變信號pwM及一控 制信號至該交流渡波模、组i,該脈衝寬度調變信號pwM之 脈衝寬度與該量測值及該待測交流„之均方根值兩者之 誤差值成正比,以供該交流濾波模組1調整該第-輸出端 AC—OUT之輸出電壓,該控制信號可控制該交流濾波模組i 在不同之電壓里測範圍時將該待測交流電壓適當地做衰減 後由該第一輸出端AC—OUT輸出。 踗; 坦度的交流遽波模組1包含-交流遽波電 路Π、-平坦度調整電路13、一補償電路14及一放大電路 12。該交«波電路u可接收該待測交流電黯 號FLATNESS ADJ,日可脸外外, …、、 — 了將该待測電壓予以適當地信號奢 減並濾波後,輸出一第一 ^ # 义 弟琥匕〇至該放大電路12,並 輸出一由該第一作跋F 八 乐仏免%分壓及濾波後所得之修正信號 1279551 至該平坦度調整電路13,使該平坦度調整電路Η可取 樣該第一信號之電壓。該放大電路12經由該第一輸出 端AC一OUT與該交流轉直流電壓模組2電性連接,且可將 該第一信號^c/予以適當地放大後輸出至該第一輸出端 AC 一 OUT。該補償電路14可接收由該數位信號處理模組3 輸出之脈衝I度调變信號’並輸出一補償信號至該平坦度 調整電路13,該補償信號之電壓值與該脈衝寬度調變信^ PWM之脈衝寬度成反比。該平坦度調整電路13接收該補 償信號及該修正信號後可輸出該校準信號 FLATNESS—ADJ至該交流濾波電路u,該校準信號 FLATNESS—ADJ可調整該交流濾波電路丨丨之第一信號厂 該交流渡波電路11包括一第一運算放大器ai、一第一 電容C1、-第二電容C2、一第三電容〇、一第四電容C4 、-第五電容C5、一第六電容C6、一第七電容π 一電阻R1、一第二電阻R2、一第二 乐一寬阻R3、一第四電阻 R4、一第五電阻R5、一第六電 矛、电阻R6、一第七電阻R7及_ 第一開關S1。 該第一運算放大A 1夕X h 土人 益A1之正相輸入端接地,且复反相鈐 入端與該第五電阻R5之一端、 /、反相輪 而δ亥第四電容C4之一媸、— 第二電容C2之一端、兮笛 „日日 而石亥 ^ °亥弟一開關S1之一端、命楚丄雨 C6之一端及該第二電阻R2 /、電容 电I丑之一端電性連 輪出該第一信號匕c/,且盥而輪出端可 且與忒弟六電阻如之_端 %路12、該第三電阻R3之一 μ放大 、该第二電阻R2之另—端 12 1279551 ::亥:五電容C5之一端及該第一電阻R1之一端電性連接 帝第/、電阻R6之另一端與該平坦度調整電路13及該第 七電阻R7之—端電性連接,並可輸出該修正信號而 該第七電阻R7之另一端為接地電壓。 4第七電谷C7與該第六電阻R6並聯,該第四電容 之另-端與該第三電容C3之—端及該第四電㉟R4之一端 電性連接,該第三電容C3之另一端即為該第一輸入端 ACJN ’該第三電阻R3之另一端與該第六電容之另一 端電性連接,該第五電容C5之另一端與該第一開關si之 另一端、該第一電容C1之一端及該第一電阻Rl之另一端 電性連接,該第二電容C2之另-端與該第-電容C1之另 一端電性連接並可接收該校準信號FLATNess—adj,該第 四電阻R4之另一端與該第五電阻R5之另一端電性連接。 該放大電路12包括一第二開關S2、一第三開關幻、 一第四開關S4、-第五開關S5、—第六開關%、一第一放 單元121 弟一放大單元122及一緩衝單元^23。該第 二開關S2之一端與該交流濾波電路n電性連接,且可接 收該第一信號匕c/,而另一端與該第一放大單元121電性 連接。該第一放大單元121經由該第二開關S2接收該第一 信號Gc/,並可將該第一信號放大1〇倍後成為一第二 L號。该第五開關S5之一端與該交流濾波電路Η電 性連接,且可接收該第一信號,而另一端與該二放大 單元電性連接。該第六開關S6之一端與該第一放大單元 121電性連接,並可接收該第二信號,而另一端與該第 13 1279551 二放大單元m電性連接。該第二放大單元i22可經由咳 五Μ接收該第-信號^,且可經由該第六開關%接^ 5亥弟二信號〜2,並可將該等信號放大10倍後成為-第三 仏號Fw該第四開關84之—端與該交流缝電路^電 险連接,且可接收該第一信號匕。,而另一端與該緩衝單 疋123電性連接。該第三開關S3之一端與該第二放大單元 =電性連接,並可接收該第三信號^,而另__端與該緩 衝早^ 123電性連接。該緩衝單元⑵可經由該四開關接 收5亥弟-信號〜,且可經由該第三開關s3接收該第三信 旒‘,並可將該等信號^輸出至該第一輸 出端AC—OUT。該等開關S1〜S6可由該數位信號處理模組3 輸出之控制信號控制開啟或關閉。 該第一放大單元121包括一第十四電阻幻4、一第十五 電阻R15、一第+ ^ 、電阻R16及一第二運算放大器A2。該 第十四電阻R14之一端與該第二開關、該第二運算放大 器A2之正相輸人端電性連接’該第十四電阻R14之另-端 為接:,該第十五電阻R15跨接於接地電壓與該第二運算 从大器A2之反相輸人端之間,該第十六電阻Μ $跨接於該 ^二運纽大器A2之反相輸人端與輸出端之間,該第二運 叶放大為A2之輸出端與該第六開關%電性連接並輸出該 第二信號。 〆第一放大單元!22包括一第十七電阻Ri7、一第十八 ,阻川、'第十九電阻R19及-第三運算放大器A3。該 第—運才放大态A3之正相輸入端與該第五開關Μ及該第 14 1279551 該」、連接’該第十七電阻R17跨接於接地電位與 rJ:: ’放大器A3之正相輪入端之間,該第十八電阻 接地電位與該第三運算放大器A3之反相輸入端 ^ '"弟十九電阻R19跨接於該第三運算放大器A3之反 二=j出端之間,該第三運算放大器Μ之輸出端可 •二/ 一^諕^C2,並與該第三開關幻電性連接。 /、友衝單疋123包括一第四運算放大器A4、一第十電 ⑽、-第十-電容C11、一第二十一電阻R21 二 十電阻R20。續®本兩— 一 哭 ° 一電谷CU之一端、該第四運算放大 i第輪人端及該第二十電阻㈣之—端電性連接, =* CU之另—端與該第四開關S4及該第三開關 =電性連接,而該第四運算放大$A4之反相輸入端與其 輸出端、該第二十一雷阳 +電阻R21之一端電性連接,該第二十 R20之另-端為接地電壓,該第二十—電P且R21之另 -端即為該第-輸出端AC_0UT,而該第十電容C10跨接 於4第二十—電阻R21之兩端。 該平坦度調整電路13包括—第五運算放Al§ A5、 八電谷C8、一第八電阻R只、^ 矛冤阻R8、一弟九電阻R9、一加法單元 m及一電_可變電阻單元132。該加法單元13…亥 補償電路Η電性連接,且接㈣補償信號,並將該補償信 t周整直流電塵位準後輸出成為一阻抗調整信號。該第五 運算放大器A5之正相輪入端接收該修正信號‘,而反相 輪入端與該第九電阻以之―端電性連接,且輸出端輸出該 技準信號歸麵_ADJ’該第八電容α及該第八電阻 15 1279551 R8跨接於該第五運算放大器,A5之反相輸人端與輸出端間 忒第九電阻R9之另一端與該電壓控制可變電阻單元1Μ 之第一端1321電性連接。該電壓控制可變電阻單元之 第,端1322—與該加法單元131電性連接且接收該阻抗調整 ^ 而/、苐一玄而1為接地電麼。該電產控制可變電阻 早70 132之第一端與第三端間的電阻值可藉由改變其第二端 之電壓來凋整。在本發明之較佳實施例中,該電壓控制可 變電阻單it 132是-Ν型通道場效電晶體(;FET),但不以此 该加法單元131包括一第六運算放大 容C9、一第十電阻Rl〇、一第十一電阻心、一第十 =R12及-第十三電阻幻3。該第六運算放大器从之 輸二端與該第十三電阻R13之—端及第十二電阻川之一 知電性連接,而其反相輸入端與該第十一電阻Ml之 、该第十雷/¾ > 抗听整彳—Γ 端電性連接,且其輸出端輸出該阻 琥’並與該第十電阻R10之另一端電性連接,該 -電⑯R13之另—端為接地電M,該第十二電阻⑽ t另一端輕合至—g ^ + φ 貞15V_壓源,該第九電容C9跨接於 以十電@㈣之兩端’該第十 該補償信號。 r電阻如之另-端接收 z補仏電路14包括一第七運算放大 容C12、一第+二弟十一電 ^ 一電谷C13、一第十四電容C14、一第-+ 二電阻R22、一第-本一不 昂一十 該第二+ -千—十二電阻肪及—第二十四電阻R24。 一二電&R23之—端與㈣十四電容C14之-端及 16 1279551The AC voltage to be tested corresponds to the measured value, and is output to a display (not shown) and can output a pulse width modulation signal pwM and a control signal to the AC mode, group i, the pulse The pulse width of the width modulation signal pwM is proportional to the error value of the measured value and the root mean square value of the AC to be tested, so that the AC filter module 1 adjusts the first output terminal AC_OUT The output voltage, the control signal can control the AC filter module i to appropriately attenuate the AC voltage to be tested when being measured in different voltages, and then output the AC output from the first output terminal AC-OUT. 踗; The chopper module 1 includes an AC chopper circuit, a flatness adjustment circuit 13, a compensation circuit 14, and an amplifying circuit 12. The interfering circuit u can receive the AC nickname FLATNESS ADJ to be tested. Externally, ...,, - After the voltage to be tested is appropriately deducted and filtered, a first ^ #义弟胡匕〇 is outputted to the amplifying circuit 12, and a first 跋F is outputted Ba Le 仏 %%% partial pressure and filter after the repair The signal 1279551 is sent to the flatness adjustment circuit 13 to enable the flatness adjustment circuit Η to sample the voltage of the first signal. The amplifying circuit 12 is electrically connected to the AC-DC voltage module 2 via the first output terminal AC-OUT. Connected, and the first signal ^c/ can be appropriately amplified and output to the first output terminal AC_OUT. The compensation circuit 14 can receive the pulse I degree modulation signal output by the digital signal processing module 3. And outputting a compensation signal to the flatness adjustment circuit 13, the voltage value of the compensation signal is inversely proportional to the pulse width of the pulse width modulation signal PWM. The flatness adjustment circuit 13 receives the compensation signal and the correction signal. The calibration signal FLATNESS_ADJ can be output to the AC filter circuit u, and the calibration signal FLATNESS_ADJ can adjust the first signal of the AC filter circuit. The AC wave circuit 11 includes a first operational amplifier ai, a first Capacitor C1, - second capacitor C2, a third capacitor 〇, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor π, a resistor R1, a second resistor R2, a first Two a wide resistance R3, a fourth resistor R4, a fifth resistor R5, a sixth electric spear, a resistor R6, a seventh resistor R7 and a first switch S1. The first operational amplification A 1 Xi X h aborigines The positive phase input terminal of the benefit A1 is grounded, and the complex inverting input terminal and one end of the fifth resistor R5, /, the inverting wheel and the fourth capacitor C4 of the ?H, one end of the second capacitor C2, The flute „日日石海^°Haidi one switch S1 one end, the life Chu Yuyu C6 one end and the second resistor R2 /, the capacitor electric I ug one end electrically connected the first signal 匕c/ And the turn-out end can be the same as the six-reactor, such as the _ terminal % channel 12, the third resistor R3, a μ amplification, the second resistor R2, the other end 12 1279551 :: Hai: five capacitor C5 One end and one end of the first resistor R1 are electrically connected to the other end of the resistor/6, and the other end of the resistor R6 is electrically connected to the end of the flatness adjusting circuit 13 and the seventh resistor R7, and the correction signal can be output. The other end of the seventh resistor R7 is a ground voltage. 4, the seventh electric valley C7 is connected in parallel with the sixth resistor R6, the other end of the fourth capacitor is electrically connected to the end of the third capacitor C3 and one end of the fourth electric 35R4, and the third capacitor C3 is another One end of the third input R3 is electrically connected to the other end of the sixth capacitor, and the other end of the fifth capacitor C5 is opposite to the other end of the first switch si. One end of a capacitor C1 and the other end of the first resistor R1 are electrically connected, and the other end of the second capacitor C2 is electrically connected to the other end of the first capacitor C1 and can receive the calibration signal FLATNess_adj. The other end of the fourth resistor R4 is electrically connected to the other end of the fifth resistor R5. The amplifying circuit 12 includes a second switch S2, a third switch, a fourth switch S4, a fifth switch S5, a sixth switch%, a first discharge unit 121, an amplification unit 122, and a buffer unit. ^23. One end of the second switch S2 is electrically connected to the AC filter circuit n, and can receive the first signal 匕c/, and the other end is electrically connected to the first amplifying unit 121. The first amplifying unit 121 receives the first signal Gc/ via the second switch S2, and can amplify the first signal by a factor of 1 to become a second L number. One end of the fifth switch S5 is electrically connected to the alternating current filter circuit ,, and can receive the first signal, and the other end is electrically connected to the two amplifying units. One end of the sixth switch S6 is electrically connected to the first amplifying unit 121, and can receive the second signal, and the other end is electrically connected to the 1331307951 two amplifying unit m. The second amplifying unit i22 can receive the first signal ^ via the cough, and can receive the second signal ~2 via the sixth switch %, and can amplify the signals by 10 times to become - third. The end of the fourth switch 84 of the nickname Fw is electrically connected to the AC slot circuit and can receive the first signal 匕. And the other end is electrically connected to the buffer unit 123. One end of the third switch S3 is electrically connected to the second amplifying unit, and can receive the third signal ^, and the other __ terminal is electrically connected to the buffer. The buffer unit (2) can receive the 5th-signal~ via the four switches, and can receive the third signal ' via the third switch s3, and can output the signals to the first output AC-OUT . The switches S1 S S6 can be controlled to be turned on or off by a control signal output from the digital signal processing module 3. The first amplifying unit 121 includes a fourteenth resistor phantom 4, a fifteenth resistor R15, a +^, a resistor R16 and a second operational amplifier A2. One end of the fourteenth resistor R14 is electrically connected to the positive terminal of the second switch and the second operational amplifier A2. The other end of the fourteenth resistor R14 is connected: the fifteenth resistor R15 Connected between the ground voltage and the second operation from the inverting input end of the amplifier A2, the sixteenth resistor 跨 $ is connected to the inverting input end and the output end of the second amplifier A2 Between the output of the second blade and the output of the second switch is electrically connected to the sixth switch and output the second signal. 〆 The first magnification unit! 22 includes a seventeenth resistor Ri7, an eighteenth, a Chuanchuan, a 'thirteenth resistor R19, and a third operational amplifier A3. The first phase input terminal of the first amplification state A3 and the fifth switch Μ and the 14th 1279551 are connected, the seventeenth resistor R17 is connected to the ground potential and the positive phase wheel of the rJ:: 'amplifier A3 Between the input terminals, the eighteenth resistor ground potential and the inverting input terminal of the third operational amplifier A3 are connected to the opposite end of the third operational amplifier A3. The output terminal of the third operational amplifier 可 can be connected to the third switch and electrically connected to the third switch. /, 友冲单疋123 includes a fourth operational amplifier A4, a tenth electric (10), a tenth-capacitor C11, a twenty-first resistor R21 twenty-resistance R20. Continued ® This two - a cry ° One of the electric CU one end, the fourth operational amplification i the first round of the human end and the twentieth resistance (four) - the end of the electrical connection, = * CU the other end and the fourth The switch S4 and the third switch are electrically connected, and the inverting input end of the fourth operational amplifier $A4 is electrically connected to one end of the second eleventh yang + resistor R21, and the twentieth R20 The other end is a ground voltage, the twentieth-electric P and the other end of R21 is the first-output AC_0UT, and the tenth capacitor C10 is connected across the two twentieth-resistors R21. The flatness adjustment circuit 13 includes a fifth operational amplifier Al§ A5, an eight electric valley C8, an eighth resistor R only, a spear resistor R8, a young nine resistor R9, an adding unit m, and an electric_variable Resistor unit 132. The adding unit 13 is electrically connected to the compensation circuit, and is connected to the (4) compensation signal, and outputs the compensation signal to the DC dust level to be an impedance adjustment signal. The positive phase wheel terminal of the fifth operational amplifier A5 receives the correction signal ', and the inverting wheel terminal is electrically connected to the ninth resistor, and the output terminal outputs the reference signal _ADJ' The eighth capacitor α and the eighth resistor 15 1279551 R8 are connected across the fifth operational amplifier, and the other end of the ninth resistor R9 between the inverting input terminal and the output terminal of the A5 and the voltage control variable resistance unit 1 The first end 1321 is electrically connected. The first terminal 1322 of the voltage control variable resistance unit is electrically connected to the adding unit 131 and receives the impedance adjustment ^ and /, and the ground is electrically connected. The resistance of the electric control variable resistor between the first end and the third end of the early 70 132 can be reduced by changing the voltage of the second end. In a preferred embodiment of the present invention, the voltage-controlled variable resistor single-it 132 is a Ν-type channel field effect transistor (FET), but the addition unit 131 does not include a sixth operational amplification capacitor C9. A tenth resistor R1〇, an eleventh resistor core, a tenth=R12 and a thirteenth resistor illusion 3. The sixth operational amplifier is electrically connected to the end of the thirteenth resistor R13 and the twelfth resistor, and the inverting input terminal and the eleventh resistor M1 are Ten lightning / 3⁄4 > anti-listening - Γ end electrical connection, and its output terminal outputs the resistance s and is electrically connected to the other end of the tenth resistor R10, the other end of the electric 16R13 is grounded Electric M, the other end of the twelfth resistor (10) t is lightly coupled to a -g ^ + φ 贞 15V_voltage source, and the ninth capacitor C9 is connected across the tenth of the tenth electric power (four) to the tenth compensation signal. The r resistor as the other end receiving z compensation circuit 14 includes a seventh operational amplification capacitor C12, a second + eleven eleven electric ^ one electric valley C13, a fourteenth capacitor C14, a first - + two resistor R22 One, the first - the first one is not the same as the second + - thousand - twelve resistors and - the twenty-fourth resistor R24. One or two electric & R23 - end and (four) fourteen capacitor C14 - end and 16 1279551

-x第Γ十四電阻R24之—端電性連接,且另—端與該第十 ,電:C12之一端及該第二十二電阻R22之一端電性連接 一十四電阻R24之另一端接收該脈衝寬度調變信號 亥第十四電谷C14之另一端為接地,該第十二電容C12 之另-端與該第七運算放大器A7之反相輸入端及輸出端電 :連接’該第二十二電p且R22之另一端與該第七運算放大 :土7之正相輪入端、該第十三電容⑶之一端電性連接, 忒第十二電容C13之另一端為接地電壓。 沪該交流濾波電路11及該放大電路12須將由該第一輸入 端/C—IN接收之該待測電壓加以適當地調整及濾波,以使 :第一輸出端AC 一 0UT之電壓之均方根值在2V以内。該第 電阻R1、該第三電阻R3、該第六電戸且R6、該第七電阻 ^ ^第電谷C1、該第五電容C5、該第六電容C6及該 第七電备C7組成之電路具有濾波效果,可使所有量測範圍 =待測交流電壓於頻率8MHz時便可衰減達3〇此以上。該 2電容C4跨接於該第四電阻R4及第五電阻R5可增加該 又/危渡波電路11之頻寬到300KHZ。 王#當量測均方根值在〇.1V以内之電壓時,該數位信號處 :模組3將該第二開關S2、第三開關S3及第六開關%設 疋為關閉,且將該第一開關S1、第四開關S4及第五開關 “開啟,该第一運算放大器A1、該第二電阻R2、該第四 電二R4及該第五電阻R5組成增益值為一及池+幻_〇 2(在 本實知例中’調整第二、第四、第五電阻R2、R4、R5的值 ,使增益為-0.2,但不以此為限),使該待測電壓衰減5倍-x the fourth end of the fourteenth resistor R24 is electrically connected, and the other end and the tenth, the one end of the electric: C12 and one end of the twenty-second resistor R22 are electrically connected to the other end of the fourteen resistor R24 Receiving the pulse width modulation signal, the other end of the fourteenth electric valley C14 is grounded, and the other end of the twelfth capacitor C12 is electrically connected to the inverting input end and the output end of the seventh operational amplifier A7. The twenty-second electric power p and the other end of the R22 are amplified by the seventh operation: the positive phase wheel of the soil 7 and one end of the thirteenth capacitor (3) are electrically connected, and the other end of the twelfth capacitor C13 is the ground voltage. . The AC filter circuit 11 and the amplifying circuit 12 must appropriately adjust and filter the voltage to be tested received by the first input terminal /C-IN so that the voltage of the first output terminal AC-UT is squared. The root value is within 2V. The first resistor R1, the third resistor R3, the sixth power and R6, the seventh resistor, the fifth capacitor C5, the sixth capacitor C6, and the seventh device C7 The circuit has a filtering effect, so that all measurement ranges = the AC voltage to be tested can be attenuated by more than 3 于 at a frequency of 8 MHz. The two capacitors C4 are connected across the fourth resistor R4 and the fifth resistor R5 to increase the bandwidth of the /over-wave circuit 11 to 300 kHz. When the voltage of the rms value is less than 11V, the digital signal is: the module 3 sets the second switch S2, the third switch S3 and the sixth switch % to be off, and The first switch S1, the fourth switch S4 and the fifth switch are "on", and the first operational amplifier A1, the second resistor R2, the fourth electrical two R4 and the fifth resistor R5 form a gain value of one and a pool + magic _〇2 (In the present example, 'adjust the values of the second, fourth, and fifth resistors R2, R4, and R5 so that the gain is -0.2, but not limited thereto), and the voltage to be tested is attenuated by 5 Times

17 1279551 成為δ亥第一信號。該第一信號^C/送至該第一放大單 元丨21放大1〇倍後成為均方根值〇·2ν以内之第二信號 Gc,,再由該第二放大單元122放大1〇倍後成為均方根值 2V以内之第三信號,由該緩衝單元123輸出至該第一 輪出端AC—OUT。 當量測均方根值在0.1V〜IV之電壓時,該數位信號處 • 理模組3將該第三開關S3及第五開關S5設定為關閉,且 •鲁 將該第一開關S1、該第二開關S2、第四開關S4及第六開 關S6開啟。同樣地,該第一運算放大器A1、該第二電阻 R2、該第四電阻R4及該第五電阻R5所組成之電路,可將 "亥待/則電壓衰減5倍成為該第一信號^。該第一信號 dc/ 11至忒第_放大單元122放大1〇倍後成為均方根值2ν 以内之第二信號G口,再由該緩衝單元123輸出至該第一 輸出端AC—OUT 〇 ^當量測均方根值在IV〜10V之電壓時,該數位信號處理 % 模、且3將"亥第四開關S4設定為關閉,且將該第一開關s J、 该第一開關S2、第三開關S3、第五開關S5及第六開關% ,啟:同樣地,該第一運算放大器A1、該第二電阻R2、該 第:電阻R4及該第五電阻R5組成之電路,可使該待測電 [衰減5倍成為均方根值2V以内之第—信號^。該第一 佗唬GC/送至該緩衝單元123,並輸出至該第一輸出端 AC_OUT 〇 當置測均方根值在10V〜100V之電壓時,該第一 S1關閉。哕坌 + 違第一電阻R1及該第二電阻R2並聯,連同該第 18 1279551 -運算放大器A1、該第四電阻R4及該第五電阻r5組成增 益值為V汍-ο·〇〇2之電路且具有反相放大 效果,可使該待測電壓衰減500倍成為該第一信號匕〇。 該數位信號處理模組3將該放大電路12之第三開關s3及 第五開關S5設定為關閉,且將第二開關S2、該第四開關 S4及第六開關S6開啟’該第_信號^送至該第二放大17 1279551 becomes the first signal of δhai. The first signal ^C/ is sent to the first amplifying unit 21 to be amplified by 1〇 and becomes a second signal Gc within the root mean square value 〇·2ν, and then amplified by the second amplifying unit 122 by 1〇 times. The third signal within 2V of the rms value is outputted by the buffer unit 123 to the first round-out terminal AC_OUT. When the rms value of the RMS is between 0.1V and IV, the digital signal processing module 3 sets the third switch S3 and the fifth switch S5 to be off, and • the first switch S1 The second switch S2, the fourth switch S4, and the sixth switch S6 are turned on. Similarly, the circuit composed of the first operational amplifier A1, the second resistor R2, the fourth resistor R4, and the fifth resistor R5 can attenuate the "Hui/wait voltage by 5 times to become the first signal^ . The first signal dc / 11 to 忒 the amplifying unit 122 is amplified by a factor of 1 and becomes a second signal G port within the root mean square value 2ν, and then outputted by the buffer unit 123 to the first output terminal AC_OUT 〇 ^The equivalent rms value is at a voltage of IV~10V, the digital signal processing % modulo, and 3 sets the "Hai fourth switch S4 to off, and the first switch s J, the first switch S2, the third switch S3, the fifth switch S5, and the sixth switch %, in the same manner, the circuit of the first operational amplifier A1, the second resistor R2, the first resistor R4 and the fifth resistor R5, The electric power to be tested can be attenuated by 5 times to become the first signal within the rms value of 2V. The first 佗唬GC/ is sent to the buffer unit 123 and output to the first output terminal AC_OUT. When the rms value is set to a voltage of 10V~100V, the first S1 is turned off.哕坌+ violates the first resistor R1 and the second resistor R2 in parallel, together with the 18th 1279551 - the operational amplifier A1, the fourth resistor R4 and the fifth resistor r5 form a gain value of V汍-ο·〇〇2 The circuit has an inverting amplification effect, and the voltage to be tested is attenuated by 500 times to become the first signal 匕〇. The digital signal processing module 3 sets the third switch s3 and the fifth switch S5 of the amplifying circuit 12 to be off, and turns on the second switch S2, the fourth switch S4 and the sixth switch S6. Send to the second zoom

單元122放大1〇倍後成為均方根值2V以内之第三信號 再由該緩衝單元123輸出至該第一輸出端ac—〇υτ。 當S測均方根值在100V〜750V之電壓時,該第一開關 si關閉。同樣地,該第一電阻R1、該第二電阻R2、該第 一運异放大态A1、該第四電阻R4及該第五電阻R5組成增 益值為-0.002之電路,可使該待測電壓反相衰減5〇〇倍成為 忒第一佗號6 c/。該數位信號處理模組3將該放大電路丄2 之第四開關S4設定為關閉,且將該第二開關S2、第三開關 S3、第五開關S5及第六開關S6開啟,該第一信號6C7送 至该緩衝單元123 ’並輸出至該第一輸出端ac OUT。 值付注思的是’該交流慮波電路11中之第四電容C4 跨接於該第四及第五電阻R4、R5,因此會在該交流濾波電 路11引進一極點(pole)頻率。參閱圖5,橫軸為該第一輸入 端AC一IN之電壓頻率,且縱軸為該第一信號^〇與該第— 輸入端AC一IN電壓之比值,即該交流濾波電路n之增益值 。當該校準信號FLATNESS_ADJ未輸入該交流濾波電路^ 前,由於該第四電容C4引進一頻率約為3MHz之極點,若 该待測電壓中具有相對應於該極點頻率成分之交流電壓, 19 1279551 該交流濾波電路η對該交流電壓之増益值為負_,將比 頻寬内之其他頻率電壓之增益值負13 979此特別大 ’圖5中頻率約為1 Hz的交法雷厭;—以、, ]又/爪電麼之增益值約為-16db,遠 較13.979db為小,此部份頻率 只千又、盈值可精由調整該第三 電容C3之大小而加以平坦化。 為了避免該極點頻率之交流待測電壓被衰減的倍數不 :於頻寬内之其他頻率電壓,以維持該交㈣波電路^頻After the unit 122 is amplified by a factor of 1 and becomes a third signal having a root mean square value of 2 V, the buffer unit 123 outputs the first signal to the first output terminal ac_〇υτ. When S measures the rms voltage at a voltage of 100V to 750V, the first switch si is turned off. Similarly, the first resistor R1, the second resistor R2, the first different polarization state A1, the fourth resistor R4, and the fifth resistor R5 form a circuit with a gain value of -0.002, and the voltage to be tested can be used. The inverse attenuation is 5〇〇 times and becomes the first 佗6 c/. The digital signal processing module 3 sets the fourth switch S4 of the amplifying circuit 丄2 to be turned off, and turns on the second switch S2, the third switch S3, the fifth switch S5 and the sixth switch S6, the first signal 6C7 is sent to the buffer unit 123' and output to the first output terminal ac OUT. It is worth noting that the fourth capacitor C4 in the AC wave circuit 11 is connected across the fourth and fifth resistors R4 and R5, so that a pole frequency is introduced in the AC filter circuit 11. Referring to FIG. 5, the horizontal axis is the voltage frequency of the first input terminal AC-IN, and the vertical axis is the ratio of the first signal and the first input terminal AC-IN voltage, that is, the gain of the AC filter circuit n. value. Before the calibration signal FLATNESS_ADJ is not input to the AC filter circuit ^, since the fourth capacitor C4 introduces a pole having a frequency of about 3 MHz, if the voltage to be tested has an AC voltage corresponding to the pole frequency component, 19 1279551 The AC filter circuit η has a negative value of 交流 for the AC voltage, and the gain value of the other frequency voltages within the bandwidth is negative by 13 979. This is particularly large. The frequency of the signal in FIG. 5 is about 1 Hz. , , ] / / claw power, the gain value is about -16db, which is much smaller than 13.979db. This part of the frequency is only a thousand, and the profit value can be flattened by adjusting the size of the third capacitor C3. In order to avoid the multiple of the AC voltage to be measured at the pole frequency is not attenuated: other frequency voltages within the bandwidth to maintain the cross (four) wave circuit

見内之增i值的-致性’須預先對該極點頻率之電塵做校 正處理。 田句方根值Μ之頻寬内且不等於極點頻率的低頻基 準信號由該第一輸入端AC—IN送入時,該數位信號處理模 組3儲存該基準信號的電壓值M。接著送入另一頻率正好 為極點頻率且均方根值同樣為Μ之極點頻率信號,由於該 交流濾波模組i對該極點頻率信號之電壓增益值不同,該 數位信號處理模組3將得到該信號之量測值為M,,並比 車又Μ與JV[之决差值。若誤差超出容許範圍則該數位信號 處理模組3儲存Μ_Μ,之值,並送出該脈衝寬度與龍, 相對應成正比的該脈波寬度調變信號PWM至該補償電路 。中、、、二忒補償電路14將該脈波寬度調變信號PWM濾成 電壓值與該脈波寬度調變信號PWM之脈衝寬度成反比之 直流的補償信號,再送入該加法單元131。 該負15V之電壓與該補償信號分別送入該加法單元i3i 相加孩加法單元131將調整該補償信號之直流電壓位準 了 ^工制違為场效電晶體之電塵控制可變電阻單元 20 1279551 132操作於電阻區(triode region)之阻抗調整信號,且該阻抗 調整信號之電壓值不可大於其夹止電壓(pinch_〇ff v〇hage)。 该阻抗_整^號調整該電壓控制可變電阻單元1 之 電阻值,連同該第九電阻R9可改變該第五運算放大器A5 之回授增益(feed-back gain)。而該修正信號匕〜是由該第 六電阻R6及第七電阻R7將對應於該極點頻率信號之第一 信號Gc/加以分壓及濾波所得,並送入該第五運算放大器 A5之正相輸入端,並加以放大輸出成為該正相之校準信號 FLATNESS—ADJ。該校準信號]pLATNESS-ADJ透過該第二 電谷C2送入该弟一運算放大器人丨之反相輸入端,可調整 相對於該極點頻率信號之第一信號之電壓值,連帶地 使该數位信號處理模組3接收到之該極點頻率信號的量測 值Μ接近Μ,且達到可接受的誤差範圍。 由於該交流濾波電路11對每一交流電壓量測範圍之極 點頻率皆相同,因此該平坦度調整電路13也只須對該極點 頻率之不同電壓量測範圍作調整。為了不讓每次量測都須 送一基準信號而增加量測困難度,所以該數位信號處理模 組3可預先將不同電壓範圍之交流電壓相對應的誤差值Μ-Μ儲存起來,只要選取到該交流電壓量測範圍,即可將預 存於該數位信號處理模組3之誤差值Μ_Μ,經由脈波寬度 调變信號PWM輸出,以補償該極點頻率之交流電壓的量測 值Μ’ ,使該交流濾波電路11於頻寬範圍内之交流電壓的 增益值維持一致。 參閱圖6’該校準信號FLATNESS—ADJ輸入該交流濾 21 1279551 波電路 11 /夂 >正该極點頻率之增盈值後,可使該交流渡波電 路11之頻寬達到3〇〇KHz,且維持頻寬内增益值之一致性 0 、、’τ、合上述,本發明透過該交流濾波電路11之第一電阻 R1、第二電阻R3、第六電阻R6、第七電阻R7、第一電容 ci、第五電容。、第六電容C6及第七電容C7,使該待測 交流電壓之頻率於8MHz時便可衰減達3〇db以上,使該交 流濾波電路U對所有量測範圍之交流電壓皆有良好濾波效 果,且透過該第四電容C4使頻寬增加到300KHZ。而雖然 忒第四電谷C4會於該交流濾波電路u之3〇〇KHz頻寬範圍 内引進一極點頻率,但可藉由該數位信號處理模組3、該補 償電路14及該平坦度調整電路13將對應於該極點頻率之 交流電壓予以增益補償,以維持該交流濾波電路u在 300KHz頻寬内增益值之一致性,確實能達到本發明之目的 〇 惟以上所述者,僅為本發明之較佳實施例而已,當不 能以此限定本發明實施之範圍,即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾,皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一習知電壓量測裝置之簡化電路圖,說明一交 流濾波模組之電路; 圖2是一該習知電壓量測裝置之交流濾波模組之波德 圖,說明遠父流渡波板組之頻寬不及3ookHz ; 22 1279551 圖3是本發明電壓量測裝'置之方塊圖; 圖4是一交流濾、波模組之詳細電路圖; 圖5是一未接收一校準信號之一交流濾波模組的波德 圖,說明一極點頻率之增益值較大;及 圖6是一經過該校準信號修正增益值之該交流濾波模 組的波德圖。Seeing the value of the increase in the value of i must be corrected in advance for the dust of the pole frequency. The digital signal processing module 3 stores the voltage value M of the reference signal when the low frequency reference signal within the bandwidth of the field and not equal to the pole frequency is fed by the first input terminal AC_IN. Then, another frequency signal whose peak frequency is exactly the pole frequency and whose rms value is also Μ is sent. Since the voltage gain value of the pole frequency signal is different for the AC filter module i, the digital signal processing module 3 will obtain The measured value of this signal is M, and is more than the difference between the car and the JV. If the error exceeds the allowable range, the digital signal processing module 3 stores the value of Μ_Μ, and sends the pulse width modulation signal PWM proportional to the pulse width to the dragon, to the compensation circuit. The middle, and second compensation circuit 14 filters the pulse width modulation signal PWM into a DC compensation signal whose voltage value is inversely proportional to the pulse width of the pulse width modulation signal PWM, and sends the compensation signal to the addition unit 131. The voltage of the negative 15V and the compensation signal are respectively sent to the adding unit i3i, and the adding unit 131 adjusts the DC voltage level of the compensation signal. The electric dust control variable resistance unit that violates the field effect transistor 20 1279551 132 operates an impedance adjustment signal in a triode region, and the voltage value of the impedance adjustment signal cannot be greater than its pinch voltage (pinch_〇ff v〇hage). The impedance_integrator adjusts the resistance value of the voltage control variable resistance unit 1, and the ninth resistor R9 changes the feedback-back gain of the fifth operational amplifier A5. The correction signal 匕~ is obtained by dividing and filtering the first signal Gc/ corresponding to the pole frequency signal by the sixth resistor R6 and the seventh resistor R7, and feeding the positive phase of the fifth operational amplifier A5. The input terminal is amplified and becomes the calibration signal FLATNESS_ADJ of the positive phase. The calibration signal] pLATNESS-ADJ is sent to the inverting input terminal of the analog amplifier by the second electric valley C2, and the voltage value of the first signal relative to the pole frequency signal can be adjusted, and the digit is associated The measured value of the pole frequency signal received by the signal processing module 3 is close to Μ and reaches an acceptable error range. Since the AC filter circuit 11 has the same pole frequency for each AC voltage measurement range, the flatness adjustment circuit 13 only needs to adjust the different voltage measurement ranges of the pole frequency. In order not to increase the measurement difficulty by sending a reference signal for each measurement, the digital signal processing module 3 can store the error value Μ-Μ corresponding to the AC voltage of different voltage ranges in advance, as long as the selection is performed. Up to the AC voltage measurement range, the error value Μ_Μ prestored in the digital signal processing module 3 can be output via the pulse width modulation signal PWM to compensate the measured value of the AC voltage of the pole frequency Μ', The gain value of the AC voltage in the bandwidth range of the AC filter circuit 11 is maintained to be uniform. Referring to FIG. 6 'the calibration signal FLATNESS_ADJ inputting the AC filter 21 1279551 wave circuit 11 /夂>, after the gain value of the pole frequency, the bandwidth of the AC wave circuit 11 can be 3 〇〇 KHz, and Maintaining the consistency of the gain values in the bandwidth 0, , 'τ, and the above, the first resistor R1, the second resistor R3, the sixth resistor R6, the seventh resistor R7, and the first capacitor through the AC filter circuit 11 of the present invention Ci, the fifth capacitor. The sixth capacitor C6 and the seventh capacitor C7 enable the frequency of the AC voltage to be tested to be attenuated by more than 3 〇db at 8 MHz, so that the AC filter circuit U has a good filtering effect on the AC voltages of all measurement ranges. And the bandwidth is increased to 300 kHz through the fourth capacitor C4. The fourth electric valley C4 introduces a pole frequency in the range of 3 〇〇 KHz of the AC filter circuit u, but the digital signal processing module 3, the compensation circuit 14 and the flatness adjustment can be adopted. The circuit 13 performs gain compensation on the AC voltage corresponding to the pole frequency to maintain the consistency of the gain value of the AC filter circuit u in the 300 kHz bandwidth, and can indeed achieve the object of the present invention. The preferred embodiments of the present invention are not intended to limit the scope of the present invention, and the simple equivalent changes and modifications made in the scope of the invention and the description of the invention are still within the scope of the invention. Inside. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified circuit diagram of a conventional voltage measuring device, illustrating a circuit of an alternating current filtering module; FIG. 2 is a Bode diagram of an alternating current filtering module of the conventional voltage measuring device. It is shown that the bandwidth of the far-passing wave board group is less than 3 oo kHz; 22 1279551 Figure 3 is a block diagram of the voltage measuring device of the present invention; Figure 4 is a detailed circuit diagram of an AC filter and wave module; Figure 5 is an unreceived A Bode diagram of an AC filter module of a calibration signal indicates that the gain value of one pole frequency is large; and FIG. 6 is a Bode diagram of the AC filter module that corrects the gain value after the calibration signal.

23twenty three

1279551 【主要元件符號說明】 1 · . ♦ 交流濾波模組 2 · · · 交流轉直流電壓 模組 3 · ·. 數位信號處理模 組 11··· 交流濾波電路 12 · ·. 放大電路 121… 第一放大單元 122… 第二放大單元 123 · · 緩衝單元 1 3 · · ♦ 平坦度調整電路 1 3 1 ♦ · 加法單元 132 · · 電壓控制可變電 阻單元 14· . ♦ 補償電路 A1 ♦ · 第一運算放大器 A2 · · 第二運算放大器 A3 · · 第三運算放大器 A4 ♦ · 第四運算放大器 A5 · · 第五運算放大器 A6 · · 第六運算放大器 A7 · · 第七運算放大器 C1 · · 第一電容 C2 · · C3 · · C4 · · C5 · · C6 · · C7 · · C8 ·. C9 · * CIO · · CH · · C12 * · C13 · · C14 · · R1 , · R2 * · R3 ·. R4 · · R5 · · R6 · · R7 ·. R8 ♦. R9 · · R10 · · 第二電容 第三電容 第四電容 第五電容 第六電容 第七電容 第八電容 第九電容 第十電容 第十一電容 第十二電容 第十三電容 第十四電容 第一電阻 第二電阻 第三電阻 第四電阻 第五電阻 第六電阻 第七電阻 第八電阻 第九電阻 第十電阻 24 12795511279551 [Description of main component symbols] 1 · . ♦ AC filter module 2 · · · AC to DC voltage module 3 · ·. Digital signal processing module 11··· AC filter circuit 12 · ·. Amplifier circuit 121... An amplifying unit 122... A second amplifying unit 123 · · Buffer unit 1 3 · · ♦ Flatness adjusting circuit 1 3 1 ♦ · Adding unit 132 · · Voltage control variable resistance unit 14 · . ♦ Compensation circuit A1 ♦ · First Operational amplifier A2 · · Second operational amplifier A3 · · Third operational amplifier A4 ♦ · Fourth operational amplifier A5 · · Fifth operational amplifier A6 · · Sixth operational amplifier A7 · · Seventh operational amplifier C1 · · First capacitor C2 · · C3 · · C4 · · C5 · · C6 · · C7 · · C8 ·. C9 · * CIO · · CH · · C12 * · C13 · · C14 · · R1 · · R2 * · R3 ·. R4 · · R5 · · R6 · · R7 ·. R8 ♦. R9 · · R10 · · Second capacitor third capacitor fourth capacitor fifth capacitor sixth capacitor seventh capacitor eighth capacitor ninth capacitor tenth capacitor eleventh capacitor Twelfth capacitor thirteenth Receiving a fourteenth resistor capacitance of the first resistance of the second resistor of the fourth resistor third fifth resistor sixth resistor seventh resistor eighth resistor ninth resistor tenth resistor 241,279,551

Rll · ♦ 第十一電阻 R12… 第十二電阻 R13… 第十三電阻 R14 ·. 第十四電阻 R15 · ♦ 第十五電阻 R16 · · 第十六電阻 R17 · · 第十七電阻 R18 . · 第十八電阻 R19… 第十九電阻 R20 ·, 第二十電阻 R21 · · 第二十一電阻 R22 · · 第二十二電阻 R23 ·. 第二十三電阻 R24 · · 第二十四電阻 AC—IN 第一輸入端 AC—OUT第一輸出端 FLATNESS_ADJ 校準信 號 PWM · 脈衝寬度調變信 號 VAcr、 第 — 信 號 VAC2· · 第 二 信 號 Vacs' * 第 三 信 號 vAC4· · 修 正 信 號 SI 第 一 開 關 S2—· 第 二 開 關 S3*… 第 三 開 關 S4· · · 第 四 開 關 S5,· · 第 五 開 關 S6· ·. 第 六 開 關R11 · ♦ eleventh resistor R12... twelfth resistor R13... thirteenth resistor R14 ·. fourteenth resistor R15 · ♦ fifteenth resistor R16 · · sixteenth resistor R17 · · seventeenth resistor R18 · The eighteenth resistor R19... The nineteenth resistor R20 ·, the twentieth resistor R21 · · The twenty-first resistor R22 · · The twenty-second resistor R23 · The twenty-third resistor R24 · · The twenty-fourth resistor AC —IN first input AC—OUT first output FLATNESS_ADJ calibration signal PWM · pulse width modulation signal VAcr, first signal VAC2· · second signal Vacs′ * third signal vAC4· · correction signal SI first switch S2 —·Second switch S3*... Third switch S4· · · Fourth switch S5, · · Fifth switch S6· ·. Sixth switch

2525

Claims (1)

Ϊ279551 十、申請專利範圍: h ~種電壓量測裝置,包含: 一可調整平坦度的交流濾波模組,具有一可接收待 測交流電壓之第一輸入端及一第一輸出端,並可針對該 寺貝]電壓予以適當地做“號衰減並據波後,經由該第一 輸出端輸出; 一交流轉直流電壓模組,與該交流濾波模組電性連 _ 接,並可接收該第一輸出端之交流電壓,且可將該交流 電壓轉換為一電壓值與該第一輸出端之交流電壓之均方 根值相等之直流電壓;及 一數位信號處理模組,可接收該交流轉直流電壓模 =輪出之直流電壓,且將該直流電壓依據其所在的量測 範圍轉換成一與該待測交流電壓相對應之量測值,並可 輸出一脈衝寬度調變信號及一控制信號至該交流濾波模 組,該脈衝寬度調變信號之脈衝寬度與該量測值及該待 Φ 測交流電壓之均方根值兩者之誤差值成正比,以供該交 流濾波模組調整該第一輸出端之輸出電壓,該控制信號 可控制邊父流濾波模組在不同之電壓量測範圍時,將該 待測交流電壓適當地做衰減後再由該第一輸出端輸出。 2·依據申請專利範圍第丨項所述之電壓量測裝置,其中, 該可調整平坦度的交流濾波模組包括一交流濾波電路、 平坦度凋整電路、一補償電路及一放大電路,該交流 濾波電路可接收該待測交流電壓,且可將該待測電壓予 以信號衰減並濾波成為一第一信號,並輸出至該放大電 26 •1279551 路,且輸出一由該第一信號分壓及濾波後所得之修正信 號至該平坦度調整電路,使該平坦度調整電路可取樣該 第一仏號之電壓,戎放大電路與該交流濾波電路電性連 接,且可將該第一信號予以適當地放大後輸出至該第一 輸出端,該補償電路可接收由該數位信號處理模組輸出 之脈衝寬度調變信號,並輸出一電壓值與該脈衝寬度調 變信號之脈衝寬度成反比之補償信號至該平坦度調整電 路,該平坦度調整電路接收該補償信號及該修正信號, 並可輸出一校準信號至該交流濾波電路,該校準信號可 調整該交流濾波電路之增益值以使該數位信號處理模組 判讀之量測值與該待測交流電壓之均方根值相等。 3·依據申請專利範圍帛2項所述之電壓量測裝置,其中, 該交流濾波模組之交流濾波電路包括一第一運算放大器 、'第-電容、一第二電容、一第三電容、一第四電容 、一第五電容、一第六電容、-第七電容、-第一電阻 、一第二電阻、一第三電阻、-第四電阻、-第五電阻 、'第六電阻、-第七電阻及-第-開關,該第—運算 放大盗之正相輸入端接地,且其反相輸入端與該第五電 :且之-端、該第四電容之-端、該第二電容之一端、該 “’關之一端、該第六電容之一端及該第二電阻之一 端電性連接’而其輸出端可輸出該第一信號,且 :電電:之-端、該放大電路、該第三電阻之-端:該第 一卩之另一端、該第五電容之一端及該 端電性連接,該篦山雪阳夕兄 电丨之 ’、 另一端與該平坦度調整電路 27 1279551 及該f七電阻之-端電性連接,並可輸出該修正信號, 而该第七電阻之另-端為接地電壓,該第七電容與該第 六電阻並聯,該第四電容之另一端與該第三電容之一端 及該第四電阻之一端電性連接,該第三電容之另—端= 為該第-輸入端’該第三電阻之另一端與該第六電容之 另-端電性連接,該第五電容之另一端與該第一開關之 另一端、該第一電容之一端及該第一電阻之另一端電性 連接,該第二電容之另—端與該第—電容之另—端電性 連接並可接收該校準信號,該第四電阻之另一端與該第 五電阻之另-端電性連接,該第一開關是受該數位信號 處理模組輸出之控制信號控制開啟或關閉。 4·依據申請專利範圍第3項所述之電壓量測裝置,其中 當該待測交流電壓之均方根值在〇·1ν以下、〇·1ν〜ιν以 及IV〜10V之範圍時,該數位信號處理模組輸出之控制 信號設定該第一開關為開啟;當該待測交流電壓之^方 根值在10V〜100V以及100V〜750V之範圍時,該數位俨 號處理模組輸出之控制信號設定該第一開關為關閉。 5 ·依據申請專利範圍第2項所述之電壓量測裝置,其中 該交流濾波模組之放大電路包括一第二開關、一第三開 關、一第四開關、一第五開關、一第六開關、一第—放 大單元、一第二放大單元及一緩衝單元,該第二開關之 一端與該交流濾波電路電性連接,且可接收該第_作號 ’而另一端與該第一放大單元電性連接,該第一放大單 元經由該第二開關接收該第一信號,並可將該第一传蒙Ϊ 279551 X. Patent application scope: h ~ kind of voltage measuring device, comprising: an AC filter module capable of adjusting flatness, having a first input end and a first output end capable of receiving an AC voltage to be tested, and According to the voltage of the temple, the voltage is appropriately attenuated and outputted through the first output terminal; an AC-to-DC voltage module is electrically connected to the AC filter module, and can receive the voltage An AC voltage of the first output terminal, and converting the AC voltage into a DC voltage having a voltage value equal to an rms value of the AC voltage of the first output terminal; and a digital signal processing module capable of receiving the AC The DC voltage mode is a DC voltage that is rotated, and the DC voltage is converted into a measured value corresponding to the AC voltage to be tested according to the measurement range in which it is located, and a pulse width modulation signal and a control are outputted. Signaling to the AC filter module, the pulse width of the pulse width modulation signal is proportional to the error value of the measured value and the root mean square value of the AC voltage to be measured for the communication The wave module adjusts an output voltage of the first output end, and the control signal can control the edge of the parental flow filter module to be appropriately attenuated after the voltage measurement range is different, and then the first output is The voltage measuring device according to the application scope of the invention, wherein the adjustable flatness AC filter module comprises an AC filter circuit, a flatness trimming circuit, a compensation circuit and an amplification a circuit, the AC filter circuit can receive the AC voltage to be tested, and can attenuate and filter the voltage to be measured into a first signal, and output the signal to the amplifying circuit 26 • 1279551, and output a first The signal obtained by dividing and filtering the signal is sent to the flatness adjusting circuit, so that the flatness adjusting circuit can sample the voltage of the first nickname, and the 戎 amplifying circuit is electrically connected to the alternating current filter circuit, and the A signal is appropriately amplified and output to the first output end, and the compensation circuit can receive the pulse width modulation signal output by the digital signal processing module, and input a compensation signal is inversely proportional to a pulse width of the pulse width modulation signal to the flatness adjustment circuit, the flatness adjustment circuit receives the compensation signal and the correction signal, and outputs a calibration signal to the AC filter circuit The calibration signal can adjust the gain value of the AC filter circuit such that the measured value of the digital signal processing module is equal to the root mean square value of the AC voltage to be tested. 3. According to the scope of the patent application 帛 2 The voltage measuring device of the AC filter module includes a first operational amplifier, a 'first capacitance, a second capacitance, a third capacitance, a fourth capacitance, a fifth capacitance, and a a sixth capacitor, a seventh capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a -th switch The first-phase input terminal of the first operation amplification ground is grounded, and the inverting input terminal and the fifth power: the - terminal, the end of the fourth capacitor, one end of the second capacitor, and the "off one end" One of the sixth capacitors The terminal and the second resistor are electrically connected to each other and the output terminal can output the first signal, and: the electric current: the end, the amplifying circuit, the end of the third resistor: the other end of the first One end of the fifth capacitor and the end are electrically connected, and the other end of the mountain is electrically connected to the flatness adjusting circuit 27 1279551 and the end of the f seven resistor, and can be output The correction signal, wherein the other end of the seventh resistor is a ground voltage, the seventh capacitor is connected in parallel with the sixth resistor, and the other end of the fourth capacitor is electrically connected to one end of the third capacitor and one end of the fourth resistor The other end of the third capacitor is electrically connected to the other end of the sixth capacitor, and the other end of the fifth capacitor is connected to the first The other end of the switch, one end of the first capacitor and the other end of the first resistor are electrically connected, and the other end of the second capacitor is electrically connected to the other end of the first capacitor and can receive the calibration signal. The other end of the fourth resistor is electrically connected to the other end of the fifth resistor The first switch control signal is the digital signal processing module receiving the output on or off. 4. The voltage measuring device according to claim 3, wherein when the root mean square value of the AC voltage to be tested is in the range of 〇·1ν, 〇·1ν~ιν, and IV~10V, the digit The control signal outputted by the signal processing module sets the first switch to be turned on; when the square root value of the AC voltage to be tested is in the range of 10V~100V and 100V~750V, the control signal output by the digital 处理 processing module Set the first switch to off. The voltage measuring device according to the second aspect of the patent application, wherein the amplifying circuit of the AC filter module comprises a second switch, a third switch, a fourth switch, a fifth switch, and a sixth a switch, a first amplifying unit, a second amplifying unit and a buffering unit, wherein one end of the second switch is electrically connected to the alternating current filter circuit, and can receive the _th sign and the other end and the first zoom The unit is electrically connected, the first amplifying unit receives the first signal via the second switch, and can transmit the first pass 28 1279551 放大倍後成為—第二信號,該第五開關之“端與該交流 遽波電路電性連接,且可接收該第_錢n端與 該二放大單元電性連接,該第六開關之-端與該第-放 $單元電=連接,並可接㈣第二信號,而$ 一端與該 第放大單元電性連接,該第二放大單元可經由該五開 關接收該第-信號,且可經由該第六開關接收該第二信 號並可將δ亥等仏號放大倍後成為一第三信號,該第四 «之-端與該交㈣波電路電性連接,且可接收該第 -信號,而另一端與該緩衝單元電性連接,該第三開關 ,一端與該第二放大單元電性連接,並可接收該第三信 说’而另-端與該緩衝單元電性連接,該緩衝單元可經 由:四開關接收6亥第一信號’且可經由該第三開關接收 該第三信號,並可將該等信號輸出至該第—輪出端,今 等開關是受該數位信號處理模組輸出之控 啟或關閉。 1 6.依據申請專利範圍第5項所述之電屢量測裝置,盆中, 當該待測交流之均方根值在㈣以下之範圍時,兮 數位信號處理模組輸出之控制信號設定該第二開闕、第 二開關及第六開關設定為關閉’且設定該第四開關及第 二開關開啟,·當量測均方根值在Q lv〜iv<電塵時,兮 1立=理模組將該第三開關及第五開關設定為關:; 均方根值在lv~lov之電=2開啟;當量測 兮莖 ^ 、 守,5亥數位信號處理模組將 "四汗關設定為關閉,且將該第二開關、第三開關、 29 1279551 第五開關及第六開關開啟;當量測均方… 10V〜100V之電壓時,^ f w亥數位信號處理模組將該第三開 關及第五開關設定為關閉’且將第二開關、該第四開關 以六開關開啟;當量測均方根值在膽〜750V之電壓 時’該數位信號處理握έΒ收4 Μ — 、、、、將该第四開關設定為關閉,且28 1279551 becomes a second signal after being amplified, and the "terminal" of the fifth switch is electrically connected to the AC chopper circuit, and can receive the first end of the n-th power and the second amplifying unit, the sixth switch The second terminal is electrically connected to the first signal, and the second signal is electrically connected to the first amplifying unit, and the second amplifying unit can receive the first signal via the five switches. And the second signal is received by the sixth switch, and the δ 仏 仏 放大 is amplified to become a third signal, and the fourth terminal is electrically connected to the alternating (four) wave circuit, and can receive the a first signal, and the other end is electrically connected to the buffer unit, the third switch is electrically connected to the second amplifying unit at one end, and can receive the third signal and the other end and the buffer unit are electrically connected. Connected, the buffer unit can receive the first signal by the four switches and can receive the third signal via the third switch, and can output the signals to the first wheel, and the switch is The digital signal processing module outputs the control on or off. 1 6. According to the electric measuring device according to item 5 of the patent application scope, in the basin, when the rms value of the to-be-tested communication is in the range below (4), the control signal output of the digital signal processing module is set. The second opening, the second switch and the sixth switch are set to be off and the fourth switch and the second switch are set to be turned on, and the rms value of the equivalent measurement is in the Q lv~iv<dust dust, = rational module sets the third switch and the fifth switch to off:; rms value in lv~lov power = 2 on; equivalent measurement stalk ^, shou, 5 hai digital signal processing module will be &quot ; four sweat off is set to off, and the second switch, the third switch, 29 1279551 fifth switch and the sixth switch are turned on; the equivalent measurement mean square ... 10V ~ 100V voltage, ^ fw Hai digital signal processing mode The group sets the third switch and the fifth switch to be off' and turns the second switch and the fourth switch to be turned on by six switches; when the equivalent rms value is at a voltage of biliary ~750V, the digital signal processing grip Receive 4 Μ — , , , , and set the fourth switch to off, and 將肩弟:開關、第三開關、第五開關及第六開關開啟。 忙據申明專利圍第5項所述之電壓量測裝置,其中, 忒放大電路之第一放大單元包括一第十四電阻、一第十 五電阻、—第十六電阻及—第二運算放大器,該第十四 電阻之-端與該第二開關、該第二運算放大器之正相輸 入端電性連接,該第十四電阻之另一端為接地,該第十 ,電阻跨接於接地電壓與該第二運算放大器之反相輸入 '而之間,該第十六電阻跨接於該第二運算放大器之反相 ,入端與輸出端之間,該第二運算放大器之輸出端與該 弟六開關電性連接並輸出該第二信號。 依據申。月專利範圍第5項所述之電壓量測裝置,直中, 該放大電路之該第二放大單元包括—第十七電阻y一第 十:)電阻、一第十九電阻及—第三運算放大器,該第三 運π放大盗之正相輸入端與該第五開關及該第六開關電 連接D亥第十七電阻跨接於接地電位與該第三運算放 ,器之正相輸入端之間,該第十八電阻跨接於接地電位 :該第三運算放大器之反相輸入端之間,該第十九電阻 〜接於該第三運算放大器之反相輸入端與輸出端之間, 该弟三運算放大器之輸出端可輸出該第二信號,並與該 30 1279551 第二開關電性連接。 9 ·依據申W專利範圍第5 Jg辦、+、七+ 示項所述之電壓量測裝置,其中, 第 該放大電路之該緩衝單亓☆社 十 野早兀包括一第四運算放大器 % 十電容、一第十一電容、一楚— 弟一十一電阻及一第二十雷 阻,該第十一電容之一妒 _ ^ 而、该弟四運算放大器之正相 入端及該第二十電阻之_六山中 ' * 丁电但之立而電性連接,該第十一電容 另:端與該第四開關及該第三開關電性連接,而該第四 運算放大器之反相輸人端與其輸出端、該第二十一 之一端電性連接,該第二+ 卜 卞窀阻之另一端為接地電壓, 5亥弟·一十'一電阻之另^一 % » Ms . 而P為该弟一輸出端,而該第 電容跨接於該第二十一電阻之兩端。 τ 10.依射請專利範圍第2項所述之《量測裝置,其中, 該交流濾波模組之平坦度調整電路包括一第五 器、一第八電容、-第八電阻、-第九電阻、一力 元及一電麼控制可轡雷k 佐剌了文電阻早兀,該加法單元與該補償 路電性連接且接收該補償传卢抑 丨貝乜唬,忒加法早凡可調整該補 償信號之直流電麗位準後成為一阻抗調整信號,該第五 f算放f器之正相輸人端接收該修正信號,而反相輸入 女而與该苐九電阻之一端雷把、* 4 ^而電性連接,且輸出端輸出該校準 佗號’該第八電容及該第八電阻跨接於該第五運算放大 器之反相輸入端與輸出端間’該第九電阻之另㈣ 電壓控制可變電阻單元之筮,山+ ^ ^ 〃 Μ 电丨早$之弟一端電性連接, 可變電阻單元之第二端盥兮,氺留—士以土 而一。亥加去早兀電性連接且接收該 阻抗調整信號,而盆第二☆山兔 八弟一而為接地電壓,該電壓控制可 31 1279551 變電阻單元之第一矬盘筮_山 知間的電阻值可藉由改變其 弟一知上阻抗調整信號之電壓來調整。 η·依據申請專利範圍第10項所述之電壓量測裳置,”, 該平坦度調整電路之加法 八 一楚干兀a栝弟/、運算放大器、 電谷、一第十電阻、-第十-電阻、一第十-電 該第十三電阻之一端二ΓΓ 正相輸入端與 而及弟十二電阻之-端電性連接,而 /、反相輸人端與該第十-電阻之—端、該第十電阻之一 接’且其輸出端輪出該阻抗調整信號,並與該 之另—端電性連接,該第十三電阻之另一端為 二該第十二電阻之另一端麵合至—電壓源,該 弟九電谷跨接於該第十電阻之兩端,該第十-電阻之另 一端接收該補償信號。 12.依據申請專利範圍第1〇項所述之電壓量測農置, 該平坦度調整電路之電壓控制可變電阻單元是一 N、型場 ==場效電晶體之源極接地,且其閘極接收該 几°正,而其汲極與該第九電阻電性連接。 U.依據中請專·圍第2項所述之電壓量測裝置,其中, ,交流據波電路之補償電路包括—第七運算放大器、一 第十一電谷、-第十三電容、-第十四電容、一第二十 二電阻、-第二十三電阻及一第二十四電阻,該第:十 二電阻之一端與該第十四電容之-端及該第二十四電阻 ΓΓ性連接,且另一端與該第十二電容之-端及該 十二電阻之—端電性連接,該第二十四電阻之另一 32 1279551 端接收該脈衝寬度調變信號,該第十四電容之另一端為 接地,#亥第十^電容之另一端肖該第七運算放大器之反 相輸入端及輸出端電性連接,該第二十二電阻之^一端 斤衷之正相輸入端、該第十三電容之一 端電性連接,該第十三電容之另一 ☆而為接地電壓。The shoulder brother: the switch, the third switch, the fifth switch, and the sixth switch are turned on. The voltage measuring device according to claim 5, wherein the first amplifying unit of the 忒 amplifying circuit comprises a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a second operational amplifier The end of the fourteenth resistor is electrically connected to the second switch and the non-inverting input terminal of the second operational amplifier, and the other end of the fourteenth resistor is grounded. The tenth, the resistor is connected to the ground voltage. And the inverting input ' of the second operational amplifier, the sixteenth resistor is connected across the inversion of the second operational amplifier, between the input end and the output end, and the output end of the second operational amplifier The sixth switch is electrically connected and outputs the second signal. According to Shen. The voltage measuring device according to item 5 of the patent scope of the present invention, wherein the second amplifying unit of the amplifying circuit comprises a seventeenth resistor y - tenth :) a resistor, a nineteenth resistor and a third operation An amplifier, the third phase π amplification thief of the positive phase input terminal is electrically connected to the fifth switch and the sixth switch, and the seventeenth resistor is connected to the ground potential and the third phase of the third operational amplifier The 18th resistor is connected to the ground potential: between the inverting input terminals of the third operational amplifier, the 19th resistor is connected between the inverting input terminal and the output terminal of the third operational amplifier The output of the third operational amplifier can output the second signal and is electrically connected to the 30 1279551 second switch. 9 · The voltage measuring device according to the 5th Jg, +, and 7+ indications of the patent application scope, wherein the buffering unit of the first amplifying circuit includes a fourth operational amplifier% Ten capacitors, one eleventh capacitor, one Chu—the eleventh resistor and one twentieth lightning resistance, one of the eleventh capacitors 妒 _ ^, the positive phase of the fourth operational amplifier and the first Twenty-six resistors _ Liushanzhong ' * Ding Dian but stand and electrically connected, the eleventh capacitor is another: the end is electrically connected to the fourth switch and the third switch, and the fourth operational amplifier is inverted The input end is electrically connected to the output end and the one end of the 21st, and the other end of the second + 卞窀 卞窀 is the ground voltage, and 5 亥 · 一 ' 一 一 » » » » » » » » » » » » » For the output of the brother, the first capacitor is connected across the second eleventh resistor. τ 10. The measuring device according to the second aspect of the patent, wherein the flatness adjusting circuit of the alternating current filtering module comprises a fifth device, an eighth capacitor, an eighth resistor, a ninth The resistance, the force element and the one electric control can be controlled by the 辔雷 k. The addition unit is electrically connected to the compensation circuit and receives the compensation. The addition method can be adjusted as early as possible. The DC signal of the compensation signal becomes an impedance adjustment signal, and the positive input terminal of the fifth f-counter receives the correction signal, and the inverting input is connected to the female and the thunder of the ninth resistor. * 4 ^ is electrically connected, and the output terminal outputs the calibration nickname 'the eighth capacitor and the eighth resistor are connected across the inverting input terminal and the output terminal of the fifth operational amplifier' (4) After the voltage-controlled variable resistance unit, the mountain + ^ ^ 〃 Μ is electrically connected to one end of the younger brother, the second end of the variable resistance unit is 盥兮, and the —-- Haijia goes to the early electrical connection and receives the impedance adjustment signal, while the second ☆ mountain rabbit eight brothers are the grounding voltage, the voltage control can be the first 矬 31 山 山 山 山The resistance value can be adjusted by changing the voltage of the impedance adjustment signal. η·According to the voltage measurement according to item 10 of the patent application scope,” the addition of the flatness adjustment circuit is abbreviated to a younger brother, an operational amplifier, an electric valley, a tenth resistance, and a Ten-resistor, a tenth-electrical one of the thirteenth resistors, one of the two terminals, the positive-phase input terminal and the other end of the twelve-second resistor are electrically connected, and the /-inverting input terminal and the tenth-resistor One end of the tenth resistor is connected to the end and the output end thereof rotates the impedance adjustment signal, and is electrically connected to the other end, and the other end of the thirteenth resistor is two of the twelfth resistor The other end is coupled to a voltage source, the dipole is connected across the tenth resistor, and the other end of the tenth resistor receives the compensation signal. 12. According to the scope of claim 1 The voltage measurement of the agricultural device, the voltage control variable resistance unit of the flatness adjustment circuit is an N, the field = the field source of the field effect transistor is grounded, and the gate receives the positive phase and the drain Electrically connected to the ninth resistor. U. According to the voltage measuring device described in item 2, The compensation circuit of the AC wave circuit includes a seventh operational amplifier, an eleventh electric valley, a thirteenth capacitance, a fourteenth capacitance, a twenty-second resistance, a twenty-third resistance, and a twenty-fourth resistor, one end of the twelve: twelve resistor is connected to the end of the fourteenth capacitor and the twenty-fourth resistor, and the other end and the end of the twelfth capacitor and the ten The other end of the two resistors is electrically connected, and the other 32 1279551 end of the twenty-fourth resistor receives the pulse width modulation signal, and the other end of the fourteenth capacitor is grounded, and the other end of the tenth capacitor is The inverting input end and the output end of the seventh operational amplifier are electrically connected, and the second-phase resistor is electrically connected to the positive-phase input end and one end of the thirteenth capacitor, and the thirteenth capacitor is electrically connected The other ☆ is the ground voltage. 3333
TW94115027A 2005-05-10 2005-05-10 Voltage measurement apparatus for filter module with adjustable planarity TWI279551B (en)

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