1278011 九、發明說明： 【發明所屬之技術領域】 本發明係有關於積體電路元件之測試技術，特別係有 關於一種適用於測試一積體電路元件之非壓迫式接觸方 法。 【先前技術】 習知積體電路元件需經過電性測試，以確保品質。在 ’則"式時’會預先在一測試機台之一插座板（socket board)上 結合一已安裝有複數個探觸針之測試插座（test socket)。之 後’將一積體電路元件放置於該測試插座上，並以一壓合 頭®迫δ亥積體電路元件，以使該測試插座之該些探觸針能 電性接觸至該積體電路元件，以供測試時之訊號與電源傳 輸。但隨著積體電路元件之薄化與高密度佈線設計，以直 接壓迫積體電路元件進行測試步驟係會造成積體電路元 件變形而導致探觸針接觸不良或是導致積體電路元件内 部之晶片或基板線路損傷。 睛參閱第1圖，一種積體電路元件1 〇係為球格陣列 封裝構造（Ball Gdd Array package，BGA)，其係為覆晶封 裴型態，以達到薄化、導熱佳與高密度傳輸之優點。該積 體電路元件10主要包含有一基板11、一設置於該基板U 上表面之晶片12以及複數個設置於該基板11下表面之外 接端13，如銲球（s〇lder baii)。該晶片12係以複數個凸塊 14覆晶接合至該基板u。並且，一底部填充膠15係可形 成於該晶片12與該基板11之間以密封該些凸塊14，由於 5 1278011 該晶片12係具有一裸露背面12A，因此整體結構強度比 傳統具有模封膠體（m〇lding c〇mp〇und)之積體電路元件更 弱且更薄。 請再參閱第1圖，在測試該積體電路元件1 〇時，— 測試插座110係已預先裝設一插座板（圖未繪出），該測試 插座11 0係具有一容置穴i i丨並結合有複數個探觸針 112，通常該些探觸針112係為彈簧針（p〇g〇 pin)並具有彈 • 性。之後，以一取放吸嘴120吸附該裸露背面12A或該積 體電路元件10之其它部位。接著，移動並放置該積體電 路元件10於該測試插座i丨〇之該容置穴i i J。 請參閱第2圖，藉由一壓合頭130壓迫該積體電路元 件1〇之該裸露背面12A，以使該積體電路元件1〇之該些 外接端13接觸該些探觸針112，其中該些探觸針ιΐ2係受 力而彈性收縮於該測試插座丨丨〇。由於該壓合頭13 〇係為 局部壓迫該積體電路元件10,因此容易造成該積體電路元 丨件10之該基板u翹曲變形，而使得部分探觸針112無法 接觸該積體電路元件10之該些外接端13，因而導致電性 測試時，發生誤判之情形。為避免部分探觸針丨Η無法接 觸該些外接端13,通常係增加該壓合頭13〇之壓迫力，以 確保該些探觸針112全部接觸該些外接端13，但因此亦造 成該積體電路元件10之該基板U之變形量增大，而導致 該積體電路元件10之該晶片12或該基板u之線路損壞。 【發明内容】 本發明之主要目的係在於提供一種適用於測試一積 6 1278011 體電路元件之非壓迫式接觸方法，首先，提供一測試插 座，該測試插座係設置有複數個探觸針並具有一容置穴以 及連通該容置穴之複數個排氣孔，藉由一抽氣減歷之步 驟，將該測試插座内之氣體經由該些排氣孔排出，令該容 置穴内之氣壓為低於外部環境壓力，以使在該容置穴内之 一積體電路元件之複數個外接端接觸至該些探觸針，由於 該測試插座係以該些排氣孔平均吸附該積體電路元件，因 丨此該些外接端係可均勻地接觸該測試插座之該些探觸 針，以避免該積體電路元件變形而造成該積體電路元件之 晶片或基板損壞，本發明特別適用於具有晶片裸露背面之 積體電路元件，例如覆晶型態之球格陣列封裝構造（bgA package) 〇 本發明之次一目的係在於提供一種非壓迫式接觸之 測试插座，其係設置有複數個探觸針並具有一容置穴、一 抽氣口以及連通該容置穴與該抽氣口之複數個排氣孔，每 ► 探觸針係具有_位於該容置穴内之接觸端。當抽氣減壓 夺在為谷置穴内空氣係經由該些排氣孔與該抽氣口排 出，而形成~ +A Λη ^ ^ ^勾之吸附力，因此該些探觸針之該些接觸 端係可W生接觸_位在該容置穴内之積體電4元件之複 數個外接端，&目+ 阳，、有一致之彈性收縮量，該測試插座係可 X適用於彈性接觸各式薄型、晶背裸露、覆晶型態或是困 難直接壓珀> 士 4 。 狀七陣列封裝構造（BGA package)，減少測試 損失與測試失真。 依據本發明之_種適用於測試一積體電路元件之非 7 1278011 壓迫式接觸方法，其係包含··提供一測試插座，談測試插 座係具有一容置六以及連通該容置穴之複數個排氣孔，且 該測試插座係設置有複數個探觸針，每一探觸針係具有一 位於該容置穴内之接觸端；取放一包含有一晶片及複數個 外接端之積體電路元件至該容置穴，並使得該些外接端對 準於該些探觸針之該些接觸端；以及，進行一抽氣減壓之 步驟，將該測試插座内之氣體經由該些排氣孔排出，令該1278011 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a test technique for integrated circuit components, and more particularly to a non-compressive contact method suitable for testing an integrated circuit component. [Prior Art] Conventional integrated circuit components are subjected to electrical testing to ensure quality. In the case of ''", a test socket with a plurality of probe pins installed in advance on a socket board of a test machine is combined. Then, an integrated circuit component is placed on the test socket, and a press-fit head is used to force the circuit components to electrically contact the probe pins of the test socket to the integrated circuit. Component for signal and power transfer during testing. However, with the thinning of the integrated circuit components and the high-density wiring design, the test step of directly pressing the integrated circuit components may cause the integrated circuit components to be deformed, resulting in poor contact of the probe pins or internal components of the integrated circuit components. The wafer or substrate line is damaged. Referring to Fig. 1, an integrated circuit component 1 is a Ball Gdd Array package (BGA), which is a flip chip type to achieve thinning, good thermal conductivity and high density transmission. The advantages. The integrated circuit component 10 mainly includes a substrate 11, a wafer 12 disposed on the upper surface of the substrate U, and a plurality of external terminals 13 disposed on the lower surface of the substrate 11, such as solder balls. The wafer 12 is flip-chip bonded to the substrate u by a plurality of bumps 14. Moreover, an underfill 15 can be formed between the wafer 12 and the substrate 11 to seal the bumps 14. Since the wafer 12 has a bare back surface 12A, the overall structural strength is more than the conventional one. The integrated circuit components of the colloid (m〇lding c〇mp〇und) are weaker and thinner. Referring to FIG. 1 again, when testing the integrated circuit component 1 ,, the test socket 110 is pre-installed with a socket board (not shown), and the test socket 110 has a receiving hole 丨In combination with a plurality of probe pins 112, the probe pins 112 are generally pistol pins and have elastic properties. Thereafter, the bare back surface 12A or other portions of the integrated circuit component 10 are adsorbed by a pick-and-place nozzle 120. Next, the integrated circuit component 10 is moved and placed in the receiving cavity i i J of the test socket. Referring to FIG. 2, the exposed back surface 12A of the integrated circuit component 1 is pressed by a pressing head 130 so that the external terminals 13 of the integrated circuit component 1 are in contact with the probe pins 112. The probe pins ι 2 are mechanically and elastically contracted to the test socket 丨丨〇. Since the pressing head 13 is partially pressed against the integrated circuit component 10, the substrate u of the integrated circuit component element 10 is easily warped and deformed, so that part of the probe pins 112 cannot contact the integrated circuit. The external terminals 13 of the component 10 thus cause a misjudgment when the electrical test is performed. In order to prevent some of the probe pins from contacting the external terminals 13, the pressing force of the pressing heads 13 is generally increased to ensure that the probe pins 112 all contact the external terminals 13, but this also causes The amount of deformation of the substrate U of the integrated circuit component 10 is increased, resulting in damage to the wiring of the wafer 12 or the substrate u of the integrated circuit component 10. SUMMARY OF THE INVENTION The main object of the present invention is to provide a non-compressive contact method suitable for testing a body circuit component of a 12 1278011 body. First, a test socket is provided. The test socket is provided with a plurality of probe pins and has a cavity and a plurality of vent holes connecting the accommodating hole, wherein the gas in the test socket is discharged through the vent holes by a step of evacuation, so that the gas pressure in the accommodating hole is Lower than the external environment pressure, so that a plurality of external terminals of the integrated circuit component in the receiving cavity contact the probe pins, because the test sockets adsorb the integrated circuit components on the average of the exhaust holes Therefore, the external terminals can uniformly contact the probe pins of the test socket to prevent the integrated circuit component from being deformed to cause damage to the wafer or substrate of the integrated circuit component, and the present invention is particularly suitable for having The integrated circuit component of the bare back side of the wafer, such as a flip-chip type of package array structure (bgA package). The second object of the present invention is to provide a non-compressive contact. The test socket is provided with a plurality of probe pins and has a receiving hole, a suction port and a plurality of exhaust holes connecting the receiving hole and the suction port, and each of the probe pins has a The contact end in the cavity is accommodated. When the air is decompressed and depleted, the air in the valley is discharged through the vent holes and the suction port, and the adsorption force of the ~+A Λη ^ ^ ^ hook is formed, so the contact ends of the probe pins The system can be contacted with a plurality of external terminals of the integrated electrical component 4 in the receiving cavity, & amp + yang, with a consistent elastic contraction, the test socket can be applied to various types of elastic contact Thin, bare back, flip-chip or difficult direct pressure > 士4. Seven-package package construction (BGA package) reduces test loss and test distortion. The non- 7 1278011 pressure contact method for testing an integrated circuit component according to the present invention comprises: providing a test socket, the test socket having a plurality of receiving portions and connecting the plurality of receiving holes a venting hole, and the test socket is provided with a plurality of probe pins, each of the probe pins having a contact end located in the receiving hole; and an integrated circuit including a chip and a plurality of external terminals Disposing the components to the receiving holes, and aligning the external terminals with the contact ends of the probe pins; and performing a pumping and depressurizing step to pass the gas in the test socket through the exhaust gases Hole discharge, so that
容置穴内之氣壓為低於外部環境壓力，進而吸附該積體電 路元件以使該些外接端接觸至該些探觸針之該些接觸端。 【實施方式】 — ° 本發明在第一具體實施例中例舉一種適用於測試一 積體電路元件之非壓迫式接觸方法，可參閱第3及4圖並 說明如後。首先，力第3圖所示，提供—測試插座2工〇， 用以電性接觸-積體電路元件，例如上述之該積體電路元 件10,該積體電路元件10係至少包含有一基板u、一晶 片12及複數個外接端13。在本實施例中，該晶片u係為 -覆晶晶片，其係以複數個凸塊14覆晶接合至該基板⑴ 且該晶片12係具有-裸露背面12A。此外，該些外接蠕 13係可為録球。該測試插座21〇係具有-容置穴211、一 抽氣口 212以及連通該容置穴211與該抽氣π 2U之複數 個排氣孔213。該容置穴211之開口係朝上，用以容納該 積體電路元件1〇。太士替# /丨丄 ^ 在本實施例中，該抽氣口 212之開口係 月:，並連接至-真空泵（圖未繪出），以利集中抽氣，該 氣口 212亦可變更設計在該測試插座㈣側邊，該些耕 8 1278011 氣孔213係可為矩陣排列。此外，該測試插座210係設置 - 有複數個探觸針214，例如彈簧針（p〇g〇 pin)，每一探觸針 ， 214係具有一位於該容置穴211内之接觸端214A。此外， 在測試之前，該測試插座2丨〇係結合至一插座板（圖未繪 出）。 明再參閱第3圖，藉由一取放吸嘴220取放該積體電 路元件1〇至該容置穴211内，並使得該積體電路元件1〇 _ 之複數個外接端13對準於該些探觸針214之該些接觸端 214A。較佳地，該容置穴211係具有往底面漸縮（taper)之 一内侧壁2 1 5，以導引該積體電路元件1 0至正確位置並可 增進氣密效果。 请參閱第4圖，進行一抽氣減壓之步驟，利用該真空 ，將該測試插座210内之氣體經由該抽氣口 212與該些排 氣 排出以使該谷置穴211之氣壓為低於外部環境 壓力由於忒些排氣孔2 i 3能均勻分散吸附力，使該積體 • 冑路70件1G能往該些探觸針214貼近，並使得該積體電 路凡件10之该些外接端13均能對應接觸至該些探觸針 214之該些接觸端214A，其係可避免該積體電路元件 變形或而造成該積體電路元件1〇之該晶片12或基板損 褒並且4些探觸針2 i 4會有較為一致之彈性收縮。本發 明係以非壓迫式接觸該積體電路元件10取代習知直接對 〇積體電路tl件1 G之局部壓迫，以有效減少測試錯誤發 生或損壞該積體電路元件1〇，特別適用於覆晶型態之球格 陣列封裝構造之測試。 9 1278011 請參閱第5圖，在本發明之第二具體實施例中，首先， 提供另一測試插座310，用以電性接觸一積體電路元件 20，該積體電路元件20係為球袼陣列封裝構造（BaU GHdThe air pressure in the receiving cavity is lower than the external environmental pressure, and the integrated circuit component is adsorbed to contact the external terminals to the contact ends of the probe pins. [Embodiment] - The present invention exemplifies a non-compressive contact method suitable for testing an integrated circuit component in the first embodiment, and can be referred to Figs. 3 and 4 and explained later. First, as shown in FIG. 3, a test socket 2 process is provided for electrically contacting an integrated circuit component, such as the integrated circuit component 10 described above, the integrated circuit component 10 including at least one substrate u. A wafer 12 and a plurality of external terminals 13. In the present embodiment, the wafer u is a flip chip, which is flip-chip bonded to the substrate (1) by a plurality of bumps 14 and has a bare back surface 12A. In addition, the external slings 13 can be recorded. The test socket 21 has a receiving hole 211, a suction port 212, and a plurality of exhaust holes 213 connecting the receiving hole 211 and the pumping gas π 2U. The opening of the receiving hole 211 is directed upward to accommodate the integrated circuit component 1〇. In the present embodiment, the opening of the air suction port 212 is a month: and is connected to a vacuum pump (not shown) for concentrated pumping, and the air port 212 can also be modified in design. On the side of the test socket (4), the cultivating 8 1278011 pores 213 can be arranged in a matrix. In addition, the test socket 210 is provided with a plurality of probe pins 214, such as pogo pins, each of which has a contact end 214A located in the receiving pocket 211. In addition, the test socket 2 is coupled to a socket board (not shown) prior to testing. Referring to FIG. 3 again, the integrated circuit component 1 is taken into the receiving cavity 211 by a pick-and-place nozzle 220, and the plurality of external terminals 13 of the integrated circuit component 1〇_ are aligned. The contact ends 214A of the probe pins 214. Preferably, the receiving hole 211 has an inner side wall 2 15 which tapers toward the bottom surface to guide the integrated circuit component 10 to the correct position and enhance the airtight effect. Referring to FIG. 4, a step of depressurizing and decompressing is performed, and the gas in the test socket 210 is discharged through the air suction port 212 and the exhaust gas to make the gas pressure of the valley hole 211 lower than the vacuum. The external environment pressure can uniformly disperse the adsorption force due to the vent holes 2 i 3 , so that the 70 1 1G of the integrated circuit can be close to the probe pins 214, and the integrated circuit 10 The external terminals 13 can respectively contact the contact terminals 214A of the probe pins 214, which can prevent the integrated circuit components from being deformed or causing damage to the wafer 12 or the substrate of the integrated circuit component 1 and 4 probe pins 2 i 4 will have a more consistent elastic contraction. In the present invention, the integrated circuit component 10 is replaced by a non-compressive type, and the partial compression of the entangled circuit tl component 1 G is directly replaced to effectively reduce the occurrence of test errors or damage the integrated circuit component 1 〇, which is particularly suitable for Testing of flip chip type ball grid array package construction. 9 1278011 Referring to FIG. 5, in a second embodiment of the present invention, first, another test socket 310 is provided for electrically contacting an integrated circuit component 20, which is a ball 袼. Array package construction (BaU GHd
Array package，BGA)，其包含之複數個外接端21係可為 銲球或是其它導電球。該測試插座31〇係具有一容置穴311 以及連通該容置穴311之複數個排氣孔312。在本實施例 中，一抽氣口係可位在該測試插座310底部結合之測試板The Array package (BGA), which includes a plurality of external terminals 21, may be solder balls or other conductive balls. The test socket 31 has a receiving hole 311 and a plurality of exhaust holes 312 communicating with the receiving hole 311. In this embodiment, a suction port is a test board that can be combined at the bottom of the test socket 310.
(圖未繪出）’故該須I]試插座310係可不具有抽氣口，而能 達到相同集合排氣之功效。該測試插座310係設置有複數 個探觸針313,每一探觸針313係具有一位於該容置穴311 該測試插座3 1 0 内之接觸端313A。此外，在本實施例中 係設置有一彈性體314，其係位於該容置穴3ιι之一内侧 壁315,以在抽氣減壓時可供該積體電路元件2〇抵觸，以 達到較佳之氣密效果。之後，取放該積體電路元件2〇至 忒谷置八3 11内並進仃一抽氣減壓之步驟，在該測試插座 31〇内之氣體係經由該些排氣孔312排出，以令該容置穴 311之氣壓為低於外部環境壓力（或是負壓狀態之控制）， 而吸附該積體電路元件2〇，计蚀 ^ Τ ΖΌ並使得該些外接端21能均勻 受力地接觸至該也探觸料1q 兮 一休觸針313之該些接觸端313Α，以供 電性測試。 " 附之申請專利範圍所界定 在不脫離本發明之精神和 ，均屬於本發明之保護範 本發明之保護範圍當視後 者為準，任何熟知此項技藝者， 範圍内所作之任何變化與修改 圍0 10 1278011 【圖式簡單說明】 第1圖：習知測試插座在取放一積體電路元件時之截面示 意圖。 μ 習知測試插座在壓迫式接觸該積體電路元件之外 接蠕時之截面示意圖。 依據本發明之適用於測試一積體電路元件之非壓 迫式接觸方法’在第一具體實施例中一測試插座 卜 .在取放一積體電路元件時之截面示意圖。 第4圖.依據本發明之適用於測試_積體電路元件之非壓 4式接觸方法，在第-具體實施例中該測試插座 在非壓迫式接觸該積體電路元件之外接端時之 截面示意圖。 依據本發明之適用於測試—積體電路元件之非壓 迫式接觸方法，在第二具體實施例中另一測試插 座在取放一積體電路元件時之€面示tl 第2圖 第3圖 第5圖 φ 【主要元件符號說明】 10 積體電路元件 11 基板 13 外接端 20 積體電路元件 110測試插座 120取放吸嘴 2 10測試插座 211容置穴 12甜 14凸 21外接端 111容 130壓 片 塊 置穴 合頭 212抽氣口 12A裸露背面 15 底部填充膠 112探觸針 213排氣孔 1278011 2 14探觸針 220取放吸嘴 3 1 0測試插座 311容置穴 313A接觸端 214A接觸端 3 12排氣孔 314彈性體 21 5内侧壁 313探觸針 3 1 5内側壁(The figure is not shown) 'Therefore, the test socket 310 does not have an air suction port, but can achieve the same effect of collecting exhaust gas. The test socket 310 is provided with a plurality of probe pins 313. Each of the probe pins 313 has a contact end 313A located in the test socket 310 of the receiving hole 311. In addition, in the embodiment, an elastic body 314 is disposed on the inner side wall 315 of the receiving hole 3 ι to provide a good resistance to the integrated circuit component 2 when the air is decompressed and decompressed. Airtight effect. After that, the integrated circuit component 2 is taken into the valley set 八 3 11 and subjected to a pumping and depressurizing step, and the gas system in the test socket 31 is discharged through the vent holes 312. The air pressure of the receiving hole 311 is lower than the external environmental pressure (or the control of the negative pressure state), and the integrated circuit component 2 is sucked, the eclipse is 计 ΖΌ ΖΌ and the external terminals 21 are uniformly stressed. The contact ends 313A of the probe 1q, the touch pin 313 are contacted to test the power supply. The scope of the invention is defined by the scope of the invention and the scope of the invention is intended to be included in the scope of the invention. Circumference 0 10 1278011 [Simple description of the diagram] Fig. 1 is a schematic cross-sectional view of a conventional test socket when picking up an integrated circuit component. μ A schematic cross-sectional view of a conventional test socket when it is pressed into contact with the integrated circuit component. A non-compressive contact method suitable for testing an integrated circuit component in accordance with the present invention' is a cross-sectional view of a test socket in the first embodiment. Figure 4 is a cross-sectional view of a non-pressive type 4 contact method for a test-integrated circuit component in accordance with the present invention. In a specific embodiment, the test socket is non-compressively contacted with the external terminal of the integrated circuit component. schematic diagram. According to the non-compressive contact method of the present invention, which is suitable for the test-integrated circuit component, in the second embodiment, the other test socket is placed on the side of the integrated circuit component. Figure 2 Figure 3 Fig. 5 φ [Description of main component symbols] 10 Integrated circuit component 11 Substrate 13 External terminal 20 Integrated circuit component 110 Test socket 120 Pickup nozzle 2 10 Test socket 211 accommodating hole 12 Sweet 14 convex 21 External end 111 130 pressure piece block hole sealing head 212 suction port 12A bare back 15 bottom filling glue 112 probe pin 213 vent hole 1278011 2 14 probe pin 220 pick and place nozzle 3 1 0 test socket 311 receiving hole 313A contact end 214A Contact end 3 12 vent 314 elastomer 21 2 inner side wall 313 probe pin 1 1 5 inner side wall
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