JP3958252B2 - Semiconductor integrated circuit device test carrier - Google Patents

Semiconductor integrated circuit device test carrier Download PDF

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Publication number
JP3958252B2
JP3958252B2 JP2003155203A JP2003155203A JP3958252B2 JP 3958252 B2 JP3958252 B2 JP 3958252B2 JP 2003155203 A JP2003155203 A JP 2003155203A JP 2003155203 A JP2003155203 A JP 2003155203A JP 3958252 B2 JP3958252 B2 JP 3958252B2
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JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
chip
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2003155203A
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Japanese (ja)
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JP2003344484A (en
Inventor
茂幸 丸山
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富士通株式会社
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Publication date
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Priority to JP2003155203A priority Critical patent/JP3958252B2/en
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Description

[0001]
[Industrial application fields]
The present invention relates to a test carrier for a semiconductor integrated circuit device, and more particularly to improvement of a test carrier for housing a semiconductor integrated circuit device chip and using it for an acceleration test or the like.
[0002]
In recent years, LSIs have been highly integrated, and at the same time, electronic devices have been downsizing. In order to meet these demands, not only high integration of LSI chips but also high-density mounting technology of chips is great. This tendency is particularly noticeable in bare chip mounting, MCM (multi-chip module), and the like.
[0003]
Against this background, the level of content required for testing in the LSI chip state is increasing.
[0004]
[Prior art]
Hereinafter, a test of a semiconductor integrated circuit device according to a conventional example will be described with reference to FIGS. FIG. 15B is a cross-sectional view taken along the line EE of FIG.
[0005]
When supplying a product as a product to the user in a chip state, an acceleration test (hereinafter referred to as a B · I test) and FT (Final Test) for removing initial defects must be performed in the chip state.
[0006]
In addition, a package composed of a plurality of chips, such as MCM, will naturally fail if the package contains at least one defective chip. Therefore, according to the contents of conventional chip tests, The final yield tends to decrease significantly.
[0007]
For this reason, with respect to a package in which a plurality of chips as described above are mounted, it is highly necessary to perform a B / I test in a state where the chip is a bare chip. This is a process that will be more and more necessary in the future, but the B / I test in the bare chip state is currently seeking and establishing technology.
[0008]
Usually, a test in a wafer state uses a PP (Production Prove) test using a wafer prober, that is, a method of contacting a fine electrode on a wafer using a prober. This method is shown in FIG. It has been proposed as a first method to divert to a chip.
[0009]
That is, the prober 1 connected to an external test apparatus is aligned with the fine contact electrode 2 of the chip 2 to make a contact, and put in a furnace (hereinafter referred to as a B / I furnace) for performing a B / I test. The B / I test is performed by operating the circuit while heating at a high temperature.
[0010]
As a second method, there has been proposed a method of contacting a chip electrode using a conventionally used IC socket.
[0011]
Further, as a third method, as shown in FIG. 15, a fine contact electrode 3B is formed at a position corresponding to the electrode of the IC chip on a film-like sheet made of a highly electrically insulating material such as polyimide. A method has been proposed in which a contact sheet 3 provided with a wiring pattern 3A for making contact with an external test apparatus is pressure-bonded to the chip 2 to make contact between the chip 2 and the test apparatus.
[0012]
[Problems to be solved by the invention]
However, the conventional first to third methods have the following problems.
[0013]
That is, in the PP test of the first method, as shown in FIG. 14, in order to contact the fine electrodes on the chip using the prober, the probers 1 arranged with high precision corresponding to the electrodes of the chip are used. It can be achieved only by using a high-precision alignment device that recognizes an image of the contact electrode 2A of the chip 2 and corrects a positional deviation from the prober 1, but the prober is generally very expensive, It is not practical to prepare the prober 1 and the alignment device for each chip and perform the B / I test, and even if possible, the cost is enormous, so there is no merit of performing the B / I test with the chip. .
[0014]
Further, according to the second method, the size of the tip of the contact pin of the conventional IC socket and the position variation thereof are large and the alignment error between the IC socket and the chip is large compared to the size of the electrode of the chip. If the size of the chip electrode is not larger than the conventional one, the alignment cannot be performed, and there is a problem that the test according to the state of the fine chip electrode cannot be performed.
[0015]
Further, in the third method, it is difficult to align the electrode 3B of the contact sheet 3 and the contact electrode 2A of the chip 2, and even if the alignment is performed by the image recognition method or the like, vibration or transportation during the B · I test is performed. There is a problem that the positions of the two easily shift due to an impact inside. Further, since the electrode 3B of the contact sheet is fine and the contact sheet itself is made of a film such as polyimide, it is flexible. Therefore, if the entire contact sheet is not pressed uniformly against the chip, the contact electrode 2A and the contact sheet 3 There was also a problem that a stable contact with the electrode 3B could not be obtained.
[0016]
Further, as a common problem with the above first to third methods, when a B / I test is performed in an atmosphere equivalent to that of a normal packaged IC, there may be a problem such that dust adheres to the chip and causes burn-in. . In addition, when heated for a long time in a high temperature state, there has been a problem that oxidation of the electrode portion of the chip proceeds and deteriorates, and subsequent mountability / connectivity deteriorates.
[0017]
As described above, the test in the bare chip state is actually very difficult with the existing technology. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a test carrier for a semiconductor integrated circuit device that enables a test such as a bare chip acceleration test, which has been difficult in the past.
[0018]
[Means for Solving the Problems]
As illustrated in FIG. 12, the above-described problem includes a base 21 on which a semiconductor integrated circuit device is mounted, and a film that covers the base 21 and makes contact between the semiconductor integrated circuit device 23 and an external device. A lid 22 and a semiconductor which is a sealed space formed between the lid 22 and the base body 21 and accommodates the entire semiconductor integrated circuit device 23 in an atmosphere reduced in pressure compared to the outside air. and a device accommodating chamber, the substrate 21 is made of a film of the same material as the lid body 22, and the semiconductor integrated the lid 22 is pressed by the semiconductor integrated circuit device 23 by the atmospheric pressure of the outside world solved by circuit device 23 is characterized Rukoto sandwiched between the base 21 and the lid 22.
[0019]
[Operation]
According to the present invention, since the pressure in the semiconductor device storage chamber is reduced compared to the atmospheric pressure in the outside, the lid 22 is uniformly pressed by the atmospheric pressure in the outside. Even if the lid 22 is used, even if the contact electrode of the lid 22 and the contact electrode of the semiconductor integrated circuit device 23 are uniformly pressed, and there is vibration during the B / I test or impact during transportation, It is possible to prevent misalignment easily.
[0020]
Further, by changing the degree of decompression, the contact pressure can be manipulated, and the contact electrode of the semiconductor integrated circuit device 23 and the contact electrode of the lid 22 can be brought into a contact state at an optimum pressure. Therefore, since it is possible to make contact with external equipment corresponding to the fine electrode pattern of the semiconductor integrated circuit device, it is possible to test the semiconductor integrated circuit device, which has been difficult in the past, such as an acceleration test using a bare chip. become.
[0021]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1B is a cross-sectional view taken along the line AA in FIG. 1A, and FIG. 4B is a cross-sectional view taken along the line BB in FIG.
[0022]
First, each member of the test carrier of the semiconductor integrated circuit device according to the first embodiment of the present invention will be described. A test carrier of the semiconductor integrated circuit device according to the present embodiment includes a contact sheet 11 and a case 12 as shown in FIG.
[0023]
The contact sheet 11 is connected to a conductive contact pad 11C formed on a film 11A made of polyimide having a film thickness of about 0.05 to 0.1 mm corresponding to the electrode pattern of the chip 13 to be tested, and the contact pad 11C. Then, a conductive wiring pattern 11B for making contact with an external test apparatus is formed.
[0024]
The case 12 is made of an epoxy resin or the like, and is provided with a pocket 12A, and a chip is accommodated in the pocket 12A.
[0025]
A method for accommodating the chip to be tested in the above member will be described below with reference to FIGS.
[0026]
First, as shown in FIG. 2, the chip 13 to be tested, the contact sheet 11, and the case 12 are carried into the vacuum furnace 14, and are placed in the pocket 12 </ b> A of the case 12 so that the contact electrode of the chip 13 is on the upper side. The chip 13 is accommodated and placed on the XY stage 15.
[0027]
Next, while confirming the positional deviation between the contact electrode 13A of the chip and the contact pad 11C of the contact sheet 11, the XY stage 15 is moved to align the both.
[0028]
Next, after an adhesive is applied to a partial region of the contact sheet 11 in the vacuum furnace 14, the contact sheet 11 and the case 12 that have been aligned are bonded as shown in FIG.
[0029]
The above steps are performed in a low-pressure atmosphere below atmospheric pressure. At this time, the atmosphere in the vacuum furnace 14 is made to contain no oxygen, for example, by using an inert gas atmosphere such as nitrogen.
[0030]
Thereafter, the contact sheet 11, the case 12, and the chip 13 integrated (hereinafter referred to as a test carrier) are unloaded from the vacuum furnace 14 and put into a normal pressure atmosphere. As a result, the contact sheet 11 is uniformly pressed and pressed against the chip 13 and the case 12 by the pressure difference between the pressure inside the pocket 12 in which the chip 13 is stored and the atmospheric pressure outside. This ensures that the contact pad 11C and the contact electrode 13A of the chip are pressure-bonded.
[0031]
Through the above steps, a test carrier as shown in FIG. 4 is completed. In this test carrier, the contact pad 11C and the contact electrode are securely crimped and fixed with an appropriate contact force, and therefore, during the B · I test as in the conventional third method using the contact sheet. It is possible to suppress as much as possible the problem that the positions of the two easily shift due to vibration or impact during transportation.
[0032]
In addition, since the first conventional method is not adopted, it is possible to prevent enormous costs by preparing a high-accuracy probe head and alignment function for each chip and conducting a B / I test. Furthermore, since the second conventional method is not adopted, the chip electrode does not have to be larger than the conventional one. Therefore, the test can be performed with a normal size chip, and the chip can be tested according to the actual condition of the chip. Testing is possible.
[0033]
After that, as shown in FIG. 5, the test carrier is stored in a conventional IC socket 17 and then placed in a B / I furnace, and is kept at a high temperature of about 125 ° C. for a certain time (for example, 48 hours). , 96 hours), and conduct the B · I test by energizing the chip during that time.
[0034]
The test carrier according to the present embodiment is provided with a notch 12B as shown in FIGS. 4 and 6 in the case 12, so that the test carrier is accommodated in the case 12 after the B / I test is completed. When it is desired to take out the chip 13, as shown in FIG. 6, the chip 13 can be easily taken out by peeling the contact sheet 12 from the notch 12 </ b> B.
[0035]
Further, in the first method using a conventional prober as shown in FIG. 7, in order to test an area bump chip or the like in which the electrode portion of the chip is spherical, the contact with the spherical chip electrode is particularly removed. In addition, the test was very difficult to perform because it was easily displaced by vibration during the test. However, according to the test carrier according to this example, as shown in FIG. 13A can be easily contacted, and since it is not easily displaced by being crimped, it is more effective particularly in the test of such a chip.
[0036]
In addition, since the back surface of the chip 13 and the bottom surface of the pocket 12A of the case 12 are in close contact with each other, the heat dissipation of the chip under test can be improved by forming the case 12 with a material having a high heat dissipation property such as aluminum. This facilitates test reliability.
[0037]
Further, during assembly, the inside of the vacuum furnace 14 is in a vacuum or a low-pressure inert gas atmosphere, and in particular, an atmosphere in which oxygen is not mixed. Therefore, even if the B · I test is heated at a high temperature for a long time, the contact electrode 13A of the chip 13 can be prevented from being oxidized and deteriorated.
Second Embodiment Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. Note that a description of the same items as those in the first embodiment is omitted. 8B is a cross-sectional view taken along line CC in FIG. 8A, and FIG. 10B is a cross-sectional view taken along line DD in FIG.
[0038]
First, each member of the test carrier of the semiconductor integrated circuit device according to the present embodiment will be described with reference to FIG. The test carrier of the semiconductor integrated circuit device according to the present embodiment includes a contact sheet 11 and a case 12 as shown in FIG.
[0039]
Similar to the first embodiment, the contact sheet 11 is formed on the film 11A made of polyimide having a film thickness of about 0.05 to 0.1 mm corresponding to the pattern of the contact electrode 13A of the chip 13 to be tested. A conductive contact pad 11C and a conductive wiring pattern 11B connected to the contact pad 11C for making contact with an external test apparatus are formed.
[0040]
The case 12 is made of an epoxy resin or the like, and is provided with a pocket 12A and a coupler 12C. This coupler 12B is different from the first embodiment.
[0041]
The pocket 12A accommodates the chip 13 in the same manner as in the first embodiment, and the coupler 12C communicates with the pocket 12A. The air in the pocket 12A is exhausted, and the pocket is stored when the chip is accommodated. This is an exhaust valve for reducing the pressure of 12A from the outside.
[0042]
A method for accommodating the chip to be tested in the above member will be described below with reference to FIGS.
[0043]
First, as shown in FIG. 9A, the test chip 13 is accommodated in the pocket 12A of the case 12 so that the contact electrode 13A is on the upper side, and the contact between the contact electrode 13A of the chip 13 and the contact sheet 11 is obtained. After aligning the pad 11B in a normal pressure atmosphere, the contact sheet 11 and the case 12 are bonded with an adhesive (not shown).
[0044]
After that, as shown in FIG. 9B, a suction device (not shown) is connected to the coupler 12B, the coupler 12B is opened, and the air in the pocket 12A is sucked by the suction device, so that the air pressure in the pocket 12A is reduced. , Depressurize until almost vacuum. Thereafter, the coupler 12B is closed, and the inside of the pocket 12A is evacuated.
[0045]
Thus, the test carrier as shown in FIG. 10 is completed. According to the test carrier according to the present example, not only can the same effect as in the first example be obtained, but also in the normal pressure atmosphere without being assembled in a reduced pressure or vacuum atmosphere at the time of assembly. After bonding the contact sheet 11 to the case 12, the air pressure in the pocket 12A can be easily reduced by sucking the air in the pocket 12A from the coupler 12C, so that a large-scale facility such as a vacuum furnace is required. Therefore, it can be formed easily and inexpensively.
Third Embodiment Hereinafter, a third embodiment of the present invention will be described with reference to FIG. Note that a description of the same items as those in the first and second embodiments is omitted.
[0046]
As shown in FIG. 11, the test carrier of the semiconductor integrated circuit device according to the present embodiment includes a contact sheet 11 and a case 12, and has the same configuration as that of the first embodiment. Is different from the first embodiment only in that a highly adhesive O-ring 12E such as rubber is embedded therein and is in close contact with the contact sheet 11.
[0047]
For this reason, since the O-ring 12E having high adhesion is formed between the contact sheet 11 and the case 12, the adhesion between the two is higher than that of the test carrier of the first embodiment, and vibration during the test is performed. In addition, there is an effect that the positional deviation that is likely to occur in the vibration during the conveyance is much stronger.
Fourth Embodiment Hereinafter, a fourth embodiment of the present invention will be described with reference to FIGS. Note that a description of the same items as those in the first to third embodiments is omitted.
[0048]
The most different point from the first to third embodiments of the test carrier of the semiconductor integrated circuit device according to this embodiment is that the test carrier of the first to third embodiments is used as a base on which a test chip is mounted. Instead of using the case 12 made of a rigid body such as an epoxy resin and provided with pockets 12A, a sheet made of polyimide, for example, similar to the material of the contact sheet 11 is used.
[0049]
An example is shown in FIG. As shown in FIG. 12, the test carrier according to this example includes a substrate film 21 serving as a base and a contact sheet 22. The contact sheet 22 is basically the same as in the first to third embodiments. As the substrate film, a film made of polyimide having the same thickness as the contact sheet 22 and a thickness of about 0.05 to 0.1 mm is used.
[0050]
When this is assembled, the chip 23 to be tested is placed and fixed on the substrate film 21, and each member is carried into a vacuum furnace (not shown) in the same manner as in the first embodiment. The electrode 23A and the contact pad 22A of the contact sheet 22 are aligned, and the substrate film 21 and the contact sheet 22 are bonded with an adhesive or the like.
[0051]
Thereafter, the test carrier in which the contact electrode 23A and the contact pad 22A are pressure-bonded is completed as shown in FIG.
[0052]
Similarly to the test carrier shown in FIG. 12, as shown in FIG. 13, a substrate film 30 made of a material such as polyimide having a rigidity higher than that of the contact sheet 22 may be used as a substrate.
[0053]
As described above, according to the test carrier according to the present embodiment shown in FIGS. 12 and 13, it is not necessary to use the case provided with the pocket for storing the chip as in the first to third embodiments. Therefore, there is an advantage that the test carrier can be easily formed and the cost can be reduced.
[0054]
【The invention's effect】
As described above, according to the present invention, the base on which the semiconductor integrated circuit device is mounted, the lid that covers the base and contacts the external device, and the semiconductor integrated circuit device between the lid and the base Since the semiconductor device storage chamber is depressurized compared to the atmospheric pressure, it can be easily positioned even if there is vibration during the B / I test or impact during transportation. It becomes possible not to shift.
[0055]
In addition, since an appropriate contact pressure can be applied to the chip, it is possible to reliably make contact with an external device corresponding to the fine electrode pattern of the semiconductor integrated circuit device.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating members of a test carrier of a semiconductor integrated circuit device according to a first embodiment of the present invention.
FIG. 2 is a view (No. 1) showing a process for assembling a test carrier of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 3 is a view (No. 2) showing an assembly process of the test carrier of the semiconductor integrated circuit device according to the first example of the invention.
FIG. 4 is a diagram for explaining the structure of a test carrier of the semiconductor integrated circuit device according to the first example of the present invention.
FIG. 5 is a diagram for explaining a test method using a test carrier for the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 6 is a view (No. 1) for explaining the function and effect of the test carrier of the semiconductor integrated circuit device according to the first example of the present invention;
FIG. 7 is a diagram (No. 2) for explaining the function and effect of the test carrier of the semiconductor integrated circuit device according to the first example of the present invention.
FIG. 8 is a diagram illustrating members of a test carrier of a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 9 is a diagram showing an assembling process of a test carrier of a semiconductor integrated circuit device according to a second example of the present invention.
FIG. 10 is a diagram illustrating the structure of a test carrier for a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 11 is a diagram illustrating the structure of a test carrier for a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIG. 12 is a diagram (part 1) illustrating the structure of a test carrier of a semiconductor integrated circuit device according to a fourth example of the present invention.
FIG. 13 is a diagram (No. 2) illustrating the structure of a test carrier in a semiconductor integrated circuit device according to a fourth example of the present invention;
FIG. 14 is a diagram (No. 1) for explaining a test of a semiconductor integrated circuit device according to a conventional example;
FIG. 15 is a diagram (No. 2) for explaining a test of a semiconductor integrated circuit device according to a conventional example;
[Explanation of symbols]
11, 22 Contact sheet (lid)
11A Film 11B Wiring pattern 11C Contact pad 11D Adhesive part 12 Case (base)
12A pocket (semiconductor device storage room)
12B Notch 12C Coupler (Exhaust valve)
12D Groove 12E O-ring (Highly adhesive member)
13,23 chip (semiconductor integrated circuit device)
13A, 23A Contact electrode 14 Vacuum furnace 15 XY stage 16 Image recognition device 21, 30 Substrate film (base)

Claims (3)

  1. A substrate on which the semiconductor integrated circuit device is mounted;
    A lid made of a film that covers the base and makes contact between the semiconductor integrated circuit device and an external device;
    A sealed space formed between the lid and the base body, and a semiconductor device storage chamber for storing the entire semiconductor integrated circuit device in an atmosphere reduced in pressure compared to the outside air;
    The base body is made of a film of the same material as the lid body, and the lid body is pressed against the semiconductor integrated circuit device by an atmospheric pressure of the outside world so that the semiconductor integrated circuit device is interposed between the lid body and the base body. test carrier for the semiconductor integrated circuit device sandwiched characterized Rukoto to.
  2.   2. The wiring film according to claim 1, wherein a wiring pattern corresponding to an electrode of the semiconductor integrated circuit device is formed on the film, and the lid body has an adhesive portion for bonding to the base. A carrier for testing the semiconductor integrated circuit device described.
  3.   3. The semiconductor integrated circuit device test carrier according to claim 1, wherein the semiconductor integrated circuit device is an area bump chip.
JP2003155203A 2003-05-30 2003-05-30 Semiconductor integrated circuit device test carrier Expired - Lifetime JP3958252B2 (en)

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Cited By (1)

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CN103116120A (en) * 2011-11-16 2013-05-22 株式会社爱德万测试 Test carrier

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JP2009042028A (en) * 2007-08-08 2009-02-26 Syswave Corp Socket for testing semiconductor device
JP2011086880A (en) * 2009-10-19 2011-04-28 Advantest Corp Electronic component mounting apparatus and method of mounting electronic component
JP5368290B2 (en) 2009-12-18 2013-12-18 株式会社アドバンテスト Carrier assembly device
JP5616119B2 (en) * 2010-05-10 2014-10-29 株式会社アドバンテスト Test carrier
JP2011237260A (en) * 2010-05-10 2011-11-24 Advantest Corp Carrier disassembler and carrier disassembly method
US8999758B2 (en) * 2011-08-12 2015-04-07 Infineon Technologies Ag Fixing semiconductor die in dry and pressure supported assembly processes
JP5684095B2 (en) 2011-11-16 2015-03-11 株式会社アドバンテスト Test carrier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103116120A (en) * 2011-11-16 2013-05-22 株式会社爱德万测试 Test carrier

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