JP2003344484A - Test carrier for semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test package of a semiconductor device integrated circuit and, more specifically, improve a test package for a BI test in a bare chip state. <P>SOLUTION: A test carrier for a semiconductor integrated circuit device has a base mountable with a semiconductor integrated circuit device, a cover of a film for covering the base to establish contact between the semiconductor integrated circuit device and external equipment, and a semiconductor device storage chamber formed between the cover and the base to store the semiconductor integrated circuit device in an atmosphere depressurized below the outside air. The base is made of a film of the same material as that of the cover, and the cover is pressed against the semiconductor integrated circuit device under the outside atmospheric pressure. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test carrier for a semiconductor integrated circuit device, and more particularly to improvement of a test carrier for accommodating a semiconductor integrated circuit device chip for use in an acceleration test or the like.

In recent years, the degree of integration of LSI has been remarkably increased, and at the same time, the tendency of downsizing of electronic devices has been remarkable. In order to meet these requirements, not only high integration of LSI chips but also high-density chip mounting technology is important. This tendency is particularly remarkable in bare chip mounting and MCM (multi-chip module).

From such a background, the degree of enrichment of the contents required for the LSI chip state test is increasing.

[0004]

2. Description of the Related Art A test of a semiconductor integrated circuit device according to a conventional example will be described below with reference to FIGS. Note that FIG. 15B is a sectional view taken along the line EE of FIG.

When the chip state is supplied to the user as a product, an acceleration test (hereinafter referred to as BI test) and an FT (Final Test) for removing initial defects must be performed in the chip state.

Further, in a package including a plurality of chips such as MCM, if even one defective chip is included in the package, the entire product will naturally be defective. In that case, the final yield of the product is likely to be significantly reduced.

For this reason, it is highly necessary to carry out the B / I test in the bare chip state of the package mounting a plurality of chips as described above. This is a process that seems to be required more and more in the future, but in the present state, the BI test in the bare chip state is currently seeking and establishing a technology.

Normally, as a test in a wafer state, a PP (Production Prove) test using a wafer prober, that is, a method of contacting fine electrodes on a wafer by using a prober is widely used. As a first method, it has been proposed to convert it into a chip as shown in FIG.

That is, the prober 1 connected to an external tester is aligned with the fine contact electrodes 2 of the chip 2 to make contact, and a B / I test is performed in the furnace (hereinafter referred to as the B / I furnace). Then, the circuit is operated while being heated at a high temperature to perform the BI test.

As a second method, there has been proposed a method of contacting an electrode of a chip by using a conventionally used socket for IC.

Further, as a third method, as shown in FIG. 15, a film-like sheet made of a material having high electrical insulation such as polyimide is used for fine contact at a position corresponding to the electrode of the IC chip. Electrode 3B is provided and wiring pattern 3 for making contact with external test equipment
A method has been proposed in which a contact sheet 3 provided with A is pressure-bonded to the chip 2 to make contact between the chip 2 and the test apparatus.

[0012]

However, the above-mentioned first to third conventional methods have the following problems.

That is, in the PP test of the first method, in order to contact the fine electrodes on the chip by using the prober, as shown in FIG. 14, the electrodes were arranged with high precision corresponding to the electrodes of the chip. This can be achieved only by using a high-precision alignment device that uses the prober 1 to image-recognize the contact electrode 2A of the chip 2 and correct the positional deviation from the prober 1, but the prober is generally very expensive, It is not realistic to prepare such a prober 1 and alignment device for each individual chip and to carry out the B / I test, and even if it is possible, the cost will be enormous. There is no merit.

Further, according to the second method, the size of the tip of the contact pin of the conventional IC socket and the position variation thereof are large as compared with the size of the electrode of the chip, and the alignment error between the IC socket and the chip is large. However, if the size of the chip electrode is larger than that of the conventional one, the alignment cannot be performed, and there is a problem that the test according to the state of the fine chip electrode cannot be performed.

Further, according to the third method, it is difficult to align the electrode 3B of the contact sheet 3 and the contact electrode 2A of the chip 2, and even if the alignment is performed by the image recognition method or the like, the B / I test is being performed. There is a problem that the positions of the two are easily displaced due to vibration or shock during transportation. Further, since the electrodes 3B of this contact sheet are fine and the contact sheet itself is made of a film such as polyimide, it is flexible, so that the contact electrode 2A and the contact sheet 3 must be pressed uniformly against the chip. There was also a problem that it was not possible to obtain stable contact with the electrode 3B.

Further, as a common problem with the above-mentioned first to third methods, when a BI test is conducted in an atmosphere equivalent to that of an ordinary packaged IC, dust adheres to the chip to cause burn-in and the like. Can be considered. Further, when the chip is heated at a high temperature for a long time, the electrode portion of the chip is oxidized and deteriorated, and there is a problem that subsequent mountability and connectivity deteriorate.

As described above, in the existing technology, the test in the bare chip state was actually very difficult. The present invention has been made in view of such circumstances,
An object of the present invention is to provide a carrier for testing a semiconductor integrated circuit device, which makes it possible to perform a test such as an acceleration test of a bare chip which has been difficult in the past.

[0018]

[Means for Solving the Problems]
As illustrated in FIG. 2, a base 21 on which a semiconductor integrated circuit device is mounted, a lid 22 made of a film that covers the base 21 to make contact between the semiconductor integrated circuit device 23 and an external device, and the lid. The semiconductor device storage chamber is formed between the body 22 and the base 21, and stores the semiconductor integrated circuit device 23 in an atmosphere that is decompressed compared to the outside air. The base 21 includes the lid 22. It is made of a film made of the same material as the above, and the lid 22 is pressed against the semiconductor integrated circuit device 23 by the atmospheric pressure of the outside world.

[0019]

[Operation] According to the present invention, since the atmospheric pressure of the semiconductor device storage chamber is reduced as compared with the atmospheric pressure of the outside, the lid 2
Since 2 is uniformly pressed by the atmospheric pressure of the outside world, even if the film-shaped lid 22 having low rigidity is used, the contact electrode of the lid 22 and the contact electrode of the semiconductor integrated circuit device 23 are even. It is possible to prevent the position from being easily displaced even when there is a vibration during the B / I test or a shock during transportation due to being pressed by.

Further, the contact pressure can be controlled by changing the degree of pressure reduction, and the semiconductor integrated circuit device 2
The contact electrode of No. 3 and the contact electrode of the lid body 22 can be brought into contact with each other at an optimum pressure. Therefore, it is possible to make contact with an external device corresponding to the fine electrode pattern of the semiconductor integrated circuit device.
It is possible to test the semiconductor integrated circuit device, which has been difficult in the past, such as an acceleration test using a bare chip.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 7. 1B is a sectional view taken along the line AA of FIG. 1A, and FIG. 4B is a sectional view taken along the line B- of FIG.
It is a B line sectional view.

First, each member of the test carrier of the semiconductor integrated circuit device according to the first embodiment of the present invention will be described. The test carrier of the semiconductor integrated circuit device according to the present embodiment comprises a contact sheet 11 and a case 12, as shown in FIG.

The contact sheet 11 has a film thickness of 0.05 to 0.1 m.
On a film 11A made of polyimide of about m
A conductive contact pad 11C formed corresponding to the electrode pattern of the chip 13 to be tested, and a conductive wiring pattern 11B connected to the contact pad 11C for making contact with an external test apparatus are formed. It becomes.

The case 12 is made of epoxy resin or the like and is provided with a pocket 12A. The pocket 12A accommodates a chip.

A method for accommodating the chip to be tested in the above member will be described below with reference to FIGS.

First, as shown in FIG. 2, the chip 13, the contact sheet 11, and the case 12 to be tested are carried into the vacuum furnace 14, and the pocket of the case 12 is placed so that the contact electrode of the chip 13 is on the upper side. The chip 13 is housed in the 12A and placed on the XY stage 15.

Next, while confirming the positional deviation between the contact electrode 13A of the chip and the contact pad 11C of the contact sheet 11, the XY stage 15 is moved to align the two.

Next, after applying an adhesive to a partial area of the contact sheet 11 in the vacuum furnace 14, FIG.
The aligned contact sheet 11 and the case 12 are bonded as shown in FIG.

The above steps are carried out in a low pressure atmosphere below atmospheric pressure. At this time, the atmosphere in the vacuum furnace 14 is made to contain no oxygen, for example, by making the atmosphere of an inert gas such as nitrogen.

Thereafter, these contact sheets 11,
An integrated case 12 and chip 13 (hereinafter referred to as a test carrier) is unloaded from the vacuum furnace 14 and placed in a normal pressure atmosphere. As a result, the chip 13
Due to the atmospheric pressure difference between the internal pressure of the pocket 12 in which is stored and the atmospheric pressure of the outside world, the contact sheet 11 becomes the chip 13
And it is uniformly pressed and pressure-bonded to the case 12. As a result, the contact pad 11C and the contact electrode 13A of the chip are securely pressure-bonded.

Through the above steps, a test carrier as shown in FIG. 4 is completed. In this test carrier, since the contact pad 11C and the contact electrode are securely pressed and fixed with an appropriate contact force, the test carrier is subjected to the BI test during the BI test as in the third conventional method using the contact sheet. It is possible to suppress as much as possible the problem that the positions of the two are easily displaced due to vibration or shock during transportation.

Further, since the conventional first method is not adopted, by preparing a highly accurate probe head and a positioning function for each individual chip and conducting a BI test,
Since enormous cost can be suppressed and the second method of the related art is not adopted, the size of the chip electrode does not need to be larger than that of the related art, so a test is performed using a chip of a normal size. Therefore, it is possible to perform a test according to the actual condition of the chip.

Then, as shown in FIG. 5, the test carrier was stored in a conventionally used test IC socket 17 and then placed in a B / I furnace and kept at a high temperature of about 125 ° C. for a predetermined time ( For 48 hours or 96 hours), the chip is energized and the BI test is conducted during that time.

Since the test carrier according to this embodiment is provided with the notch 12B as shown in FIGS. 4 and 6 in its case 12, after the B / I test is completed,
When the chip 13 stored in the case 12 is desired to be taken out, as shown in FIG.
The chip 13 can be easily taken out by peeling off the contact sheet 12 from the above, which is also effective in that sense.

Further, in the first method using a conventional prober as shown in FIG. 7, in order to test an area bump chip or the like in which the electrode portion of the chip is spherical, contact with a spherical chip electrode is particularly required. It was very difficult to carry out the test because it was difficult to move and it was easily displaced due to vibration during the test. However, according to the test carrier of the present example, as shown in FIG. Contact electrode 1
3A can be easily contacted and can be easily displaced by being crimped, so that it is more effective especially in the test of such a chip.

In addition, the back surface of the chip 13 and the case 12
Since the bottom surface of the pocket 12A is in close contact, the case 12 is made of a material having a high heat dissipation property, such as aluminum, so that the heat dissipation property of the chip under test is promoted and the reliability of the test is improved. .

Further, at the time of assembly, the inside of the vacuum furnace 14 is in a vacuum or a low pressure inert gas atmosphere,
In particular, since the atmosphere is set so that oxygen is not mixed in, since there is no oxygen in the pocket 12A that accommodates the chip 13, even if it is heated at a high temperature for a long time in the BI test,
There is also an effect that it is possible to prevent the contact electrode 13A of the chip 13 from being oxidized and deteriorated. Second Embodiment Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 8 to 10. It should be noted that description of items that are the same as those of the first embodiment will be omitted. 8B is a sectional view taken along line CC of FIG. 8A, and FIG. 10B is a sectional view taken along line DD of FIG. 8A.

First, each member of the test carrier of the semiconductor integrated circuit device according to this embodiment will be described with reference to FIG. The test carrier of the semiconductor integrated circuit device according to the present embodiment is provided with a contact sheet 11 as shown in FIG.
And case 12.

Similar to the first embodiment, the contact sheet 11 corresponds to the pattern of the contact electrode 13A of the chip 13 to be tested on the film 11A made of polyimide having a film thickness of about 0.05 to 0.1 mm. Been formed,
A conductive contact pad 11C and a conductive wiring pattern 11B that is connected to the contact pad 11C and is used to make contact with an external test apparatus are formed.

The case 12 is made of epoxy resin or the like, and is provided with a pocket 12A and a coupler 12C.
The difference from the first embodiment is that this coupler 12B is provided.

The pocket 12A is for accommodating the chip 13 in the same manner as in the first embodiment.
C communicates with this pocket 12A, and pocket 12
The air in A is exhausted and pocket 12A is used when storing chips.
This is an exhaust valve for reducing the atmospheric pressure of the external pressure.

A method for accommodating the chips to be tested in the above members will be described below with reference to FIGS. 9 to 10.

First, as shown in FIG. 9A, the case 1
The test chip 13 is housed in the pocket 12A of No. 2 so that the contact electrode 13A is on the upper side.
After the contact electrode 13A of No. 3 and the contact pad 11B of the contact sheet 11 are aligned in a normal pressure atmosphere, the contact sheet 11 and the case 12 are bonded to each other with an adhesive (not shown).

Then, as shown in FIG. 9 (b), a coupler (not shown) is connected to the coupler 12B, the coupler 12B is opened, and the air in the pocket 12A is sucked by the suction device. The atmospheric pressure is reduced until it becomes almost vacuum. Then, the coupler 12B is closed and the inside of the pocket 12A is evacuated.

As described above, the test carrier as shown in FIG. 10 is completed. According to the test carrier of the present embodiment, not only the same effects as those of the first embodiment can be obtained, but also at the time of assembling, in a normal pressure atmosphere without assembling under reduced pressure or a vacuum atmosphere. After adhering the contact sheet 11 to the case 12, the air pressure in the pocket 12A can be easily reduced by sucking the air in the pocket 12A from the coupler 12C. Therefore, large-scale equipment such as a vacuum furnace is required. Therefore, it can be easily formed at low cost. Third Embodiment A third embodiment of the present invention will be described below with reference to FIG. Note that description of items that overlap with those of the first and second embodiments will be omitted.

As shown in FIG. 11, the test carrier of the semiconductor integrated circuit device according to the present embodiment comprises a contact sheet 11 and a case 12, which has the same structure as that of the first embodiment, but the case 12 A groove 12D is formed in the groove 12A, and an O-ring 12E having high adhesiveness such as rubber is embedded in the groove 12D and is in contact with the contact sheet 11 only.
This is different from the embodiment.

Therefore, since the O-ring 12E having high adhesiveness is formed between the contact sheet 11 and the case 12, the adhesiveness between the contact sheet 11 and the case 12 is higher than that of the test carrier of the first embodiment. The effect of being even stronger against the positional deviation that is likely to occur due to the internal vibration and the vibration during conveyance is produced. Fourth Embodiment Hereinafter, a fourth embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to. Note that description of items that overlap with those of the first to third embodiments will be omitted.

The most different point of the test carrier of the semiconductor integrated circuit device according to the present embodiment from the first to third embodiments is that the base for mounting the test chip is the base of the first to third embodiments. It is that a case similar to the material of the contact sheet 11, for example, a sheet such as polyimide is used instead of the case 12 that is made of a rigid body such as an epoxy resin and has the pocket 12A like the test carrier. .

FIG. 12 shows an example thereof. As shown in FIG. 12, the test carrier according to this example includes a substrate film 21 serving as a base and a contact sheet 22.
The contact sheet 22 is basically the same as that used in the first to third embodiments. As the substrate film, a film made of polyimide having the same thickness as the contact sheet 22 and having a film thickness of about 0.05 to 0.1 mm is used.

When assembling this, the substrate film 2
The chip 23 to be tested is placed and fixed on 1 and each member is carried into a vacuum furnace (not shown) in the same manner as in the first embodiment.
The contact electrode 23A of the chip 23 and the contact pad 22A of the contact sheet 22 are aligned,
Substrate film 21 and contact sheet 22 with an adhesive or the like
Glue and.

After that, by removing from the vacuum furnace and returning to the normal pressure condition, as shown in FIG.
A test carrier in which A and the contact pad 22A are pressure bonded is completed.

Similarly to the test carrier shown in FIG. 12, a substrate film 30 made of a material such as polyimide having a rigidity higher than that of the contact sheet 22 may be used as the base, as shown in FIG.

As described above, according to the test carrier of the present embodiment shown in FIGS. 12 and 13, unlike the first to third embodiments, the case provided with the pocket for storing the chip is not used. Therefore, there is an advantage that the test carrier can be easily formed and the cost is low.

[0054]

As described above, according to the present invention, a base on which a semiconductor integrated circuit device is mounted, a cover for covering the base to make contact with an external device, and a space between the cover and the base. Has a semiconductor device storage chamber for storing the semiconductor integrated circuit device, and since this semiconductor device storage chamber is decompressed compared to the atmospheric pressure of the outside world, there are vibrations during the BI test and shocks during transportation. Also, it is possible to easily prevent the displacement.

Further, since an appropriate contact pressure can be applied to the chip, it is possible to surely make contact with an external device corresponding to the fine electrode pattern of the semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a diagram illustrating each member of a test carrier of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a view showing a process of assembling the test carrier of the semiconductor integrated circuit device according to the first embodiment of the present invention (No. 1).
Is.

FIG. 3 is a view showing a process of assembling the test carrier of the semiconductor integrated circuit device according to the first embodiment of the present invention (No. 2).
Is.

FIG. 4 is a diagram illustrating a structure of a test carrier of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a test method using the test carrier of the semiconductor integrated circuit device according to the first example of the present invention.

FIG. 6 is a view for explaining the function and effect of the test carrier of the semiconductor integrated circuit device according to the first example of the present invention (No. 1).
Is.

FIG. 7 is a view for explaining the function and effect of the test carrier of the semiconductor integrated circuit device according to the first embodiment of the present invention (No. 2).
Is.

FIG. 8 is a diagram illustrating each member of the test carrier of the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 9 is a diagram showing a process of assembling the test carrier of the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 10 is a diagram illustrating the structure of a test carrier of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 11 is a diagram illustrating the structure of a test carrier of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 12 is a view (No. 1) for explaining the structure of the test carrier of the semiconductor integrated circuit device according to the fourth example of the present invention.

FIG. 13 is a view (No. 2) for explaining the structure of the test carrier of the semiconductor integrated circuit device according to the fourth example of the present invention.

FIG. 14 is a diagram (No. 1) explaining a test of a semiconductor integrated circuit device according to a conventional example.

FIG. 15 is a diagram (No. 2) explaining the test of the semiconductor integrated circuit device according to the conventional example.

[Explanation of symbols] 11,22 Contact sheet (lid) 11A film 11B wiring pattern 11C contact pad 11D adhesive section 12 cases (base) 12A pocket (semiconductor device storage room) 12B cutout 12C coupler (exhaust valve) 12D groove 12E O-ring (member with high adhesion) 13,23 chips (semiconductor integrated circuit devices) 13A, 23A contact electrode 14 vacuum furnace 15 XY stage 16 Image recognition device 21,30 Substrate film (base)

Claims (3)

[Claims] 1. A base on which a semiconductor integrated circuit device is mounted, a lid made of a film covering the base to make contact between the semiconductor integrated circuit device and an external device, the lid and the base. And a semiconductor device accommodating chamber that accommodates the semiconductor integrated circuit device in an atmosphere that is decompressed compared to the outside air, and the base is made of a film made of the same material as the lid, and A test carrier for a semiconductor integrated circuit device, wherein the lid is pressed against the semiconductor integrated circuit device by the atmospheric pressure of the outside world. 2. A wiring pattern corresponding to an electrode of the semiconductor integrated circuit device is formed on a film of the lid body,
The carrier for testing a semiconductor integrated circuit device according to claim 1, which is a wiring film having an adhesive portion for adhering to the base. 3. The carrier for testing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is an area bump chip.