TWI272684B - Package structure for a semiconductor sensing chip and method for packaging the same - Google Patents

Package structure for a semiconductor sensing chip and method for packaging the same Download PDF

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Publication number
TWI272684B
TWI272684B TW094113805A TW94113805A TWI272684B TW I272684 B TWI272684 B TW I272684B TW 094113805 A TW094113805 A TW 094113805A TW 94113805 A TW94113805 A TW 94113805A TW I272684 B TWI272684 B TW I272684B
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Taiwan
Prior art keywords
sensing
wafer
substrate
semiconductor
inclined surface
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TW094113805A
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Chinese (zh)
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TW200638494A (en
Inventor
Bruce C S Chou
Chen-Chih Fan
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Lightuning Tech Inc
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Priority to TW094113805A priority Critical patent/TWI272684B/en
Publication of TW200638494A publication Critical patent/TW200638494A/en
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Publication of TWI272684B publication Critical patent/TWI272684B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Image Input (AREA)

Abstract

A package structure includes a substrate, a frame body and a sensing chip. The frame body is disposed on the substrate and has a first step portion and a second step portion, which defines a window and is higher than the first step portion to form a step therebetween. The sensing chip has one sensing surface for sensing a to-be-sensed object. The sensing chip is disposed on the substrate and electrically connected to the substrate. The sensing chip is accommodated in the window, and the sensing surface is substantially flush with the second step portion. When a finger sweeps across the sensing chip, the step may scrape off the contamination on the finger and thus prevent the contamination from being left on the sensing surface and keep the sensing chip clean.

Description

1272684 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種半導體感測晶片之封裝結構及其 封裝方法’尤其關於一種能刮除受測物體上所附著之殘 污之半導體感測晶片之封裝結構及其封裝方法。本發明 係關聯到讓渡給本案受讓人之下述專利申請案:中華民 國發明專利申請案號00931〇〇27〇,申請曰為2004年1 月6曰,發明名稱為「半導體感測晶片之封裝結構及其 封裝方法」。 【先前技術】 曰曰片式4曰紋感測器之封裝不同於一般傳統ic(積體電 路)之封裝方法。一般IC封裝是利用射出或上膠將晶片 王邛包裝起來以保護1C晶片不受外力破壞,而晶片式指 、、文感測1C封裝除保護1C晶片不受外力破壞以外還需要 使指紋感測區域裸露,才可進行指紋之讀取,其封裝之 困難度遠高於一般1C封裝。 目前晶片式指紋感測IC之封裝有幾種方式,一是將 指紋感測1C固定於電路板打線後,將打線區及晶片四週 使用點膠方式保護’此方法必須控制點膠於指紋感測區 域内不可有溢膠發生,利用直接點膠方式封裝的產 觀不易控制且封膠部分易產生氣泡及不平整等問題, 主要之優點是成本較低不需花#昂貴特殊機台且= 封裝。另-是利用特殊機台將指紋感: 或用〜、保濩避免於射出成型時指紋感測區遭受污染或 5 溢膠,其餘部分則是和一 模具必須克服機台於又1c封裝方式一樣,此機台及 具接觸晶片時對晶片中的畚塵掉落於晶片表面及模 外觀-致性高無氣二:;;衰;, 但是必須花費昂貴 4且封裝尺寸較小, m f σ及杈具成本。 因此本發明提出—種 裝方法,即可封,出“而化費甲貴之特殊機台之封 決上述技術之問題。 ^且小尺寸之封裝’解 【發明内容】 本發明之主要目的’係在提供 二裳結構及其封装方法,其能達到製程簡單=片良 平回且成本低之優點。 本:明之另一目的,係將框體設計成具有高低位段 八’俾能在手指於滑過感測晶片時刮除手指上的水潰與 :/必物以減少其殘留於感測區域,來保持感測晶片之潔 本發明之又另一目的,係於封裝膠體上加之以一上 蓋’可&供封膠與導線連接的良好保護,以及維護整體 封裝結構外形的美觀。 為達到上述之目的,本發明提供一種半導體感測晶 片之封裝結構,其包含一基板、一框體及一感測晶片。 框體設置於基板上,並具有一第一階梯部分及一第二階 梯部分,第二階梯部分定義出一開窗,第二階梯部分高 於第一階梯部分而形成一段差。感測晶片具有一感測面 1272684 來感測一待測物體。感測晶片設置於基板上並電連接至 基板。感測晶片容置於開窗中,且感測面實質上與第二 階梯部分齊平。 、 人本發明亦提供一種半導體感測晶片之封裝方法,包 •、下^驟·知:供一基板,基板具有複數個基板焊塾; 在基板上形成一框體,框體具有一第一階梯部分及一第 白梯口P刀,第一階梯部分定義出一開窗,第二階梯部 、 刀回於第一階梯部分而形成一段差;將一感測晶片設置 在土板上並谷置於開窗中,感測晶片具有-感測面來感 測一待測物體以及複數個晶片焊墊,感測面實質上與第 白梯口P刀A平,以複數條引線將感測晶片之此等晶片 、電連接至基板之此等基板焊墊;提供一封裝膠體用 以匕覆此等引線、此等晶片焊塾及此等基板焊塾;及將 一上蓋罩覆於封裝膠體及感測晶片上。 接、=之說明為藉由具體實施例配合所附的圖式詳加 祝明’當更容易瞭解本發明之目的、技術内容、特點及 • 其所達成之功效。 ’ 【實施方式】 , 圖至1D顯示本發明之半導體感測晶片之封裝結 構之不圖。圖2顯示本發明之半導體感測晶片之封裝 結構之局部立體示意圖。如圖1A至1D及圖2所示,本 貝施例之半導體感測晶片之封裳結構丄包含—基板1〇、 框體20、一感测晶片30、一封装膠體4〇及一上蓋5〇。 基板10可以是一印刷電路基板,並具有複數個基板 7 1272684 焊塾11。框體20設置於基板上,框體20設置於基 板10可以是分離的部件或一體成形的部件。框體2〇是 一種高低位框體,並具有一第一階梯部分21及一第二階 梯部分22。第二階梯部分22定義出一開窗23。第二階 梯部分22高於第一階梯部分21而形成一段差25。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package structure for a semiconductor sensing wafer and a method of packaging the same, and more particularly to a semiconductor sensing wafer capable of scraping residuals attached to an object to be tested. The package structure and its packaging method. The present invention is related to the following patent application granted to the assignee of the present application: Republic of China Invention Patent Application No. 00931〇〇27〇, application filed January 6, 2004, entitled "Semiconductor Sensing Wafer" Package structure and its packaging method". [Prior Art] The package of the chip type 4 感 sensor is different from the package method of the conventional ic (integrated circuit). Generally, the IC package uses the injection or sizing to package the wafer enamel to protect the 1C wafer from external force damage, and the wafer-type finger and the sensation 1C package need to protect the 1C wafer from external force damage. When the area is bare, the fingerprint can be read, and the difficulty of packaging is much higher than that of the general 1C package. At present, there are several ways to package the chip-type fingerprint sensing IC. One is to fix the fingerprint sensing 1C on the circuit board and then use the dispensing method to protect the wire-bonding area and the wafer. This method must control the dispensing of the fingerprint in the fingerprint sensing. There is no possibility of overflowing in the area. The production view by direct dispensing method is difficult to control and the sealing part is easy to produce bubbles and unevenness. The main advantage is that the cost is lower and it is not necessary to spend expensive special machine and = package . Another - is to use a special machine to sense the fingerprint: or use ~, to prevent the fingerprint sensing area from being contaminated or spilled when the injection molding, the rest is the same as a mold must overcome the machine in the 1c package When the machine and the contact wafer are in contact with the wafer, the dust on the wafer is dropped on the surface of the wafer and the appearance of the mold is high and the air is not high; but; it must be expensive 4 and the package size is small, mf σ and Cookware costs. Therefore, the present invention proposes a method of seeding, which can be sealed, and the problem of the above-mentioned technology is blocked by a special machine that is expensive and expensive. ^And a small-sized package' solution [invention] The main purpose of the present invention is In the provision of the two-shoulder structure and its packaging method, it can achieve the advantages of simple process = good film back and low cost. Ben: Another purpose of the frame is to design the frame to have a high and low position eight '俾 can be slipped on the finger Another purpose of the invention is to scrape off the water on the finger when the wafer is sensed, and to reduce the residue in the sensing area to keep the sensing wafer clean. The present invention provides a package structure for a semiconductor sensing wafer, which comprises a substrate, a frame, and a good protection for the connection of the sealing material and the wire. a sensing chip is disposed on the substrate and has a first stepped portion and a second stepped portion, the second stepped portion defines a window opening, and the second stepped portion is higher than the first stepped portion Forming a gap. The sensing wafer has a sensing surface 1272684 to sense an object to be tested. The sensing wafer is disposed on the substrate and electrically connected to the substrate. The sensing wafer is received in the window, and the sensing surface is substantially The invention also provides a method for packaging a semiconductor sensing chip, which comprises: providing a substrate, the substrate having a plurality of substrate soldering pads; forming a frame on the substrate The body has a first stepped portion and a first stepped P-knife, the first stepped portion defines an open window, and the second stepped portion and the knife are returned to the first stepped portion to form a difference; The wafer is disposed on the earth plate and the valley is placed in the window. The sensing wafer has a sensing surface to sense an object to be tested and a plurality of wafer pads, and the sensing surface is substantially flat with the white ladder P knife A. Providing the substrate of the sensing wafer to the substrate pads of the substrate by a plurality of leads; providing an encapsulant for covering the leads, the wafer pads and the substrate pads; Covering an upper cover on the encapsulant and the sensing wafer The description of the present invention is made by the specific embodiments in conjunction with the accompanying drawings. It is easier to understand the purpose, technical contents, features and functions of the present invention. 1D shows a package structure of the semiconductor sensing chip of the present invention. Fig. 2 is a partial perspective view showing the package structure of the semiconductor sensing chip of the present invention. As shown in Figs. 1A to 1D and Fig. 2, the embodiment of the present invention The semiconductor sensing chip sealing structure comprises a substrate 1 , a frame 20 , a sensing wafer 30 , an encapsulant 4 , and an upper cover 5 . The substrate 10 can be a printed circuit substrate and has a plurality of Substrate 7 1272684 Weld 11. The frame 20 is disposed on the substrate, and the frame 20 is disposed on the substrate 10 as a separate component or an integrally formed component. The frame 2 is a high and low frame and has a first step. Part 21 and a second step portion 22. The second stepped portion 22 defines an opening window 23. The second step portion 22 is higher than the first step portion 21 to form a gap 25.

感測晶片30具有一感測面31來感測一待測物體60 之育訊’譬如是手指之指紋圖像。具有複數個晶片焊墊 32之感測晶片30係設置於基板1〇上並電連接至基板 1〇 °通常’可以將感測晶片30容置於開窗23中並黏著 於基板10上,然後藉由複數條引線12將晶片焊墊32打 線連接至基板焊墊丨丨。如此,可使感測面3丨實質上與 第二階梯部分22齊平。當手指60滑過感測晶片30時, 可2藉由高低位框體之設計刮除手指6〇上的殘污(譬如 火/貝灰塵與分泌物)61以減少其殘留於感測面31,以 保持感測晶片之潔淨。 曰封裝膠體40用以包覆引線12、晶片焊墊32及基板 焊墊11,藉以保護引線12及焊墊32與11。上蓋50罩 覆於封A膠體40及感測晶片3〇上,並可與框體2q相結 合:藉以提供封裝膠體40與引線12的良好保護,以及 維護整體封裝結構外形的美觀。 _ /、η π对朔间激凋晶月 30 =右斜面51,框體20具有傾斜朝向感測晶片之一 ^面24。左斜面24與右斜面51可以單獨存在或一起 ’用以導引待測物冑6〇於感剛面Η上完成感測。 “列而言’當手指滑動通過感測31時,左斜面24與 8 1272684 右斜面5 1可以限制住手指之左右晃動情形,藉以使指紋 的感測結果更加良好。 以下將參見圖3至圖5說明本發明之封裝方法之步 驟。如圖3A至3C所示,首先提供一基板1〇,常用者為 • 印刷電路基板,在基板10之近外側處已設有複數基板焊 墊11。然後,利用移轉成型(transfer molding)技術在基 板10上形成一框體20,框體20具有一第一階梯部分21 • 及一第二階梯部分22,第二階梯部分22定義出一開窗 • 23,第二階梯部分22高於第一階梯部分21而形成一段 差。或者,於其他實施例中,框體20亦可以是與基板1〇 分離之構件。因此,可以直接提供框體20設置於基板1 〇 上。 接著,如圖4A至4C所示,將一感測晶片30以譬 如黏著的方式設置在基板10上並容置於開窗23中,感 測晶片30具有一感測面3 1來感測一待測物體6〇(圖iD), 並具有複數個晶片焊墊32與基板焊墊u相對應。感測 # 面31只質上與第二階梯部分22齊平。然後,以複數條 , 引線12將感測晶片30之晶片焊墊32電連接至基板1〇 之基板焊塾11。 接著’如圖5A至5C所示,提供一封裝膠體40用 、匕覆引線12、晶片焊墊32及基板焊墊11,達到保護 作用。 另a最後,如圖1A至1D所示,將一上蓋5〇罩覆於封 I膠體40及感測晶片3〇上。如此即封裝完成感測晶片 之封裝結構1。此感測晶片之封裝結構1可組裝於各種 9 1272684 電子裝置上 手機等。 例如隧身碟、個人數位處理器(PDA )及 圖6係為對應於圖K之另一種封裝結構之示意圖。 圖之封裝、、、。構1係類似於圖1C,不同之處在於框體⑼ 不’、有左邊之凸起構造’而是以上蓋的左斜面52來 配口右斜面51以達成導引手指滑動之功能。或者,左邊 之左斜面的形成亦可利用外在模具之設計來達成。 本么月係、纟"合了美觀的小尺寸封裝及低成本之優 ”沾利用傳統移轉成型(transfer molding)技術於基板上先 形成一框體,此框體設計將感測晶片及基板焊墊區包圍 保護起來,再將感測晶片自合於基板之框冑中,再利用 打線(wire bond)方式將感測晶片之輸出/輸入焊墊電連接 至基板相對之焊墊,上膠保護此打線區域,最後將一上 盍黏合於此區完成晶片式指紋感測器之封裝。移轉成型 技術於基板形成一框體可解決感測晶片之溢膠發生,上 蓋之設計可避免封膠部分易產生氣泡及不平整等美觀問 題,此封裝設計不需投資昂貴之特殊機台成本,也無粉 塵掉落於晶片表面及模具接觸晶片時對晶片造成之破壞 等問題。 藉由本發明之上述構造及方法,本案發明人實際製 作出的封裝結構具有14.9mm*6mm*l _68mm的尺寸,感 測晶片之露出表面具有l〇.3lmm*i_95mm的尺寸,上蓋 高於感測面之高度為〇.75mm。值得注意的是, 工盖兩於 感測面之高度最好是小於或等於2mm,以免因高度差異 大而造成感測面之邊緣無法接觸手指造成有效感测面矜 10 Ϊ272684 變小的狀況。因此可達成一種小尺寸之封裝結構。 在較佳實施例之詳細說明令所提出之具體實施 用以方便制本發明之技彳㈣容,而非 限制於上述實施例,扃尤如山丄☆ x d狹義地 專利範圍之情況,所傲 夂U下申請 汀做之種種變化實施,皆屬 月 之範圍。 0屬於本發明The sensing wafer 30 has a sensing surface 31 for sensing a fingerprint of a subject 60 to be measured, such as a fingerprint image of a finger. The sensing wafer 30 having a plurality of wafer pads 32 is disposed on the substrate 1 and electrically connected to the substrate 1[Generally, the sensing wafer 30 can be received in the opening window 23 and adhered to the substrate 10, and then The wafer pads 32 are wire bonded to the substrate pads by a plurality of leads 12. Thus, the sensing surface 3 is substantially flush with the second step portion 22. When the finger 60 slides over the sensing wafer 30, the residual dirt (such as fire/shell dust and secretions) 61 on the finger 6 is scraped off by the design of the high and low frame to reduce its residual on the sensing surface 31. To keep the sensing wafer clean. The encapsulant 40 is used to cover the leads 12, the wafer pads 32, and the substrate pads 11 to protect the leads 12 and pads 32 and 11. The upper cover 50 covers the seal A colloid 40 and the sensing wafer 3, and can be combined with the frame 2q: thereby providing good protection of the encapsulant 40 and the lead 12, and maintaining the appearance of the overall package structure. _ /, η π vs. inter-day spurting crystal 30 = right bevel 51, the frame 20 has an inclination toward one of the sensing wafers. The left bevel 24 and the right bevel 51 may be present alone or together to guide the object to be tested 6 to the sensing surface. "For the column", when the finger slides through the sensing 31, the left bevel 24 and the 8 1272684 right bevel 5 1 can limit the left and right shaking of the finger, thereby making the sensing result of the fingerprint better. See Figure 3 to Figure 3 below. 5 illustrates the steps of the packaging method of the present invention. As shown in Figs. 3A to 3C, a substrate 1 is first provided, which is commonly used as a printed circuit board, and a plurality of substrate pads 11 are provided near the outer side of the substrate 10. Then A frame 20 is formed on the substrate 10 by a transfer molding technique. The frame 20 has a first stepped portion 21 and a second stepped portion 22, and the second stepped portion 22 defines a window. 23, the second stepped portion 22 is higher than the first stepped portion 21 to form a difference. Alternatively, in other embodiments, the frame 20 may also be a member separate from the substrate 1〇. Therefore, the frame 20 can be directly provided. The sensing wafer 30 is disposed on the substrate 10 and placed in the opening window 23, as shown in FIGS. 4A to 4C. The sensing wafer 30 has a sensing. Face 3 1 to sense an object to be measured 6〇 (Fig. iD), and having a plurality of wafer pads 32 corresponding to the substrate pads u. The sensing #31 is qualitatively flush with the second step portion 22. Then, in a plurality of lines, the leads 12 will feel The wafer pad 32 of the wafer 30 is electrically connected to the substrate pad 11 of the substrate 1. Next, as shown in FIGS. 5A to 5C, an encapsulant 40, a cap 12, a pad 32 and a substrate pad are provided. 11. A protective effect is achieved. Finally, as shown in FIGS. 1A to 1D, an upper cover 5 is covered on the cover I 40 and the sensing wafer 3. Thus, the package structure 1 for sensing the wafer is packaged. The package structure 1 of the sensing chip can be assembled on various mobile phones, etc., such as a tunnel disk, a personal digital processor (PDA), and FIG. 6 is a schematic diagram of another package structure corresponding to FIG. The package 1 is similar to FIG. 1C except that the frame body (9) does not have a convex structure on the left side but a left slope 52 of the upper cover to match the right slope 51 to achieve the guiding finger. The function of sliding. Or, the formation of the left bevel on the left side can also utilize the design of the external mold. To achieve this. This month, 纟 " beautiful small package and low cost of the best" using the traditional transfer molding (transfer molding) technology on the substrate to form a frame, the frame design will The sensing wafer and the substrate pad region are surrounded and protected, and then the sensing wafer is self-contained in the frame of the substrate, and the output/input pad of the sensing chip is electrically connected to the substrate by wire bonding. The pad is glued to protect the wire area, and finally a top tape is bonded to the area to complete the package of the wafer type fingerprint sensor. The transfer molding technology forms a frame on the substrate to solve the occurrence of overflow of the sensing wafer. The design of the upper cover can avoid the aesthetic problems such as bubbles and unevenness in the sealing part. The package design does not need to invest in expensive special machines. Cost, and no problems such as dust falling on the surface of the wafer and damage to the wafer when the mold contacts the wafer. With the above configuration and method of the present invention, the package structure actually produced by the inventor of the present invention has a size of 14.9 mm*6 mm*1 _68 mm, and the exposed surface of the sensing wafer has a size of l〇.3lmm*i_95mm, and the upper cover is higher than the sensing. The height of the face is 〇.75mm. It is worth noting that the height of the sensing surface of the cover is preferably less than or equal to 2 mm, so as to avoid the situation that the edge of the sensing surface cannot contact the finger due to the large difference of height, and the effective sensing surface 矜 10 Ϊ 272684 becomes small. Therefore, a small-sized package structure can be achieved. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The specific implementations set forth in the preferred embodiments are intended to facilitate the fabrication of the present invention, and are not limited to the above-described embodiments, and are particularly advantageous in the context of patents. The implementation of various changes in the application for the application of the U is within the scope of the month. 0 belongs to the invention

11 !272684 【圖式簡單說明】 圖1A至id顯示本發明之半導體感測晶 構之示意圖,其中圖1B係為圖ia之 、于裝… ^ ^ m t a A剖面,圖 1 p11:272684 [Simplified Schematic] FIGS. 1A to 1D are schematic views showing the semiconductor sensing crystal of the present invention, wherein FIG. 1B is a diagram of FIG. 1A, and is mounted on a ^ ^ m t a A profile, FIG. 1 p

係為圖1A之前視圖,圖1D係為圖以之 ㈡1C 照比例繪製。 C „彳面但未 部立體示意圖 圖3Α至3C顯示本發明之半導 Φ夕千立闽々 ^ 等體以/則日日片之封裝方 法之不忍圖之一,其中圖3β係為圄a Α 則為圖3Α之前視圖。為圖3Α之Α-Α剖面,圖 圖:Α至4C顯示本發明之半導體感測晶片之封裝方 思圖之二’其中圖4B係盖圓ο 士 A A…— 圖 圖2顯*本發明之半導體感測晶片 體示意圖。 』衣π構之局 、-^土^翊不奉發明之半導體感測晶片之封屢 法之不思圖之二,盆中Bl 4v么认 八平圖4B係為圖4A之a-A叫面, 4C係為圖4A之前視圖。 土」U顒不本發明之半導體感測晶片之封裝 法之不意圖之三,其中圖5B係為圖5AKA剖面, 5C係為圖5A之前視圖。 圖6係為對應於圖1 c夕_ . 、口丄匕之另一種封裝結構之示意圖 圖至5C顯示本發明之半導體感測晶片之封裝方 意圖之三’其中圖5B係盔国“ > A a 一 圖 【主要元件符號說明】 1〜封裝結構 10 板 11〜基板焊墊 12〜^ |線 20〜框體 21〜第一階梯部分 12 1272684 22〜第二階梯部分 23〜開窗 24〜左斜面 25〜段差 3 0〜感測晶片 3 1〜感測面 32〜晶片焊墊 40七裝膠體 50〜上蓋 51〜右斜面 52〜左斜面 6 0〜待測物體(手指) 61〜殘污It is a front view of Fig. 1A, and Fig. 1D is a drawing of the figure (2) 1C. C 彳 但 但 未 未 未 立体 Α Α 3 3 显示 显示 显示 显示 显示 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本Α is the front view of Fig. 3。. It is the Α-Α section of Fig. 3, and the figure: Α to 4C shows the package of the semiconductor sensing wafer of the present invention. The figure 2B is the cover circle ο AA... Figure 2 shows a schematic diagram of the semiconductor sensing wafer body of the present invention. The device of the π-construction, the ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Figure 4B is a front view of Fig. 4A, and 4C is a front view of Fig. 4A. The earth is not intended to be the third embodiment of the semiconductor sensing wafer packaging method of the present invention, wherein Fig. 5B is a diagram 5AKA profile, 5C is a front view of Figure 5A. 6 is a schematic view corresponding to another package structure of FIG. 1 to 5C, and 5C shows the intent of the package of the semiconductor sensing wafer of the present invention, wherein FIG. 5B is a helmet country> A a picture [main element symbol description] 1 ~ package structure 10 board 11 ~ substrate pad 12 ~ ^ | line 20 ~ frame 21 ~ first step part 12 1272684 22 ~ second step part 23 ~ window 24 ~ Left inclined surface 25~step difference 3 0~ sensing wafer 3 1~ sensing surface 32~ wafer bonding pad 40 seven-packing body 50~ upper cover 51~right inclined surface 52~left inclined surface 6 0~ object to be tested (finger) 61~

1313

Claims (1)

1272684 十Λ申請專利範圍: 1 · 一種半導體感測晶片之封裝結構,包含: 一基板; 一框體,設置於該基板上,並具有一第一階梯部分 及一第二階梯部分,該第二階梯部分定義出一開窗,該 第二階梯部分高於該第一階梯部分而形成一段差;及 一感測晶片’具有一感測面來感測一待測物體,該 感測晶片設置於該基板上並電連接至該基板,該感測晶 鲁片容置於該開窗中,且該感測面實質上與該第二階梯部 分齊平。 2 ·如申請專利範圍第1項所述之半導體感測晶片之 封裝結構’其中該基板具有複數個基板焊塾,該感測晶 片更具有複數個晶片焊墊,且該等基板焊墊係藉由複數 條引線而電連接至該晶片焊墊。 3·如申請專利範圍第2項所述之半導體感測晶片之 封裝結構,更包含一封裝膠體,用以包覆該等引線、該 φ 等晶片焊墊及該等基板焊塾。 _ 4·如申請專利範圍第3項所述之半導體感測晶片之 封裝結構’更包含一上蓋,罩覆於該封裝膠體及該感測 • 晶片上。 5·如申請專利範圍第4項所述之半導體感測晶片之 封裝結構,其中戎上蓋具有傾斜朝向該感測晶片之一右 斜面,用以導引該待測物體於該感測面上完成感測。 6_如申請專利範圍第4項所述之半導體感測晶片之 封衷、、Ό構,其中該上蓋具有傾斜朝向該感測晶片之一右 14 1272684 斜面,該框體具有傾斜朝向該感測晶片之一左斜面,該 左斜面與該右斜面用以導引該待測物體於該感測面上完 成感測。 7·如申請專利範圍第4項所述之半導體感測晶片之 封裝結構,其中該上蓋具有傾斜朝向該感測晶片之一右 斜面及一左斜面,該左斜面與該右斜面用以導引該待測 物體於該感測面上完成感測。 8 ·如申請專利範圍第4項所述之半導體感測晶片之 φ 封裝結構,其中該上蓋高於該感測面之一高度實質上小 於或等於2公釐。 9 ·如申睛專利範圍第1項所述之半導體感測晶片之 封裝結構,其中該框體具有傾斜朝向該感測晶片之一左 斜面,該左斜面用以導引該待測物體於該感測面上完成 感測。 1 〇 · —種半導體感測晶片之封裝方法,包含以下步 驟: , 提供一基板,該基板具有複數個基板焊墊; ® 在該基板上形成一框體,該框體具有一第一階梯部 - 分及一第二階梯部分,該第二階梯部分定義出一開窗, 該第二階梯部分高於該第一階梯部分而形成一段差; 將一感測晶片設置在該基板上並容置於該開窗中, 該感測晶片具有一感測面來感測一待測物體以及複數個 晶片焊墊,該感測面實質上與該第二階梯部分齊平; 以複數條引線將該感測晶片之該等晶片焊墊電連接 至該基板之該等基板焊墊; 15 1272684 该專晶片焊塾 將-上蓋罩覆於該封|膠體及該感測晶片上。 ^ _如申明專利範圍第10項所述之半導體感測晶片 方法中°亥上蓋具有傾斜朝向該感測晶片之一 斜面用以‘引该待測物體於該感測面上完成感測。 、/·如申明專利範圍第10項所述之半導體感測晶片 之封波方法’其中該上蓋具有傾斜朝向該感測晶片之一1272684 The application scope of the Shiyan application: 1 · A package structure of a semiconductor sensing wafer, comprising: a substrate; a frame disposed on the substrate and having a first step portion and a second step portion, the second The step portion defines an open window, the second step portion is higher than the first step portion to form a difference; and a sensing wafer 'haves a sensing surface to sense an object to be tested, and the sensing chip is disposed on the The substrate is electrically connected to the substrate, the sensing crystal piece is received in the window, and the sensing surface is substantially flush with the second step portion. The package structure of the semiconductor sensing chip of claim 1, wherein the substrate has a plurality of substrate pads, the sensing wafer further has a plurality of wafer pads, and the substrate pads are borrowed Electrically connected to the wafer pad by a plurality of leads. 3. The package structure of the semiconductor sensing chip of claim 2, further comprising an encapsulant for covering the leads, the die pads of the φ, and the substrate pads. The package structure of the semiconductor sensing chip as described in claim 3 further includes an upper cover overlying the encapsulant and the sensing wafer. The package structure of the semiconductor sensing chip of claim 4, wherein the upper cover has a right inclined surface facing the sensing wafer to guide the object to be tested to be completed on the sensing surface. Sensing. [6] The sealing of the semiconductor sensing wafer of claim 4, wherein the upper cover has a slope facing the right 14 1272684 of the sensing wafer, the frame having an oblique orientation toward the sensing One of the left bevels of the wafer, the left bevel and the right bevel are used to guide the object to be tested to perform sensing on the sensing surface. The package structure of the semiconductor sensing chip of claim 4, wherein the upper cover has a right inclined surface and a left inclined surface inclined toward the sensing wafer, the left inclined surface and the right inclined surface are used for guiding The object to be tested completes sensing on the sensing surface. 8. The φ package structure of the semiconductor sensing wafer of claim 4, wherein the upper cover is substantially less than or equal to 2 mm above a height of the sensing surface. The package structure of the semiconductor sensing chip of claim 1, wherein the frame has a left inclined surface inclined toward the sensing wafer, the left inclined surface for guiding the object to be tested The sensing is completed on the sensing surface. 1 . A method for packaging a semiconductor sensing wafer, comprising the steps of: providing a substrate having a plurality of substrate pads; and forming a frame on the substrate, the frame having a first step a minute step portion defining a window, the second step portion being higher than the first step portion to form a difference; placing a sensing wafer on the substrate and accommodating In the fenestration, the sensing wafer has a sensing surface for sensing an object to be tested and a plurality of wafer pads, the sensing surface being substantially flush with the second step portion; The substrate pads of the sensing wafer are electrically connected to the substrate pads of the substrate; 15 1272684 The wafer bonding pad covers the sealing body and the sensing wafer. In the semiconductor sensing wafer method of claim 10, the upper cover has a slope toward one of the sensing wafers to cause the object to be tested to perform sensing on the sensing surface. The method of sealing a semiconductor sensing wafer according to claim 10, wherein the upper cover has an oblique orientation toward the sensing wafer 右斜面,該框體具有傾斜朝向該感測晶片之一左斜面, 二左斜面與该右斜面用以導引該待測物體於該感測面上 元成感測。 13·如申請專利範圍第1〇項所述之半導體感測晶片 之封裝方法,其中該框體具有傾斜朝向該感測晶片之一 左斜面,該左斜面用以導引該待測物體於該感測面上完 成感測。 14· 一種半導體感測晶片之封裝方法,包含以下步 驟 _ 提供一基板,該基板具有複數個基板焊墊; k供一框體設置於該基板上,該框體具有一第一階 梯邛分及一第二階梯部分,該第二階梯部分定義出一開 囪’該第二階梯部分高於該第一階梯部分而形成一段差; 將一感測晶片設置在該基板上並容置於該開窗中, 邊感測晶片具有一感測面來感測一待測物體以及複數個 晶片焊墊,該感測面實質上與該第二階梯部分齊平; 以複數條引線將該感測晶片之該等晶片焊墊電連接 16 1272684 至該基板之該等基板焊墊; 該等晶片焊墊 提供一封裝膠體用以包覆該等引線 及该等基板焊塾;及 將一上蓋罩覆於該封裝膠體及該感測晶片上。 15·如申請專利範圍第14項所述之半導體感測晶 之封裝方法,其中該上蓋具有傾斜朝向該感測晶片^一 右斜面,用以導引該待測物體於該感測面上完成感測。The right inclined surface, the frame has a left inclined surface inclined to the sensing wafer, and the second left inclined surface and the right inclined surface are used to guide the object to be tested to sense on the sensing surface. The method of packaging a semiconductor sensing chip according to the first aspect of the invention, wherein the frame has a left inclined surface inclined toward the sensing wafer, the left inclined surface for guiding the object to be tested The sensing is completed on the sensing surface. A method for packaging a semiconductor sensing chip, comprising the steps of: providing a substrate having a plurality of substrate pads; k providing a frame on the substrate, the frame having a first step and a second stepped portion defining a chimney 'the second stepped portion is higher than the first stepped portion to form a difference; placing a sensing wafer on the substrate and housing the opening In the window, the edge sensing chip has a sensing surface to sense an object to be tested and a plurality of wafer pads, the sensing surface is substantially flush with the second step portion; and the sensing chip is formed by a plurality of wires The wafer pads electrically connect 16 1272684 to the substrate pads of the substrate; the wafer pads provide an encapsulant for covering the leads and the substrate pads; and overlaying an upper cover The encapsulant and the sensing wafer. The method of encapsulating a semiconductor sensing crystal according to claim 14, wherein the upper cover has a right inclined surface facing the sensing wafer to guide the object to be tested to be completed on the sensing surface. Sensing. 16·如申請專利範圍第14項所述之半導體感測晶片 之封裝方法,其中該上蓋具有傾斜朝向該感測晶片之一 右斜面’該框體具有傾斜朝向該感測晶片之一左斜面, 該左斜面與該右斜面用以導引該待測物體於該感測面上 完成感測。 17 ·如申請專利範圍第14項所述之半導體感測晶片 之封裝方法,其中該框體具有傾斜朝向該感測晶片之一 左斜面,該左斜面用以導引該待測物體於該感測面上完 成感測。The method of packaging a semiconductor sensing wafer according to claim 14, wherein the upper cover has a right inclined surface facing the sensing wafer, and the frame has a tilting direction toward a left inclined surface of the sensing wafer. The left bevel and the right bevel are used to guide the object to be tested to complete sensing on the sensing surface. The method of packaging a semiconductor sensing chip according to claim 14, wherein the frame has a left inclined surface that is inclined toward the sensing wafer, and the left inclined surface is used to guide the object to be tested. The sensing is completed on the measuring surface. 1717
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