1271855 16317twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種記憶體元件，且特別是有關於一 種非揮發性記憶體及其製造方法與操作方法。 【先前技術】 葛半導體進入深次微米(Deep Sub-Micron)的製程時， 元件的尺寸逐漸縮小，對於記憶體元件而言，也就是代表 圮憶體元件的尺寸愈來愈小。然而，記憶體元件尺寸縮小 的結果將造成記憶體之通道長度(channdLength)縮短，導 致短通道效應問題的產生，使記憶體無法正常地運作。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a memory device, and more particularly to a non-volatile memory, a method of fabricating the same, and a method of operating the same. [Prior Art] When Ge Semiconductor enters the Deep Sub-Micron process, the size of the components is gradually reduced, and the size of the memory components, that is, the memory components, is getting smaller and smaller. However, as a result of the size reduction of the memory component, the channel length (channdLength) of the memory is shortened, resulting in a short channel effect problem, which prevents the memory from functioning properly.
立再者，為了在單位面積的矽晶片裡頭，放入更多的記 憶體元件’―般半導體製程多會從元件_隔離結構 開始作起，使各個元件之間能夠有所隔離，不會互相影= 然而’隔離結構的形成勢必料财晶片的佈局空間夂 ^兀^積集度，且於後續製程中也可能會產生其他新^ 效果的元件，將會是我們殷又一達到隔離 除此之外，由於在操作記憶體元件的時候 源極/汲極施加適當之電。目前的作法通 、、^ 極區上，形成接觸窗開口（contact 及 1271855 16317twf.doc/g 【發明内容】 有鑑於此，本發明的目的就是在提供一 憶體，在不影響元件積集度的情形之下， ，性冗 =的發生’且由於無須設置隔離結構，▲能夠“:: 本=的另—目的是提供—種非揮發性記憶體的以 ft 簡單’不必形成隔離結構與接觸窗開口，又 月b夠與互補式金氧半導體電晶體的製程相整合。 本發^的又—目狀提供—種非揮發性記憶體的操作 =猎由施加適當電壓’於選擇閘極旁邊形成強反轉層， 用采私式化、讀取與抹除此非揮發性記憶體。 選擇= 月ΪΓ種非揮發性記憶體’：基底、多數個 二 閘介電層、多數個摻雜區、多數個控制 荷儲存結構。基底巾具有紐個溝渠，這 r晋排列’並往—第―方向延伸。多數個選擇閘極 :^ &中，填滿這些溝渠。多數個閘介電層設置於選 擇閘，與基底之間。多數個摻雜區設置於溝渠下方之基底 夕數個控制閘極設置於基底上，這些控制閑極平行排 上並往―第二方向延伸，且第二方向與第—方向交錯。 ^個電荷儲存結構分職置於㈣__的基底 間。 #依照本發明的實施例所述之非揮發性記憶體，上述電 何儲存結構，更可以延伸至選擇閘極上，往第二方向延伸。 依照本發明的實施例所述之非揮發性記憶體，更可以 1271855 16317twf.doc/g 包括多數個卩相介電厚 之間。 "，i別設置於選擇閘極與控制閘極 依照本發明的實 荷儲存結構由基底起歹lJ所述之非揮發性記憶體，上述電 一阻擋介電層。盆中穿隧介電層、—電荷儲存層與 矽或是氮化石夕。此外，^何儲存層之材質可以是摻雜多晶 如是氧化矽。 牙隧介電層與阻擋介電層之材質例 制閉極之材斤述之非揮發性記億體，上述控 摻雜=:閘介;材質例如是 中’填滿==;=可:==置於基底 夠避免==影^ 乂徒阿凡件的積集度。 迫 、此外，倘若非揮發性記憶體的電荷儲存芦 捕捉電子㈣性，射人於储齡層之巾^ 貝ς 電荷儲存層之中，而是以高斯分佈的= 儲Ϊ層的局部區域上。則具備此種電荷儲存層的 軍毛性记憶體就可以在單-記憶胞中儲存兩個位元，而 且’即使電荷儲存層未區分成-個一個區塊，也不合与塑 其儲存資料的功能。 曰…曰 本發明提出一種非揮發性記憶體的製造方法，首先提 1271855 16317twf.doc/g 供基^ ’並於基底巾形成多油溝渠，這些溝評行排列， 方向上延伸 '然後，於溝渠下方之基底中形成多 接著’於溝如之基底表面喊多數個問介 电層m職多數㈣擇閘極填滿這祕渠。之後， 於選擇閘極上形成多數個_介電層。接下來，於 荷儲存結構。然後’於電荷儲存結構上形成ί數個 二制，極’這些控制閘極平行排列，並往-第二方向上延 申’第二方向與第一方向交錯。 依照本發明的實施例所述之非揮發性記憶體的製造方 带上述電荷儲存結構由基底表面起包括一穿隧介電層、 =荷儲存層與—阻播介電層。其中電荷儲存層之材士可 疋备雜多晶石夕或是說化石夕。 依照本發明的實施例所述之非揮發性記憶體的製造方 / ’上述形成閘介電層之方法可以是熱氧化法。上述形成 甲間介電層之方法例如是熱氧化法。 依照本發明的實施例所述之非揮發性記憶體的製造方 Μ ί物成溝渠之方法可以是先於基底上形成—層圖案 罩幕層。之後，以圖案化罩幕層為罩幕蝕刻基底，以形 成溝渠。 依照本發明的實施例所述之非揮發性記憶體的製造方 ^上述形成選擇閘極，填滿溝渠之方法例如是先於基底 葚：成一層導體層’再回蝕刻導體層’以暴露出圖案化罩 暴層的表面。 本發明之非揮發性記憶體的製造方法，其製程簡單， 1271855 16317twf.doc/g 不必形成隔離結構與接觸窗開口，不但減少製程的複雜 度’而且可以避免在形成接觸窗開口的過程中，因為錯誤 • 對準所造成的不正常電性導通問題。除此之外，又能夠與 ， 互補式金氧半導體電晶體的製程相整合，相當具有產業上 利用價值。 本發明提出一種非揮發性記憶體的操作方法，適用於 一記憶胞陣列’記憶胞陣列包括：多數條選擇閘極線，設 ^ 置於基底中’且填滿基底中之多數個溝渠，這些溝渠於一 第一方向平行排列；多數條位元線，設置於溝渠下方之基 底中；多數條字元線，於第二方向平行排列，且第二方向 與第一方向交錯；其中，相鄰兩記憶胞共用一選擇閘極線 與一位元線’第二方向上之記憶胞共用一字元線，且各個 記憶胞包括一電荷儲存層，位於相鄰兩選擇閘極線之間； 此操作方法包括： 於進行程式化操作時，於選定之記憶胞所連接之第一 擇閘極線施加第一電壓；於選定之記憶胞所連接之第二 選擇閘極線施加第二電壓；於選定之記憶胞的第一選擇閘 極線相鄰之第三選擇閘極線施加第三電壓；於選定之記憶 胞的第二選擇閘極線相鄰之第四選擇閘極線施加第四電 壓；於選定之記憶胞所連接之字元線施加第五電壓；於第 一選擇閘極線下方之第一位元線施加第六電壓；於第二選 擇閘極線下方之第二位元線施加第七電壓，以於選定之記 憶胞中之電荷儲存層存入一位元，其中第五電壓大於第二 電壓，且第二電壓大於第一電壓。 1271855 16317twf.doc/g 、依照本發明的實施例所述之非揮發性記憶體的操作方 法，上述於進行讀取操作時，於第一選擇間極線施加第八 •電壓；於第二選擇閘極線施加第九電壓；於第三選擇閘極 •線施加第十電壓；於第四選擇閘極線施加第十一電壓；於 字^線施加第十二電壓；於第一位元線施加第十三電壓； 於第二位元線施加第十四電壓，以讀取此位元，其中第十 二電壓大於第人電壓且小於第五電壓，且第人電壓大於第 九電壓。 依照本發明的實施例所述之非揮發性記憶體的操作方 法，上述於進行抹除操作時，於第二選擇閘極線施加第十 五電壓，於字凡線施加第十六電壓；於第二位元線施加第 十七電壓，以抹除此位元。 依照本發明的實施例所述之非揮發性記憶體的操作方 法，上述之位元是位於電荷儲存層中，靠近第二選擇閘極 線的一側。 依照本發明的實施例所述之非揮發性記憶體的操作方 法，更可以於電荷儲存層中，靠近第一選擇閘極線側的一 側，進行另一位元的操作，操作方法包括：於進行程式化 操作時’於第一選擇閘極線施加第二電壓；於第二選擇問 極線施加第一電壓；於第三選擇閘極線施加第四電壓；於 第四選擇閘極線施加第三電壓；於字元線施加第五電壓； 於第一位元線施加第七電壓；於第二位元線施加第六電 壓，以於電荷儲存層中，靠近第一選擇閘極線的一側，存 入另一位元。 1271855In addition, in order to put more memory components in the unit area of the wafer, 'the semiconductor process will start from the component_isolation structure, so that the components can be isolated, not each other. Shadow = However, the formation of the isolation structure is bound to be the layout space of the chip, and the other components of the new effect may be generated in the subsequent process. In addition, the source/drain applies appropriate power when operating the memory component. In the current practice, the contact window opening is formed on the contact area, and the contact window opening is formed (contact and 1271855 16317twf.doc/g). In view of the above, the object of the present invention is to provide a memory element without affecting the component accumulation degree. Under the circumstances, the occurrence of sexual redundancy = and because there is no need to set up an isolation structure, ▲ can ":: This is another - the purpose is to provide a kind of non-volatile memory with ft simple 'do not have to form isolation structure and contact The window opening, and the monthly b is enough to be integrated with the process of the complementary MOS transistor. The operation of the present invention provides a non-volatile memory operation = hunting by applying an appropriate voltage 'to the selected gate A strong inversion layer is formed, which is used to read, erase, and erase the non-volatile memory. Select = Moonlight non-volatile memory': substrate, most of the two gate dielectric layers, and most doping The area and the majority of the control storage structure. The base towel has a new ditches, which are arranged in the same direction and extend in the direction of the first direction. Most of the selection gates: ^ & fill the trenches. Most of the gates are dielectric The layer is set on the selection gate, Between the substrates, a plurality of doped regions are disposed on the substrate below the trenches, and a plurality of control gates are disposed on the substrate. The control idle electrodes are arranged in parallel and extend in the second direction, and the second direction is interleaved with the first direction. ^ A charge storage structure is placed between the substrates of (4)__. According to the non-volatile memory of the embodiment of the present invention, the above-mentioned electrical storage structure can be extended to the selective gate to the second direction. The non-volatile memory according to the embodiment of the present invention may further include a plurality of germanium phase dielectric thicknesses between 1271855 and 16317 twf.doc/g. ", i is not set in the selection gate and the control gate The solid storage structure in accordance with the present invention has a non-volatile memory as described by the substrate, and the electrical-blocking dielectric layer. The pothole tunnels the dielectric layer, the charge storage layer and the germanium or the nitride. In addition, the material of the storage layer may be doped polycrystal such as yttrium oxide. The material of the tunnel dielectric layer and the blocking dielectric layer is a non-volatile material of the closed-loop material, and the above-mentioned controlled doping =: 介介; material is for example ' Full ==; = can be: == placed on the substrate enough to avoid == shadow ^ 乂 阿 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡 凡The storage layer of the layer 2 is in the charge storage layer, but is distributed in a Gaussian = local area of the reservoir layer. The military memory with such a charge storage layer can be in the single-memory cell. Two bits are stored in the middle, and 'even if the charge storage layer is not divided into one block, it does not function with the plastic storage material. 曰... The present invention proposes a method for manufacturing non-volatile memory, first mentioning 1271855 16317twf.doc/g Supply base ^ 'and form a multi-oil ditches in the base towel, these grooves are arranged in the direction, extending in the direction 'and then formed in the base below the ditch and then on the surface of the ditch as the base surface shouts most Ask the majority of the dielectric layer m (4) select the gate to fill this secret channel. Thereafter, a plurality of _ dielectric layers are formed on the selection gate. Next, the storage structure is stored. Then, a plurality of two terminals are formed on the charge storage structure, and the control gates are arranged in parallel, and the second direction is extended in the second direction to be staggered with the first direction. Manufacture of Non-Volatile Memory According to Embodiments of the Invention The charge storage structure described above includes a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer from the surface of the substrate. Among them, the material of the charge storage layer can be prepared with a heteropolylith or a fossil. The method of manufacturing the non-volatile memory according to the embodiment of the present invention / The above method of forming the gate dielectric layer may be a thermal oxidation method. The above method of forming the inter-electron dielectric layer is, for example, a thermal oxidation method. The method for fabricating a non-volatile memory according to an embodiment of the present invention may be to form a layer pattern mask layer on the substrate. Thereafter, the substrate is etched with a patterned mask layer as a mask to form a trench. The method for manufacturing a non-volatile memory according to an embodiment of the present invention forms a selective gate, and the method of filling the trench is, for example, preceded by a substrate 葚: forming a layer of a conductor layer and then etching back the conductor layer to expose Pattern the surface of the storm layer. The method for manufacturing the non-volatile memory of the invention has a simple process, and the 1271855 16317twf.doc/g does not need to form the isolation structure and the contact window opening, which not only reduces the complexity of the process, but also avoids the process of forming the contact window opening. Because of the error • Alignment caused by abnormal electrical conduction problems. In addition, it can be integrated with the process of complementary MOS transistors, which is quite industrially valuable. The invention provides a method for operating a non-volatile memory, which is suitable for a memory cell array. The memory cell array includes: a plurality of strip select gate lines, and is disposed in the substrate and fills a plurality of trenches in the substrate. The trenches are arranged in parallel in a first direction; a plurality of bit lines are disposed in the substrate below the trench; a plurality of word lines are arranged in parallel in the second direction, and the second direction is interlaced with the first direction; wherein, adjacent The two memory cells share a select gate line and a bit line 'the memory cells in the second direction share a word line, and each memory cell includes a charge storage layer between adjacent two select gate lines; The operation method includes: applying a first voltage to a first selected gate line connected to the selected memory cell during the stylizing operation; applying a second voltage to the second selected gate line connected to the selected memory cell; Applying a third voltage to a third selected gate line adjacent to the first selected gate line of the selected memory cell; applying a fourth voltage to a fourth selected gate line adjacent to the second selected gate line of the selected memory cell Applying a fifth voltage to the word line connected to the selected memory cell; applying a sixth voltage to the first bit line below the first selected gate line; and a second bit line below the second selected gate line A seventh voltage is applied to store a charge in the selected one of the memory cells, wherein the fifth voltage is greater than the second voltage and the second voltage is greater than the first voltage. 1271855 16317 twf.doc/g, according to the method for operating a non-volatile memory according to an embodiment of the invention, the eighth voltage is applied to the first selected interpolar line during the reading operation; Applying a ninth voltage to the gate line; applying a tenth voltage to the third selected gate line; applying an eleventh voltage to the fourth selected gate line; applying a twelfth voltage to the word line; and the first bit line Applying a thirteenth voltage; applying a fourteenth voltage to the second bit line to read the bit, wherein the twelfth voltage is greater than the first person voltage and less than the fifth voltage, and the first person voltage is greater than the ninth voltage. According to the method for operating a non-volatile memory according to the embodiment of the present invention, when performing the erasing operation, the fifteenth voltage is applied to the second selected gate line, and the sixteenth voltage is applied to the word line; The second bit line applies a seventeenth voltage to erase the bit. In accordance with a method of operating a non-volatile memory according to an embodiment of the invention, the bit is located on a side of the charge storage layer adjacent to the second select gate line. According to the method for operating a non-volatile memory according to the embodiment of the present invention, another bit operation may be performed on a side of the charge storage layer adjacent to the first selection gate line side, and the operation method includes: Applying a second voltage to the first selected gate line during the programming operation; applying a first voltage to the second selected gate line; applying a fourth voltage to the third selected gate line; and selecting the fourth gate line for the fourth Applying a third voltage; applying a fifth voltage to the word line; applying a seventh voltage to the first bit line; applying a sixth voltage to the second bit line to be adjacent to the first selected gate line in the charge storage layer On one side, save another bit. 1271855
於弟二選擇閘極線施加第十一電壓； 性記憶體的操作方 進行讀取操作時，於第_選擇 一選擇閘極線施加第八電壓； 一電壓；於第四選擇閘極線施 加第十電壓；於字元線施加第十二電壓；於第一位元線施 加第十四電壓，於第一位元線施加第十三電壓，以讀取另 • 依照本發明的實施例所述之非揮發性記憶體的操作方 去，上述操作方法包括·於進行抹除操作時，於第二選 閘極線施加第十五電壓；於字元線施加第十六電壓；於第 —位元線施加第十七電壓，以抹除另一位元。 依照本發明的實施例所述之非揮發性記憶體的操作方 法，上述第一電壓為2伏特左右，第二電壓為6伏特左右， 第三電壓為0伏特左右’第四電壓為〇伏特左右，第五電 壓為10伏特左右，第六電壓為〇伏特左右，第七電壓為2 伏特左右。 依照本發明的貫施例所述之非揮發性記憶體的操作方 法，上述第八電壓為4伏特左右，第九電壓為2伏特左右， 第十電壓為0伏特左右，第十一電壓為0伏特左右，第十 二電壓為5伏特左右，第十三電壓為1〜3伏特左右，第十 四電壓為0伏特左右。 依照本發明的實施例所述之非揮發性記憶體的操作方 法，上述第十五電壓為4伏特左右，第十七電壓為^伏特 左右。上述第十六電壓小於〇伏特，例如是-1 〇伏特乂右 1271855 16317twf.doc/g 本發明之非揮發性記憶體的操作方法，藉由對此非發 揮發性Alt體施加適當電壓，而於選擇閘極旁形成的強反 轉層，將電子注入電荷儲存層之中，程式化、 此非揮發性記憶體。 、/、抹除 >為襄本明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉實施例，並配合所附圖式，作詳細說明如 下。Yu Di 2 selects the gate line to apply the eleventh voltage; when the operator of the memory memory performs the read operation, the eighth voltage is applied to the first select gate line; a voltage is applied to the fourth select gate line a tenth voltage; applying a twelfth voltage to the word line; applying a fourteenth voltage to the first bit line, applying a thirteenth voltage to the first bit line to read another embodiment according to the present invention In the operation of the non-volatile memory, the above operation method includes: applying a fifteenth voltage to the second gate line when performing the erase operation; applying the sixteenth voltage to the word line; The seventeenth voltage is applied to the bit line to erase the other bit. According to the method for operating a non-volatile memory according to an embodiment of the invention, the first voltage is about 2 volts, the second voltage is about 6 volts, and the third voltage is about 0 volts. The fourth voltage is about volts. The fifth voltage is about 10 volts, the sixth voltage is about volts, and the seventh voltage is about 2 volts. According to the method for operating a non-volatile memory according to the embodiment of the present invention, the eighth voltage is about 4 volts, the ninth voltage is about 2 volts, the tenth voltage is about 0 volts, and the eleventh voltage is 0 volts. Around the volt, the twelfth voltage is about 5 volts, the thirteenth voltage is about 1 to 3 volts, and the fourteenth voltage is about 0 volts. According to the operation method of the non-volatile memory according to the embodiment of the present invention, the fifteenth voltage is about 4 volts, and the seventeenth voltage is about volts. The above sixteenth voltage is less than 〇V, for example, -1 〇 volt 乂 right 1271855 16317 twf.doc / g The method of operating the non-volatile memory of the present invention, by applying an appropriate voltage to the non-volatile Alkene body, A strong inversion layer formed next to the gate is selected to inject electrons into the charge storage layer to stylize the non-volatile memory. The above and other objects, features and advantages of the present invention will become more apparent and understood.
【實施方式】 圖1A是繪示本發明一實施例之一種非揮發性記憶體 的結構上視圖。圖1B是繪示圖1A中沿A-A，線的結構剖 面圖。圖2A是繪示本發明另一實施例之一種非揮發性記 憶體的結構上視圖。圖2B是繪示圖2A中沿A_A，線的結 構剖面圖。 請參照圖1A，本發明之非揮發性記憶體包括基底 100、夕數個選擇閘極SG1〜SG4、多數個摻雜區DR1〜 DR4與多數個控制閘極cgi〜CG4。其中，選擇閘極SG1 〜SG4與摻雜區DR1〜DR4例如是平行排列，並往X方向 延伸·’控制閘極CG1〜CG4例如是平行排列，並往γ方向 延伸，且X方向與γ方向交錯。 請同時參照圖1A與圖1B，基底1〇〇中具有多數個溝 渠T1〜T4，這些溝渠T1〜T4例如是平行排列，並往X方 向延伸。多數個選擇閘極SG1〜SG4設置於基底1〇〇中， 填滿這些溝渠T1〜T4。多數個閘介電層110設置於選擇閘 極SG1〜SG4與基底100之間。多數個摻雜區DR1〜DR4 12 1271855 16317twf.doc/g 設置於溝渠T1〜T4下方之基底loo中。多數個控制閘極 CG1〜CG4設置於基底1〇〇上，這些控制閘極CGi〜〔Μ 例如是平行排列，並往γ方向延伸，且γ方向與χ方向 交錯。多數個電荷儲存結構120分別設置於控制閘極 〜CG4與相鄰兩溝渠之間的基底1〇〇之間，如圖1a所八， 電荷儲存結構120是一個一個的區塊。請參照圖1B，電1荷 儲存結構120位於基底100與控制閘極CG4之間。多 閘間介電層13G，分別設置於χ方向與γ方向交錯的位置 上，亦即設置於控制閘極CG4與選擇閘極SG1〜SG4上下 重叠的位置之間，如圖1B所示，用來隔離這控制閘極 與選擇閘極SG1〜SG4。 請參照圖1B，上述電荷儲存結構m由基底起 穿随介電層121、電荷儲存層123與阻擔介電層125。，、、、， 電荷儲存層123之材質可以是摻雜多晶石夕或是氮化秒、 是其他能夠使電荷儲存或陷人於其中之材質，例如j 物、鈦酸_與铪氧化物等。其中，氮化销可以依 石夕比例的不同，分為啊或是_9等。穿隨介電層 與阻擒介電層125之材質例如是氧切之類的適當材θ質。 上述控制閘極CG1〜CG4之材質可以是摻 . 選擇閘極SG1〜SG4之材質例如是摻雜多晶石夕。當: 制閘極CG1〜CG4與選擇間極SG1〜SG4之:二: 其他導體材料如金屬、金屬魏物等。閘介^ = 2如是氧切。閘間介電層130的材質例“氧化3 適备的介電材料。摻舰DR1〜DR4植人的摻質可以是p[Embodiment] FIG. 1A is a structural top view showing a non-volatile memory according to an embodiment of the present invention. Fig. 1B is a cross-sectional view showing the structure taken along line A-A of Fig. 1A. Fig. 2A is a structural top view showing a non-volatile memory of another embodiment of the present invention. Fig. 2B is a cross-sectional view showing the structure taken along line A_A of Fig. 2A. Referring to FIG. 1A, the non-volatile memory of the present invention includes a substrate 100, a plurality of select gates SG1 to SG4, a plurality of doped regions DR1 to DR4, and a plurality of control gates cgi to CG4. The selection gates SG1 to SG4 and the doping regions DR1 to DR4 are, for example, arranged in parallel and extend in the X direction. The control gates CG1 to CG4 are, for example, arranged in parallel and extend in the γ direction, and the X direction and the γ direction. staggered. Referring to Fig. 1A and Fig. 1B, the substrate 1 has a plurality of trenches T1 to T4, and the trenches T1 to T4 are, for example, arranged in parallel and extend in the X direction. A plurality of selection gates SG1 to SG4 are disposed in the substrate 1A to fill the trenches T1 to T4. A plurality of gate dielectric layers 110 are disposed between the selection gates SG1 SGSG4 and the substrate 100. A plurality of doping regions DR1 to DR4 12 1271855 16317twf.doc/g are disposed in the substrate loo below the trenches T1 to T4. A plurality of control gates CG1 to CG4 are disposed on the substrate 1A, and the control gates CGi to [Μ are, for example, arranged in parallel and extend in the γ direction, and the γ direction is staggered with the χ direction. A plurality of charge storage structures 120 are respectively disposed between the control gates -CG4 and the substrate 1〇〇 between the adjacent two trenches. As shown in FIG. 1a, the charge storage structure 120 is a block one by one. Referring to FIG. 1B, the electrical storage structure 120 is located between the substrate 100 and the control gate CG4. The multi-gate dielectric layer 13G is respectively disposed at a position where the χ direction and the γ direction are staggered, that is, between the control gate CG4 and the selection gates SG1 SGSG4, as shown in FIG. 1B. To isolate the control gate and select gates SG1 ~ SG4. Referring to FIG. 1B, the charge storage structure m is etched from the substrate by the dielectric layer 121, the charge storage layer 123, and the resistive dielectric layer 125. The material of the charge storage layer 123 may be doped polycrystalline or nitrided second, and is another material capable of storing or trapping charges, such as j, titanate and antimony oxide. Wait. Among them, the nitriding pin can be divided into ah or _9 according to the different ratio of Shi Xi. The material of the dielectric layer and the barrier dielectric layer 125 is, for example, a suitable material such as oxygen. The material of the control gates CG1 to CG4 may be doped. The material of the gates SG1 to SG4 is, for example, doped with polycrystalline spine. When: Gate CG1 ~ CG4 and selected interpole SG1 ~ SG4: Two: Other conductor materials such as metals, metal objects and so on. The gate is ^ 2 if it is oxygen cut. The material of the inter-gate dielectric layer 130 is "oxidized 3 suitable dielectric material. The dopant of the implanted DR1 ~ DR4 implanted may be p
13 1271855 16317twf.doc/g 料姑：貫f,中’假使電荷儲存層的材質是能夠捕捉電 •的方式ΐ中子在此㈣質中是以高斯分佈 •、结構就可以不t =部區域上。因此’電荷儲存 m? 220也可以是呈長條狀地設置於基底 • 控制開⑽丨〜⑽而排列，姉m 月…圖2B’電荷儲存結構22〇由基底1〇 =!，221、電荷儲躺_4: 矽“ ：：221與阻擋介電層225的材質例如是氧化 可以而電荷儲存層223的材質則必須是 與^化物等。至於摻雜多晶料類導 223 Lt 長條狀電荷儲存結構220中之電荷儲存層 § ^注人電子_候，將使得整條電荷儲存層223 Ϊ = 通狀恶’反而會導致非揮發性記憶體無法正常運作。 荷儲ί:播t 口2Β可以看到，由於非揮發性記憶體之電 °G子^ 1長條狀設置於控制閘極CG4與選擇間極 姓L〜SG4之間。因此，閘間介電層130是位於電荷儲存 220與選擇閘極SG1〜犯4之間。至於圖2b中^ 軍=記憶體的其他元件’其位置和材質與圖ΐβ 不的非揮發性記憶體皆相同，因此，圖2a與圖2b就直^ 14 1271855 16317twf.doc/g 以圖1A與圖IB中的元件符號表示這些相同的元件 存二條狀的電荷健 疋基於此種電荷儲存層223 其材备的特性，電荷儲存結構22〇也可以是—曰 基底100上，端視元件的設計而定，於此不再費 上述實施例中，係以四個選擇閘極SG1〜sg ^ :極CG1〜CG4構成的陣列為例作說 T，舉例來說，於¥方向上可以形成3二 軸32至64個控她 設置二。由於選擇開極― 控制溝㈣〜二it基=中之溝mTi〜T4，藉由 中填入選擇閘極SG1〜SG4。 疋於溝术τι〜τ4 空間，在單位面積上形成更1計不但能夠節省佈局 集度，而且也可以達到己憶體’而提高元件的積 的問題。 、效果’不會發生漏電或短路 此外’倘右電荷儲存厚 $ 斯分佈的形式阻陷於電荷儲存材質’電子係以高 憶胞令便可以儲存兩個位元的“局:區域上’則單二 电何儲存層的電荷儲存結構，可以呈長條狀地設= 1271855 16317twf.doc/g 100上（如圖2A中之電荷儲存 個-個區塊(如圖則之電; 裡Γ更多的資料，也提供糾錢大以 接二：：不同來設計電荷儲存結構的形狀。 圖3F是ί示本:的製造方法。圖3Α至 造流程剖面圖。圖3Α至f非揮發性記憶體的製 線之剖面圖。 圖3F^_圖1A中之A-A’ _=====織-細，於基底 層硬罩幕』二;;層=層3Glb與一 ^ ，、虱化層3〇1&的形成方法例如是 ^口 4岛1b的材質例如是氮化石夕，其形成方法 m r氣相沈積法。硬罩幕層3Qie的材質例如是氧化 =〇法例如是化學氣相沈積法。之後，於硬罩幕 l λ上形成一層圖案化光阻層3〇3。圖案化光阻層3〇3 例如是μ旋轉塗佈(响⑽11财式於硬罩 上軸Γ層光阻材料層（未繪示），於曝光後進 4丁圖案的顯影而形成圖案化光阻層303。 接著，請參照圖3B，以圖案化光阻層3〇3為罩幕，蝕 亥J下方之硬罩幕層3〇lc、罩幕層3〇lb與墊氧化層3〇ia。 触刻的方法例如是等向㈣刻法。之後，移除圖案化光阻 層303與硬罩幕層301c，移除的方法例如是非等向性蝕刻 法並以召下的圖案化之罩幕層301b與墊氧化層3〇ia為 罩幕，蝕刻基底300，以形成溝渠305。蝕刻基底3〇〇的方 16 1271855 16317twf.doc/g 法例士疋非等向性式餘刻法。然後 曰0中=多數個摻雜區3G9。摻雜區^的开^成方法 i行:Ϊ:二單:層3:與墊氧化層3，為罩幕’ 所，:王植入之摻質例如是P型摻質或！^型摻 貝，八鈿視兀件之型態而定。 p 照圖3C，於溝渠305内之基底卿表面形 夕f ;丨包層310。閘介電層310的材質例如是氧化 ，其形成方法例如是熱氧化法。繼而， 曰石夕、金屬或是金屬石夕化物等導體材 ㈣、）先於基底300上形成一層導體層（未 以曰利用：Ξ 貝可以是摻雜多晶矽，其形成方法可 ":::虱相沈積法形成-層未摻雜多晶矽層後，進 驟以形成之，當然也可以採用臨場植入摻質 的方式化千乳相沈積法形成換雜 ==’使導體層表面低於罩幕層心‘ 33； 315 私占方心,上 包層的材質例如是氧化石夕，1 成例如是熱氧化法或化學氣相沈積法。接著再㈣ 向性蚀刻法移除罩幕層遍與塾氧化層鳥接者再以專 介電層321、;構^^底3〇0起依序是包括—層穿隨 豆中穿隱八带曰包何储存層323與一層阻擋介電層325。 ，、 電層321之材質例如是氧化石夕’其形成方法例 1271855 16317twf.doc/g 層325之材質匕學氣相沈積法。阻擋介電 沈積法。當秋，穿其形成方法例如是化學氣相 是其他類似的材：二笔層，及阻擔介電層325也可以 石夕或摻雜多晶^也^讀存層323之材質並不限於氮化 材質，例如其他能夠㈣荷儲存於其中之 化層、鈦酸锶層與铪氧化層等。 成抗反ΐ層•’於麵存結構挪之凹陷處形 材質例Γ=t l1Gn CGating)327。抗反射層切的 所^、@、氮氧切或是其它材質例如由高分子 物，其形成方法例如是旋轉塗佈。由於抗反 係數較低，因此可以糊 荷#m2凹陷處。繼而以抗反射層327為罩幕，_電 储存、，，。構32G，移除關介電層330上的電荷儲存 32〇’將電荷儲存結構32()分隔成與選擇閘極3丨5平行 條狀’其巾，移除的方法例如是料向性細j法。接菩，、 ，移除抗反射層327，移除抗反射層327的方法例如是1 式餘刻或濕式餘刻等適當的製程。 乙 利用抗反射層327材質的特殊性質，移除部分之❿^ 儲存結構320，就不必再進行一般微影、蝕刻製程。 二來，將可以省去塗佈光阻、曝光、顯影等步驟，降^ 程的複雜度，同時也節省這些步驟所耗費的時間。-衣 然後，請芩照圖3F，於基底300上形成_層控制閘極 340。控制閘極340的材質例如是摻雜多晶矽、金^或^金 18 1271855 16317twf.doc/g 屬矽化物等適當的導體材料。控制閘極340的形成方法可 以是依照材質的不同’以化學氣相沈積法或是物理氣相沈 積法等合適的製程，先於基底300上形成-層閘極材料層 (未繪不），再進行圖案化的步驟，以形成多個長條狀之 控制閘極340 ’如圖1A的上視圖所示。其中，於圖案化問 極材料層的步驟中，會同時圖案化其下方之電荷儲 32〇，因此，電荷儲存結構32〇的形狀就會如目u所、;， 為一個區塊—個區塊，使電荷得_存在各區塊當中。 請參考圖3G，其係接續於圖3D。在一實施例中，假 採用的是能夠捕捉電子或是其他能夠使 电何入於其中之材f，例如氮切、纽氧化物、 =給氧化物等此類的材f。由於電子係以高斯 形 =陷於電荷儲存層的局部區域上。因此，不必如 =、、會示’需要形成抗反射層327 ’填滿電荷儲存 〇 :處，用來移除選擇閘極315上之電荷儲存結構32〇。 存結構32G上形成控制_ J =/步驟’於電荷儲 的e士技u 制閘極34〇。如果在形成控制閘極340 户π候’也同日年圖案化電荷儲存結構32〇 存結構320最終的形狀就會如同圖2Α所示 = 了储 3控制閉極平行，當然，倘若形成控制閉=的 就會，-整層地設置於基底遍上。電域存結構汹 當然’為了操作此非揮發性記憶體，後續 他疋件’以便於選定的選擇閘極、控制閘極與摻 19 1271855 16317twf.doc/g . * 二壓’而程式化、讀取與抹除此—非揮發性記憶體。上述 凡成非揮奄性§己憶體的製程應為熟悉此技術者所週知，於 . 此不再資述。 - 、/上述之非揮發性記憶體的製造方法，其製程簡單，不 必形成隔離結構與接觸窗開口，大大地縮減了製程的複雜 度二而且，由於無須形成接觸窗開口，還可以避免形成接 觸窗開口的過程中，因為錯誤對準所造成的不正常電性導 _ 通問題。除此之外，上述非揮發性記憶體又能夠與互補式 &氧半^體電晶體的製程相整合，相當具有產業上利用價 值。 、 以下說明上述非揮發性記憶體的操作方法。圖4A所 繪示為本發明一實施例之一種非揮發性記憶體的程式化操 作示意圖。圖4B所繪示為本發明一實施例之一種非揮發 性記憶體的讀取操作示意圖。圖4C所繪示為本發明一實 施例之一種非揮發性記憶體的抹除操作示意圖。 請參考圖1A與圖1B，此操作方法適用於一記憶胞陣 籲列，記憶胞陣列包括多數條選擇閘極（即選擇閘極線）SQ1 〜SG4，設置於基底1〇〇中，且填滿基底中之多數個溝渠 T1〜T4，溝渠T1〜T4在X方向平行排列；位於溝渠T1 〜T4下方之基底1〇〇中的多數個摻雜區（即位元線）DR1 〜DR4 ;多數個控制閘極（即字元線）CG1〜CG4，於γ 方向平行排列，且Y方向與X方向交錯。 請參考圖1B，我們可以定義虛線圈出的方框為一個記 憶胞，其中，Y方向上相鄰的兩記憶胞共用一選擇閘極與13 1271855 16317twf.doc/g 料:: f, in the 'when the material of the charge storage layer is able to capture electricity · ΐ neutron in this (four) quality is Gaussian distribution • structure can not t = part of the area on. Therefore, 'charge storage m? 220 can also be arranged in a strip shape on the substrate. • Control open (10) 丨 ~ (10) and arrange, 姊m month... Figure 2B' charge storage structure 22 基底 by substrate 1 〇 =!, 221, charge The storage material _4: 矽 ": 221 and the material of the barrier dielectric layer 225 is, for example, oxidized, and the material of the charge storage layer 223 must be a compound, etc. As for the doped polycrystalline material, the 223 Lt strip The charge storage layer in the charge storage structure 220 is such that the entire charge storage layer 223 Ϊ 通 通 通 通 通 通 通 通 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反 反2Β It can be seen that the non-volatile memory is disposed between the control gate CG4 and the selected gate polarity L~SG4. Therefore, the gate dielectric layer 130 is located in the charge storage. 220 is between the selection gate SG1 and the crime 4. As for the other components of the memory in Fig. 2b, the position and material of the memory are the same as those of the non-volatile memory of Fig. β, therefore, Fig. 2a and Fig. 2b Straight ^ 14 1271855 16317twf.doc / g These elements are represented by the symbol in Figure 1A and Figure IB The second charge-like charge is based on the characteristics of the charge storage layer 223. The charge storage structure 22 can also be on the substrate 100, depending on the design of the device, and the above embodiment is not required. In the case of an array of four selection gates SG1 to sg ^ : poles CG1 to CG4, for example, T can be formed in the direction of the ¥, and 32 to 64 controllers can be set in the direction of the ¥. Select the opening pole - control groove (four) ~ two it base = Zhongzhigou mTi ~ T4, fill the selection gates SG1 ~ SG4 by filling in. 疋 沟 τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ Save layout, and also achieve the problem of improving the product's product. The effect 'will not leak or short circuit. In addition, if the right charge storage thickness is thick, the form of the distribution is trapped in the charge storage material' With high memory, you can store two bits of the "bureau: area", the charge storage structure of the single and second storage layers, which can be set in strips = 1271855 16317twf.doc/g 100 (as shown The charge in 2A stores one block (as shown in the figure; More information is also provided to correct the money to meet the second:: different to design the shape of the charge storage structure. Figure 3F is the manufacturing method of Figure: Figure 3 to the process flow profile. Figure 3 Α to f non-volatile A cross-sectional view of the line of memory. Figure 3F^_A-A' in Figure 1A _===== weaving-fine, in the base layer hard mask" two;; layer = layer 3Glb and a ^, The method for forming the deuterated layer 3〇1& is, for example, a material of the island 4b, which is, for example, a nitride, and a method of forming the mr vapor deposition method. The material of the hard mask layer 3Qie is, for example, an oxidation = 〇 method such as chemical vapor deposition. Thereafter, a patterned photoresist layer 3〇3 is formed on the hard mask l λ. The patterned photoresist layer 3〇3 is, for example, a micro-rotation coating (a film of a photoresist layer on a hard mask) (not shown), and is developed into a patterned photoresist after exposure. Layer 303. Next, referring to FIG. 3B, the patterned photoresist layer 3〇3 is used as a mask, and the hard mask layer 3〇lc, the mask layer 3〇1b, and the pad oxide layer 3〇ia under the etched layer J. The method of etching is, for example, an isotropic (four) lithography. Thereafter, the patterned photoresist layer 303 and the hard mask layer 301c are removed, and the removal method is, for example, an anisotropic etching method and a masked pattern is called. The layer 301b and the pad oxide layer 3〇ia are masks, and the substrate 300 is etched to form the trench 305. The side of the substrate 3 is etched 16 1271855 16317 twf.doc/g The law is a non-isotropic remnant method. 0 medium = a plurality of doped regions 3G9. The opening method of the doping region ^ i row: Ϊ: two single: layer 3: with the pad oxide layer 3, for the mask ',: King implanted dopants such as It is a P-type doping or a ^-type doped shell, depending on the type of the goblet. p. Figure 3C, the base surface of the ditch 305; the clam layer 310. The gate dielectric layer 310 The material is for example The formation method is, for example, a thermal oxidation method. Then, a conductor material (four), such as a sinite, a metal or a metal stellite, is formed on the substrate 300 to form a conductor layer (not used as a ruthenium: the oyster may be doped Heteropolycrystalline germanium, the formation method thereof can be formed by the formation of a layer of undoped polycrystalline germanium layer by a germanium phase deposition method, and then formed by a stepwise implantation method. Replacement == 'Make the surface of the conductor layer lower than the center of the curtain layer' 33; 315 privately occupy the square center, the material of the upper cladding layer is, for example, oxidized stone, for example, thermal oxidation or chemical vapor deposition. (4) The etch etching method removes the mask layer and the tantalum oxide layer bird connector and then uses the special dielectric layer 321; the structure bottom is 3〇0, and the sequence is included. The storage layer 323 and the protective dielectric layer 325 are formed, and the material of the electric layer 321 is, for example, an oxide oxide ' 。 。 。 127 127 127 127 127 127 127 127 127 127 127 127 127 Electrodeposition method. When autumn, the method of forming it is, for example, the chemical vapor phase is other similar materials. The two-layer layer and the resistive dielectric layer 325 may also be made of a stone or doped polycrystalline layer. The material of the memory layer 323 is not limited to a nitrided material, for example, other layers capable of being stored in the layer, titanic acid锶 layer and 铪 oxide layer, etc.. Anti-reverse layer • 'In the case of the surface structure, the concave shape material Γ = t l1Gn CGating) 327. The antireflection layer is cut, the @, the oxynitride or the other material is, for example, a polymer, and the method of forming it is, for example, spin coating. Since the anti-reverse coefficient is low, it is possible to paste the #m2 depression. Then, the anti-reflection layer 327 is used as a mask, _electric storage, ,,. The structure 32G removes the charge storage 32 on the off dielectric layer 330. The charge storage structure 32() is divided into strips parallel to the selected gate 3丨5, and the method of removing is, for example, thinner. j method. The method of removing the anti-reflection layer 327 and removing the anti-reflection layer 327 is, for example, a suitable process such as a type 1 residual or a wet residue. B. By using the special properties of the anti-reflective layer 327 material, the portion of the storage structure 320 is removed, and the general lithography and etching processes are not required. Secondly, the steps of coating photoresist, exposure, and development can be omitted, and the complexity of the process can be reduced, and the time taken for these steps can be saved. - Clothing Next, please refer to FIG. 3F to form a layer control gate 340 on the substrate 300. The material of the control gate 340 is, for example, doped polysilicon, gold or gold 18 1271855 16317twf.doc/g is a suitable conductor material such as a telluride. The control gate 340 may be formed by a suitable process such as chemical vapor deposition or physical vapor deposition according to different materials, and a layer of gate material is formed on the substrate 300 (not shown). The patterning step is further performed to form a plurality of elongated control gates 340' as shown in the upper view of FIG. 1A. Wherein, in the step of patterning the layer of the interposing material, the charge storage underneath is patterned at the same time. Therefore, the shape of the charge storage structure 32 is as shown in the figure; Blocks, so that the charge is stored in each block. Please refer to FIG. 3G, which is continued from FIG. 3D. In one embodiment, it is possible to capture electrons or other materials f that can cause electricity to enter, such as nitrogen cut, neo-oxide, = oxide, and the like. Since the electrons are Gaussian = trapped in a localized area of the charge storage layer. Therefore, it is not necessary to fill the charge storage 〇: as needed to form the anti-reflective layer 327' to remove the charge storage structure 32〇 on the selection gate 315. On the memory structure 32G, a control _ J = / step ' is stored in the e-technical gate 34 电荷 of the charge. If the control gate 340 is formed, the final shape of the patterned charge storage structure 32 storage structure 320 will be as shown in Fig. 2Α = the storage 3 control is closed parallel, of course, if the control is closed = Will, - the entire layer is placed on the substrate. The electrical domain structure is of course 'in order to operate this non-volatile memory, the subsequent components are used to facilitate the selection of the selected gate, the control gate and the doping 19 1271855 16317twf.doc/g. * Two-pressure' and stylized, Read and erase this - non-volatile memory. The above-mentioned process of non-voluntary § ** recalls should be well known to those familiar with this technology, and will not be described. - / / The above non-volatile memory manufacturing method has a simple process, does not need to form an isolation structure and a contact window opening, and greatly reduces the complexity of the process. Moreover, since it is not necessary to form a contact window opening, contact can be avoided. In the process of window opening, the problem of abnormal electrical conduction caused by misalignment. In addition, the above non-volatile memory can be integrated with the process of the complementary & oxyhalide transistor, which is quite industrially valuable. The method of operating the above non-volatile memory will be described below. FIG. 4A is a schematic diagram showing the stylized operation of a non-volatile memory according to an embodiment of the invention. FIG. 4B is a schematic diagram of a read operation of a non-volatile memory according to an embodiment of the invention. 4C is a schematic view showing a wiping operation of a non-volatile memory according to an embodiment of the present invention. Referring to FIG. 1A and FIG. 1B, the operation method is applicable to a memory cell array, and the memory cell array includes a plurality of selection gates (ie, select gate lines) SQ1 to SG4, which are disposed in the substrate 1 and filled in a plurality of trenches T1 to T4 in the full substrate, the trenches T1 to T4 are arranged in parallel in the X direction; and a plurality of doped regions (ie, bit lines) DR1 to DR4 in the substrate 1〇〇 under the trenches T1 to T4; The control gates (i.e., word lines) CG1 to CG4 are arranged in parallel in the γ direction, and the Y direction is interleaved with the X direction. Referring to FIG. 1B, we can define that the dotted circle is a memory cell, wherein two memory cells adjacent in the Y direction share a selection gate and
20 1271855 16317twf· doc/g 摻雜區，Y方向上鄰接的多個記憶胞，共用_個 極。且每個記憶胞中皆具有—電荷儲存層12 ς 4 =擇閘極間之基底上。電荷儲存層123的材質例== 化物、鈦_物與給氧化物等此類的材質，能 句使仔電荷儲存層123中的電$以古斯八 ' 電荷儲存声的月邮射Γ 方式集中於 作方、、= U °本㈣之非揮發性記憶體之操 /疋以二個圮憶胞為一組來進行操作。舉例而士，告 =記憶胞C2進行操作時，除了對於記憶胞C21:; =極CG4、選擇閘極SG2、選擇閘極SG3、摻工 外，還需要對記憶胞:之選 下,J、記憶胞C3中之選擇閘極犯4施加電壓。以 P以§己憶胞C2的操作為例作說明。 C2之^^ 4A ’於進行程式化操作時，於選定之記憶胞 之k擇閘極SG2施力π電愿v # ar η λ 於記憶胞C2之選極f例如是2伏特左右； 伏特左右；於記_胞C2 & 口电壓VpS3，其例如是6 V甘^ 側之選擇閘極SG1施加電愿 極SG4施加雷屙v甘/( L、胞C2另一側之選擇閘 CG4施加電〇伏特左右，·於控制閘極 SG? . ^ ，、例如疋10伏特左右；於選擇閘極 /右.於雜區聰施加電壓VpD2，其例如是0伏特 閘極抑下方之摻雜區贈施加電壓V削， S〇3^：：r： 的作用會產生紅制15G。強反轉層150 5 /及極一般，使得摻雜區DR2至摻雜區DR3 21 1271855 16317twf.doc/g 之間Ά者基底100的通道打開，將電子從播雜區DR2注入 吕己憶胞M2靠近選擇間極SG3 —侧的電荷儲存声123中， 而存入位元160a。其中電壓VpG大於電壓Vps3 f電壓Vps3 大於電壓VPS2，且注入電子的方式例如是通道熱電子注入 (Channel Hot Electron Injection)效應或是源極側 (Source-Side Injection)效應。 請參照圖4B，進行讀取操作時，於記憶胞C2之選擇 閘極SG2施加電壓VRS2 ’其例如是4伏特左右；於記憒胞 C2之選擇閘極SG3施加電壓VrS3，其例如是2伏特左右； 於5己fe胞C2 —側之選擇閘極SG1施加電壓,其例如 二〇伏特左右，於記憶胞C2另一側之選擇閘極SG4施加 電壓，其例如是〇伏特左右；於控制問極⑽施加電 壓VRG，其例如是5伏特左右；於選擇閘極沁2下方之摻 ，區DR2施加讓電流可以流通之—正電壓v_，其例如 =1 3伏特左右左右，於選擇閘極SG3下方之推雜區DR] 施加電壓vRD3，其例如是G伏特左右，其中v咖較佳大 於vRW。由於控制閘極的電壓Vrg大於選擇閘極sg2的 =vRS2，且選擇閘極SG2的電壓Vrs2大於選擇間極仰 電壓vRS3。因此，藉由判斷從摻雜區DR3流向捧雜區贈 的電=大^ ’就可以讀取先前存入之位元160a。 請麥照圖4C，進行抹除操作時，於記憶胞c2 閘極SG3施加雷w ES3 ’ /、例如疋4伏特左右；於控制鬧 極CG4施加電壓v ^ ^ . eg，其例如疋-ίο伏特左右；於選擇閘 極SG3下方之摻雜區咖施加電壓v腳，其例如是〇伏 22 1271855 16317twf.doc/g 特左右，以將電洞注入電荷儲存層123之中，抹除先前存 入之位元1。注入電洞之方式例如是穿隨增強型熱電洞 注入(Tunneling Enhanced Hot Hole Injection)模式或 F_N 穿 遂效應（Fowler-Nordheim tunneling)。20 1271855 16317twf· doc/g Doped area, a plurality of memory cells adjacent in the Y direction, sharing _ poles. And each memory cell has a charge storage layer 12 ς 4 = on the substrate between the gates. The material of the charge storage layer 123 is a material such as a compound, a titanium material, a donor oxide, or the like, which can cause the electricity in the charge storage layer 123 to be stored in the moon. The operation of the non-volatile memory concentrated on the recipe, = U ° (4) is performed in groups of two memory cells. For example, if the memory cell C2 is operating, in addition to the memory cell C21:; = pole CG4, select gate SG2, select gate SG3, blending work, it is also necessary to select the memory cell: J, The selection gate in the memory cell C3 is 4 to apply a voltage. Take the operation of P as the memory of C2 as an example. ^^ 4A' of C2 is used for the stylization operation, and the selected gate SG2 of the selected cell is forced to π. The v-ar η λ is selected in the memory cell C2, for example, about 2 volts; In the memory cell C2 & port voltage VpS3, which is, for example, the selection gate SG1 of the 6 V gamma side, the application of the electric pole SG4, the application of the Thunder v Gan / (L, the selection gate CG4 of the other side of the cell C2 is applied 〇 volts, around the control gate SG?. ^, for example, about 10 volts; in the selection gate / right. In the miscellaneous area Cong applied voltage VpD2, which is for example 0 volt gate below the doping area gift Applying voltage V, the effect of S〇3^::r: will produce red 15G. Strong inversion layer 150 5 / and very general, so that doped region DR2 to doped region DR3 21 1271855 16317twf.doc / g The channel of the interposer substrate 100 is opened, and electrons are injected from the miscellaneous region DR2 into the charge storage sound 123 of the side of the selected interpole SG3, and stored in the bit 160a. The voltage VpG is greater than the voltage Vps3 f The voltage Vps3 is greater than the voltage VPS2, and the method of injecting electrons is, for example, a channel hot electron injection effect or a source. (Source-Side Injection) Effect. Referring to FIG. 4B, when the read operation is performed, the voltage VRS2' is applied to the selection gate SG2 of the memory cell C2, which is, for example, about 4 volts; and is applied to the selection gate SG3 of the cell C2. The voltage VrS3 is, for example, about 2 volts; a voltage is applied to the selection gate SG1 on the C2 side of the hexene cell, for example, about two volts, and a voltage is applied to the selection gate SG4 on the other side of the memory cell C2, for example, It is about volts; it applies voltage VRG to the control pole (10), which is, for example, about 5 volts; in the doping below the selection gate 沁2, the region DR2 applies a positive voltage v_, which is, for example, 13 volts. The left and right sides, the dummy region DR] under the selection gate SG3, applies a voltage vRD3, which is, for example, about G volts, wherein the v coffee is preferably larger than vRW. Since the voltage Vrg of the control gate is greater than the =vRS2 of the selection gate sg2, And the voltage Vrs2 of the gate SG2 is selected to be larger than the inter-selective pole voltage vRS3. Therefore, the previously stored bit 160a can be read by judging that the electric current from the doping region DR3 to the doping region is large. Mai Zhao Figure 4C, when performing the erase operation, The memory cell c2 gate SG3 applies a lightning w ES3 ' /, for example, 疋 4 volts; a voltage v ^ ^ . eg is applied to the control CG4, which is, for example, 疋-ίο volts; a doping region under the selective gate SG3 The coffee applies a voltage v-foot, which is, for example, about 22 1271855 16317 twf.doc/g, to inject a hole into the charge storage layer 123, and erase the previously stored bit 1. The method of injecting a hole is, for example, a tunneling Enhanced Hot Hole Injection mode or a F_N piercing effect (Fowler-Nordheim tunneling).
請參照圖4D，由於本實施例中之電荷儲存層123係採 用氮化石夕、组氧化物、鈦酸錄物與铪氧化物等此類的材質 為例作說明，故而電荷儲存層123中的電荷是以高斯分佈 的方式集中於電荷儲存層123的局部區域上。因此，記憶 胞C2中’除了位元i60a之外，還可以於靠近選擇閘極SG2 一側的電荷儲存層123中，存入位元i60b，亦即在單一記 憶胞中可以儲存兩個位元的㈣，進—步增加記憶胞儲存 電荷的功效。當然，電荷儲存層123也可以是摻雜多晶矽 等導體材料，不過，由於導體材料儲存電荷的方式迥異於 氮化石夕類的材質。因此，非揮發性記憶體之電荷儲存層⑵ 的材質若為導體材料，則於單—記憶胞中便只能夠 ^ 個位元的資料。 本發明之轉發性記憶體的操作方法，藉由對此非 揮發性記憶體施加適當㈣，而於雜·旁形成的強 轉層150 ’利用強反轉層15〇與基底1〇〇之接合介 將電子注人電荷儲存層123之巾，程式化 非揮發性3憶體。 胃 綜上所述，本發明將選擇閘極設置於基底中， 長通迢的長度，避免短通道效應的發生。料，] 設置隔離結構，因料但關提高元件的難度，且= 23 1271855 16317twf.doc/g 減少製程的_度。㈣’本㈣提出之轉發性記憶體 的製造方法’不必形成接觸窗’還可以達到避免在 觸窗開口的雜巾，由於錯誤對準所減料正常電 通問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保1 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A是繪示本發明一實施例之一種非揮發性記情體 的結構上視圖。 " 圖1B是繪示圖1 a中沿A-A線的結構剖面圖。 圖2A是繪示本發明另/實施例之一種非揮發性圮情 體的結構上視圖。 U忌 圖2B是繪示圖2A中沿A-A’線的結構剖面圖。 圖3A至圖3F是繪示本發明一實施例之一種非揮發性 記憶體的製造流程剖面圖。 圖3G是繪示本發明另一實施例之一種非揮發性記情 體的製造流程剖面圖。 〜 圖4A所繪示為本發明一實施例之一種非揮發性記愤 體的程式化操作示意圖。 圖4B所繪示為本發明/實施例之一種非揮 體的讀取操作示意圖。 X ° % 圖4C所繪示為本發明一實施例之一種非揮發性圮情 ⑧ 24 1271855 16317twf.doc/g 體的抹除操作示意圖。 圖4D所繪示為本發明一實施例之一種非揮發性記憶 . 體的二位元電荷陷入示意圖 【主要元件符號說明】 Λ 100、300 :基底 110、310 :閘介電層 120、 220、320 :電荷儲存結構 121、 22i、321 :穿隧介電層 ® 123、223、323 ··電荷儲存層 125、225、325 :阻擋介電層 130、330 :閘間介電層 150 :強反轉層 160a、160b :位元 301a ··墊氧化層 301b :罩幕層 301c :硬罩幕層 • 303 ··圖案化光阻層 305、T1 〜T4 ··溝渠 309、DR1〜DR4 :摻雜區 315、SG1〜SG4 :選擇閘極 327 :抗反射層 340、CG1〜CG4 :控制閘極 Cl、C2、C3 : I己ItJ包 25Referring to FIG. 4D, since the charge storage layer 123 in this embodiment is made of a material such as a nitride, a group oxide, a titanate, and a tantalum oxide, the charge storage layer 123 is used. The charge is concentrated on a partial region of the charge storage layer 123 in a Gaussian distribution. Therefore, in the memory cell C2, in addition to the bit i60a, the bit storage element 123 can be stored in the charge storage layer 123 on the side close to the selection gate SG2, that is, two bits can be stored in a single memory cell. (4), step by step to increase the memory cell storage charge. Of course, the charge storage layer 123 may also be a conductive material such as doped polysilicon, but the manner in which the conductor material stores charge is different from that of the nitride nitride. Therefore, if the material of the charge storage layer (2) of the non-volatile memory is a conductor material, only one bit of data can be obtained in the single-memory cell. In the method for operating the transmissive memory of the present invention, by applying appropriate (4) to the non-volatile memory, the strong-transfer layer 150' formed by the impurity is bonded to the substrate 1 by the strong inversion layer 15'. The towel is electronically injected into the charge storage layer 123, and the non-volatile 3 memory is stylized. Stomach In summary, the present invention sets the selection gate in the substrate, the length of the long-passing, and avoids the occurrence of short-channel effects. Material,] Set the isolation structure, but it is difficult to improve the component due to the material, and = 23 1271855 16317twf.doc / g Reduce the _ degree of the process. (4) The manufacturing method of the transmissive memory proposed by the present invention does not require the formation of a contact window. It is also possible to avoid the problem of the normal electric flux due to misalignment due to misalignment of the opening of the window. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the insurance 1 is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a structural top view showing a non-volatile quotation body according to an embodiment of the present invention. " Fig. 1B is a cross-sectional view showing the structure taken along line A-A of Fig. 1a. Fig. 2A is a structural top view showing a non-volatile sputum of another embodiment of the present invention. U. Fig. 2B is a cross-sectional view showing the structure taken along line A-A' in Fig. 2A. 3A to 3F are cross-sectional views showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention. Fig. 3G is a cross-sectional view showing the manufacturing process of a non-volatile grammar according to another embodiment of the present invention. ~ Figure 4A is a schematic diagram showing the stylized operation of a non-volatile anger in an embodiment of the present invention. Figure 4B is a schematic diagram of a non-volley read operation of the present invention/embodiment. X ° % FIG. 4C is a schematic view showing the erasing operation of a non-volatile lyrical 8 24 1271855 16317 twf.doc/g body according to an embodiment of the present invention. FIG. 4D is a schematic diagram of a two-element charge trapping of a non-volatile memory according to an embodiment of the present invention. [Main component symbol description] Λ 100, 300: substrate 110, 310: gate dielectric layer 120, 220, 320: charge storage structure 121, 22i, 321: tunneling dielectric layer® 123, 223, 323 · charge storage layer 125, 225, 325: blocking dielectric layer 130, 330: inter-gate dielectric layer 150: strong anti- Transfer layer 160a, 160b: bit 301a · pad oxide layer 301b: mask layer 301c: hard mask layer 303 · patterned photoresist layer 305, T1 ~ T4 · ditch 309, DR1 ~ DR4: doping Zone 315, SG1 ~ SG4: Select gate 327: anti-reflection layer 340, CG1 ~ CG4: control gate Cl, C2, C3: I have ItJ package 25