TWI263343B - Non-volatile memory and fabrication and operation of the same - Google Patents

Abstract

A non-volatile memory device and fabrication and operation of the same are described. A cell of the memory device includes a semiconductor layer with a charge-trapping layer thereon, a central gate and two side gates each spanning the semiconductor layer interposed with the charge-trapping layer, and two S/D regions in the semiconductor layer outside the two side gates.

Description

1263343 14692twf. doc/006 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor element method, and particularly relates to a type of non-volatile purchase using the charge tantalum: Memory unit and memory "two: private, and its operation methods of writing, erasing and reading. [Previous technology] = can be electrically programmed non-volatile memory system using floating gate to store electricity - 5 memory cells can only Store one bit. In order to improve the early capacity of this non-volatile note, the size of the sneak peek + $ squad is as small as possible. However, when the size of the cell is too small, The process and electrical properties are not easy to control, and its development encounters the neck. The other direction of the unit capacity of the South memory is to increase the storage capacity of a single memory. For example, this Β 咖 (4) proposed a new ^ in 1999 Non-volatile memory, called nitriding 7 read-only memory (NR 〇 M), its memory cell can store 2 bits of data, and store the required face of each bit and about 2. 5~ 3I?2 (F is the [feature size]). An NR〇m array consists of multiple buried people. Bit line, bit line _ a plurality of strip-shaped help layers, and a plurality of word lines crossing each of the element lines and each strip of 〇N〇 layers, ^ y sub-element lines and a 〇N 〇 layer The overlapping portion acts as a memory cell. When writing the selected memory cell, the channel current direction is controlled to inject electrons into the tantalum nitride layer on the left and right sides of the memory cell, respectively, so that the 2-bit data can be stored. However, since this NROM memory cell has only a single channel, the second

1263343 14692twf.doc/006 Sub-threshold swing is not easy to reduce. In addition, since the two-dimensional system of such a memory cell is stored in the same layer of nitriding stone, there is electron lateral migration (electr〇n lateral such as the problem of (4); plus the doping of the buried bit line The quality also spreads laterally, so the memory cell and the array size are not easily reduced. Furthermore, since the conventional buried bit line is a heavily doped region formed in a semiconductor substrate, its resistance value has its limit, so the bit line The electrical resistance cannot be lowered, and the component speed is difficult to increase. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a structure of a non-volatile memory unit to solve the problems of the prior art. A structure of a non-volatile memory array is provided, which is based on the structure of the present invention for forwarding memory cells. The present invention further provides a method for fabricating a non-volatile memory unit for making the non-volatile matter of the present invention. The present invention is also directed to providing a non-systematic process for making the non-volatile memory array of the present invention. The method of writing, erasing and reading the element. The purpose of the invention is to provide a method for writing, erasing and reading the non-volatile memory array of the present invention. : a semiconductor layer, a charge trapping layer, a gate 盥-copper gate ^ ^ ^ , /, a side gate, and a two source/drain region, wherein the pen-trap layer is located on the semiconductor layer. The middle pole and the side closed pole both span 1263343] 4692 twf.doc/006 The more the semi-conductance m, and the above-mentioned capture layer per-_ and the semiconductor-like coffee. The two sources/not in the semiconductor layer on the outer side of the two-sided pole. A two source/drain contact layer may be included, which is in contact with the two/drain electrodes, respectively, to provide an electrical connection. The non-volatile memory array of the present invention includes a conductor layer that is oriented in the first direction and The plurality of word lines and control lines in the second direction, the plurality of source level polar regions, and the plurality of bit lines that are oriented in the first direction. wherein the word line and the control (four) line are in the word line And the two control lines on both sides are a 3-wire group, and each 3-line group is arranged at intervals, wherein each 3, = white, and each semiconductor a layer and a charge trapping layer spaced apart from each of the semiconductor layers. Each source/drain region is located in a semiconductor layer between each of the 3 lines, wherein the overlapping portion of the -3 line group and a semiconductor layer, the overlapping portion The charge trapping layer and the 'source, the bungee area of the two sub-i--the memory unit. The bit line fish is electrically connected to the source/drain region, and the two-source/no-polar region of the memory cell is separately Optionally, it is connected to two adjacent bit lines. In addition, a plurality of source// and contact layers are further included to contact the respective source/drain regions to provide electrical connection. The non-volatile memory unit of the present invention. The manufacturing method is to form a semiconductor layer on the insulating substrate, and then form a two-source/no-polar region on the semiconductor layer: a charge trapping layer is formed on the semiconductor layer, and then an intermediate pole and a gate are formed. This three gates are located between the two source/drain regions. In addition, the method can further contact/record the contact layer, and the second source-level polar region contacts to provide an electrical connection. Next, the writing method of the above nonvolatile memory array of the present invention is as follows. For the sake of convenience, the two control 1263343, 14692twf.doc/〇〇6 gate line and the two source/dual pole area corresponding to one memory unit in the array are distinguished by left and right 'and the word line corresponds to the second control gate line. The memory cells are distinguished by middle, left and right. Among them, the middle (left, right) memory cell erases the sadness / writes the grief of the beginning of the electric Fort for VtEc / Vtpc (VtEL / VtpL, VtER / VtPR), left and right source / no pole area respectively connected to the left and right Bit lines BLL, BLr. In addition, the voltages applied to the word lines, the left and right control gate lines of the memory cell are Vw, VcGL, and VcGR, the voltage of the semiconductor layer is VB, and the voltages of the bit lines BL1 and BLR are VI and Vr. When writing to the left memory cell of the selected memory cell, Vw > Vtpc, VCGR > VtPR, VCGL > VtEI^ is set to turn on the channel under the three gates, and Vl > Vr to cause the electrons to flow to the left. Among them, the difference between % and Vr is sufficient to generate channel hot electrons' and VCGL is sufficient to inject hot electrons into the left memory cells. When writing a memory cell, VB, vCGR, vCGL < 〇 v, Vw > VtEC are set, and a source and a polar region are floated. Among them, vw is enough to make electrons in the memory cells. When writing to the right memory cell, Vw > Vtpc, V^pvtpL, VCGR > VtER is set to open the channel under the three gates, and vr > vi to cause the electrons to flow to the right. Among them, the difference between VI and Vr is enough to generate channel hot electrons, and VcGR is enough to inject hot electrons into the right memory cells. > The method for erasing the non-volatile memory array of the invention is such that the selected two-bit line of the unit is floated, and is applied to the word line and the second control side line corresponding to the memory unit. The voltage is applied to the semiconductor layer of the memory cell, and the difference between the positive and negative voltages is sufficient to discharge the electrons in the memory cell. ^... In the reading method of Ben Maoming's non-volatile memory array, when reading the left memory cell of the unit of the k疋, the system is set, 1263343 fH / 006 14692twf.doc / 006 VCGR > VtPR, VtPL >VCGL>VtEL and Vl<Vr, and judge the left memory cell as an erased state or a write state by the magnitude of the current flowing through the memory cell. When reading the memory cell, VCGL>VtPL, VC(}R>VtPR, VtPC>Vw>VtE(: and Vi^Vl are set, and the current flowing through the memory cell to the left or right is judged. The memory cell erases or writes. When reading the right memory cell, Vw>VtPC, VCGL>VtpL, VtPR>VCGR>VtERa Vl>Vr is set, and the right memory is judged by the current flowing through the memory cell. The cell is erased or written. Further, the method for writing, erasing, and reading the non-volatile memory cell of the present invention is similar to the non-volatile memory array of the present invention, wherein the gate voltage vc corresponds to the latter The word line voltage ^^, the left and right gate voltages VL, VR correspond to the latter left and right control gate voltage Vd, and the left and right source/drain regions voltage V Bu Vr corresponds to the latter The voltage Vh Vr of the bit lines BL1 and BLr. The voltage application mode when writing, erasing, and reading the middle, left, and right memory cells can be according to the above corresponding relationship, and the above-described nonvolatile memory array operation method of the present invention The narrative is replaced by x. In the memory unit (or array) of this book, The middle gate (or the word ru, 4)% over half of the body layer 'so can form a channel in the top of the semiconductor layer and in the two sidewall portions. Therefore, the sub-critical swing of the memory cell is reduced. In addition, due to the 2 source / drain There is a distance between the three gate widths, so there is no need to worry about the lateral diffusion of the pusher. Further, in the preferred embodiment, the memory cell of the present invention (or the charge trapping layer of the array) is located at the middle pole. a charge trapping layer under (or a word line) and a second charge trapping layer under the side gate (or control gate), wherein the middle (or word line) is separated by a gap and a side Pole 1263343 14692twf.d〇c/〇〇6 ======:, _ and lateral diffusion == ruler = migration problem can be solved 'so it is beneficial to memory array cutting and then due to the invention of the dragon _ 鳞 采 转 埋 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : , and the operating speed of the component can be improved. It will be more apparent that the preferred embodiments are described below in detail with reference to the accompanying drawings, and are described in detail below. [Embodiment] [Structure and Process of Non-volatile Memory Unit] Month>,,, Figure 1, The top view of the non-volatile Luiyi Yi 7L of the preferred embodiment of the present invention is shown in the accompanying drawings. Please refer to FIG. 2 (A), (B), (c), and 1), respectively, which illustrate the non- A cross-sectional view of the a_a, b_b, c_c, and D-D' sections of the volatile memory unit. As shown in FIGS. 1 and 2, the non-volatile memory unit 1 is disposed on an insulating substrate 100, and basically includes a The semiconductor layer 11A and the charge trapping layers 122 and 132 thereon, the separated gate 130 and the two side gates 140a and 140b, the spacer 135, and the two source/drain regions 116 & and 116b. The insulating substrate 100 is, for example, an insulating layer having a germanium (SOI) substrate on an insulating layer. The semiconductor layer 110 is, for example, a pale P-doped polycrystalline layer, and the example 1263343 14692twf.doc/006 is long. Strip. The SOI substrate is obtained, for example, by depositing a polycrystalline germanium layer on the surface formation = 曰曰 circle, and its oxygen: base, 峨 韵 被 被 被 被 被 被 被 被 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 122 is, for example, a tantalum oxide-niobium nitride-yttria (0N0) bonding layer. The intermediate pole 130 spans the semiconductor layer η〇 and is separated from the semiconductor layer 11G by () 122 to form a channel in the semiconductor layer 110 and 2 (FIG. 2B), which is a triple channel (four)^

The two source/drain regions 116a and 116b are semiconductors located on the outer side of the two sides, and are, for example, in the top of the semiconductor layer and in the two side wall portions (Fig. 2D). The two source-level polar regions (10) and 116b are respectively configured with two source/drain contact layers 12〇& and port (nine), which are in contact with the two source/drain regions 116a and 116b to provide an electrical connection, and The material is, for example, doped polycrystal 11. The source/secret contact layer /b is, for example, spanned over the semiconductor layer 110, and is spaced apart from the latter by a portion of the hard mask layer 112 that was previously used by the latter, and on both sidewalls of the semiconductor layer n〇 The corresponding source/drain regions 116a/b are in contact. In addition, the portions of the two source/drain regions 116 & and 116b at the sidewalls of the semiconductor layer 11 are, for example, diffused only by the dopants in the source/drain contact layers 120a and 120b, and are located in the semiconductor. The method of forming the portion of the top of layer 110 will be described later. Further, as shown in FIGS. 2(A), (B), and (D), the middle gate 130 is, for example, a hard mask layer 128 which is used for definition, and the source/drain contact layers 120a and 120b are provided. For example, the hard mask layer 118c3 used for the definition is provided, for example, a sidewall formed on the charge trap layer 122, the middle gate 13A and the 11 1263343 14692twf.doc/006 hard mask layer 128, and the source/ The drain contact layer 12A/12〇b and the sidewall of the hard mask layer 118 are formed on the sidewall of the semiconductor layer 11 which is not covered by the gate electrode 130 and the source/drain contact layer 120a/120b. on. The charge trap layer 132 is formed over the above members, for example, so as to be spaced apart from the charge trap layer 122 by the spacers 135 (FIG. 2(A)), and also with the sidewalls of the semiconductor layer 110. Walls 135 are separated, as shown! , 2(c) _ is shown. The side gates 14〇a/b are filled in the middle gate 13〇 (or plus the hard mask layer 128) and the source/dead contact layer i20a/b (or plus the hard cover 1 (8) •• (4) The charge layer (4) b is separated from the half (four) layer by 2 (a)), and is separated from the side of the semiconductor layer by the charge trap layer 132 and the spacer 135, as shown in Fig. 2(c). Therefore, the channels of the memory cells 17〇a/17〇b formed by the side gates 14A/b and the charge trapping layers 132a/b thereunder are formed only on the top of the semiconductor layer 110. In the non-volatile memory unit 10 of the preferred embodiment, the middle gate 130 and the underlying charge trapping layer 122 constitute a memory cell 160 which is separated by a spacer 135 and a two-sided gate 14 and 14% thereof. The lower charge trapping layer 132 & • is separated from the 13 沘. Due to the barrier of the spacers 135, the bits stored in the cells and the _ do not have the problem of lateral migration of the conventional electrons. The method of writing to the memory cells 160 and 170a/b will be described later. [Structure of Non-volatile Memory Array]. Cup Photo® 3, which shows a layout of a non-volatile memory array of the embodiment of the present invention. Referring also to Figure 4, there is shown a circuit diagram of the upper half of the non-volatile memory array of Figure 3. 12 1263343 14692twf.doc/006 As shown in FIGS. 3 and 4, the non-volatile memory array includes a q-direction parallel strip-shaped semiconductor layer 310, a longitudinal parallel word line 33〇 and a control gate line 340a/b, A plurality of source/drain regions 316 (FIG. 4), and lateral parallel bits 350, wherein source/drain regions 316 are not depicted in FIG. 3 to simplify the drawing. The sub-line 330 and the control gate 34〇a/b are connected by a word line 330 and two control lines on both sides thereof are a -3 line group 345, and each of the three line groups 345 are arranged at intervals. Each of the 3-wire groups 345 spans each of the semiconductor layers 31, and is separated from the respective semiconductor layers 31 by a charge trapping layer (not shown). Here, the partial structure of the 3-wire group 345 across the semiconductor layer 310 and the charge trap layer can be similar, for example, as shown in Figs. Further, the parallel strip-shaped semiconductor layers 310 may be, for example, four units, and the cells of the semiconductor layer 3 are electrically connected to each other, and connected to the voltage supply circuit by the contact window 3 = . Please continue to see Figures 3 and 4, and at the same time, compare the graphs, 2, the source layer 316 is located between each of the 3-wire groups 345, and the semiconductor layer overlaps with a semiconductor layer 31, yang, fruit, And ^ ^ ^ The charge trap 1 of the heavy part and the two source/secret area 316 on both sides constitute a memory cell paste. The bit element, the spring 35 〇 is electrically connected to the source/no-pole region, wherein the - source/drain region 316 of the memory cell is electrically connected to the adjacent two horizontal memory cells 360, for example, for the mound. - Fan, Spring, but the phase is 疋 /, with - bit line 35 〇. In addition, the memory array is more sinister 320a/b, which is located at the n^s solid source/no-polar contact layer of each 3-wire group 345 to provide an electrical connection. Among them, as in the picture ^ each secret pole area 316 source / 汲 赖 偷 偷 ( ( 四 四 四 四 , , , , , 偶 偶 ' ' ' ' 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 奇 源 源 源 源 源 源006 320b are mutually opposite: 3 and 3 are different from each other in the two columns: only one source/dual contact layer 32_ is simultaneously in contact with: the mouth: the same side of the unit 360 - For the source/drain region 3 6, for example, the contact window is still connected to a single bit line 35〇. The material of the other 35G is preferably a low-resistance metal such as copper to increase the speed of the element. v 加士2图^ 'In this layout, one memory unit 360 is shared with the 3-phase (four) memory unit 36〇_contact window, and unit 360 shares another contact window, so i memory unit 3 "^/4 +1嗣_contact window. Since the above-mentioned memory cells can store all the materials, the conversion of one contact window corresponds to 6 bits, and the space utilization efficiency is very high. [Non-volatile memory system] < The first example > u is referred to the figure from ~5E 'the scale of the invention is difficult to implement an example of a non-volatile memory process. Please refer to item 5A, first form the first on the insulating substrate 5〇〇 The direction parallel parallel strip-shaped semiconductor layer 510 is made of, for example, doped clutter, and is formed by using a hard mask layer 512 such as a hafnium oxide layer. The method of forming the semiconductor layer 510 is, for example, provided by a s〇I substrate formed of a polycrystalline ruthenium layer having an insulating surface layer deposited on the insulating surface layer, and then patterned into a semiconductor layer 51 by lithography. Ion implantation, through the hard mask layer 512 and on the semiconductor layer 51〇14 1263343 14692 The source/drain regions 51 are formed in the top of twf.doc/006, such as 51 牝. Please look at Figure 5B, then form a source/drain contact layer 52 and 520b across the semiconductor layer 51, the source and source. The / drain regions 514a are in contact with 514b, and the material is, for example, doped with a single crystallite, and is defined, for example, by using a hard mask layer 522, thereby forming stacked structures 523a and 523b (= 520a/b+522). Since the source drain contact layer 52A/b is in direct contact with the sidewall of the semiconductor layer 510, the dopant in the former can diffuse into the sidewall of the semiconductor layer 510 in subsequent thermal processes, so that the source/drain region The range extends to the semi-conductor • the sidewall portion of the bulk layer 510 (covered by 52〇a/b, so it is not edged out), at which point the source/drain contact layer 52〇a/b is corresponding to the source/drain The regions are in contact on both sidewalls of the semiconductor layer 51. Next, the hard mask layer 512 exposed to the source/drain contact layer 520a/b is removed. In Figure 5B, the source/drain contact layer 52〇b Contacting the two source/drain regions on the same side of the two semiconductor layers M0; the source/dipole contact layer & two, respectively, in contact with the two source/drain regions on the other side, and The source/drain contact layer 520a is further in contact with a source/n-f region of the adjacent semiconductor layer (not edged out). As shown by the source-level contact layer 520b, The spacing between the adjacent two source/drain contact layers in the first direction (take 520a as an example) is smaller than the distance between the two semiconductor layers, which will be described later. Please refer to FIG. A charge trapping layer 526 is formed over the substrate (this is not fully illustrated), which is, for example, a muse composite layer, and then forms a strike between the two rows of source/drain contact layers 520a and 52B. A character line 53q composed of a conductor such as a complex (four) or the like may be formed using a hard mask layer 532 to form a stacked structure 533. Next, the charge trap layer 526 which is not covered by the word line 530 is removed, and the structure of Fig. 5 is obtained. Referring to FIG. 5D, a spacer 537 is formed on the sidewall of the stacked structure 523a, the sidewalls of the stacked structure 533 and the charge trapping layer 526, and the sidewalls of the semiconductor layer 51 that are not covered by the stacked structures 523a/b and 533. The method is, for example, to deposit a substantially conformal insulating layer, such as an oxide or a nitride, and then anisotropically etch. At this time, the spacing of the adjacent two source/drain contact layers in the second direction (in the case of 52 〇 a as an example) is sufficiently small that the gap between the two can be in the insulating layer deposition step of the spacer 537 process. Filled with this insulating material. The control lines thus formed can be isolated from each other without having to be separated by patterning. . The monthly record, FIG. 5E', then forms another charge-trapping layer 539 on the substrate, which covers, for example, all the component words (or stacked structures 533) formed by the previous steps and the fourth direction (four), the layer 520a/b (or the stacked structures 523a/b) are filled with a V-body layer such as a polycrystalline stone to form a control line which spans 1 〇 and is separated from the top of the semiconductor layer 510 by the charge trap layer 539. However, since the side wall of the control layer _ 54_ and the semiconductor layer 51 () J5r , is formed only on the top. ^The next step of the shield is to remove the hard mask Mashan 522 and =5=Saki 5 is a cut-off butterfly _, in the word, the spring melon into the upper layer, etc., due to familiar with this artist Should be 16

1263343 l4692twf.d〇c/〇〇6 These steps can be inferred on their own, so they are not here. <Second Example> Figs. 6A to 6D illustrate a first half process of another example of the non-volatile memory process of the preferred embodiment of the present invention. Fig. 6A, in this example, after a layer of semiconductor material 6l〇a is formed on the insulating substrate 6(10), a mask layer 2' is formed on the semiconductor material_, and a strip is formed after the direction is the second direction (10). The semiconductor layer is formed by a trench 6〇4 that is oriented in the first direction, exposing a portion of the semiconductor material 610a that is intended to form a source/drain region. Next, an elongated doped region 614 is formed in the semiconductor material 61Ga exposed by the trench 6G4, for example, by ion implantation. Please refer to item 6B, and then remove the mask layer pass, and then define the hard mask 2 and the semiconductor material 61Ga continuously in the m-direction of the semiconductor material covering * hard mask layer to form a parallel strip-shaped semiconductor layer 'at the same time The elongated doped region 614 is divided into a plurality of source/drain regions 614a and 614b. The correction layer 6C' then removes the hard mask layer 612 and forms a charge trapping layer 626 on the surface of the substrate 6. In the charge trapping layer 626, the second patterned mask layer 606 is, for example, a patterned photoresist layer, and the first direction trench 608 exposes a portion of the semiconductor layer where the source/drain regions 014a/b are located. Charge trapping layer 626. Next, the exposed charge trapping layer 626 in the trench _ is removed to expose the source regions 614a and 614b. The pattern 6D is removed, and then the mask layer 6〇6 is removed, and at the same time a character 17 1263343 14692twf.doc/0〇6 line 530 is connected to the source/drain contact layer 52〇a/b. Since the charge trapping layer 626 of the source/drain region η tantalum strip has been removed in the previous step, the source/drain contact layer 520a/b can be in contact with the source/; and the polar regions 6i4a/b. Of course, as in the case of the first example, the dopant in the source/drain contact layer 52〇a/b in the second example can still diffuse into the semiconductor layer 610 in a subsequent thermal process, and the source/diode region The range of 614a/b extends to both side wall portions of the semiconductor layer 61〇. The subsequent steps are, for example, to remove the charge trapping layer 610 that is not covered by the word line 530 to obtain the structure of FIG. 5C, and the subsequent steps can be, for example, the two examples.

[Operation of Non-volatile Memory Array I] Fig. 7 is a top view of a non-volatile memory of a preferred embodiment of the present invention for explaining the operation of the non-volatile memory. Please refer to FIG. 7. If the selected memory cell 700 is to be operated, the voltage must be applied to the corresponding 530, the corresponding control gate 54 plus 54〇b and the corresponding semiconductor layer $(7), and at the same time A voltage is applied or floated on the two bit lines of the source/drain contact layer 52^ and 520b. For the convenience of description, the two control gates corresponding to the memory unit 7〇〇 and the two source regions (in the corresponding 520a and the subordinate semiconductor layer, so the edge is not) are left. (L) Right (R) distinction, and adjacent two-dimensional lines electrically connected to the left and right source/drain regions are also distinguished by left and right! ^ and 81^). At the same time, the charge trapping layers 539a and 53% under the control lines 540a and 540b (the two memory cells not shown in the memory cell are also distinguished by left and right, called left and right memory cells, and captured by the charge under the word line 530. The memory cell of layer 526 (not shown) is a memory cell. 18 1263343 14692twf.doc/006 is called a medium memory cell. In addition, hereinafter, on the corresponding character line 53〇, left-handed and right control gate line 5働The applied voltage is Vw, %: Erquan 5,: the voltage applied to the corresponding semiconductor layer 51G is Vb, and correspondingly: the voltages on BL1 and BLR are V1 and Vr respectively. Furthermore, the erased state of the cell/ The write state start voltage is v / VWVtPR) 〇Bc/VtPC (VtEL/VtPL ^

Further, the auxiliary patterns 8Am 10A to 10C described in the following operation methods are the AA of the structure of Fig. 7, a schematic sectional view in which the source on the curtain layer, the spacer, and the source/drain region 514a/b is omitted/ Bungee contacts eight to simplify the drawing. Oh,. Knife <Write Operation> Referring to Figures 8A, 8B, and 8C, the method for writing the above-mentioned middle, right, and left memory cells is shown, respectively, which captures the charge of the middle, right, and left cells respectively. The labels 526, 53%, and 539a of the layers are used as the codes for the middle, right, and cell. work. The heart has been set to VB, VCGR, VCGL <0V, Vw»VtEC and the two source/drain regions 514a/b are floated when writing to the memory cells of the selected memory cell, as shown in FIG. Vw is high enough that electrons can be injected into the memory cell 526 by the Fowler-Nordheim tunneling effect. When such a writing mechanism is used, the 1-bit data can be stored in the middle memory cell 526. Next, as shown in Fig. 8B, channel hot electron injection (Channel Electron) can be employed when writing to the right memory cell 539b of the selected memory cell.

Injection, CHEI) mechanism, which sets Vw>VtPC, VCGL>VtPL, 19 VCGR"VtER, νΒ: 〇ν and Vr>V:l, where V1 can be 〇v, and Vr is less than or equal to VCGr (〇V<VrSVCGR ). Since the gate voltages of the middle and left memory cells 526 and 53% are set to Vw > VtPC and VCGL > VtPL, the channels that are written to the middle, left, and right cells 526 and 539a will be opened regardless of whether they are previously or not; Due to the gate voltage VcGR»VtER of the right memory cell 539b, the channel of the right memory cell 539b is also turned on, and a continuous channel is generated between the left and right source/drain regions 514a and 514b. At the same time, due to Vr > Vl, the electrons in the channel flow to the right. The difference between VI and Vr must be large enough to generate enough power to generate hot electrons in the channel under right memory cell 539b; and VCGR must be high enough to allow some of the hot electron tunneling into right memory cell 539b. . As shown in FIG. 8C, when writing to the left memory cell 539a of the selected memory cell, a channel hot electron injection mechanism can also be used, which is set to ¥%>¥4〇:, VcGR>VtpR, VcGL>〉VtEL, Vb = OV and Vl > Vr ' where Vr can be OV and VI is less than or equal to VCGL (〇V<VKVCGL). Since the gate voltages of the middle and right memory cells 526 and 539b are set to Vw > VtPC and VCGR > VtPR, 526 and 53% of the channels of the middle and right memory cells are turned on regardless of whether they have been written before or not; The voltage of cell 539a is VCGL»VtEL, so the channel of left memory cell 539a will also open, and a continuous channel will be created between left and right source/drain regions 514a and 514b. At the same time, due to Vl > Vr, the electrons in the channel flow to the left. The difference between VI and Vr must be large enough to generate sufficient power to generate hot electrons in the channel of left memory cell 539a; and VCGL must be high enough to allow some of the hot electrons to tunnel into left memory cell 539a. 20 1263343 14692twf.doc/006 <Erasing Operation> The lenses are shown in Figures 9A to 9B, which illustrate a method of erasing non-volatile memory according to a preferred embodiment of the present invention, wherein Figure 9B shows a wipe. A method other than the entire block. As shown in FIG. 9A, in this example, three memory cells 539a, 526 and 539b of the selected memory cell are simultaneously erased by floating the source/drain regions 514a and 514b (bit lines BL1 and BLr). And it is set that Vcgl, Vw and Vcgr are much smaller than GV', and Vb is set to be much larger than Gv, and the electrons in the three memory cells 539a, 526 and 53% are simultaneously discharged. μ again, as shown in FIG. 9B, if you want to erase the memory block of the entire block at a time, all the bit lines coupled to the memory cells can be floated, and all the word lines corresponding to the block are 33〇 and all control idle lines 340a and 3^〇b apply a voltage much lower than 〇v, while applying a voltage much higher than 0V on all corresponding strip-shaped half V bodies 1 310 to induce aFN tunneling effect At the same time, the electrons stored in all the memory cells in the block are discharged. <Reading Operation> π Referring to Figs. 10A, 10B, and 10C, the reading methods of the above-described middle, right, and left memory cells 526, 539b, and 539a are respectively shown. = as shown in Fig. 10A, in reading the selected memory cell, the memory cell 526 is set to "set VCGL" VtPL, VCGR > VtPR, VtPC > Vw > VtEC, VB 0V and Vr^Vl, and to the left or to the left The amount of current flowing through the memory cell is judged to be in the erased state or the written state. Since the gate voltages VCGL>VtPL and VCGR>VtPR of the left and right memory cells 39a and 539b are not stored, the channels of the left and right memory cells 539a and 539b are turned on 21 1263343 14692twf.doc/006. When the middle -> one, the, the work π to eight and the existence of electrons, Shishi

Vw<VtPC 'So the channel of PASS 526 does not hit the door, and the channel of 539a and the channel cannot be connected; only: the ID of the stream is produced; otherwise, the memory cell 526 is not written without Since the electronic j power is due to Vw > VtEC, the channel of the memory 16526 will be opened: the channels of the right memory cells 539a and 539b are connected, so that the normal channel stream Id can be generated.

In addition, if the memory cell current is to be left, then Vr > vl, the combination may be V1 = 0V and OV <VGVw; if the memory cell current is to be right, Vl > Vr, the combination may be Vr 2V And 0V < V1SVW. As shown in Fig. 10B, when the right memory cell 539b of the selected memory cell is read, Vw > VtPC, VCGL > VtPL, VtpR > VcGR > VtER, VB = OV, and Vl > Vr are set and flow through the memory. The current magnitude of the cell is judged to be erased or written. In this example, the direction of the read current is opposite to the direction of the write current, so it is a reverse reading mode. Since the gate voltages vCGL > VtPL and Vw > VtPC of the left and middle memory cells 539a and 526, the channels of the left and middle memory cells 539a and 526 are opened regardless of the presence or absence of electrons. When the right memory cell 539b has been written and there is electrons, the channel of the right memory cell 539b does not open due to VCGR<VtPR, so that the channels of the left and middle memory cells 539a and 526 cannot be connected to the right source/> The polar region 514b is connected to 'only generates a small current lD; conversely, when 53% of the right memory cell is not written without electrons, the channel of the right memory cell 5 3 9b is opened because Vcgr>VtER ' The channel connecting the middle memory cell 526 and the right source/drain region 514b can thus generate a normal 22 1263343 14692 twf.d〇c/006 channel current ID. In addition, the combination of V:l, Vr(Vl>Vr) may be Vr=z〇v, and 〇V<Vl幺Vcgr 〇 as shown in FIG. 10C, when reading the left memory cell of the selected memory cell Vw > VtPc, VCGR > VtPR, VtpL > vCGL > vtEL, vB = 〇v and Vl < Vr are set, and the left memory cell is judged to be erased or written by the magnitude of the current flowing through the memory cell. Since the gate voltages Vcgr>Vi:pr and vw>VtPC' of the right and middle memory cells 539b and 526, the channels of the right and middle redundant cells 539b and 526 are opened regardless of the presence or absence of electrons. When the left memory cell 539a has been written and there is electrons, the channel of the left blister 539a will not open due to VCGL<VtPL, so that the channels of the right and middle memory cells 53% and 526 cannot be combined with the left source/deep pole. The area 514a is connected, and only a small current ID can be generated; conversely, when the left memory cell 539a is not written without electrons, the channel of the left memory cell 539a is opened and the memory is connected due to vCGL>vtEL. The channel of cell 526 is connected to left source/drain region 514a, thus producing a normal channel current ID. In addition, the example described in this example is still the reverse read mode, and the combination of vl, Vr (vl < Vr) may be vbov, and 0v < VgVa^. [Operation of Nonvolatile Memory Unit] The writing, erasing and reading method of the nonvolatile memory unit of the present invention is similar to the operation of the above nonvolatile memory array of the present invention, and can be referred to Figs. 8A to 8C, 9A and 10A. UK: The three gate structure depicted. In detail, the gate voltage of the memory cell corresponds to the word line voltage Vw of the memory array, and the voltages Vl and Vr of the left and right gates correspond to 1263343 14692twf.doc/006. The latter left and right control gate lines The voltage Vcgl, I, and the left, and the (4) V1 and Vr of the polar region correspond to the bit line of the latter, and bLr = [VI Vr. The application mode for writing, erasing, and reading the towel, left and right memory cells can be replaced by the above description of the method of operating the array of the present invention.仏 Medium: The memory ^ (or array) T is formed by the middle gate (or the spur line) across the charge trapping layer. The channel can be formed at the top of the semiconductor layer and the two (four) portions. _ Therefore, the sub-threshold swing is reduced. In addition, due to the distance of the width of the gates, it is not necessary to carry out the four-quality (four) diffusion of the memory sheet of the preferred embodiment of the present invention as a result of the towel layer (or the material line) under the (four) load layer. 1 Separated from the charge trapping layer under the side gate (or control gate), so avoid the lateral migration problem of electrons with $=NRQM. The size of the memory array can be reduced by the help of the push-to-pole push-to-peak ratio of the diffusion f and the adjacent storage location. White

Furthermore, since the memory array of the present invention does not use a doped buried bit line, it is first doped to form a source/drain region, and then an external bit line is formed. Therefore, the bit line can be made of a low-resistance metal such as copper, so that the resistance can be greatly reduced, and the operating speed of the component can be improved. A. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is to be understood that those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a non-volatile statistic view of a preferred embodiment of the present invention. Fig. 2Α, 2Β, 2C, 2D respectively show the cross-sectional views of the Α-Α', B_B, C_C, and D-D of the non-volatile symmetry unit of Fig. 1, respectively. Heart, early Fig. 3 is a diagram showing the layout of a non-volatile grammar of a preferred embodiment of the present invention. 〜平夕丨J _ Figure 4 shows the upper half of the non-volatile memory array of Figure 3. Circuits shown in Figures 5A to 5E illustrate an example of a non-volatile process in accordance with a preferred embodiment of the present invention. 6A to 6D illustrate the first half of the process of another example of the non-volatile process of the preferred embodiment of the present invention. Figure 7 is a partial top elevational view of a non-volatile memory in accordance with a preferred embodiment of the present invention for illustrating the operation of the non-volatile memory. " • Figs. 8A to 8C illustrate a method of writing a nonvolatile mark in accordance with a preferred embodiment of the present invention. . Figure 9A to 9B illustrate a method of erasing a non-volatile memory in accordance with a preferred embodiment of the present invention, wherein Figure 9A illustrates a method of erasing the entire block at a time. • Figures 10A to 10C illustrate a method of reading a non-volatile memory of a preferred embodiment of the present invention. ° " [Main component symbol description] 10 : Non-volatile memory unit 25 1263343 14692twf.doc / 006 100, 300, 500, 600: Insulating substrate 110, 310, 510, 610: Semiconductor layer _ 112, 512, 612: Hard Mask layer 116a/b, 316, 514a/b, 614a/b: source/drain region '118, 128, 522, 532: hard mask layer 120a/b, 320a/b, 520a/b: source/汲Pole contact layers 122, 132 (a/b), 526, 539 (a/b), 626 · Charge trapping layer 130: Middle gates 135, 537: Clearance walls 140a, 140b: Side gates 160: Medium memory Cells 170a, 170b: side memory cells 310a: connection layers 312, 323 of semiconductor layer 310: contact windows 330, 530: word lines 340a, 340b, 540a, 540b: control gates 345: 3-line group 350: bits Line 360: memory unit 523a/b: stack structure of 520a/b+522 - 533: 530+532 stack structure 602, 606: mask layer 604, 608: trench 610a: semiconductor material 26 1263343 14692twf.doc/006 614 : Long strip doped region 700: selected memory cells AA, B_B, CC, DD,: hatching WL: word line CGL: control gate BL: bit line IF, 2F, 4F: length indication

27

Claims (1)

1263343 14692twf.doc/〇〇6 X. Patent application scope: 1. A non-volatile memory unit comprising: a semiconductor layer; a charge trapping layer on the semiconductor layer; a two-side gate, wherein the three gates span the semiconductor layer and the t-conductor layer with the charge trapping layer = and "r and ϋ" are located in the semiconductor layer outside the two side open electrodes. =:= Around the first item, a ^ ^ ^ - charge trapping layer, located under the secret of the towel; and the charge: 苡:: the capture layer 'is located under the two side gates, and with the third, each of the three The non-volatile memory unit according to Item 2, wherein the spacer is spaced apart from the middle gate, and the second electric is separated from the first charge trapping layer, and includes the non-volatile as described in claim 3 The memory unit, and the second source/toucher are located on the outer side of the i-side gate, and are divided into the non-volatile memory unit of the fifth item of the fifth item, and the layer=the middle layer is connected to the side wall of the layer and Each of the source/drain regions in the half (four) is at the top of the semiconductor layer: sidewall portion; 28 1263343 14692 In twf.doc/006, and each of the source/drain contact layers is in contact with the corresponding source/drain region across the two sidewalls of the bulk layer: the semi-conductor 7. As claimed in the patent application The semiconductor layer has a strip shape, and the direction of the semiconductor layer is earlier than the three closed electrodes, wherein the semiconductor layer is disposed on an insulating layer. In the early element, the non-volatile memory array includes: a plurality of strips a semiconductor layer having a direction of a first direction; a word line of a second direction and a control line of the opening line are spaced apart from each other by 23, and the line of question is a 3-line group, each of which is 3 Each of the semi-conductor/the middle-mother-three-wire group of the line group spans the semiconductor layers, and has a charge trapping layer spaced apart from the body layer; wherein the bungee region is located between the three line groups a semiconductor layer, the overlapping portion of the iiL-I line group and a semiconductor layer, the overlapping portion and the 2 source/drain regions of the capturing layer and the two sides thereof constitute a memory unit; the electrical Ϊ i is the first direction a plurality of bit lines, which are adjacent to the source/no-polar regions, respectively: the two source/drain regions of the unit are respectively electrically connected to the phase strip A non-volatile memory array as described in claim 9 wherein the charge trapping layer comprises: - a first charge trapping layer under each word line; and - a second charge trapping layer, located Each of the control gates is separated from the charge trapping layer of the 29th 1263343 14692twf.doc/006. 11. As described in the patent specification, the non-volatile memory array is described in a 3-wire group. The word line is separated from any of the control gates by a spacer, and the first charge trapping layer is separated from the second charge trap layer by the spacer. 12. The non-volatile memory array of the 11th item of the patent application scope includes: a source/' and a contact layer, located between each of the 3-line groups, and with the source/drain regions Contact, wherein each source/drain contact layer simultaneously contacts the same/source/drain region on the same side of the two memory cells adjacent in the second direction, and is electrically connected to one bit line. The non-volatile memory array of claim 12, wherein the spacer is located further on a sidewall of each source/drain contact layer and each of the semiconductor layers is not associated with the word line The sidewalls covered by the source/drain contact layers. 14. A non-volatile memory array as described in claim 2, wherein each source/drain contact layer is electrically connected to a bit line by a contact window. 15. The non-volatile memory array of claim 12, wherein the mother-source/;:-polar region is in the top portion and the two sidewall portions of the corresponding semiconductor layer, and each source/drainage The contact layer spans the adjacent two semiconductor layers and contacts either of the corresponding two source/drain regions on the corresponding sidewalls of the semiconductor layer. 16. A non-volatile memory array as described in claim 9 of the patent scope 30 1263343 14692 twf.doc/006 column wherein the adjacent two rows of memory cells in the 4th-direction direction share a "slot line. 17. The non-volatile memory array of claim 9, wherein the bit lines are made of metal. 18. A non-volatile memory array as recited in claim 9 wherein three of the strip-shaped semiconductor layers are disposed on an insulating layer. 19. A method of fabricating a non-volatile memory cell, comprising: forming a semiconductor layer on an insulating substrate; forming a 2-source/drain region in the semiconductor layer; and forming a charge trapping layer on the "Hai half body layer And forming a middle and two gates, the 3 gates being located between the 2 source/gt; and the pole regions, wherein each of the pads extends across the semiconductor layer and the semiconductor layer The charge trapping layer is spaced apart. 20. The method of fabricating a non-volatile memory cell according to claim 19, wherein the charge trapping layer comprises a first and a second charge trapping layer, and the second charge trapping layer The step of forming the gate includes: forming the first charge trapping layer on the semiconductor layer; forming the middle gate across the semiconductor layer; removing a portion of the first charge trapping layer not covered by the 4 doped dopant; to. a gate in the middle of the sea and a sidewall of the first charge trap layer and a sidewall of the semiconductor layer not covered by the gate; forming the second charge trapping layer on the "Half' body layer And forming the two side gates on both sides of the middle gate, and the two side gates are spaced apart from the gate of the middle 31 1263343 14692twf.doc/006. 21. The method of fabricating a non-volatile memory cell according to claim 19, further comprising forming a source/drain contact layer on the insulating substrate, which is in contact with the 2 source/drain regions, respectively. 22. The non-volatile manufacturing method according to claim 21, wherein the semiconductor layer is elongated and has - the u charge trapping layer comprises first and second charge trapping layers formed successively, and « The forming process of the first half of the body layer, the 5th hole 2 source/drain region, the first charge trapping layer, the middle electrode and the 2 source/drain contact layer comprises: forming a layer of semiconductor material on the insulating substrate; Forming a strip of the second doped region from the layer of semiconductor material, a second direction; 〃 defining the layer of semiconductor material to form the semiconductor layer, such that a long doped region is defined as a source/drain Forming the first-charge trapping layer on the "Her semiconductor layer; removing the portion of the semiconductor source; and; and the portion of the semiconductor region where the polar region is located; and forming the middle portion from The gate is in contact with the 2 source/drain electrodes. The source/drain contact layer of the non-volatile memory cell described in item 21 is formed after the source/drain region and before the gate and the two gates.制 申 4 4 4 4 4 ^ ^ 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 你 你 你 你 你 你 你 你 你 你 你 你 你Corresponding to the source/drain region range 32 1263343 14692twf.doc/006 due to the source/drain contact layer sidewall. The step S of the non-volatile memory unit described in Item 23 of the third embodiment includes the 3 μ-di, the second charge trapping layer and the 3 gate. Polar formation a first charge trapping layer after the formation of the 2 source/drain contact layer; forming the middle gate of the semiconductor layer on the semiconductor layer; removing a portion not covered by the middle gate a first charge trapping layer; the sidewall of the first gate/charge trapping layer, the sidewall of the 2 source/drain, the sidewall of the germanium layer, and the layer of the poem conductor are not covered by the pad and the 2 The sidewalls covered by the source/pole contact layer form a spacer; (4) forming the second charge trap layer on the semiconductor layer; and forming a gate between the gate and a source/drain contact layer On the same day, the other side interpole is formed between the middle gate and the other source-level contact layer. The method of fabricating a non-volatile memory unit according to claim 25, wherein a hard mask layer is used in forming the 2 source/drain contact layer, and in the formation Use another hard mask layer for the gate. A method for writing a non-volatile memory unit, comprising: providing a non-volatile memory unit as described in claim 1 wherein the middle gate corresponds to a middle memory cell, and the two side gates are extremely left/ A right gate corresponds to a left 7-right memory cell, and the 2 source/drain regions are a left/right source/pole region, wherein one of the middle (left and right) memory cells is erased/written State start 33 1263343 14692twf.doc/006 The voltage is VtEc/Vtpc (VtEL/VtpL, VtER/VtPR), written to the left memory cell (the voltage applied to the middle/left/right gate is Vc/Vj/Vr, The voltage of the left/right source/no-polar region is Vl/Vr, and the voltage applied to the semiconductor layer is vB), including: setting vc>vtpc, vR>vtpR, VL>VtEd Vl>Vr, Wherein the difference between VI and Vr is sufficient to generate channel hot electrons, and VL is sufficient to inject into the left memory cell; writing the § memory, including: setting vB, vl, vr < 〇 v and vc > vtEC, Floating the two source/: and polar regions, wherein vc is sufficient for electron tunneling to be injected into the memory cell; and writing the right 6 cells 'includes. Setting Vc>vtpC, \^>Vt p, VR > VtERX Vr > Vl, wherein the difference between V1 and Vr is sufficient to generate 'dao=electron' and VR is sufficient to inject hot electrons into the right memory cell. 28. The method for writing a forwarding memory unit as claimed in claim 27, wherein when writing a 6-left cell, the command is Vb=〇v vr=uv OV<VKVL; and writing When the right memory cell is used, let VBK)V, Vl=〇v, 〇v<V]r<v. 29. A method for erasing a non-volatile memory unit, comprising: R providing a non-volatile one as described in claim 1 of the patent application; and causing the 2 source/no-polar region to float; and X-heart early 70, in the A negative voltage is applied to the middle, left and right gates, and a positive voltage is applied thereto, the difference between the positive and negative voltages being sufficient to discharge the germanium electrons. A method for reading a non-volatile memory unit in a capture layer, comprising: 34 1263343 14692 twf.doc/〇〇6 providing a non-volatile memory unit as described in the scope of the patent application, wherein the corresponding - towel memory cell, the 2 side gates are extremely - the left and right gates correspond to a left/right cell, and the 2 source/drain regions are a left/right source/no-polar region, where the middle (left and right) The memory cell-erase/write state start voltage is VtEC/VtPC (VtEL/VtpL, VtER/VtPR); read the left memory cell (the voltage applied to the middle/left/right gate is VC/ VL/VR, the voltage applied to the left/right source/drain region is V1/Vr, and the voltage applied to the semiconductor layer is VB), including: setting Vc>Vtpc, VR>VtpR, VtpL>VL> VtEL and Vl<Vr, and determining, by the magnitude of the current flowing through the memory unit, that the left memory cell is in an erased state or a written state; reading the memory cell includes: setting vL>VtpL, vR>vtpR, VtPC&gt Vc>VtEC and Vi^v and determine the amount of current flowing through the memory unit to the left or right to determine whether the memory cell is erased or written; and read The right memory cell, comprising: setting vc > vtpc, vL > vtpL, VtPR > VR > VtERa Vl > Vr, and to flow through the memory magnitude of the current cell to determine the the right memory cell was erased state or write state. 31. The method of reading a non-volatile memory unit according to claim 3, wherein when reading the left memory cell, the command is vB=ov, νι=ον, and OV<Vr<VL; When taking the right memory cell, let VB=〇V, Vr=OV, and OV<VlSVR; and when reading the memory cell, make VB two ον, and let Vr 2V, 0V<VKVc or Vl =〇V, 〇v<Vr^Vc. 35