TW200701439A - Non-volatile memory and manufacturing method and operating method thereof - Google Patents

Non-volatile memory and manufacturing method and operating method thereof

Info

Publication number
TW200701439A
TW200701439A TW094121376A TW94121376A TW200701439A TW 200701439 A TW200701439 A TW 200701439A TW 094121376 A TW094121376 A TW 094121376A TW 94121376 A TW94121376 A TW 94121376A TW 200701439 A TW200701439 A TW 200701439A
Authority
TW
Taiwan
Prior art keywords
plural
substrate
trenches
volatile memory
gates
Prior art date
Application number
TW094121376A
Other languages
Chinese (zh)
Other versions
TWI271855B (en
Inventor
Pin-Yao Wang
Rex Young
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW94121376A priority Critical patent/TWI271855B/en
Publication of TW200701439A publication Critical patent/TW200701439A/en
Application granted granted Critical
Publication of TWI271855B publication Critical patent/TWI271855B/en

Links

Abstract

A non-volatile memory includes a substrate, plural select gates, plural gate dielectric layers, plural doped regions, plural control gates, and plural charge storage structure. There are plural trenches in the substrate, these trenches are aligned in parallel and extend in a first direction. Plural select gates are located in the substrate and fill these trenches. Plural gate dielectric layers are located between the select gates and the substrate. Plural doped regions are located in the substrate below the trenches. Plural control gates are located above the select gates and aligned in parallel and extend in a second direction. The second direction is across to the first direction. Plural charge storage structures are respectively located between the control gates and the substrate that is among the trenches.
TW94121376A 2005-06-27 2005-06-27 Non-volatile memory and manufacturing method and operating method thereof TWI271855B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94121376A TWI271855B (en) 2005-06-27 2005-06-27 Non-volatile memory and manufacturing method and operating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94121376A TWI271855B (en) 2005-06-27 2005-06-27 Non-volatile memory and manufacturing method and operating method thereof

Publications (2)

Publication Number Publication Date
TW200701439A true TW200701439A (en) 2007-01-01
TWI271855B TWI271855B (en) 2007-01-21

Family

ID=38435337

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94121376A TWI271855B (en) 2005-06-27 2005-06-27 Non-volatile memory and manufacturing method and operating method thereof

Country Status (1)

Country Link
TW (1) TWI271855B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7939451B2 (en) 2007-06-07 2011-05-10 Macronix International Co., Ltd. Method for fabricating a pattern
CN105762150A (en) * 2014-12-03 2016-07-13 力晶科技股份有限公司 Flash memory and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7939451B2 (en) 2007-06-07 2011-05-10 Macronix International Co., Ltd. Method for fabricating a pattern
CN105762150A (en) * 2014-12-03 2016-07-13 力晶科技股份有限公司 Flash memory and manufacturing method thereof
CN105762150B (en) * 2014-12-03 2018-09-11 力晶科技股份有限公司 Flash memory and manufacturing method thereof

Also Published As

Publication number Publication date
TWI271855B (en) 2007-01-21

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees