TWI271807B - Chip embedded package structure and fabrication method thereof - Google Patents
Chip embedded package structure and fabrication method thereof Download PDFInfo
- Publication number
- TWI271807B TWI271807B TW094109709A TW94109709A TWI271807B TW I271807 B TWI271807 B TW I271807B TW 094109709 A TW094109709 A TW 094109709A TW 94109709 A TW94109709 A TW 94109709A TW I271807 B TWI271807 B TW I271807B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- wafer
- opening
- carrier
- semiconductor wafer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 131
- 239000004065 semiconductor Substances 0.000 claims abstract description 80
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 239000012790 adhesive layer Substances 0.000 claims abstract description 17
- 238000009713 electroplating Methods 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims description 8
- 239000011241 protective layer Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 239000011135 tin Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- 239000007788 liquid Substances 0.000 claims 2
- 229920002120 photoresistant polymer Polymers 0.000 claims 2
- 238000007639 printing Methods 0.000 claims 2
- 238000004528 spin coating Methods 0.000 claims 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims 1
- 229910052787 antimony Inorganic materials 0.000 claims 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- 238000002425 crystallisation Methods 0.000 claims 1
- 229910052733 gallium Inorganic materials 0.000 claims 1
- 229910052738 indium Inorganic materials 0.000 claims 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 1
- 238000003475 lamination Methods 0.000 claims 1
- 239000011133 lead Substances 0.000 claims 1
- 229910052749 magnesium Inorganic materials 0.000 claims 1
- 239000011777 magnesium Substances 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 claims 1
- 238000007747 plating Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000007769 metal material Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229920001940 conductive polymer Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 241001272720 Medialuna californiensis Species 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 241000220259 Raphanus Species 0.000 description 1
- 235000006140 Raphanus sativus var sativus Nutrition 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 239000005864 Sulphur Substances 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000002496 gastric effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 125000001741 organic sulfur group Chemical group 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920001197 polyacetylene Polymers 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
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- H01L2924/01—Chemical elements
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- H01L2924/01—Chemical elements
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/15165—Monolayer substrate
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- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electroplating Methods And Accessories (AREA)
Description
1271807 九、發明說明: 【發明所屬之技術領域】 結構及其製法, 固定於承载板内 更詳 之構 本發明係有關於一種半導體構裝 而言之,係有關於一種將半導體晶片 裝結構及其製法 【先前技術】 隨著電子產業的蓬勃發展,電子產品亦朝輕、薄、短、 積度、多功能化方向發展。為滿足半㈣封裝件 尚和木度(Integm臟)以及微型化(Miniaiudzaii叫 需求’半導體晶片之封裝形逐漸由單„晶片之球栅陣列、 ㈣A)封裝或覆晶式(Flip Chip,FC)封裝演進到封裝和 模組化封裝形態,使得封裝之結構產生了不同的面貌例如 SiP(System m Package) ^ SIP(System Integrated Package). SiB(System in Board)等多種形式。 •惟,該些3D及模組化封裝形態係以覆晶技術(fiip chip),或打線技術(wire b〇ndmg)將單一的半導體元件—個 接们的連接至基板表面,亦或以表面黏貼技術(smt)霉占 貼於基板表面。該些元件係全部分佈於基板表面,因而不 利於模組化結構尺寸之縮小及性能的提高。 爲此’遂有業界提出將半導體元件埋入高密度之電略 板之作法。如第1圖所示,係為習知的半導體元件埋入電 路板之構裝結構之剖面示意圖。如圖所示,該構裝結構係 包括承載板1 0,且該承載板i 〇之一表面1 〇〇形成有至少 一開口 100a ;至少一半導體晶片11,且該半導體晶片u 6 18425 1271807 ==有多數電極墊11G,魅置㈣承條ig上且收納 上二職中;線路增層結構12係形成於該承載板10 祖X、泉路立曰層結構12係藉由複數導電盲孔120電性連 接至該半導體晶月η上之電極墊110。 2其雖可解決上述問題’但是將半導體晶片埋入高密 板,因無法控製半導體晶片在電路板中的精度和 誤差值的存在,使該半導體晶片埋人電路板之作 _法存在如下之諸多缺點·· 時,=旦t整合有半導體晶片電路板上進行增層製程 限制;丰型機台的誤差值和增層後各製程的誤差值, 製二t::晶片上電極塾的規格,機台精度和增層後各 之線會造成增層後無法對位精準而造成增層 之、,泉路無法有效對位於晶片電極墊上。 程,:ί在=有效固定半導體晶片就直接進行增層製 曰因在增層後要檢驗半導髀曰 ,造成現場作業之困H 板的對位度, '、 支 而造成產品隱藏性問題增加、良 率降低,使生産成本增加。 良 【發明内容】 鑒於上述習知技術之缺失,本發明之主要 =-種晶片嵌埋式構裝結搆及其製法,以: 效將半導體晶片定位於承載板中,使半導體有 成爲一體,以利於進行後續製程。 s 〃八載板 ::明之再—目的在於提供一種晶片嵌埋式構 及心法,以利用電鑛製程將半導體晶片有效定位於:载 18425 1271807 ,俾可避免習知技術中由於增層製程之成型 =後各製程的誤差值,造成增層之線路無法有:; 位於日日片電極墊上等缺點。 " 本發明之又另一目的A认ω 搆及i制、去,+、—種晶片嵌埋式構裝結 ,板行檢驗半導體晶片於承載板中的對位^ 低。 良率增加、生産成本降 • _ 為達上揭及其他目的,本發 裝結構之製法,係包括··首先提供—具第=讀式構 面之承載板,且該承載板中、及第二表 板弟—衣面形成—黏著 …氧載 動面及相對非主動面心’亚將至少-具主 , u +導體晶片以其非主動面接胃 黏者層上,且容設於該承載板 力面接置於该 定位於該開口中;於該半# 1巾,以將該晶片預先 •層,且對應於該承载板第一二:之::面上形成-保護 一表面、該保護層表面、—側王面於該承载板第 表面與該開口周緣表面形成載=處之黏著層 形成—阻層,以定義出電_/二=於該導電層上 f露出對應於該承載板開口與該半導體\;:开電鍍開口係 中形成預定高度之金屬層成::: 广曰曰片有效固著於承載板開 二以使该 所復盍之導電層與該黏著層。 于…亥阻 本發明亦揭露出該晶 甘入埋式構裝結構之製法另一實 J8425 8 1271807 施態樣,該製法與上述絮 移除,且於該承載板之第處在於··係先將黏著層 面上形成第-增+ β 、 该半導體晶片之非主動 凹上φ成弟—辱電層;於F王動 層,以定義出電鑛開口,且::h層上復形成第二阻 該承載板開口位置;以及進;;電二層之電鑛開口係對應 開口中形成—預定 以於該阻層之電鑛 層逸散半導體晶片運作時 、匕5亥弟二金屬 該第 護層 第二阻層及其所覆蓋之第 該第一、第二阻展β 之熱量。其後再加以移除 第一導電層與該保 透過上述之製程,本發明之S山 實施態樣係包括:具至少^式構裝結構之- 晶片,係容設於該承載板之開口中;7反―至少一半導體 係形成於該承載板開口與該半導體:預二…金屬f 以將該半導體晶片定位於該 主動面上形1=二,處在於該半導體晶片之非 片之散熱件。度之金屬層,可供作為該晶 in口技術’本發明之晶片嵌埋式構裝結構及並 衣法’主要係透過電鑛製程預先在半導體晶片與承载板開 隙間形成金屬層,以將該半導體晶片有效固定於‘ 八反之開口中’因而可在進行後續之增層製程前控制、 檢驗該半導體晶片於該承載板中之對位精度,所以可避免 心成型機台本身存在的誤差值和機台極限’使得該半導 18425 9 1271807 體晶片的結構受到限制。 於承^由本發明係透過電鐘製程將半導體晶片有效定位 成刑::而可不受限於後續的增層製程所需要考量 、,土 .、口的玦差值和增層後各製程的誤差值,從 增層製程之前將半導妒曰 行 、辟备,,, 干¥版日日片扣準固定於承載板中,進而可 精度和各#程的片的"極塾尺寸小於成型機台 線路無法有效對位於半導ρ片之上曰層衣㈣成的增層 牛¥肢日日片之電極墊等問題。 L貝她方式】 以下藉由特定的具體實施例說 熟悉此技蓺之人+ π Α 个知乃之貝方式, 本發明之其他優點及功效。本發明地瞭解 體實施例加以施行^由-他不同的具 於不同的觀點與應用,在 負、,、田即亦可基 修飾與變h 不丨子_本發明之精神下進行各種
> 請參閱第2A圖至第2F 構裝結構之製法第知為本發明之晶片嵌埋式 罘只施例之剖面示意圖。 如第2A圖所示’首先提供— 具有一第一表面200及與該第一本 该承載板20 別,且於該承載板2〇中 弟—表面 開口加。其中,該承載板20係二=弟^第二表面之 熱板,此外,該承載板亦可為βτ樹脂、所裂成之散 樹脂、破璃纖维、聚乙醯 ^ 树月曰、環氧 緣板,亦或為形成有線路結構=寻树月曰材料所製成的絕 、°傅之琶路板。 18425 1271807 . * ^第2B圖所不,於該承載板20之第二表面201形成 著層21以封住該承載板2〇之開口 2〇2,並將至少一 半導體晶片22接置於該黏著層21上且容設於該承載板2〇 開口 2〇2中,從而將該半導體晶片22預先固定於該開口 中”中,6玄半導體晶片22係具有多數電極墊22〇a 220及與該主動面相對之非主動面22卜且該半 、 片2係以其非主動面2 21與該黏著層21接觸並收 φ 、、,内於該承載板20之開口 202中。 成 …亥丰¥月豆日日片22之主動面220形 成一保護層23以保護該半導俨日 带托勒日日片22主動面22〇上之該 甩極2 22〇a。接著於該承載板2 Μ ^ π秋极川之弟一表面200、該保護 —載板開口加處之黏著層21表面、及該 传作形成一導電層24。該導電層叫 二、”、讀金屬材料所需的電流傳導路徑,其可由全 ^或沉積數層金屬層所構成,如選自銅 =成銅Γ金編合金等所構成之群組之其中-者所組成’或可使用例如聚乙炔 、甲 等導電高分子材胃+ ^本胺或有機硫聚合物 刀卞材科以作為該導電層24 〇 如第2D圖所示,於該導電層24 進行圖案化製程,以使該阻層25形成二成—阻層25’並 出部分之導電層24。該阻層25可為:口 250 ’以外露 式形成於料電層24表面,再藉由絲合等方 圖案化,而形成有欲電鍍開口 25〇 广寺方式加以 5玄.250位置係顯 18425 11 1271807 露出相對應該承载板20開口 2〇2 成之間隙位置。 千^日日片22_ 如第2E圖所示,再對該承載板2〇進行電鍍 ecti〇p〗atlng)製程,藉由該 ^ ^ ^ ^ 進行電鑛時可作為電、、,值塞玫"寸性,俾在 中^〇 導路徑,以在該欲電鐘開口 250 电、又/成預疋尚度之第一金屬層26。 :村:可―錫、銀、銅、金一銻= :之經驗-者。惟,依_ 兮今麗“幻為成4之电鍍材料且成本較低,因此, 由二二:由電鑛銅所構成者為較佳,但非以此為限。 片22所形成於該承載板開口 202與該半導體晶 定於承載板,將得以有效使該半導體晶片22固 、取戰扳20中。另外,兮厶鏖 Μ ^ , 〜w蜀s 26之南度可依實際製 而求加以調整而非以本圖式為限。 、、 如第2F圖所不,復可移除該黏著層21、阻芦% 甘 所覆蓋之導電層24、以及 日21阻層25與其 導髀曰κ 99 、 呆。又層23,以便將該固定有半 ' 之承載板20提供給後續之萝浐佶ra "丨;、祍 線路增層製程),以完成該半 片::使用(例如進行 導接。 干日日片之封裝與向外之電性 由於本發明中係可形成具預定古 係填充於該承載板開口2〇2^二^之金屬層26,且其 中,故可將半導體晶片22精準+二;;片22所形成之間陳 而楫右对、隹一 V 早疋位方U亥承載板20中,進 、有效進仃例如增層製程之後續製程。 如圖所示,應用上述之製法所得之本發明之晶片嵌埋 18425 ]2 1271807 式構裝結構係包括·承葡知9 A 2^ , ^ a 冰載板20、至少—半導體晶片22、導 電層24、以及具預定古译 μ 等 、回又之弟一金屬層26。其中,該永哉 板20係具有第一表面2〇〇及與該 ”欣σ 201,且該承載板% JL # 乂 目對之第二表面 ml: 有貫穿其第-、第二表面之開口 02’该+ ¥肢晶片22係容設於該開口 24係形成於該承載板 ^ 〜層 & U2表面及該開口 202周绫# 面;而該金屬層26係形成於該導電層24上,且埴二: 承載板m202與該半導體晶片22所形成之間^ 二:二1:422有效、精準的定位於該承載板2。中, 以利進仃後、,.員之例如線路增層等製程。 。月’閱第3A圖至第31圖’係為本 構綱之製法第二實施例之剖面示意圖。以-埋式 如弟3A圖所不,首务蔣极 &古一笛一主 先棱(、—承载板30,該承載板30 /、有#表面300及與該第一表面相對之第二表面 二^於=载板30中形成有貫穿其第一、第二表面之 u 該承载板3G係可為金屬材料所製成之散 … 為騎板,亦或為形成有線路結構之電路板。 =3β圖所示,於該承載板3〇之第二表面301形成 一黏者層31以封住該承載板30之開口 302,並將至少一 半導體晶片3 2接置於★玄为;基思 接置方…亥黏者層31上且容設於該承載板3〇 之開〇2中,從而將該半導體晶片㈣固於該開口地 中°其中,該半導體晶片32係具有多數電極塾通之主 動面320及與該主動面相對之非主動面32卜且該半導體 晶片d係以其非主動自功接置於該黏著層^上並收納 J8425 13 1271807 於5亥承載板3 〇之開口 3 〇2中。 如第3C圖所示,於該半導體 成一保護層33,以保護該半導體晶片3ΐ φ之叙主動面320形 該電極墊320a。接著於該承載板 ® .上之 護層33表面、該承哉妃μ ^弟—表面300、該保 玄承载板開口 302處之黏著 该開口 302周緣表面上形成一導電』者層31表面、及 要係作為後續電鍍金屬材料所需的:。该導電層Μ主 子材料。積數層金屬層所構成,亦可使用導電高分 如第3D圖所示,於該導電層34 於該阻層35中形成欲電鐘開口 35〇,二成二阻層”,並 係顯露出相對應該承载板3〇開 ;:电鍍開口 350 所形成之間隙位置。 人该半導體晶片32 了斤示,對該承载板3〇進行電物,藉由 。亥弟- ¥電層34具導電特性,俾 “錯由 傳導路徑,以在該欲電鑛開口 35〇中寺可作為電流 第一今Μ尽以社丄 鍍形成預定高度之 乐孟屬層36。其中該金屬層刊之 以 成者為較佳,但非以此為限。該金…4 =鍍銅所構 板開口 302與該半導體晶 二“成於該承载 導俨曰片M足間隙中,以有效將該半 ^版日日片32疋位於該承載板3〇中。該 依實際製程需求加以調整,而非以本圖式為^ 之第如示,移除該黏著層31,並於該承載板3。 =:^301及該半導體晶片32之非主動面321形成第 該導電層37主要係作為後續電錢金屬材料 18425 ]4 1271807 所需的電流傳導路徑,其 層所構成,或為導電高分子材料蜀δ孟或沉積教層金屬 如弟3G圖所示,接著於該導電層^ 38’亚進行圖案化製程,以使該阻層卿成有二:: 380,該欲電鍍開口 有人电鍍開口 口 302位置。3㈣形成於相對應該承載板30之開 騎示,㈣該承餘3_ 由该導電層37且導命4 士从伯上 衣枉稭 導路徑,以在俾在進行電鑛時可作為電流傳 二八严乂 電鑛開口 380上電鑛形成預定高度之第 一孟萄層39,其中,該第二金屬層39 於(圖未示)车道雕 積係可大於或小 面产。另、夕 片之面積’較佳係大於半導體晶月之 面^另外,對應於形成在該承載板開口 3〇2令 3 6亦可在此次之雷雄制 ^ m m 中持續生成,惟若該金屬層36 方;无刖電鍍製程中ρ ;查 古 μ 才甲已達預疋南度時,係可在該金屬層36 上復皿一阻層以防止i牲矣 万止〃、持‘生成。该金屬層39之材料可為 : 錫、銀、銅、金、叙、銻、鋅、錄、錯、鎂、銦、 碲以及鎵等金屬之1中一 中者。惟,依貫際操作之經驗,由 、·’5 ’、、、无、之電鍍材料且成本較低,因此,該金屬層39 以由電,所構成者為較佳,但非以此為限。 、胃二圖所示,之後即可移除該阻層3 5及其所覆蓋 之534、該阻層38及其所覆蓋之導電層37、以及該 半t二B曰片32主動面上之該保護層33,以便將該固定有 半V 日日片_32之承载板3〇提供給後續之製程使用(例如進 行線路增層製程),以完成該半導體晶片之封裝與向外之電 15 18425 1271807 性導接。 ’ *於本發明中係於該承載板30開〇3〇2與半導體晶片 32間之間隙中形成具預定高度之金屬層%,故可將半導體 晶片32先行精準定位於該承载板3",俾利於進行例如 - 增層製程之後續製程。 >圖所示’應用上述製法所得之本發明之晶片歲埋式 構裝結構’係包括:承載板3G、至少—半導體晶片Μ、導 •電層34、以及具預定高度之第一金屬層%、導電層”、 以及骸高度之第二金屬層39。其中,該承載板%,係且 有第-表面300及與該第一表面相對之第二表面3〇1,且 該承載板30具有貫穿其第―、第二表面之開口鼠該半 導體晶Θ 32係具有主動面32〇及相對之非主動面321,其 係容設於該開口 302中,且該半導體晶片32之主動面⑽ -有夕數电極墊320a ;該導電層34係形成於該承載板開 口 302處表面及該該開口搬周緣表面;而該金屬層% _係形成於該金屬層34上,而填充於該承載板3〇開口 3〇2 入λ半^月且日日片3 2所形成之間隙中,以將該半導體曰 32有效、精準的定位於該承載板30中,以利進行彳^之 路增層等半導體製程;言玄導電,37,係形成於該半 導體晶片32之非主動面321上;該第二金屬層39,係形 ^該導電層37上;其中該第二金屬層39之面積係可大 於或小於(圖未示)半導體晶片之面積,較佳係大於半導體 晶片之面積。 相較於習知技術,本發明之晶片嵌埋式構裝結構及其 18425 16 1271807 製法’主要係透過電參制 .。之間隙間形成金屬;體晶片與承載板開 .制、檢驗該4體==後續之增層製程前有效控 十版曰曰片於该承載板中之對位精 避免由於成型機台本身存在 斤义可 a p . 存在的決差值和機台極限使得該半 月旦日日片的結構受到限制。 同訏,本發明係透過電鑛製程 k於承載板中,因而可不夸阳於仏〆a 日乃有效疋位 1成型機1 ^佶; 增層製程所需要考量 支枝。的^值和增層後各製程的誤差值, 名知技術中當半導俨S 了 3免 和夂f程㈣塾尺寸小於成型機台精度 i法有㈣㈣^ 後續增層M程形成的增層線路 '、,、法有效對位於丰導體晶片之電極墊等問題。 上述實施例僅為例示性說明本發明之原理及其功效, 〜限製本發明。任何熟習此項技藝之人士均可在不 =本發明之精神及範訂,對上述實施例進行修改 【圖式簡單説明】 後这之申4利乾圍所列。 意圖第1圖係為習知整合有半導體晶片之封裝結構剖面示 之係為本發明之罐埋式構裝結構 心衣法罘一貝鉍例之剖面示意圖;以及 制、圖至第31係為本發明之晶片嵌埋式構装結構之 衣法弟二貫施例之剖面示意圖。 【主要元件符號說明】 18425 17 1271807 10 、 20 、 30 承載板 11、22、32 晶片 12 線路增層結構 100 表面 100a 開口 110、220a、320a 電極墊 200 、 300 第一表面 201 、 301 第二表面 202 > 302 開口 220 、 320 主動面 221 、 321 非主動面 21、31 黏著層 23、33 保護層 24 、 34 、 37 導電層 25 、 35 、 38 阻層 250 、 350 、 380 電鍍開口 26 、 36 、 39 金屬層 18 18425
Claims (1)
1271807 十、申請專利範圍: • h 一種晶片嵌埋式構裝結構之製法,係包括: 、提供一具第一表面及第二表面之承載板,且於該承 _ 載板中形成至少一貫穿的開口; 、於°亥承載板之第二表面形成一黏著層,以封住該承 載板開口之一侧; 將至少一半導體晶片接置於該黏著層上且容設於 # =載板之開Π中,其中,該半導體晶片具有—主動面 〃 °亥主動面相對應之非主動面,該半導體晶片係以其 g主動面接置於該黏著層上; ^ ^ ϋ亥半^體晶片之主動面形成一保護層; 承載板第—表面、該保護層表面、及對應該承 —、首:口處之料層表面與該開口周緣表面形成一第
2.
口,該於:玄二—導電層上形成第一阻層,並定義出電鑛 ㈣係承載㈣口與該半導體晶 =電鑛製程以於該電賴口中形成預定高度之 於該承開?該第一金屬層將該半導體晶化 法申:::範圍第1項之晶片嵌埋式構裝結構之製 移除該第—阻層及其所覆蓋之第-導電 曰μ‘著層及該保護層。 、 專利fe圍第1項之晶片嵌埋式構裝結構之製 18425 19 1271807 法’復包括: μ移除該黏著層,並於該半導體晶片非主動面及承載 板第二表面之一侧形成第二導電層; 口於^亥第一導電層上形成第二阻層,並定義出電鍍開 "玄毛鍍開口係對應於該承載板開口位置·,以及 進行電鍍製程以於該電鍍開口中形成第二 4.=請專利範圍第]項之晶片㈣式構裝結構之^層。 :=中’該承載板係為金屬板、絕緣板、及形成有線 …構之電路板之其中一者。 法^專利範圍第1項之晶片嵌埋式構裝結構之製 6 ’,其中,該第一阻層為乾膜及液態光阻之其中一者。 、去^專利範圍第1項之晶片嵌埋式構裝結構之製 L,其中,該第一阻層係利用印刷、旋塗或貼合之χ复中 方式而形成於該導電層上,並藉由曝 ^ 圖案化者。 ,.肩衫而加以 7H專利範㈣1項之晶片嵌埋式構裝結構之製 :,其中’該第-金屬層可選自鉛、錫、銀、銅、金、 組之:中:者鎳、錯、鎂、銦、碲以及鎵金屬所構成群 δ· t申請專利範圍第1項之晶片嵌埋式構裝結構之製 9如申ΪΓ該半導體晶片之主動面具有多數電極墊。 申:專利範圍第3項之晶U埋式構裝結構之製 屌復〃包括:移除該第一阻層及其所覆蓋之第一導電 '、該第二阻層及其所覆蓋之第二導電層、以及該二 18425 20 1271807 層。 10·如申請專利範圍第3項之晶月嵌埋式構裝結構之製 法,其中,該第二阻層為乾膜及液態光阻之其: 11 ·如申請專利範圍第3項之晶片嵌埋式構裝結構之制° 2,其中,該第二阻層係利用印刷、旋塗或點合之衣皮 —方式而形成於該導電層上,並藉由曝 : 圖案化者。 兀.,肩衫而加以 2 π專利|&圍第3項之晶片巍埋式構裝結構之製 心’其中’該第二金屬層可選自錯、錫、銀、銅 ::之:中!者錄、錯、儀、-、蹄以及蘇金屬所構成群 •種晶片嵌埋式構裝結構,係包括: 有至具有第-表面及第二表面,且該承载板具 以及至少一半導體晶片,係容設於該承载板之開口中; 至屬層,係形成於該承載板開口 w形成之間隙中。 干令版日日片 括申範圍第13項之晶片嵌埋式構裝結構,復包 D巧、纟?黾^其係形成於該承載板開口處表面及該開 15 ·如:$表面’而該金屬層係形成於該導電層上。 中5 =專利範圍帛U項之晶片嵌埋式構裝結構,其‘ V承載板係為金屬板、絕緣板、及形成有線路结 I路板之其中一者。 傅 18425 21 1271807 16·如申請專利範圍第丨3項之晶片嵌埋式構裝結構,其 中’該半導體晶片之主動面係具有多數電極墊。 17· —種晶片嵌埋式構裝結搆,係包括: • 一承載板具有第一表面及第二表面,且該承載板具 .有至少一貫穿的開口; 至少一半導體晶片,係容設於該承載板之開口中; 一第一金屬層,係形成於該承載板開口與該半導體 • 晶片所形成之間隙中;以及 第二金屬層’係對應形成於該承載板第二表面侧之 該半導體晶片之非主動面上。 8·如申巧專利範圍第丨7項之晶片嵌埋式構裝結構,復包 括一第一導電層,其係形成於該承載板開口處表面及該 開口周緣表面,而該第一金屬層係形成於該第一導電層 上0 19.如申請專利範圍第π項之晶片叙埋式構裝結構,其 中,该弟二金屬層與該半導體晶片之間復具有一第二 電層。 、 〇·如申印專利範圍第17項之晶片嵌埋式構裝結構,其 中忒,忒承載板係為金屬板、絕緣板、及形成有線路 結構之電路板之其中一者。 利範圍第17項之^嵌埋式構裝結構,其 中°玄第—金屬層之面積係大於半導體晶片之面積。 2·如中請㈣範圍第17項之晶片嵌埋式構裝結構,其 中,該第二金屬層之面積係小於半導體晶片之面積。 18425 22
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US9398694B2 (en) * | 2011-01-18 | 2016-07-19 | Sony Corporation | Method of manufacturing a package for embedding one or more electronic components |
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