TWI270868B - Laser driver and optical disk drive - Google Patents

Abstract

A laser driver and an optical disk drive are provided with a laser part 1, a driving control circuit 2a, a laser driving circuit 3a and a flexible cable 5. The laser part 1 irradiates laser beam to a disk 52. The driving control circuit 2a creates a timing signal S1 for controlling the irradiating timing of the laser beam and a shuttering timing signal M1 for shuttering the timing signal M1 according to an input data. The laser driving circuit 3a calculates the timing signal S1 and the shuttering timing signal M1 and then controls the laser part 1 according to the calculation result. The flexible cable 5 transmits the timing signal S1 and the shuttering timing signal M1 to the laser driving circuit 3a. Even some signal delays are generated, the laser driver and the disc driver can record with high-reliability.

Description

I27〇8'68 -------- V. INSTRUCTION DESCRIPTION------- [Technical Field of the Invention] The present invention relates to an optical disk device, and in particular to a second A laser-controlled garment for controlling the laser for the optical pickup of the optical disk device. [Prior Art] An optical reading circuit in which the laser light irradiated to the optical disk is reflected and the reflected light is read and the reflected light is read is stored therein. d The recording density of the optical disc is increased, and the recording laser light is also developed toward the multi-valued "e 1" and the pulse I adjustment. In order to realize the multi-value leveling and pulse width adjustment of the recording trace t High precision, laser drive power, control of laser light according to timing signal and current setting signal: output daytime and output level. [Time series signal] is the timing to control the output level of laser light change. The current setting signal is used to control the output level of the laser light, and the timing signal is usually transmitted as a parallel data to the laser driving circuit. The composition of the optical disk device can be roughly divided into an optical reading head. And a printed circuit board that controls various circuits of the control system. A known first background technique is to provide a timing control circuit and a laser drive circuit for generating a timing signal in an optical pickup. The second known background art A laser driving circuit is disposed in the optical pickup, and a timing control circuit is disposed on the printed substrate. Because the optical pickup is movable from the inner circumference to the outer circumference or from the outer circumference to the inner circumference. The moving part is connected to the printed circuit board by a flexible cable (c ab 1 e ), which is a flexible cable. In the first background, the timing control circuit is set in optical reading. take

13995pif.ptd Page 8 1270868 V. INSTRUCTIONS (2) In the head, the heat generated by the timing control circuit increases the heat in the optical pickup. Further, in order to save space, the optical pickup of the movable portion is difficult to provide a heat radiation mechanism. As a result, the heat generation of the timing control circuit deteriorates the characteristics of the semiconductor laser element. Furthermore, the power required by the timing control circuit causes an increase in the power consumption of the entire optical pickup. Moreover, the timing control circuit needs to take the preset data for finely adjusting the laser light emission timing and the recording poor material modulated by the modulation circuit as an input signal. Since the preset data and the recorded data after the modulation are transmitted from the flexible cable to the timing control circuit, the number of the number of the visible lines that can be seen is increased, and the weight of the flexible cable is increased, thereby It has a bad influence on the seek performance of the optical pickup. In the second background art, a k-delay is generated when the timing passes through the salvable line. When the delay of the timing signal transmitted in parallel is generated, when the waveform distortion occurs in the laser drive flow, the accuracy of the illumination timing of the laser light is proportional to the decrease in the accuracy of the emission timing of the laser light, and the reliability of the optical disk is Sex will also decrease. In particular, it is necessary to perform high-speed recording. Therefore, what is the need to set the recording speed 2 in the optical pickup? Delay the additional circuitry for the application. In recent years, due to the high density of recording or recording media, the decomposition of the laser-driven power sequence control has been required to reach hundreds [π], thus "heart fine = work! The frequency of the pulse increases, and the delay of the person's month is limited because of the accuracy of the ,, and the reliability of the recording operation of the signal [;:::] is not sufficient. To achieve the above and other objects, the present invention provides a mine. Shooting drive

13995pi f.ptd Page 9 1270868 V. Invention description (3) ------ Two shots, according to the input data, generate control according to:: data, generate masking; letter circuit 'The present invention provides a kind of mine t: % sequence "虎. Road, generate multiple drive currents, for the two: current generation current control electric & 'for control laser: level control, and electrical timing signal to cover the shadow when the second = The timing signal, and the result of the arithmetic processing, from many: to the arithmetic processing, and according to the present invention further provides a laser drive = into;: the drive current. The field is projected to the optical disc, the drive includes the laser , according to the date of the laser output timing;:::: input data, generate = mask timing signal, and laser to the timing signal to cover = day-sequence signal execution - calculus -, for timing signals and control laser According to the result of the calculation processing, the present invention also provides a recording disc from the controller who: from: the modulation circuit, according to the recorded data after modulation, modulation, laser control; Timing of the exit timing "Controlling the laser light to the u, the root signal, and masking the timing = and the sequence signal = the filming of the film according to the processing of the fruit * * masking timing signal to perform a taste _,, mosquitoes, and Disc laser light, disc motor;;;! In order to allow the invention to control the disc motor. The disc is easy to understand, the following is a special introduction to the second A, his purpose, characteristics and excellent At is as follows. "Examples" and in conjunction with the attached „: points are more clearly rounded, for details 13995pif.ptd Page 10 1270868 V. Inventive Note (4) [Embodiment] [First Embodiment] The first aspect of the present invention As shown in FIG. 1, the disc clothing 52 of the driving male disc swearing disc 52 and the driving optical disc 52 includes: a disc motor between the optical controller 65 and the disc motor 51::; : 64 is connected to the laser control device of the controller 65, the connected high frequency UIO amplification number 66, and the signal processing circuit 63 connected to the laser control split l〇a. Modulation circuit 6;;:: "The lion is tuned. Laser control device (4) = recorded The sequence of laser light that is irradiated onto the optical disk 52: Device 1... Time series signal = ΐ; =: Controls the laser light. The disc motor 51: = disc ^ The disc motor control circuit 64 controls the disc motor 51. And the laser control device includes: an optical pickup 4a, a connection to the optical signal line 5, and a drive control and a 4t column connected by the plurality of signal lines 5, and the plurality of signal lines 5 can be used. Scratch the cable. Light; L day 4, taking the laser light that is reflected to the optical disk 52 and reflected. The plurality of signals are used to drive the timing signal 5 1 from the control circuit 23 and the masking timing ': the circuit 2 to the drop-out read head 4a. Further, the plurality of signal lines 5 communicate the first current setting signal V1 and the second number I2 from the driving unit circuit 2a to the optical pickup 4a. The RF amplifier 66 generates the track error signal TE, the convergence FE', and the information signal RF based on the read data read by the optical L read "4a". The service control circuit 62 is based on the track number J3995pi f.ptd page 1 1270868

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Further, as shown in FIG. 1, the laser drive circuit 3a includes a current generation circuit 32a connected to the first setting signal terminal 8a and the second setting signal terminal 8b, a timing signal terminal 9a, and a first shielding signal terminal. 9b, and the current control circuit 31a whose connection side is connected to the current generation circuit 32a and whose output side is connected to the current output terminal 7. In Fig. 2, the connectors 67a and 67b shown in Fig. 1 are omitted, and the current generating circuit 3 2 a generates the first driving current I 1 and the second driving current 12 . The current control circuit 31a performs an arithmetic process to control whether or not the first drive current 11 and the second drive current I 2 are transmitted to the laser unit 1. Further, the laser portion 1 includes a semiconductor laser element 丨丨 whose anode is connected to the laser drive $way 3a and whose cathode is connected to the low bit power source ss. The current generating circuit 32a includes a first voltage/current (V/I) converter 36a connected to the first setting signal terminal 8a and a second V/I converter 37a connected to the second setting signal terminal 8b. The first V/I converter 36a and the second V/I converter 37a are respectively generated in the current control circuit 31a! Drive current 丨丨 and second drive: current I 2 . The current control circuit 3 1 a includes a first logic and circuit 35a whose input side is connected to the timing signal terminal ^ and the 遮蔽1 shield # terminal 9b, and an input side connected to the timing signal terminal 9a and the ιν/ί conversion Is 3 6 a, the first switch 3 3 α whose output side is connected to the current output terminal 7 , and the input side connected to the first logic and circuit and the second V/I converter 37 a and the turn-out side connected to the current output terminal 7 The second switch 3 4 a. The first logic and circuit 35a performs the interpolation and calculation as the arithmetic processing on the timing signal S1 and the mask timing signal}. The first switch 33a switches whether or not the driving current 11 is supplied to the laser unit 1 in accordance with the timing signal §1. The second switch 34a is corresponding to the first logic

1270868 5. The invention is based on (7) and the output signal S2 of the circuit 35a, and the laser unit 1 is switched. The second driving current is supplied to the Lei Zheng shown in Fig. 3 of the timing control circuit 22a shown in Fig. 2. The knife month can be realized by, for example, a circuit that is not called. In the reference table 24A of the example terminal 127b of FIG. 3, the input includes a connection to the pre-12...photometer 240, and the output side is connected to the connection ==== data terminal mask signal output terminal 127〇1 connection cry 23 The nickname terminal 127c and the time-sharing circuits 250, 5# are connected to the connector 〇 of the connector 23 吟 and the bias i i, the circuit 2 260 connected to the connector 23 0 . Referring to Table 24(), the rising edge and falling edge time setting circuit 260 of the timing signal S1 and the heart sequence #1 are set to the shielding timing according to the (ffset) daytime setting trampoline L day/#PD. For (4) = 仃 test for 3 weeks offset F 士士士广>. When the upper 〇 ^ 时 斤 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Still going backwards. Count TS. The decoding 11230 is based on the modulated record 〇.πτ J ^ , the day-to-order control TCTL, and the offset time "^, the sequence signal S, and the mask timing signal M1. 1 n The operation of the laser control device 10 a of the first embodiment will be described with reference to Fig. 4 . j| Production two first ^ The two-wheel output level control circuit 218 shown in Fig. 1 is based on the control g 9W machine h to generate a first current setting signal VI with a predetermined voltage value and ~ "machine β and k 唬 V2. The current setting signal v丨 and the second current setting signal V2 are transmitted through the plurality of signal lines 5, and are supplied to the p setting signal terminal 8a and the second setting signal terminal (10), respectively. The first setting signal terminal 8a and the 2Set the first current setting signal n and signal terminal 8b

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The second current setting signal V2, the converter 37a performs V/I conversion drive current I 2 . In the result of the beta first V/I converter 36a and the SV/I conversion, the first drive current II and the second Μn/th order 'timer control circuit 223 are based on the recorded data after the modulation: = material PD 'generates the timing signal shown in Figure 4A. And Figure 4B shows the two masking sequence letter (4). The timing signal S1 and the masking timing signal are supplied to the timing signal terminal 9a and the masking signal terminal 9b, respectively, through the sigma line 5'. Here, when a plurality of signal lines 5 are passed, a signal delay occurs due to ~

On the other hand, during the period from time t1 to time t2 and the time period from t5 to t6, the phase difference M1 causes a phase difference. l (c) The timing signal si and the masking timing signal transmitted from the timing control circuit 22a through the timing signal terminal 9a and the worker shielding signal terminal 9b, and θ are logically ANDed by the first logic and circuit 35a. As a result, the output signal S2 of the first logic and circuit 35a shown in 4D is widely generated. The timing signal μ^ is transmitted to the first switch 33a. The output signal S2 of the first logic and circuit 35a is transmitted to the second switch 34a. (D) The first switch 3 3 a is in a period in which the timing signal S1 is at the high level, that is, in the period from the time t3 to t4 in FIG. 4A and the period from the time t7 to t8 (ON). The second switch 34a While the output signal S2 of the first logic and circuit 35a is at the high level, that is, the period from time t3 to time t4 of FIG. 4D is ON (0N). As a result, as shown in FIG. 4E, the laser driving current ild is The current value is equal to the sum of the current value of the first drive current 11 and the current value of the second drive current 丨2 during the period from time t3 to time t4. The laser drive current ILD is in the period from time t7 to time t8. The electric k value is the current value of the first driving current 11. The laser driving current I匕d

Page 15 1270868 V. Inventive Note (9) is transmitted through the current output terminal 7 to the half-turn-like dry conductor laser element 1 1 延 image, according to the first embodiment 1 timing signal M1 to the timing signal S1 = The field shot control #set l〇a, using the mask S1 and the masking timing signal M1 to generate a mask, this is wrong, even if the timing signal out of timing accuracy. That is, as shown in the figure, the laser light output timing signal M1 can be maintained, whereby the day 4ρ is not set, and the offset time is added to the mask so that 4 = = is completely shielded in Fig. 5A. Therefore, the phase difference is generated, and the H5D _2 + Fig. 5β does not block the timing signal M1. = ^ 22a is set on the optical read head "side, the mouth is the wind and ^ put the day: the sequence control circuit says 丄丄, τ M nine learning is taking the head 4 a will not cause the semiconductor laser element due to the increase of 埶曰口...in

= As the weight increases, the seek factor can be reduced. Therefore, even if the laser control device and the optical disk device of the first embodiment are subjected to the delay of the operation, the recording operation can be performed with very high reliability. D. The laser driving circuit 3a shown in Fig. 2 is monolithic integrated on the same semiconductor wafer 9 as shown in Fig. 6, and constitutes a semiconductor body circuit (semiconductor device) 94. In the illustration of Fig. 6, a plurality of pads 93a to 93e are formed on the semiconductor wafer 91. The pad 93a is an internal terminal for transmitting the first electric/finger pin V1 to the first v/I converter 36a. The pad 93b is an internal terminal for transmitting the second current setting signal V2 to the second V/I converter 37a. The glow pad 93c is an internal terminal for transmitting the timing signal si to the first switch 33a and the first logic and circuit 35a. The pad 93d is an internal terminal for transmitting the mask timing signal M1 to the first logic and circuit 35a. The pad 9 3 e is an internal end for transmitting the laser drive current I LD to the outside

1270868 V. Inventive Note (10): When the f-emission drive circuit 3a is accumulated on the semiconductor wafer 91, the timing signal S1 and the output signal S2 of the first logic and circuit 35a can be easily reached. The time difference between the switch 33a and the second switch 34a is reduced, so that laser control with high precision can be achieved. As shown in Fig. 7, the drive control circuit 2a shown in Fig. 2 is monolithically integrated on the same semiconductor wafer 92 to constitute a semiconductor integrated circuit (semiconductor device) 95. In the example of Fig. 7, the servo control circuit 62, the signal processing circuit 63, and the modulation circuit 61, which are not shown in Fig. 1, are further accumulated in the semiconductor wafer 92. However, the wheel-out level control circuit 21a may also be embedded in the cardiac amplification unit 66 as shown in Fig. or externally attached to the semiconductor integrated circuit (10). Further, a plurality of pads 96a to 96j are formed on the semiconductor wafer 92. The pads g6a and g6b are internal terminals for transmitting the error signal and the focus error signal to the servo control and the electric=. The pad 96c is for transmitting the information signal rf to the internal terminal of the #唬 processing circuit 63. The pads 96d and 96e are internal terminals for transmitting the timing signal S1 and the mask timing signal M1 to the outside. The fresh potential 96f is an internal terminal for outputting the output signal of the disc motor control circuit 64 to the outside. The pad 96g is an internal terminal for outputting the servo control circuit "number" to the outside. Solder pad 9 6 h, 刖: , 六外—a咕V1 ～ 奸 ybh and 96 ι are used to output the first electric brother 2 electric _ signal V2 to the internal end door of the ί, The internal terminal of the #5 tiger's input and output between the controller and each circuit block shown in Fig. 1. [First Modification Example] The laser control device _ in the ith modification of the third embodiment is as shown in FIG. 8, and the electric control circuit 3丨b may also include the third analog. 2 logic and circuit

1270868 V. Description of invention (11)

The input side of the 38 0 ' is connected to the timing signal terminal 9a and the high-order power supply VDD, and the output side thereof is connected to the i-th switch 33a. The second logic and circuit 38 0 performs logic and calculation on the high-level signal and the timing signal from the high-order power supply VDD. The first switch 33a is switched according to the output signal s 3 ' of the second logic and circuit 38A. The first drive current 丨丨 is supplied to the laser unit 1. The electric power control circuit 31a shown in Fig. 2 generates the timing signal S1 due to the signal delay when the output signal S 2 of the first logic and circuit 35a is generated. The small phase difference of the output signal S2 of the first logic circuit 35^. In the current control circuit 31b' shown in Fig. 8, the signal delays of the first logic and circuit 35a and the second logic circuit 38 are equal. The laser control device 1b shown in Fig. 8 can control the laser light with higher precision than the control device 10a shown in Fig. = [Second modification of the first embodiment] As the first embodiment In the laser control device 1 according to the second modification, the current control circuit 31c may include a third switch 41a connected between the second V/I and the right switch 345. The third switch 4ia is the root timing. The letter ship, whether or not the second drive current 12 is supplied to the: ϋ way π and the L flow control circuit 31 c does not include the first logic burial shown in Figure 2! = The switch 34b is based on the timing signal si,

The current 12 is supplied to the laser portion j. As shown in Fig. 9, 3' is connected to the third switch 41a and the second switch 3, and the logical AND of the current signal | According to a third modification of the third embodiment of the first embodiment, the two diodes of the third modification of the first embodiment are further connected to the electric device 5, and 10d is as shown in FIG. Switch 33a

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The fourth switch between 4 2 a, this point county disc cabinet q private - rain a with the same place.第4 and the current control circuit 31c where the current is not present, the Uth 42a is a constant N. The delay generated by the 篦3戸 bowΜ/M ni step 6. 3⁄4 moving current I 2 pass ^ can be cancelled. ^, the first driving current 丨丨 and the second driving current 丨 τ can be suppressed. [Second embodiment] _ f The laser control apparatus of the second embodiment of the invention 1 〇e: connected =;: T31e includes a logical sum circuit 71, the input side thereof is a switch 34a, and this point is the logic of the drive 2 = shown in FIG. And calculus. Moreover, the timing (4) = is set to the rising edge of i; = wl is set to be higher than the rise of the timing signal S1, and the time of the falling edge of the masking timing signal M1 is set to be higher than the ί =: falling edge . The laser drive circuit 3e and the drive control are the same as those of Fig. 6 and Fig. 7, and are integrated and integrated on the same semiconductor wafer to form a semiconductor integrated circuit. The configuration of the laser control device 10a shown is the same: he, . Structure 疋 and Fig. 2 [Λν: The laser control device of the second embodiment will be described with reference to Figs. J1 and 12 . However, the description of the portions overlapping with the operations of the laser control device 1〇3 of the first embodiment will be omitted. (A) The output level control circuit shown in Fig. u is the supply of the second current setting signal VI and the second current setting signal to /丨=36a and the first conversion switching timing control circuit (10). According to the adjusted - bedding MD and the preset data PD, i is shown in Figure m

1270868

V. INSTRUCTION DESCRIPTION (13) S1 and the mask timing signal M1 shown in FIG. 12B. Here, the masking timing signal Μ1 causes a signal delay in a period of time m2 to t3 shown in Fig. 2 for a plurality of times. The ''(Β) timing signal 81 and the masking timing signal' are logically AND calculated using the logical sum 71. The result is the output signal S2 of the logical sum; 71 shown in Fig. 12. The timing signal S1 is transmitted to the ! The output signal S2 of the AND circuit 71 is transmitted to the second switch 34a. (C) The first switch 33a is in the period from the time t1 to the time t4 of FIG. 12A and the time t5 to t8 while the timing signal si is at the high level. The period of the second switch 34a is "on" during the period in which the output signal S2 of the logic sum circuit 71 is at the high level, that is, at the time 11 to 18 of Fig. 1 2 C. The result is The current value of the laser driving current ILD is equal to the sum of the current value of the first driving current 11 and the current value of the second driving current I 2 in the period from time 11 to 14 in FIG. 1 2 D. And in FIG. 12D During the period from time t4 to time t5, the current value of the laser driving electric power ILD is equal to the current value of the second driving current I2. The current value of the laser driving current ILD is in the period from time 15 to t8 of FIG. And is equal to the sum of the current values of the first drive current 11 and the second drive current I 2 . According to the second embodiment, the mask is used. The sequence signal μ 1 is punctured by the timing signal s, and is masked, whereby the phase difference between the timing signal S1 and the masking timing signal M1 does not affect the accuracy of the laser light output timing. That is, the timing shown in FIG. The mask timing signal Μ1 shown in L1 and FIG. 1BB is logically and arithmetically calculated, whereby the laser drive circuit ILD shown in FIG. 13D does not cause waveform distortion at times other than 19 and 110. Therefore, the laser control device and the optical disk device of the second embodiment can achieve a very high reliability even if a signal delay occurs.

13995pif.ptd Page 20 1270868 V. INSTRUCTIONS (14) Sexual execution record action. [Modification of Second Embodiment] The laser control is performed in the dry/form example. As shown in Fig. 14, the current control circuit 3丨f may include the third switch 41b. And the current control power: to open the package = circuit and circuit 71. The third switch 41b is based on the shielding timing, and the electric current 12 is supplied to the laser unit 1. According to i ^ 2 乂 shown in Fig. 16, the second opening g34b is cut by the time-series signal, and the masking timing signal mi is used for cutting, thereby "= signal si and the mask timing letter leg Logic and calculation of the third embodiment of the laser control device 第g according to the third embodiment of the present invention, as shown in Fig. 5, the timing control circuit 22c generates a plurality of mask timing signals, which is related to The timing control circuit 22a is different from Fig. 2. Specifically, the mask signal generation circuit 222b of the mask timing control circuit 2+2c generates first and second mask timing signals M? and %2 that mask the timing signals. The current control circuit 13 1 g includes an input side connected to the timing signal terminal 仏 and the shimming signal terminal 9b, and an output side connected to the first switch 33b of the first logic and circuit 25, and an input side connected to the first occlusion The signal terminal 9b and the second shielding signal terminal 9C are connected to the logic sum circuit 26 of the second switch 34c on the output side. The first logic and power 5 logically and deviate the timing signal S1 and the first masking timing signal Μ1: logic And circuit 26 is for timing signal S1 and second mask timing signal Μ2, 1 □ logic and calculation. The first switch 33b switches whether or not the first drive current I1 is supplied to the laser unit 1 based on the output 仏^S2' of the logic AND circuit 25.

13995pif.ptd Page 21 Ϊ270868

=, the dynamic circuit 3g and the drive control circuit 仏 are the same as those of FIGS. 6 and 7 , and are integrated on the same semiconductor wafer to form a semiconductor integrated body, and the structure is the same as that shown in FIG. 2 . The configuration of the laser control device 丨〇a is described in detail with reference to Figs. 15 and 16 for the operation of the laser control device 1 〇g of the third embodiment. However, the description of the portion overlapping with the laser control device 第 of the first embodiment is omitted. (A) First, the output level control circuit 21β shown in Fig. 15 is the first electric*. Further, the L number V1 and the second current setting signal ν 2 are supplied to the first ν / I converter 36a and the second V/I converter 37a. The timing control circuit 22c generates the timing signal S1 shown in Fig. 16A and the first shown in Fig. 16B based on the converted data MD and the preset data PD. The timing signal M1 is masked, and the timing signal M2 shown in the figure UD is masked. Here, in the period of time t1 to t2 and time tlbtl2 of Fig. 16β, the i-th mask timing signal M1 generates a delay of seven by a plurality of signals 25. The second occlusion timing signal μ 2 causes a signal delay when a plurality of lines 5 are passed during the period from time t4 to time t5 and time t14 to t15 in Fig. 16d. ~ (B1) Next, the timing signal 8丨 and the masking timing signal M丨 are logically and arithmetically calculated by the first logic and circuit 25 as shown in Fig. 16C. The timing signal S1 and the second shading timing signal M2 are logically and arithmetically calculated using the logical sum 26 as shown in Fig. 16E. The output signal S2 of the logical AND circuit 25 is supplied to the first switch 33b. The turn-off signal S3 of the logic sum circuit 26 is & to the second switch 34c. The seek signal (C) of the first switch 33b at the first logic and circuit 25 is ancient.

13995pif.ptd Page 22 1270868 V. INSTRUCTION DESCRIPTION (16) The period of the level, that is, the period from time t3 to t6 in FIG. 16C, the period from time t7 to t8, and the period from time t9 to tio are ON (0N). . The second opening M34c is in a period in which the output signal s 3 of the logic and circuit 26 is at a high level, that is, a period of time 11 to 16 in the period of FIG. 16 e, a period of time 7 to 18, and a time 19 to 11 〇 period is open (0N). As a result, the current value of the laser drive current 丨LD is equal to the current value of the second drive current 12 in the period of the day 11-11 of the Fig. 16F and the period of time 11 3 to 11 5 . The current value of the laser driving current IL]) is the period from the time t3 to t6, the time t7 to t8, and the time t9 to the period u in the period of FIG. 16F, and is the first driving current I 丨 and the second driving current. The sum of the current values of 丨2, as described above, according to the third embodiment, by delaying the signal generated when the first logic and the circuit are connected to the output signal of the first logic and circuit, the sum circuit 26 is formed. The delay of the ^ generated when the output signal S2 of the logic 26 is generated is phase #, whereby the laser can be controlled with very high precision. Therefore, the laser control device and the optical disk device according to the third embodiment can perform the recording with very high reliability even if a signal delay occurs. [Fourth Embodiment] A laser control device 1 according to a fourth embodiment of the present invention 〇h is the drive control circuit 2d as shown in Fig. 17, and the fourth control timing signal M2 to M4 for the timing signal si is generated, which is the driving control shown in Fig. 2. The optical pickup 4h performs arithmetic processing on the timing signal si and the sequence signals Mi to M4, and this point and the 3^^ΓΛ; ; ^ - ^ ^ ! b ^ t of the figure generate the third current setting signal乂3 and the fourth current setting signal ν4.

1270868 V. INSTRUCTION DESCRIPTION (17) The current generating circuit 32b further includes a third V/I converter 38a connected to the third setting signal terminal 8c, and a fourth V/I converter connected to the fourth fourth terminal 8d. 39a, this point is different from the current generating circuit 32a shown in FIG. 2. The third V/I converter 380 a converts the third current setting signal V 3 into the third drive current 13. The 4th V/I converter 39a converts the fourth current setting signal V4 into the fourth driving current I 4 . The current control circuit 31h includes a first switch 33b connected between the first V/I converter 36a and the current output terminal 7, and is connected between the second v/I converter 37a and the current output terminal 7. The second switch 41 4 a, the third switch 41 c connected between the third V / I converter 38 8 and the current output terminal 7 , and the fourth switch connected between the second converter 39 a and the current output terminal 7 42b, the input side is connected to the timing signal terminal 9a and the first shielding signal terminal 9b, the output side is connected to the first logic and circuit 25 of the first switch 33b, and the input side is connected to the timing signal terminal 9a and the second shielding signal terminal 9. c, the output side is connected to the second logic and circuit 27 of the 34a, the input side is connected to the timing signal, the third 3rd shielding signal terminal 9d, and the output side is connected to the 3rd opening; And the logical sum of the input side connected to the timing signal terminal signal terminal 9e and the output side connected to the fourth switch 42b, respectively, is monolithically integrated in the same half as in FIG. 6 and FIG. The other structures are 盥0 _ ^^ slices to form the same semiconductor structure. L. The knot of the laser control device 1〇a, which is not shown in Fig. 1, is the first logic and the circuit 25 is over time.

Ml performs logic and calculus. 2nd " ’ and 1st timeline letter! 2 logic and circuit 27 sequence 彳tES1, and

13995pif.ptd Page 24 1270868 V. INSTRUCTIONS (18) The second masking timing signal μ 2 performs logic and calculation. The third logic and circuit 28 performs logic and calculation on the timing signal S1 and the third masking timing signal Μ3. The logical sum circuit 29 performs logic and calculation on the timing signal S1 and the fourth shading timing signal Μ4. The first switch 33b is associated with the output signal S2 of the first logic and circuit 25, and switches whether or not the first drive current π is supplied to the laser unit 1. The second switch 3 4a is an output signal S3 corresponding to the second logic and circuit 27, and switches whether or not the second drive current I 2 is supplied to the laser unit 1. The third switch 4 1 c is an output signal S4 corresponding to the third logic and circuit 28, and switches whether or not the third drive current 丨3 is supplied to the laser unit 1. The fourth switch 42b is a turn-off signal S5 corresponding to the logic AND circuit 29, and switches whether or not the fourth drive current I4 is supplied to the laser unit 1. Next, the operation of the laser control event of the fourth embodiment will be described with reference to Figs. 17 and 18. However, the description of the operation of the laser control device according to the first embodiment will be omitted. (A) First, the timing control circuit 22d shown in FIG. 17 generates the timing signal S1 shown in FIG. 18A and the first mask timing signal M1 shown in FIG. 18B based on the modulated data MD and the preset data PD. The second shading date sequence signal M2 shown in Fig. 18C, the third shading timing signal M3 shown in Fig. 18D, and the fourth shading timing signal Μ 4 shown in Fig. 18E && Here, the first masking timing signal M1, the second masking timing signal M2, the third masking timing signal M3, and the fourth masking timing signal M4 generate a signal delay when passing through the plurality of signal lines 5. ' ^ (B ) Next, the timing signal S1 and the first masking timing signal M 丨 are as shown in FIG. 18F, and the logic and calculation are performed by the first logic and circuit 25. The guard back signal S1 and the second mask timing signal M2 are as shown in Fig. 18G, and the second day is the second order. The signal and circuit 2 7 perform logic and calculation. Timing signal s丨 and 3rd masking $ =

13995pif.ptd Page 25 1270868

V. Invention Description (19) No. M3 is logical and generalized by the third logic and circuit 28 as shown in Fig. 18H. The timing signal S1 and the fourth shading timing signal M4 are as shown in Fig. 181, and the logic and circuit 29 perform logic and calculation.

(C) The first switch 33b is in a period in which the output signal S2 of the first logic and circuit 25 is at a high level, that is, a period from time 11 to 12 in FIG. 18F, a period from time 14 to 1, and a time from 17 to 18. The period is open (0N). The second switch 34a is ON during the period in which the output signal S3 of the second logic and circuit 27 is at the high level, that is, during the period from the time 11 to 12 in FIG. 18G and the time 14 to t5. The third switch 41c is ON (〇N) during the period in which the output signal S4 of the third logic and circuit 28 is at the high level, that is, in the period from the time t1 to the time t2 of Fig. 18H. The fourth switch 42b is in a period in which the output signal S5 of the logic sum circuit 29 is at the high level, that is, in the period from the time 11 to 12 in the period of FIG. 1 I, the period from the time 13 to 15, and the period from the time t6 to the t8. On (on). (D) The result is that the current value of the 'laser drive current 丨LJ' is the current value of the first drive current 、 and the second drive H2 in the period from time 11 to time t 2 in FIG. The sum of the current value of 2, the current value of the third drive current 13 and the fourth drive 1 ^ R electric value are equal. Further, the current value of the laser driving current I LD is in the period from time t 3 to t 4 P day + flute 1 thief private Φ A ” and time t6 to t7 in Fig. 18 J

The current value of the first drive current 11 ^ ^ I . ΛΑ ^ value 苐 2 the current value of the drive current I 2 and the sum of the current values of the fourth sinusoidal current I 4 - * 〇 T . . f Old and Specialized. The current value of the laser driving current ILD is in the period of & ^ # ^ ^ ^ ^ ^ at times 17 to 18 of FIG. 18 J, and is the pen value of the first driving current 11 and the fourth driving current 丨 4 According to the fourth embodiment, the sum of the motor values is equal. Line 5 causes signal delay, and also =f device 1Gh, even due to multiple signals). The moon is enough to drive the laser as shown in Figure 18.

13995pif.ptd Page 26 1270868 V. INSTRUCTIONS (20) The current value of IL D is switched in five modes (p a f f e r n ). Therefore, the accuracy of complex recording laser light control can be easily improved. [Fifth Embodiment] A laser control apparatus 丨〇i according to a fifth embodiment of the present invention, as shown in Fig. 19. The drive control circuit 2e further includes an encoder 8A for transmitting a plurality of mask timing signals. Ml~M3 are all symbolized (encoded), and this point further includes a decoder 8丨 with the current control circuit 3 1 i of FIG. 2 and FIG. 7 for using multiple masking day sequence signals Μ1~Μ3 Decoding, this point is different from Figure 2 and Figure 17. And the current control, the path 3 1 i includes a calculation processing circuit 27 7 a for performing arithmetic processing on the decoded plurality of mask timing signals ... - M3 and the timing signal S1. The arithmetic processing circuit 2 70a includes: an ith logic and circuit 25 that logically and calculates the decoded masking timing signal M1 and the timing=number, and logically and calculus the decoded $2 masking timing signal M2 and the timing signal S1. The second logic S1 enters, and the third masked timing signal M3 and the timing information after decoding are decoded; b "the third logic and circuit 28 of the subscription and calculation. The number of shot output bits increases and causes multiple The number of signal lines 5: large: the radiation noise of two or more signal lines 5 and the a, = off μ in the assembly surface, respectively, increase the number of multiple solutions, and the laser drive: the number of ^ lines 5 The semiconductor integrated circuit is formed in the same semiconductor wafer to form the same structure; the other structure is the same as that of FIG. 1 and FIG. 17, and the mine body of the fifth embodiment will be described with reference to FIGS. 19 to 21; The radiation control device 1270868 5. The operation of the invention (21) 1 0 i. However, the description of the portion overlapping with the operation of the laser control device 1 〇a of the first embodiment will be omitted. (A) First, FIG. The timing control circuit 22d shown is based on the modulated data MD and the preset data PD. The timing signal S1 and the first to third mask timing signals M1 to M3 shown in Fig. 21a are generated. Next, the encoder 80a shown in Fig. 9 generates the third mask timing based on the correspondence shown in Fig. 20. Signals M1 to M3. As a result, the first symbolized signal C1 and the second symbolized signal C2 shown in FIG. 21B and FIG. 21C are generated. The first symbolized signal C1 and the second symbolized signal C2 are transmitted through a plurality of signal lines. 5 is transmitted to the decoder 8 丨 & and, as shown in Figs. 21 A to 21C, the timing of changing the timing signal si is different from the timing of changing the first and second symbolizations " ί 。 C1 and C2. (Β) Next, the decoder 8A corresponds to the first to third mask timing signals M1 to M3, that is, the first and second symbolized signals π and C2, as shown in FIG. In the period from time t1 to time t2, the first symbolized signal C1 and the second symbolized signal C2 shown in FIG. 21β and FIG. 2B are respectively at a high level, so that the first masking timing signal M1 shown in FIG. 21D is used. The second masking timing signal M2 shown in FIG. 21E and the third masking timing signal M3 shown in FIG. 21F are set to a high level, respectively. In the period from t3 to t4, the first symbolized signal is at the level: and the second symbolized signal c 2 is at the low level. Therefore, the i-th and second mask timings are respectively used by the correspondence shown in FIG. The signal M1 & M2 is set to a high level 'sets the third masking timing signal M3 to a low level. During the period of time 15 16 'the i-th symbolized signal c 1 is a low level, and the second symbolized signal C2 Is a high level, so the first masking timing signal M is set to

13995pif.ptd Page 28 1270868 V. DESCRIPTION OF THE INVENTION (22) The high level 'sets the second and third shading timing signals M2 and M3 to the i-th symbolization signal π and the second period in the period from time t7 to t8. The symbolized production number C2 is a low level, so the 'the third third masking timing signal ~' 曰 is set to a low level, respectively.疋(D) Next, the ith logic and circuit 25 shown in FIG. 19, as shown in FIG. 2, logicalizes the timing signal si shown in FIG. 21A and the first occlusion F timing signal M1 shown in FIG. 21D. And calculus. The second logic circuit 27 performs logic and calculation on the timing signal S 1 and the second mask timing signal M2 as shown in Fig. 2ih. The third logic and circuit 28 performs logic and calculation on the timing signal S1 and the third mask timing signal Μ 3 as shown in Fig. 2 1 . (Ε) Next, the first switch 33b shown in FIG. 19 has a period in which the timing signal S1 is at a high level, that is, at times 11 to 12, at times 13 to 14, at times t5 to t6, and at times t7 to t8. It is open (0N) during the period. The second switch 34a is turned on (0N) during the period in which the output signal S2 of the first logic and circuit 25 is at the high level, that is, at the times 11 to 12, the time 13 to 14, and the time t 5 to 16. . The third switch 41c is ON (0N) in the period from the time 11 to 12 and the time 13 to 14 in the period in which the output signal S3 of the second logic and circuit 27 is at the south level. The fourth switch 42b is ON (0N) during the period in which the output signal S4 of the third logic and circuit 28 is at the high level, that is, during the period of time t丨~12. (F) As a result, the current value of the laser driving current 丨ld is the first driving current 丨丨, the second driving current I 2, and the third driving current I in the period from time t1 to t2 in FIG. 3. The sum of the current values of the fourth drive current I 4 is equal. The current value of the laser driving current 丨LD is in the period from the time 13 to 14 in FIG. 2 1 J, and is the first driving current 丨丨, the second driving current I 2, and the third driving.

13995pif.ptd Page 29 1270868 V. INSTRUCTIONS (23) The sum of the current values of the moving current I 3 is equal. The current value of the laser driving current I ld is equal to the sum of the current values of the first driving current 丨丨 and the second driving current I 2 in the period from the time 15 to 16 in Fig. 21 to J. The current value of the laser driving current I l d is equal to the current value of the first driving current 11 in the period from time t 7 to 18 in Fig. 21 1 J. The laser driving current I L D is supplied to the semiconductor laser element 11 shown in Fig. 19.

As described above, according to the fifth embodiment, the encoder 81a is added to the drive control circuit 2e, and the decoder 81a is added to the current control circuit 31i to reduce the number of the plurality of signal lines 5. When the timing signals S1, #, and 2 are transmitted to the optical pickup 4 through the plurality of signal lines 5, the timing signals S1, 1st, and 2nd are symbolized. The signal C1 & C2 can control the output level of the laser light with high precision even if the phase difference is generated. [First Modification of Fifth Embodiment]

In the laser control device j of the fifth modification of the fifth embodiment of the present invention, as shown in FIG. 22, the encoder 8〇b is a four-shielding timing signal, that is, the fourth fourth-order timing signals M1 to M4. It is also possible to use the corresponding symbolization shown in FIG. The _decoding benefit 81b is obtained by decoding the first and second symbolized signals C1 which are not shown in Figs. 24B and 24C by the correspondence shown in Fig. 23 . The current control circuit 31 J further includes a fourth logic and calculation circuit 28A for performing logic and calculation on the decoded fourth mask timing signal M4 shown in Fig. 24G and as shown in Fig. 24A. The current control signals shown in Figure 19 are delayed and decoded by C1 and C2. As a result, in the timing signal S 1 and the first to third 31 i, a slight signal delay occurs in the first and second symbols, and the third logic and circuits 25, 27, 28

13995pif.ptd Page 30 1270868 V. The output signals S 2, S3, and S4 of the invention (24) generate timing errors. The current control circuit 3 1 j shown in FIG. 22 controls the first switch 3 3b, the second switch 34a, the third switch 41c, and the fourth switch 42b by using logic and calculation results, thereby enabling high-precision control The first switch 33b, the second switch 34a, the third switch 41c, and the fourth switch 42b. [Second Modification of Fifth Embodiment]

The laser control device 丨〇k according to the second modification of the fifth embodiment of the present invention, as shown in Fig. 25, the current control circuit 3丨k can also be used in the first and The second symbolized signals Cia and c2a are processed and decoded. In other words, the current control circuit 31k includes a first logic and circuit 251 connected to the timing signal terminal 9a and the first concealer 5, and a second connection to the timing signal terminal 9a and the second shielding signal terminal 9c. The logic and circuit 2 71 is connected to the first logic and circuit 251 and the second logic and circuit 271, and the output side is connected to the decoders of the first to fourth switches 33b, 34a, 41c, and 42b. The arithmetic processing circuit 270c is constituted by the first logical AND circuit 251 and the second logical AND circuit 271. Further, the first logic circuit 251 performs logic and calculation on the timing signal 81 shown in FIG. 27A and the first symbolization signal C1 a shown in FIG. The second logic circuit 271 performs logic and calculation on the timing signal S1 shown in Fig. 27A and the second symbolization signal C2a shown in Fig. 27C. The decoder 8 1 c performs the correspondence shown in FIG. 26, and outputs the output signal C lb of the first logic and circuit 251 shown in FIG. 27D and the round signal c 2b of the second logic and circuit 271 shown in FIG. 27E. decoding. The output signals s 2 to S 5 of the decoder 8 1 c shown in Fig. 2 7 to 2 7 I are supplied to the first to fourth switches 33b, 34a, 41c, and 42b. The result is that

13995pif.ptd Page 31 1270868 V. INSTRUCTIONS (25) The laser drive current ILD shown in Figure 27J. The laser control 10 k ' according to the second modification of the fifth embodiment is similar to the laser control device 1 〇j shown in FIG. 2, and the first switch 33b and the second switch 34a are controlled again. The third switch 41c and the sixth embodiment [the sixth embodiment] The laser control device 1〇1 of the sixth embodiment of the present invention is as shown in Fig. 28, and further includes: fifth to ninth setting signal terminals 8e~ 8i, 5th to 9th converters 40 5 to 40Θ, 4th to 7th logic and circuits 264 to 267, and 3 04 to 308 logic and circuit 29 are different from those of Figs. 2 and 19 . Further, 1,800 is different from FIG. 19 by using a correspondence shown in FIG. 29 to symbolize (encode) only a part of the plurality of mask timing signals ^:. The converter 405 is connected to the fifth setting signal terminal 8e and the first. The 6V/! converter 406 is connected between the sixth set signal terminal 8f = ^6 switch 30 5 . The 7th V/I converter 4〇7 is connected between the 7th setting signal #sub and the 7th switch 30 7 . The 8th V/I converter 4〇8 is a connection center: ° ^9V/I#^ ti'409 ^^ Connected to the 9th between the signal terminal 8i and the 9th switch 3〇8. Sub J solves ί4= and circuit 264' whose input is connected to the timing signal terminal Γ and ί I 5 2 and its turn is connected to the 5th switch 3°4. The 5th Logic ^ Γ Input is connected to the timing signal terminal h and decodes the cry 2^ : ί 2 f is connected to the 6th switch 3〇5. The sixth logic and circuit: the two inputs are connected to the timing signal terminal 9a and the decoder 81d, and the beans = 疋 are connected to the seventh switch 306. The seventh logic circuit is connected to the timing signal terminal 93 and the damper 81d, and its output is connected to 疋 1270868. V. Description (26) - 8th switch 307. The logic sum circuit 29 has an input connected to the timing signal 9a and the fourth shading signal terminal 9e, and its output is connected to the ninth switch " 30 8 . The laser driving circuit 31 and the driving control circuit 讣 are stacked on the same semiconductor wafer as in Fig. 6 and Fig. 7, respectively, to constitute a bulk circuit. The other structure is the same as that of Figs. 1 and 19. Hereinafter, the operation of the laser control device 110 of the sixth embodiment will be described with reference to Figs. 28 to 30. However, the description of the portion overlapping with the laser control device 丨〇a of the i-th embodiment will be omitted. (A) First, the timing control circuit 22e shown in FIG. 28 generates the timing signal S \ shown in FIG. 3A and FIG. 3A based on the modulated data MD and the preset data PD, and the eighth. The timing signals M1 to M8 are masked. The code shown in Fig. 28 is based on the correspondence shown in Fig. 29, and generates a seventh block timing signal °° M1 to M7. As a result, the third symbolized signals C1 to C3 shown in Figs. 3A and 3C are generated. The third symbolized signals C1 to C2 are transmitted to the decoder 81d through the plurality of signal lines 5. Further, the decoder 81d decodes the first to third triplet numbers C1 to C3 shown in Fig. 29 . When the decoder § 1 d decodes the third symbolized signals C1 to C3, the eighth eighth timing signals M1 to M8 shown in Figs. 31E to 31L are generated. (B) Next, the first logic and circuit 25 shown in Fig. 28 performs logic and calculation on the timing signal S1 and the first masking timing signal M1 shown in Fig. 30F as shown in Fig. 3A. As shown in FIG. 300, the second logic circuit 27 logically and omits the timing signal S1 and the second mask timing signal M2 shown in FIG. 30G. The third logic and circuit 2 8, as shown in Fig. 30P, performs logic and calculation on the timing signal S1 and the third masking timing signal M3 shown in Fig. 30H.

1270868 V. DESCRIPTION OF THE INVENTION (27) The fourth logic circuit 264 performs logic and calculation on the timing signal 81 and the fourth mask timing signal M4 shown in FIG. 301 as shown in FIG. 30Q. As shown in Fig. 30R, the fifth logic and circuit 265' performs logic and calculation on the fifth mask timing signal M5 shown in the timing signal & and FIG. The sixth logic and circuit 266, as shown in Fig. 30S, performs logic and calculation on the timing signal S1 and the sixth concealing day sequence 彳g 5 Μ6 shown in Fig. 3 〇κ. The seventh logic circuit 267 performs logic and calculation on the timing signal S1 and the seventh mask timing signal M7 shown in FIG. 3A as shown in FIG. 30T. The logic sum circuit 29 performs a logical sum calculation on the timing signal S1 and the eighth mask timing signal M8 shown in Fig. 30E as shown in Fig. 30U. (C) Next, the first switch 3 3 b shown in FIG. 28 is in a period in which the timing signal s 1 is at a high level, that is, at times 11 to 12, times 14 to 15, time t7 to t8, and time t10. It is ON (〇n) in each period of til, time t13 to t14, time t16 to t17, time 11 9 to 12 0, and day to day 12 2 to 12 3 . The second switch 34a is in a period in which the output signal S2 of the first logic and circuit 25 is at a high level, that is, at times 11 to 12, at times 14 to 15, at times 17 to 18, at times 11 0 to 11 1 , and at time 11 3 . ～11 4. Time 11 6 to 11 7 and time 11 9 to 12 0 are ON (ON). The third switch 41c is in a period in which the output signal S3 of the second logic and circuit 27 is at a high level, that is, at times t丨 to 12, time 14 to 15, time t7 to t8, time t10 to til, and time t3. It is ON (ON) in each period from time t1 to t1 and time t1 to t17. The fourth switch 42b is in a period in which the output h number S 4 of the third logic and circuit 28 is at a high level, that is, at times 11 to 12, time 14 to 15, time t7 to t8, time 11 0 to 11 1 and time. 11 3 to 114 are open (0N) in each period. The fifth to ninth switches 304 to 308 and the fourth and fourth switches 33b and 34a,

Page 34 1270868

:===================================================================================================== Therefore, even if the laser output level is very diversified, the increase in the number of signal lines 5 can be suppressed to a minimum. [Other Embodiments] Those skilled in the art will be aware of various changes in the teachings or disclosures of the present invention. However, such variations are still within the scope of the present invention. In the first to sixth embodiments described above, an example in which the timing control circuits 22a to 22e are configured by the decoder 23 is described. However, instead of the decoder 230, a pulse generating circuit may be designed to make the timing signal si and the plurality of masking timing signals M1 to Μη independent. Further, as the timing signals become more complicated, the timing signals are not limited to one or more, and a mask timing signal corresponding to the plurality of timing signals S1 to Sm may be constructed. Further, in the description of the operation of the laser control devices 1a to 1〇h of the fourth embodiment, although the signal delay is generated in the plurality of mask timing signals M1 to Mn, even if the timing signal S1 is Signal delay is generated, and laser light can be controlled with high precision. The laser control devices 1a to 1〇1 of the sixth embodiment described above can be applied to various types of CD-R/RW drives, DVD-R/RW drives, DVD+RW drives, and next-generation optical disc drives. Recordable disc placement

13995pif.ptd

BRIEF DESCRIPTION OF THE DRAWINGS The present invention has been described in its preferred embodiments. The scope of protection of the present invention is defined by the scope of the appended claims.

13995pif.ptd Page 36 1270868 BRIEF DESCRIPTION OF THE DRAWINGS [Brief Description of the Drawings Fig. 1 is a view showing an optical disk apparatus of a first embodiment. Fig. 2 is a schematic view showing a laser control of a first embodiment. Fig. 3 is a block diagram showing the configuration of the first embodiment. Fig. 3 is a timing chart showing the first embodiment. Blocks of Structures of the Roads Figs. 4A to 4E are flowcharts showing the laser sequence of the first embodiment. The timing of the action of the two-stage display Fig. 5A to 5D show the flow chart of the laser sequence of the first embodiment. f] FIG. 6 is a schematic view showing the configuration of the semiconductor product and the circuit of the first embodiment. FIG. 7 is a schematic view showing the configuration of the semiconductor chip and the ϋ circuit of the first embodiment. Fig. 8 is a block diagram showing a ninth modification of the first embodiment. Fig. 9 is a block diagram showing a mine according to a second modification of the first embodiment. Fig. 10 is a block diagram showing a third variation of the first embodiment. <Field control device configuration Fig. 11 is a block diagram showing the configuration of the laser control device of the second embodiment. Fig. 1 2 A to 1 2 D show a second embodiment. When the laser control device is operating

13995pif.ptd Page 37 1270868 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 3 A to 1 3 D show the operation timing chart of the laser control device of the second embodiment. Fig. 14 is a block diagram showing the construction of a laser control device according to a modification of the second embodiment. Fig. 15 is a block diagram showing the configuration of a laser control apparatus according to a third embodiment. Fig. 1 is a flow chart showing the operation of the laser control apparatus of the third embodiment. Fig. 17 is a block diagram showing the construction of the laser control device of the fourth embodiment. Fig. 1A is a diagram showing the operation of the laser control device of the fourth embodiment. Fig. 19 is a diagram showing the structure of the laser control step of the fifth embodiment. A table of the decoding function of the fifth embodiment will be described. Fig. Z 1 2 1 J is a laser of the fifth embodiment. 动作 Operation of the field control device Fig. 22 is a block diagram showing a modification of the fifth embodiment. Fig. 23 of the field control device is a table showing the first modification of the fifth embodiment. The flat code and the decoding function are shown in Figs. 24A to 24L are operational timing charts of the fifth embodiment. m 9 A S ^ λ λ 1 r- control Example 1 Example of a laser of the first modification FIG. 5 shows a laser control device of a second embodiment of the fifth embodiment

13995pif-Ptd Page 38 1270868

Form a block diagram. Fig. 2 is a table showing the coding and the second modification of the fifth embodiment. Fig. 2 is a timing chart showing the operation of the laser control device according to the second modification of the fifth embodiment. Figure 28 is a block diagram showing the configuration of the laser control device of the sixth embodiment. Figure 29 is a diagram showing the coding and decoding functions of the sixth embodiment. Figs. 30A to 30V are diagrams showing the operation of the laser control device of the sixth embodiment. [Description of main component symbols] 1 laser section 2a to 2g·· drive control circuit 3a to 31 laser drive circuit 4a to 41 optical pickup 5 signal line 7 current output terminal 8a to 8i: eb ninth set signal terminal 9 a timing signal terminal 9b first shielding signal terminal 9 c second shielding signal terminal 9d third shielding signal terminal 9 e fourth shielding signal terminal 1 0 a, 1 0 b~1 0 1 : laser control device

13995pif.ptd Page 39 1270868 Schematic description 11 semiconductor laser device 2 1 a~2 1 c output level control circuit 22a 22 22e timing control circuit 25 first logic and circuit 2 6 logic and circuit 27 second logic Circuit 28 third logic and circuit 2 9 logic and circuit 3 1 a to 3 1 1 current control circuit 32a to 32c current generation circuit 33a, 33b first switch 34a to 34c: $2 f歼1 Μ 35a first logic and circuit ( AND circuit) 36a to 39a 1st to 4th V/I converters 4 1 a, 4 1 b, 4 1 c 3rd switch 42a, 42b 4th switch 5 1 disc motor 5 2 optical disc 6 1 modulation circuit 6 2 servo control circuit 6 3 signal processing circuit 64 disc motor control circuit 6 5 controller 66RF amplifier

13995pif.ptd Page 40 1270868 Schematic description 67a connector 67b connector 6 8 printed substrate 7 1 logic and circuit 8 0 a~8 0 d encoder 8 1 a, 8 1 b, 8 1 c, 8 1 d Decoder 9 1 , 9 2 semiconductor wafers 93a to 93e 塾 94, 95: semiconductor integrated circuit (semiconductor device) 9 6 a~9 6 j : pad 12 7a modulation data terminal 1 2 7b preset terminal 127c timing Signal terminal 1 27d mask signal output terminal 2 2 1 timing signal generation circuit 222a mask signal generation circuit 222b mask signal generation circuit 2 3 0 decoder 2 4 0 reference table 2 0 0 timer circuit 251 first logic and circuit 2 6 0 bias Shift (〇fiset) time setting circuit 2 64~2 6 7 4th to 7th logic and circuit 2 7 0 a~2 7 0 d calculation processing circuit

13995pif.ptd Page 41 1270868 Schematic description 271 2nd logic and circuit 280 4th logic and calculation circuit 3 04 - 308: 5th to 9th switch 380 2nd logic and circuit 4 0 5 -40 9 : 5th ～9th V/I converter C1-C3: first to third symbolization signals C1a to C2a: first to second symbolization signals Clb and C2b: output signals I1 to I9: first to ninth drive currents I LD laser drive current

M1~M8: 1st to 8th masking timing signal MD modulated data OT offset time control signal PD preset data FE focus error signal RD record data RF dual frequency S1 timing signal S2 timing signal S3~S9 output signal TCTL Timing control signal TE execution error signal TS time information VI~V9 1st to 9th current setting signal

13995pi f.ptd Page 42 1270868

13995pif.ptd第43页

Claims (1)

1270868 13995pif.ptd Page 44 1270868 VI. Application for patents The current drive 圏 雷 the laser drive device described in item 7 of the patent scope, wherein the calculation is performed. The road is a logic and calculus with - logic and calculus as Q. The laser drive device as described in item 7 of the current patent, including the ^. ^77 and Ma Jie, symbolize The plurality of masking timing signals are decoded; and at the timing 10, the current processing circuit performs the arithmetic processing on the decoded plurality of masking timing signals and signals. The laser driving device of claim 7, wherein the control circuit comprises: an f-calculation processing circuit for performing the arithmetic processing on the symbolization number; and a decoder for processing the knot of the arithmetic processing The driving device comprises: a laser portion, the plurality of masking timing signals for irradiating a laser light, and a timing signal line performing portion for decoding the optical disc light. The driving drive control circuit of 12 generates a timing signal for controlling the timing of the laser shot according to an input data, and a masking number for shielding the timing signal; and a laser driving circuit, the timing signal and the timing of the masking Signal processing, and controlling the laser according to the result of the calculation processing. The laser driving device according to claim 11 of the patent application, the dynamic control circuit and the laser driving electrical system are respectively monolithically accumulated. In 1270868 VI. Application for patents on individual semiconductor wafers. 11 The laser drive ^ - zone control circuit as described in the scope of claim 2 generates a plurality of mask timing signals. The drive control circuit breaks a motion of the plurality of mask timing signals and symbolizes the laser as described in claim 3 of the patent application. The laser drive circuit of the laser drive described in claim 14 is: the power device, the decoder, which decodes the plurality of masked timings and symbols And performing the arithmetic processing on the plurality of decoded timing signals by the calculus processing circuit. The heart-sequence signal and the magnetic drive circuit of the mine according to claim 4, wherein the laser drive circuit comprises: a heartbeat I, which is the time; the circuit, the symbolized plurality of masking timing signals and The arithmetic processing is performed on the fifth page; and the decoder 'decodes the result of the arithmetic processing. 17. A disc drive device comprising: a variable, modulation circuit for adjusting a laser control device for recording data from a controller, and generating a system according to the modulated data. Laser light illuminates to - 磾Μ amp amp 出 枓 枓 枓 枓 枓 & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & 户 户 户 户a masking timing signal 'and performing the timing signal and the mosquito sequence ^-calculation processing, and then processing the knot according to the calculation 13995pif.ptd Page 46 1270868 VI. Scope of Application The control of the laser light; a disc motor that drives the disc; and a disc motor control circuit that controls the disc motor. The optical disc drive apparatus of claim 17, wherein the laser control apparatus generates a plurality of shading timing signals. The optical disc drive device of claim 18, wherein the laser control device comprises: an encoder that symbolizes part or all of the plurality of mask timing signals; and a decoder that The symbolized plurality of masked timing signals are decoded. The optical disk drive device of claim 18, wherein the laser control device comprises: an encoder that symbolizes a part or all of the plurality of mask timing signals; and an arithmetic processing circuit, The decoded plurality of masking timing signals and the timing signal perform the arithmetic processing; and a decoder that decodes the result of the arithmetic processing. 13995pif.ptd Page 47