JPH08147697A - Semiconductor laser driving circuit - Google Patents

Abstract

PURPOSE: To obtain a semiconductor laser driving circuit which can edge record without jitter due to the length deviation even if variation exists in a transmission system or an element. CONSTITUTION: A semiconductor laser 12 is supplied with a bias current 10, predetermined currents i1, i2, i3 from current sources I0, I1, I2, I3 controlled by a current control circuit 13 in such a manner that the current i1 of the one I1 of the switched sources I1, I2, I3 is set larger than the currents i2, i3 of the other sources I2, I3. It is so switched as to include the timing information of the front and rear edges in the case of mark edge recording to generate a semiconductor laser driving current ILD which has small influence of the unevenness of a switching element, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser drive circuit for an optical recording apparatus which performs mark edge recording by superimposing a plurality of currents.

[0002]

2. Description of the Related Art The mark edge recording method is a well-known technique as one of high-density recording methods for optical disks, but the problem is that the recording mark shape is distorted into a tear drop shape due to the effect of heat accumulation under a laser driving current with a normal pulse waveform. In particular, in mark edge recording using the recording mark length as data, it causes an increase in errors during reproduction. As measures against this, there have been proposed a recording waveform compensation method (hereinafter referred to as a write competition method) and a semiconductor laser drive circuit which use several laser powers during recording as described below.

Japanese Laid-Open Patent Publication No. 5-290437 or FIG.
0 (b), a first constant current source that outputs a predetermined output current to the semiconductor laser 81 in accordance with an external instruction voltage, and an external instruction voltage from the output current I of the first constant current source. 2nd, 3rd, 4th, 5th according to
Current sources Ir, Ias, Iw1, Iw2, and the current sources Ir, Ias, I arranged between the current sources Ir, Ias, Iw1, Iw2 and the output terminal to the semiconductor laser 81.
Extraction currents of w1 and Iw2 (that is, Ir, Ias, Iw
1, Iw2) is turned on / off (or turned on / off) in accordance with a logic signal from the outside, and current switch circuits (abbreviated as CS) of current sources Ir, Ias, Iw1, and Iw2 for pulse-driving the semiconductor laser drive current. ) And a semiconductor laser drive circuit including a plurality of pulse current drive circuits having

Further, the C.I. S. Is composed of a symmetrical NPN transistor as shown in FIG. 10 (c), and the first constant current source is composed of a transistor as shown in FIG. 10 (d). Then, this semiconductor laser drive circuit generates a semiconductor laser drive current (abbreviated as LD drive current) shown in FIG.

In this semiconductor laser drive circuit, as shown in FIG.
When a mark edge recording write competition method such as 0 (a) is performed, each C.I. S. Pulse for controlling (that is, Pr, Psa, Pw
1 and Pw2) can be inferred to be set as shown in FIG. 11 (see paragraph No. [0117] in P.14 of JP-A-5-290437).

[0006]

At this time, the second, third, fourth and fifth current sources I of the individual pulse current drive circuits are used.
Although the set currents of r, Ias, Iw1, and Iw2 have a magnitude relationship, they have similar current levels. As a result, the current supply capacities of the current sources Ir, Ias, Iw1, and Iw2 need to be substantially equal.

As a result, when the semiconductor laser drive circuit corresponding to the high recording density is configured as shown in FIG. 10B, a pulse current drive circuit having a high current drive capability is required in each case. Third, fourth and fifth constant current sources Ir, I
The current values of as, Iw1 and Iw2, as described above, continuously flow from the semiconductor laser 81 to any of the GNDs regardless of whether the switching circuit is on or off. Therefore, a large power consumption is required.

Further, in FIG. 11, the input signal of SW1 is an ON / OFF signal of the bias power, and is a timing signal for preventing thermal interference between marks by providing an OFF section, and unless it is extremely deviated. The rising and falling edges of the direct signal do not determine the edge of the recording mark. On the other hand, the timing of the rising edge (for example, time t1) of the input signal of SW2 determines the front edge of the recording mark, and the timing of the last rising edge (for example, time t2) of the SW3 input signal is the rear edge of the recording mark. decide.

Here, when the timing signals for determining the leading and trailing edges of the recording mark are different from each other as the input signal of the switching circuit in the pulse current driving circuit as described above, for example, as shown in FIG. When the input signal is deviated, the LD drive current ILD "having the amplitude of i1" + i2 "is deviated by ts in the time axis direction at the timing of determining the falling edge (time t2), and the recording mark length is deviated. .

On the other hand, the next recording mark is at time t.
At the timings 1'and t2 ', since the recording mark edge is determined only by the LD drive current waveforms i1 "and i2", the recording is performed at the original timing.
As a result, the first recording mark is recorded shorter, the gap immediately after is longer, and the second recording mark is recorded as before.

In this way, when a shift occurs between the input signals due to the transmission system or the like, the record mark causes an individual shift depending on the mark length. This length deviation causes jitter during reproduction, and the data deviation cannot be removed even by using a reproduction correction method using two PLLs already proposed as a length deviation correction method for mark edge recording. The reproduced data cannot be reproduced (the reproduced data is different from the recorded data), that is, it causes a data error. In this way, the deviation between the data becomes the length deviation of the recording domain as it is, the jitter during reproduction increases, and the occurrence rate of data error increases.

The present invention has been made in view of the above points, and realizes a switching operation in which a signal displacement between input signals has the least influence on a recording domain, and recording of a domain having less jitter due to a length displacement. An object of the present invention is to provide a semiconductor laser drive circuit that can be realized.

[0013]

Means and Actions for Solving the Problems At least one constant current source for supplying a predetermined output current according to an instruction voltage from the outside, and a constant current source arranged between the constant current source and the semiconductor laser, the current is supplied from the outside. 2 or more pulse current drive circuits composed of a switching circuit for pulse-driving the semiconductor laser drive current, which is turned on / off in accordance with the logic signal A semiconductor laser driving circuit is configured by a logic circuit that converts one or more switching circuits into a logic signal for turning on and off, and at least one logic signal of the logic circuit output determines front and rear edges of a recording domain. An input signal is a logic signal including both timing information and the logic signal including the timing information. If the amount of current passing through the switching circuit is made larger than the amount of current of other switching circuits, even if data gaps occur due to variations in the characteristics of the transmission system or the elements used, edges before and after the recording domain Since the recording domain is predominantly determined by the current switched by the logic signal including all the timing information for determining the recording domain, the recording domain can be formed with almost no influence of the shift between data.

[0014]

Embodiments of the present invention will be specifically described below with reference to the drawings. 1 to 3 relate to a first embodiment of the present invention, FIG. 1 shows a circuit configuration of a semiconductor laser drive circuit of the first embodiment, and FIGS. 2 and 3 show operation explanatory diagrams of the first embodiment. .

The semiconductor laser drive circuit 11 of the first embodiment of the present invention shown in FIG. 1 is used in an optical information recording / reproducing apparatus such as a magneto-optical recording / reproducing apparatus for optically recording and reproducing information. Semiconductor laser 1 for generating laser light
2 and the current sources I0, I1, I2 of the semiconductor laser 12
, I3, a current control circuit 13 for controlling current by controlling switching elements (not shown) of the current sources I0, I1, I2, I3, a CPU 14 for controlling the current control circuit 13, and a clock for the CPU 14. And a clock generator 15 for supplying.

In response to the reproduction mode instruction signal for performing the reproduction operation, the CPU 14 instructs the current control circuit 13 to turn off the switching elements (not shown) of the current sources I1, I2 and I3, respectively. The set current of I2 and I3 is set to 0 [mA], and a predetermined read current Ir suitable for reproduction is set.
Is supplied from the bias constant current source I0.

In response to the erase mode instruction signal for performing the erase operation, the CPU 14 instructs the current control circuit 13 to bias the bias current Ir of the bias constant current source I0 or the threshold current of the semiconductor laser 12 during the reproduction. In addition to Ith, the switching element of the current source I1 having the highest current supply capability is turned on to superimpose a predetermined constant current i1 on the bias current or threshold current Ith, and the erase current Ie necessary for erasing is applied to the semiconductor laser Supply to 12.

In response to the recording mode instruction signal for performing the recording operation, the CPU 14 generates a logic signal in synchronization with the clock for the write data input to the CPU 14, and after D / A conversion together with the amplitude information, the current is supplied. Input to the control circuit 13.

Then, the current control circuit 13 turns on / off the switching elements of the respective current sources I1, I2, I3 in accordance with the logic signal to turn on / off the threshold current I of the semiconductor laser 12.
The currents i1, i2, i3 when these are turned on in th
The added current obtained by adding is supplied to the semiconductor laser 12 as the semiconductor laser drive current ILD as shown in FIG. This first
In the embodiment, the current i1 of the current source I1 is transferred to the other current sources I0 and I0.
2, larger than I3 (see (1) below,
Formula (2)).

In the recording mode, a logic signal is generated or switching control of the current source I1 is performed so as to include timing information for determining the front and rear edges of the recording domain according to the waveform of the current i1 of the current source I1. It is a feature.

Next, the operation of the semiconductor laser drive circuit 11 of the first embodiment will be described. CPU during playback
According to the instruction of 14, the current control circuit 13 causes each current source I1,
The set current of I2 and I3 is set to 0 [mA], and a predetermined read current Ir is supplied from the bias constant current source I0 (in this case, i0 = Ir).

At the time of erasing, in addition to the bias current Ir of the bias constant current source I0 or the threshold current Ith of the semiconductor laser 12 at the time of reproducing, the current source I1 having the highest current supply capacity as shown below is used. , The current control circuit 13 superimposes a predetermined constant current i1 on the bias current Ir or the threshold current Ith according to an instruction from the CPU 14,
An erase current Ie necessary for erasing is supplied to the semiconductor laser 12 (for example, Ie = Ith + i1).

Of course, all current sources I1, I2, I
3, a predetermined constant current i1, i2, i3 is superposed on the bias current or the threshold current Ith of the semiconductor laser 12, and the erase current Ie necessary for erasing is supplied to the semiconductor laser 12
(Ie, Ie = Ith + i1 + i2 +)
i3).

At the time of recording, in addition to the threshold current Ith of the semiconductor laser 12, the semiconductor laser drive current I as shown in FIG.
LD is supplied to the semiconductor laser 12 as an added current of the current sources I1, I2, and I3 (that is, ILD = i0 (= Ith)).
+ I1 + i2 + i3). For this purpose, the CPU 14 follows the write data and a predetermined clock to generate each current source I1, I2,
A logic signal for turning on / off the switching element of I3 is generated, D / A converted together with the amplitude information, and then the current control circuit 13
The current control circuit 13 controls the current values i1, i2, i3 of the current sources I1, I2, I3 as shown in FIG. As a result, the recording mark is different from the write data in FIG.
Is formed.

In this recording mark forming operation, the timing for determining the leading edge of the recording mark in the LD drive current ILD is time t1 and the timing for determining the trailing edge is time t2, as shown in FIG. Here, the current waveform of the current source I1 is used as timing information for determining the front and rear edges of the recording domain (for example, at times t1 and t in FIG. 2).
The current waveform is such that both 2 are included. Further, the output current amplitude operates so that the following relationship holds, for example.

I0 = Ith, i1 + i3> ic, i2 + i3 <ic (1) i1 >> i2, i1 >> i3 (2) However, a recording mark is formed on the recording medium to be recorded here. LD drive current value required to drive
Ith (where ic corresponds to the current of the light emission level required to form a recording mark from the threshold current Ith).

Compared with other current values, i1 >> i2, i3
From this relationship, the current source I1 is most dominant in the recording domain length. Therefore, when a deviation between data occurs due to variations in the characteristics of the transmission system or the elements used, specifically, when the current source I2 deviates from the other current sources i1 and i3, as shown in FIG. The LD drive current waveform ILD is obtained. The LD drive current waveform ILD in this case is slightly deformed by the current i2 of the current source I2, i2 <i2 +
Since i3 <ic, the current i2 has almost no effect on the recording mark.

As described above, according to the first embodiment, the times t1, t2, t of the timing for determining the edge of the recording mark are determined.
1'and t2 'are both included in the current source I1 and the current amplitude is i1 >> i2, i3, so that the other (remaining) currents i2, i3 to be switched are recorded marks from the condition of (1). Is not formed, and the recording mark edge is the current source I1.
Can be said to be dominant.

On the other hand, when the LD drive current ILD as shown in FIG. 2 is applied to the drive by the conventional method so that the waveforms thereof are substantially equal to each other, when the deviation between the drive current waveforms occurs as described above. , As shown in FIG. 3B, i1 + i2 at the time t2 of the timing for determining the falling edge.
The LD drive current ILD ″ having the amplitude of is shifted by the time ts in the time axis direction, and the length of the recording mark is shifted.

On the other hand, the next recording mark is time t.
At the timings 1'and t2 ', the recording mark edge is determined only by the LD drive current waveforms I1 "' and I2", so that recording is performed at the original timing. In FIG. 3 (b), the current source corresponding to this embodiment is replaced with the reference numeral with "".

As a result, the first recording mark is recorded longer and the second recording mark is recorded in the conventional manner. In this way, the recording marks are individually displaced depending on the mark length. This length deviation causes jitter at the time of reproduction, and even if a reproduction method using two PLLs dedicated to mark edge recording is used, the data deviation cannot be removed and causes a data error.

As described above, when the semiconductor laser is driven by combining a plurality of current sources, the semiconductor laser drive circuit 11 according to the first embodiment can be used to perform recording with little influence of deviation between signals of each power supply circuit. It is possible to realize recording of recording marks that can reduce the length deviation and the occurrence of jitter.

That is, according to the embodiment, when a semiconductor laser current waveform with a small waveform distortion conforming to the recording compensation waveform is supplied to the semiconductor laser by using a plurality of current sources to perform mark edge recording, one current source is used. Since the current includes timing information of both front and rear edges and is set to be larger than the currents of other current sources, the current of one current source predominantly determines the edge of the recording mark. Even if there is a variation in the element, it is possible to perform recording with little length deviation and recording jitter, without being greatly affected by the variation. Therefore, even when the information is reproduced, it is possible to reproduce the information with high reliability and with little reproduction error.

2 and 3, the description is made by setting i3> i2, but i3 = i2 may be set. Under this condition, for example, when the current source I2 is deviated from the other current sources i1 and i3, or when the current source I3 is deviated from the other current sources i1 and i2, the LD drive current waveform almost similar to that of FIG. ILD
Therefore, it is possible to perform recording with little influence on the deviation between the signals of each power source.

Next, a second embodiment of the present invention will be described. FIG.
Shows the configuration of the semiconductor laser drive circuit 20 of the second embodiment of the present invention. This semiconductor laser drive circuit 20 has command voltages V1, V from external command voltage generation circuits 24, 25, 26.
2 and V3, a first constant current source I1, I2, I3 for outputting a predetermined output current to the semiconductor laser 12;
Is placed between the constant current sources I1, I2, I3 and the semiconductor laser 12, and the output current of the first constant current sources I1, I2, I3 is turned on / off according to a logic signal from the outside to generate a semiconductor laser drive current. Circuit SW for pulse driving
Three pulse current drive circuits 21, 22, 23 composed of 1, SW2, and SW3, and a bias current for recording and a read current for reproduction according to the instruction of the current control circuit 27, for supplying a predetermined direct current A constant current source I0, recording data (or write data) in the recording mode, and a predetermined clock from the OSC (oscillator) 28 (here,
Logic signals D1 ', D2', D3 '(D1, D2, D in FIG. 6) from the double frequency clock of the channel clock)
Inversion signals of the logic signals of 3 are sequentially D1 ', D2', D3 '
And ) And a logic circuit 29 for converting The semiconductor laser 12 and the constant current source for bias I
A choke coil L that allows a direct current component to pass therethrough and blocks an alternating current component from passing therethrough is interposed.

Also in this embodiment, as in the first embodiment, the current i1 of the current source I1 is set larger than the other current sources I0, I2 and I3 (see the equations (1) and (2)). Further, in the recording mode, the configuration is such that a logic signal is generated or switching control of the current source I1 is performed so as to include timing information that determines the front and rear edges of the recording domain according to the waveform of the current i1 of the current source I1. Has become.

FIG. 5 shows a specific circuit configuration example of the logic circuit 29. The write data is applied to the serial input end of the shift register 31 and output from the output ends Q1, Q2, Q3, Q4 in synchronization with the clock applied to the clock input end. The output from the output terminal Q1 and the output obtained by inverting the output terminal Q3 by the inverter 32 are input to the flip-flop 34 via the AND circuit 33 and output from the output terminal Q in synchronization with the clock.

The output of the output terminal Q2 and the output of the output terminal Q4 inverted by the inverter 35 are input to the flip-flop 37 via the AND circuit 36 and output from the output terminal Q thereof in synchronization with the clock.

The output of the output terminal Q1 and the output of the output terminal Q4 are input to the flip-flop 39 via the AND circuit 38 and output from the output terminal Q thereof in synchronization with the clock. Further, the output of the output terminal Q2 and the data obtained by inverting the write data by the inverter 40 are input to the flip-flop 42 via the AND circuit 41 and output from the output terminal Q thereof in synchronization with the clock. Flip-flops 34 and 3
The output of 7 passes through an OR circuit 43 and then an OR circuit 44 and is input to a flip-flop 45, which outputs data D1 'from its output terminal Q in synchronization with a clock and an inverted output terminal / Q.
To output data D1.

The output of the flip-flop 39 is input to the OR circuit 44 via the AND circuit 46 and also to the flip-flop 47, and the data D2 'is output from its output terminal Q in synchronization with the clock and the inverted output terminal. The data D2 is output from / Q. The output of the flip-flop 39 is input to the flip-flop 49 via the AND circuit 48, the output of its output terminal Q is input to the AND circuit 46 in synchronization with the clock, and the output of the inverting output terminal / Q is the AND circuit. 48 is input. Also, the flip-flop 42
Is output to the flip-flop 50 and outputs data D3 'from its output terminal Q and data D3 from its inverted output terminal / Q in synchronization with the clock.

Next, the operation of the semiconductor laser drive circuit 20 of the second embodiment will be described. During reproduction, the switching circuit S in the pulse current drive circuits 21, 22, 23
W1, SW2, SW3 are all off (D1, D2, D
3 is set to a low state, the set current of each constant current source I1, I2, I3 is set to 0 [mA], and a predetermined read current is supplied from the bias constant current source I0 according to the instruction of the current control circuit 27.

At the time of erasing, in addition to the bias current of the bias constant current source I0 or the threshold current Ith of the semiconductor laser 12 at the time of reproducing, the pulse current drive circuit 21 having the highest current supply capability is shown below. The switching circuit SW1 is turned on (D1 is high), a predetermined constant current is superposed on the bias current by the instruction voltage V1 from the outside by the constant current source I1, and the erase current necessary for erasing is supplied to the semiconductor laser 12. .

Of course, all pulse current drive circuits 2
Switching circuits SW1, SW2, S of 1, 22, 23
All of W3 is turned on (D1, D2, D3 are high), and a predetermined constant current is applied from the constant current sources I1, I2, I3 by external instruction voltages V1, V2, V3 to the bias current or the threshold of the semiconductor laser 12. An erase current necessary for erasing may be supplied to the semiconductor laser 12 by being superimposed on the value current Ith.

At the time of recording, as in the case of erasing, in addition to the bias current of the bias constant current source I0 or the threshold current Ith of the semiconductor laser 12 at the time of reproducing, a semiconductor laser driving current as shown in FIG. Current drive circuit 21,2
The added current of 2, 23 is supplied to the semiconductor laser 12.

Therefore, first, as shown in FIG. 4, the current value of the constant current source of each semiconductor laser drive circuit 21, 22, 23 is explained in the first embodiment by the external instruction voltages V1, V2, V3 (1), Expression (2) (that is, i0 = Ith, i1 + i3
> Ic, i2 + i3 <ic, i1 >> i2, i1 >> i
3, I1 >> I2, I3).

Next, write data from the host computer and a frequency clock twice as high as the recording frequency (channel clock) are input to the logic circuit 29 of FIG. The logic circuit 29 synchronizes with the clock in accordance with the write data in these two input signals to switch circuits SW.
1, input signals D1 ', D2', D to SW2, SW3
3'is generated (see FIG. 5).

Here, the logic circuit 29 determines the timing information for determining the leading and trailing edges of the recording domain for the recording data D1 'of the pulse current driving circuit 21 having the largest semiconductor laser driving current (for example, times t1 and t2 in FIG. 2). Is a logic signal that includes both. As a result, as in the first embodiment, the current supply amount of each pulse current drive circuit 21, 22, 23 is as described above, the switching data D1 'is the most dominant for the recording mark length because of I1 >> I2, I3. Therefore, the transmission system and the logic circuit 29 between the input signals D1 ', D2', D3 'of the switching circuits SW1, SW2, SW3.
Even when a data shift occurs due to a characteristic variation of the element used in the above, the switching operation with the least influence is realized.

The non-inverted output of the output of the logic circuit 29 shown in FIG. 5 is used. This logic circuit 29 is provided with a PLD (Programmable Lo) with a relatively small data-to-data skew.
Gic Device). As a result, the switching data D is stored in each pulse current drive circuit.
Current amplitudes I1, I2, I according to 1 ', D2', D3 '
The semiconductor laser drive current ILD of 3 is supplied to the semiconductor laser 12.

Further, the pulse current drive circuits 21, 22, 2
The switching circuits SW1, SW2, and SW3 of No. 3 are generally configured symmetrically with two NPN transistors as shown in FIG. 10 (c), and operate with a symmetrical circuit configuration. Also stabilizes. However, in the case of such a circuit configuration, even if the driving current is not supplied to the semiconductor laser 12, as long as the instruction voltage of the constant current sources I1, I2, I3 is 0 V and the constant current is not 0 [mA], a current equivalent to GND is obtained. Is wasted.

However, as described above, when the input signal of the switching circuit and the current amplitude of each pulse current drive circuit are set, the current loss can be made much smaller than that of the conventional method shown in FIG. Is also advantageous.

As described above, in the second embodiment, when a plurality of pulse current drive circuits 21, 22, 23 are combined to drive the semiconductor laser 12, the logic circuit 29 decomposes the write data and the pulse current drive circuit 21 is used. , 22 and 23 are operated to drive the pulse current drive circuits 21 and 2, respectively.
The interference between 2 and 23 can be minimized and low power consumption can be realized. Further, it is possible to realize the switching operation that is less affected by the signal shift between the respective input signals, and to record the domain with less length shift and jitter.

Next, a third embodiment of the present invention will be described. Figure 7
Shows the configuration of the semiconductor laser drive circuit 57 of the third embodiment of the present invention. Sweep-out type constant current sources I1, I2, I3 for outputting a predetermined output current to the semiconductor laser 12 in accordance with external instruction voltages V1, V2, V3, and constant current sources I1, I2.
, I3, a suction type constant current source I1 ', I2', I3 'for extracting a current amount equal to I3 from the semiconductor laser drive current,
It is arranged between the suction type constant current sources I1 ', I2', I3 'and the output terminal to the semiconductor laser 12, and the extraction currents of the suction type constant current sources I1', I2 ', I3' are external logic. Switching circuit SW1 which turns on / off according to a signal and pulse-drives the semiconductor laser drive current ILD
, SW2, SW3, the three pulse current drive circuits 51, 52, 53 are connected to the diodes d1, d2,
A bias constant current source I which is connected in parallel via d3 and supplies a predetermined DC current in accordance with an instruction from a current control circuit 54 which indicates a bias current I0 during recording and a read current during reproduction.
0, the recording data and a predetermined clock (here, a double frequency clock of the channel clock) are used to configure the recording circuit 55 to convert the recording data into logical signals D1, D2 and D3 in FIG.

Also in this embodiment, the constant current sources I1, I
1'is set to be larger than the currents of the other constant current sources I2, I2 ', I3 and I3'. That is, I1 >> I2, I
3 or I1 '>>I2', I3 '. Further, the outputs and the extraction currents of the constant current sources above and below the pulse current drive circuits 51, 52 and 53 are set to be equal. That is, I
1 = I1 ', I2 = I2', I3 = I3 '. Here, for simplification, the current source and its current are indicated by the same reference numeral.

Further, the logic circuit 55 uses the recording data D of the pulse current drive circuit 51 having the largest semiconductor laser drive current.
1 is configured to generate a logic signal including both timing information that determines the front and rear edges of the recording domain. Reference numeral 56 indicates a constant current circuit for bias.

Next, the semiconductor laser drive circuit 5 of this embodiment
The operation of No. 7 will be described. During reproduction, the switching circuit SW1 in the pulse current drive circuits 51, 52, 53
, SW2, SW3 are all on (D1, D2, D3
Is set to a high state, and each constant current source I1, I2, I3,
The set currents of I1 ', I2', and I3 'are set to 0 [mA], and a predetermined read current is supplied from the bias constant current source I0 according to an instruction from a current control circuit (not shown).

At the time of erasing, in addition to the bias current of the bias constant current source I0 or the threshold current Ith of the semiconductor laser 12 at the time of reproducing, the pulse current drive circuit 51 having the highest current supply capability is shown below. The switching circuit SW1 is turned off (D1 is low), a predetermined constant current is superposed on the bias current by the instruction voltage V1 from the outside by the constant current source I1, and the erase current necessary for erasing is supplied to the semiconductor laser 12. .

Of course, all pulse current drive circuits 5
1, 52, 53 switching circuits SW1, SW2, S
A constant current is supplied from the constant current sources I1, I2, and I3 with W3 all turned off (D1, D2, and D3 are low) to the bias current or the semiconductor laser 12 by a predetermined constant voltage V1, V2, and V3. An erase current necessary for erasing may be supplied to the semiconductor laser 12 by superimposing it on the threshold current Ith.

At the time of recording, as in the case of erasing, the threshold current Ith of the semiconductor laser 12 is added as a bias current from the bias constant current source I0, and a semiconductor laser drive current as shown in FIG. 8 is applied to each pulse current drive circuit. The added current of 51, 52 and 53 is supplied to the semiconductor laser 12.

Therefore, as shown in FIG. 7, first, the current value of the constant current source of each semiconductor laser drive circuit 51, 52, 53 is set by the external instruction voltages V1, V2, V3. With this setting, I1 >> I2, I3. However, I1 = I1
', I2 = I2', I3 = I3 '.

Next, write data from the host computer and recording frequency (channel clock) 2 as shown in FIG.
The double frequency clock is input to the logic circuit 55 of FIG.
The logic circuit 55 uses the switching circuits S as shown in FIG. 8 according to the write data in these two input signals.
Input signals D1, D2 and D3 of W1, SW2 and SW3 are generated. Further, the logic circuit 55 uses the recording data D1 of the pulse current drive circuit 51 having the largest semiconductor laser drive current.
Is generated including the timing information (for example, times t1 and t2 in FIG. 8) that determines the front and rear edges of the recording domain.

Further, the current supply amount of each pulse current drive circuit is I1> as in the equations (1) and (2) described in the first embodiment.
Since> I2 and I3, the switching data D1 is most dominant to the recording domain length, and therefore the characteristic variation of the elements used in the transmission system between the input signals D1, D2 and D3 of each switching circuit and the logic circuit 55. When a deviation between the data is generated due to, for example, each switching data is deviated at the timing of determining the front and rear edges of the recording domain, and the semiconductor laser drive current waveform becomes stepwise as shown in FIG.

However, since most of the amplitude changes from I1 >> I2 and I3 at the timing of the switching data D1, the timing to reach the Curie temperature at which the recording domain is formed depends on the switching data D1 as in the first embodiment. . Therefore, the influence of the data shift between the respective switching data due to the data skew and the like on the semiconductor laser drive current is small.

As a concrete circuit of the logic circuit 55 for realizing the present embodiment, the inverted output of FIG. 5 may be used. The logic circuit 55 may be constituted by a PLD having a relatively small data-to-data skew. As a result, the semiconductor laser drive current I of the current amplitude I1, I2, I3 according to the inversion signal of the switching data D1, D2, D3 is applied to each pulse current drive circuit.
The LD is supplied to the semiconductor laser 12 via the diodes d1, d2 and d3.

However, in each pulse current drive circuit, in the transition region (region which is neither ON nor OFF) in the switching operation of the NPN transistor of the switching circuit, the constant current sources I1 ', I2' and I3 'on the extraction side (lower side) are connected. The predetermined current is not supplied and the operation becomes unstable. Therefore, the current balance between the constant current sources is disturbed, which affects other pulse current drive circuits, causing distortion in the semiconductor laser drive current waveform.

Therefore, in the present embodiment, the diodes d1, d2 and the diodes d1, d2 are provided between each pulse current drive circuit and the semiconductor laser.
By inserting d3, even if the extraction current amount of the constant current source on the extraction side (lower side) of one of the pulse current drive circuits becomes excessive, the semiconductor laser drive current of the other pulse current drive circuits is not extracted, and the semiconductor laser drive current is not extracted. It realizes laser protection and prevention of interference between each pulse current drive circuit.

The configuration of each switching circuit of the pulse current drive circuit is generally a symmetrical circuit with NPN transistors as shown in FIG. 10C, and the operation is stable. However, in the case of such a circuit configuration,
Even if the driving current is not supplied to the semiconductor laser 12, unless the indicating voltage of the lower constant current sources I1 ', I2', I3 'is 0 V and the extraction current value is 0 [mA], the same current is wastefully supplied to GND. Has been done.

When the input signal of the switching circuit and the current amplitude of each pulse current drive circuit are set as in this embodiment, the current in the shaded portion of the semiconductor LD drive current waveform of FIG. 8 is supplied to GND, causing a current loss. Becomes However, according to the conventional method as shown in FIG.
In FIG. 10, the comb-shaped portion (high section of SW3 in FIG. 10) has a large current loss. Therefore, according to the present embodiment, the current loss is small and the power consumption is also advantageous.

As described above, when a plurality of pulse current drive circuits are combined to drive a semiconductor laser, the logic circuit 55 according to the present embodiment decomposes the write data to operate the pulse current drive circuits, and thereby The interference between the pulse current drive circuits is completely prevented by the diodes d1, d2 and d3, and low power consumption is realized. Further, it is possible to realize the switching operation that is less affected by the signal shift between the respective input signals, and to record the domain with less length shift and jitter.

Next, a fourth embodiment of the present invention will be described. Figure 9
(A) is a configuration of a semiconductor laser drive circuit 60 according to a fourth embodiment of the present invention. The semiconductor laser driving circuit 60 outputs a predetermined output current to the semiconductor laser 12 in accordance with externally indicated voltages V1, V2 and V3.
2, I3, a second constant current source I1 ', I2', I3 'for extracting a current amount substantially equal to that of the first constant current sources I1, I2, I3 from the semiconductor laser drive current, and the second constant current source I1', I2 ', I3'. Switching circuits SW1, SW2 for turning on / off the extraction currents of the current sources I1 ', I2', I3 'in accordance with a logic signal from the outside and for pulse driving the semiconductor laser drive current.
Three pulse current drive circuits 61 composed of SW3,
62 and 63, a constant current source for biasing I0 for supplying a bias current to the semiconductor laser 12, write data and a channel clock or a clock that is an integer multiple of the channel clock, and the write data is supplied to each of the pulse current drive circuits by logic. A signal conversion circuit 65 for converting into a signal.

FIG. 9B shows a configuration example of the signal conversion circuit 65. The signal conversion circuit 65 includes two memories 66, 67 and 2
It is composed of two logic circuits 68 and 69. The write data D0 is once stored in the memory 66, and is stored in the memory 66.
Write data D0 is output to the logic circuits 68 and 69. The logic circuit 68 uses the write data D0 from the memory 66.
To generate data D1, D2 and D3 in synchronization with the clock and output them to the logic circuit 69 and the memory 67.

The logic circuit 69 uses the data D1, D2, D3.
The write data is generated from the write data and the write data input from the memory 66 is confirmed. When it is confirmed that they match (or there is no difference), an output permission signal is output to the memory 67 and the memory 6
The data D1, D2, and D3 stored from 7 are output. Pulse current drive circuits 61, 6
2, 63 and the biasing constant current source I0 have the same configurations and operations as those in the third embodiment, and therefore the description thereof is omitted here.

First, the operation of the signal conversion circuit 65 will be described. Write data from the host computer as shown in FIG. 8 and a clock having a frequency twice as high as the recording frequency (channel clock) here are input to the signal conversion circuit 65 of FIG. This signal conversion circuit 65 is provided with each switching circuit SW as shown in FIG. 8 according to the write signal from the two input signals.
Input signals D1, D2 and D3 of 1, SW2 and SW3 are generated.

Here, the signal conversion circuit 65 once inputs and stores the write data D0 in the memory 66. Memory 6
The write data D0 input to 6 is input to the logic circuit 68. Based on the write data D0 and the clock input, the logic circuit 68 determines the timing data for determining the recording data D1 of the pulse current driving circuit 61 having the largest semiconductor laser driving current (for example, time t in FIG. 8).
The write data is converted so that it becomes a logic signal including both 1 and t2. The specific circuit of the logic circuit 66 may be the circuit shown in FIG.

Next, the output signal D1, of the logic circuit 68 is
D2 and D3 are input to the logic circuit 69 and the memory 67. The output signal of the logic circuit 68 is reconverted into the write data by the logic circuit 69 again, and it is compared with the write data from the host computer stored in the memory 66 for comparison.

As a result of the comparison, the logic circuit 69 which confirms that there is no difference outputs to the memory 67 that the output signals D1, D2 and D3 have no abnormality. The memory 67 receiving the signal from the logic circuit 69 outputs the switching signals D1, D2 and D3 in accordance with the input clock. As a result, the same operation as that of the third embodiment can be obtained in the circuit of FIG. Here, a similar function may be realized by using a CPU as the signal conversion circuit 65.

Therefore, the signal conversion circuit 6 according to the present embodiment.
Similar to the third embodiment, the conversion of the switching circuit data by 5 suppresses the interference of each pulse current drive circuit, and enables the operation without breaking the current balance of the constant current source for the inflow and extraction of each pulse current drive circuit. . In addition, the switching operation in which the deviation between the signals between the respective input signals has the least influence on the recording domain is realized, and the recording of the domain with the small length deviation and the small jitter is realized.

In the above embodiment, one current source among the plurality of current sources has the first current source having the timing information that determines both the front and rear edges, and is always recorded by the first current source. Although it has been described that the edge of the mark is determined, it is sufficient that at least one current source has such characteristics.

[0078]

As described above, according to the present invention, at least two or more currents are superposed in a semiconductor laser driving circuit used in an optical recording device for recording at least information by using a semiconductor laser as a light source. In the semiconductor laser drive circuit for performing mark edge recording, at least one current source has a first current source having timing information that determines both front and rear edges, and the first current source always supplies the recording mark. Since the edge is determined and the amount of current from the first current source is set to be larger than the amounts of current from other current sources, even if a deviation occurs between data due to variations in the transmission system or elements, Since the edge of the recording mark is predominantly determined by the current source No. 1, the recording mark having less influence can be recorded.

Further, in a semiconductor laser drive circuit of an optical recording apparatus for recording at least information using a semiconductor laser as a light source, at least one constant current source for supplying a predetermined output current according to an instruction voltage from the outside, and an externally supplied constant current source. Two or more pulse current drive circuits composed of at least one switching element for selectively supplying the output current of the constant current source to the semiconductor laser in accordance with the above signal, and at least one logic for recording data and a predetermined clock signal. A logic circuit for converting into a logic signal for turning on / off the switching element so that the signal output includes timing information for determining the front and rear edge positions of the recording domain, and for supplying a bias current to the semiconductor laser. A timing controller configured by a constant current source and determining edge positions before and after the recording domain. Since the amount of current passing through at least one switching element that receives a logical signal containing both information as an input signal is larger than the amount of current passing through other switching elements, the edge positions before and after the recording domain are Since the recording domain is predominantly determined by the amount of current passing through the switching element whose input signal is a logic signal including both the timing information to be determined, even if there are variations in the transmission system or elements, the effect is Edge recording can be performed without receiving much.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor laser drive circuit according to a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the semiconductor laser drive circuit of the first embodiment.

FIG. 3 is an explanatory diagram of an operation expected when there is a timing shift between a plurality of input signals in the first embodiment.

FIG. 4 is a configuration diagram of a semiconductor laser drive circuit according to a second embodiment of the present invention.

FIG. 5 is a specific circuit diagram of a logic circuit.

FIG. 6 is an operation explanatory diagram of the semiconductor laser drive circuit of the second embodiment.

FIG. 7 is a configuration diagram of a semiconductor laser drive circuit according to a third embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of the semiconductor laser drive circuit of the third embodiment.

FIG. 9 is a configuration diagram of a semiconductor laser drive circuit and a signal conversion circuit according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a laser drive waveform and a laser drive circuit of a conventional example.

11 is an explanatory diagram of the operation of FIG.

FIG. 12 is an explanatory diagram of an operation expected when there is a timing shift between a plurality of input signals in the conventional example.

[Explanation of symbols]

 11 ... Semiconductor laser drive circuit 12 ... Semiconductor laser 13 ... Current control circuit 14 ... CPU 15 ... Clock generator I0, I1, I2, I3 ... Current source

Claims (3)

[Claims] 1. A semiconductor laser drive circuit used in an optical recording device for recording at least information using a semiconductor laser as a light source, wherein the semiconductor laser drive circuit performs mark edge recording by superimposing at least two currents. , At least one current source has a first current source having timing information for determining both front and back edges, said first current source always determining the edge of the recording mark,
A semiconductor laser drive circuit, wherein the amount of current from the first current source is larger than the amounts of current from other current sources. 2. A semiconductor laser drive circuit of an optical recording apparatus for recording at least information using a semiconductor laser as a light source, comprising at least one constant current source for supplying a predetermined output current according to an instruction voltage from the outside, and an external source. Two or more pulse current drive circuits composed of at least one switching element for selectively supplying the output current of the constant current source to the semiconductor laser in accordance with the above signal, and at least one logic for recording data and a predetermined clock signal. A logic circuit for converting into a logic signal for turning on / off the switching element so that the signal output includes timing information for determining the front and rear edge positions of the recording domain, and for supplying a bias current to the semiconductor laser. Timing information configured by a constant current source and determining edge positions before and after the recording domain The semiconductor laser drive circuit is characterized in that the amount of current passing through at least one switching element having a logic signal as an input signal including any of the above is larger than the amount of each current passing through other switching elements. 3. The semiconductor laser drive circuit according to claim 2, wherein the two or more pulse current drive circuits and the semiconductor laser are connected in parallel via diodes.