JP5120287B2 - Laser drive device, optical unit, optical device - Google Patents

Description

  The present invention relates to a laser driving device (laser driving circuit), an optical unit, and an optical device.

  Recording / reproducing apparatuses using a laser as a light source are used in various fields. For example, an optical disk recording / reproducing apparatus (hereinafter also simply referred to as an optical disk apparatus) that uses an optical disk as a recording / reproducing medium using a laser driving device or an optical unit has attracted attention.

  As a laser used as a light source, a semiconductor laser using a semiconductor material is extremely small and responds to a drive current at a high speed, so that it has been widely used in various devices in recent years.

  As a writable optical disk used as a recording or reproducing medium, a phase change optical disk, a magneto-optical disk, or the like is widely known. In these optical disks, recording, reproduction, and erasing are performed by changing the intensity of the irradiated laser beam. Usually, when information is recorded on an optical disc, a so-called light intensity modulation method is used in which a mark / space is formed on a recording medium by changing the intensity of a laser beam. At this time, the optical disk is irradiated with a laser beam having a high intensity such as a peak of 30 mW or more. During reproduction, the optical disk is irradiated with a laser beam having a weaker intensity (for example, 1 mW) than that during recording so that information can be read without destroying the recording mark.

  In recent writable optical discs, mark edge recording in which information is provided at both ends of a recording mark has become mainstream because of its superiority in increasing the density. In mark edge recording, a data error occurs due to the distortion of the shape of the mark. Therefore, in order to perform recording with few errors, a write strategy technique is known in which the recording power is pulse-divided and controlled to have multiple levels (see, for example, Patent Document 1 and Non-Patent Document 1).

JP 2007-141406 A

“Industry-leading low noise and high-speed response Blu-ray 8x speed recording and playback technology barrier”, CX-PAL74, [online], Sony Corporation, [searched on August 18, 2008] , Internet <URL: http://www.sony.co.jp/Products/SC-HP/cx_pal/vol74/pdf/featuring2_bd.pdf>

  The optical disc apparatus is composed of a pickup that is a movable part and a signal control system that is a fixed part. In general, the laser drive unit is disposed in the vicinity of a semiconductor laser mounted on a pickup, and the signal control system to the laser drive system are connected by a flexible printed board (flexible board). Usually, the write strategy circuit is mounted on a signal control system that is a fixed part, and the light emission timing signal of each power level is transmitted to the pickup through the flexible substrate.

  In this configuration, the frequency of the light emission timing signal transmitted through the flexible substrate increases as the recording speed increases. At this time, the transmission band is limited by the flexible substrate, and the interval between the light emission timing signals cannot be transmitted accurately, which hinders the improvement of the recording speed. Furthermore, write strategies tend to become more complex in order to achieve high-density and high-speed recording. In addition to increasing the transfer rate, it is required to subdivide the pulse division width or increase the number of power levels.

  In the conventional configuration, as the number of power levels increases, the number of lines for laser drive control increases and the flexible substrate (width) increases, and the transmission band resulting from the length to secure and route the arrangement space A degradation problem occurs. When laser light emission power control is performed, there arises a problem of how to transmit a feedback signal for controlling the light emission power and a sampling pulse.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a mechanism that can solve the problems of the number of signal transmissions and a decrease in transmission band when the write strategy technology is adopted. . It is also an object of the present invention to provide a new mechanism for generating and transmitting a light emission power control signal (feedback signal or sample pulse), preferably taking into account the application of the write strategy technique.

  In the mechanism according to the present invention, first, a recording waveform control signal pattern indicating level information about the light emission waveform of the laser element is stored in the light emission level pattern storage unit. Here, the recording waveform control signal pattern indicates level information for each of the drive signals divided to drive the laser element based on the drive signals divided into a plurality of spaces and marks. In other words, the pattern of the light emission waveform is a combination of drive signals in which both spaces and marks are divided into a plurality, at least in the information recording area. In other words, a mechanism is adopted in which the recording power is divided into pulses and converted to multilevel levels.

  In the pulse generation unit, the first transmission signal indicating the information for specifying the acquisition timing of the reference pulse indicating the switching timing of the space and the mark, and the acquisition timing of the switching pulse indicating the switching timing of the divided drive signals A reference pulse and a switching pulse are generated by detecting an edge of each transmission signal based on the second transmission signal including information defining the above.

  Then, among the power level information of the light emission waveform stored in the light emission level pattern storage unit, the reference level information which is the level information of the reference pulse position is read for each reference pulse, and other level information following the reference level information is read. Read sequentially for each switching pulse.

  The recording waveform control signal pattern when applying the write strategy technology is stored in advance in the light emission level pattern storage unit, the reference pulse and the switching pulse are generated using the two types of transmission signals, and the reference level is determined at the timing of the reference pulse. In this method, information is read and the remaining level information is sequentially read for each switching pulse. This is a simple system comprising two types of transmission signals and power level information stored in order in the recording waveform control signal pattern in the light emission level pattern storage unit. The reference level information is read for each reference pulse, and then other level information is read for each switching pulse until the reference pulse is acquired again.

  Here, the present invention includes the second storage unit. As the configuration of the second storage unit, a plurality of sub-storage units that store a plurality of different setting information, and a main storage unit that selectively stores any setting information stored in the plurality of sub-storage units And a storage information control unit that selects any setting information stored in the plurality of sub storage units and stores the selected setting information in the main storage unit.

  As a method of handling the second storage unit, a first method of storing a plurality of recording waveform control signal patterns in each sub storage unit (configuration in which the second storage unit is also used as the light emission level pattern storage unit), recording A second method for storing a plurality of setting information when generating a sampling pulse based on a light emission waveform with one waveform control signal pattern in each sub storage unit (the second storage unit is also used as a sampling pulse pattern storage unit) Any of the methods of combining them can be adopted.

  As a signal for controlling selection of a plurality of sub storage units, there is a first method that uses a plurality of reference pulses based on a plurality of first transmission signals as selection pulses. When a plurality of second transmission signals are used and a switching pulse immediately before and after the reference pulse is based on the edge of the same second transmission signal, a selection pulse is generated based on the switching pulse immediately after the reference pulse, and the reference pulse There is also a second method for switching selection using a selection pulse.

  According to one embodiment of the present invention, since there are few types of signals to be transmitted, problems with the number of transmissions and a decrease in transmission bandwidth are solved. This is because the obstacle caused by the length for securing and routing the signal line is alleviated. In addition, the power level of the light emission waveform and the setting of the sampling pulse can be switched by using information stored in the plurality of sub storage units.

It is a figure which shows one structural example of the recording / reproducing apparatus which is an example of an optical apparatus. It is a figure explaining the structural example of an optical pick-up. It is a figure explaining a write strategy. It is a figure explaining the 1st comparative example of the signal interface method to which a write strategy is applied. It is a figure explaining the 2nd comparative example of the signal interface method to which a write strategy is applied. It is a figure explaining the 3rd comparative example of the signal interface method to which a write strategy is applied. It is a figure which shows the system configuration | structure (1st example) of this embodiment. It is a figure which shows the system configuration | structure (2nd example) of this embodiment. It is a figure explaining the basic principle of this embodiment to which a write strategy is applied. It is a figure which shows the laser drive circuit which implement | achieves the laser drive system of a basic composition. It is a figure explaining the relationship between the memory information of the memory circuit used for the laser drive circuit of a basic composition, and a current switch. It is a figure (1st example) explaining operation | movement of the laser drive circuit of a basic composition. It is a figure (2nd example) explaining operation | movement of the laser drive circuit of a basic composition. It is a figure explaining the register setting information corresponding to the recording waveform control signal pattern shown to FIG. 4B and FIG. 4C. It is a figure explaining the structural example of the transmission signal generation part of 1st Embodiment. It is a figure explaining operation | movement of the transmission signal generation part of 1st Embodiment. It is a figure which shows the laser drive circuit of 1st Embodiment. It is a figure (1st example) explaining operation | movement of the laser drive circuit of 1st Embodiment. It is a figure (2nd example) explaining operation | movement of the laser drive circuit of 1st Embodiment. It is a figure explaining the register setting information corresponding to the recording waveform control signal pattern shown to FIG. 5C and FIG. 5D. It is a figure explaining the edge transition direction detection function of the comparative example with respect to the edge continuous detection function of this embodiment. It is a figure explaining the structural example of the transmission signal generation part of 2nd Embodiment. It is a figure explaining operation | movement of the laser drive circuit of 2nd Embodiment. It is a figure explaining the register setting information corresponding to the recording waveform control signal pattern shown to FIG. 6A. It is a figure explaining the structural example of the transmission signal generation part of 3rd Embodiment. It is a figure explaining operation | movement of the laser drive circuit of 3rd Embodiment. It is a figure explaining the register setting information corresponding to the recording waveform control signal pattern shown to FIG. 7A. It is a figure explaining the structural example of the transmission signal generation part of 4th Embodiment. It is a figure explaining operation | movement of the laser drive circuit of 4th Embodiment. It is a figure explaining the register setting information of the memory circuit corresponding to the recording waveform control signal pattern shown to FIG. 8A. It is a figure explaining the structural example of the transmission signal generation part of 5th Embodiment. It is a figure explaining the power level pattern for APC. It is a figure explaining operation | movement of the transmission signal generation part of 5th Embodiment. It is a figure which shows the laser drive circuit of 5th Embodiment. It is a figure (1st example) explaining operation | movement of the laser drive circuit of 5th Embodiment. It is a figure (2nd example) explaining operation | movement of the laser drive circuit of 5th Embodiment. It is a figure explaining the register setting information of the memory circuit corresponding to the recording waveform control signal pattern shown to FIG. 9C. It is a figure explaining the 1st example of a setting of a sampling pulse. It is a figure explaining the 2nd example of a setting of a sampling pulse. It is a figure (1st example) explaining the register setting information of 6th Embodiment. It is a figure (2nd example) explaining the register setting information of 6th Embodiment. It is a figure (3rd example) explaining the register setting information of 6th Embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. When distinguishing each functional element according to the embodiment, an uppercase English reference such as A, B, C,... Is added and described. Omitted and listed. The same applies to the drawings. The description will be given in the following order.

1. 1. Outline of configuration of recording / reproducing apparatus 2. Signal interface problems and principles of countermeasures 3. System configuration of signal interface Basic of sequential method (one reset signal RS and one edge signal ES)
5. First embodiment (one reset signal RS and two edge signals ES)
6). Second embodiment (land groove recording system)
7). Third Embodiment (Power Level Pattern Switching for CAV / ZCLV Recording)
8). Fourth Embodiment (OPC recording power adjustment)
9. Fifth embodiment (APC emission power adjustment)
Ten. Sixth embodiment (sampling pulse setting switching)

<Recording and playback device>
FIG. 1 is a diagram illustrating a configuration example of a recording / reproducing apparatus (optical disk apparatus) which is an example of an optical apparatus. FIG. 1A is a diagram illustrating a configuration example of an optical pickup.

  As an optical disk OD (Optical Disk), in addition to a so-called read-only optical disk such as a CD (Compact Disk) and a CD-ROM (Read Only Memory), a write-once optical disk such as a CD-R (Recordable), a CD- A rewritable optical disk such as RW (Rewritable) may be used. Furthermore, it is not limited to a CD-based optical disk, but may be an MO (magneto-optical disk), a normal DVD (Digital Video or Versatile Disk), or a next-generation DVD using a blue laser with a wavelength of about 405 nm, for example. It may be a DVD-type optical disc. The DVD system includes DVD-RAM / -R / + R / -RW / + RW. Further, it may be a so-called double density CD (DDCD; DD = Double Density), CD-R, or CD-RW in which the recording density is approximately double that of the current format while following the current CD format. .

  The recording / reproducing apparatus 1 of this embodiment includes an optical pickup 14 and a pickup control unit 32. The optical pickup 14 records information on the optical disc OD or reproduces information. The optical pickup 14 is controlled by the pickup control unit 32 and controls the radial position (tracking servo) and the focal direction position (focus servo) of the laser beam emitted from the optical pickup 14 with respect to the optical disc OD.

  The recording / reproducing apparatus 1 includes a spindle motor 10, a motor driver 12, and a spindle motor control unit 30 as a rotation control unit (rotation servo system). The spindle motor 10 rotates the optical disc OD, and the number of rotations is controlled by the spindle motor control unit 30. The recording / reproducing apparatus 1 includes, as a recording / reproducing system, an information recording unit that records information via an optical pickup 14 and a recording / reproducing signal processing unit that is an example of an information reproducing unit that reproduces information recorded on an optical disc OD. 50. The recording / reproduction signal processing unit 50 and the optical pickup 14 are connected via a signal wiring pattern formed on a flexible substrate 51 as an example of a transmission member that transmits a signal.

  The recording / reproducing apparatus 1 includes, as a controller system, a controller 62 and an interface unit that performs an interface function that is not illustrated. The controller 62 is configured by a microprocessor (MPU: Micro Processing Unit), and controls the operation of the servo system having the spindle motor control unit 30 and the pickup control unit 32 and the recording / reproduction signal processing unit 50. The interface unit has an interface (connection) function with a personal computer (hereinafter referred to as a personal computer) which is an example of an information processing apparatus (host apparatus) that performs various types of information processing using the recording / reproducing apparatus 1. A host IF controller is provided in the interface unit. The recording / reproducing apparatus 1 and the personal computer constitute an information recording / reproducing system (optical disc system).

[Optical pickup]
As shown in FIG. 1A, the optical pickup 14 includes a semiconductor laser 41, a beam splitter 42, a lens 43, a mirror 44, a light detection unit 45, and a drive current control unit 47 which is an example of a laser drive device. The drive current control unit 47 is configured by a laser drive IC (LDD) as an example. As an example, the semiconductor laser 41 and the drive current control unit 47 are connected via a signal wiring pattern formed on the flexible substrate 46.

  The drive current control unit 47 receives a recording pulse corresponding to the write strategy from the digital signal processing unit 57 of the recording / reproduction signal processing unit 50, and a laser power instruction voltage PW from the APC control unit 58 via the flexible substrate 51. Is transmitted. The drive current control unit 47 combines the recording pulse corresponding to the write strategy and the laser power instruction voltage PW for APC control to generate a recording waveform, amplifies the recording waveform, and drives the semiconductor laser 41.

  The semiconductor laser 41 emits a laser beam for recording additional information on the optical disc OD or reading information recorded on the optical disc OD. The beam splitter 42 passes or reflects the laser light from the semiconductor laser 41 and the reflected light from the optical disk OD. The mirror 44 reflects laser light and reflected light in a direction of about 90 degrees.

  The light detection unit 45 includes a first light detection unit 45a and a second light detection unit 45b. The first light detection unit 45a is configured by a photo detector IC (PDIC), and the second light detection unit 45b is configured by a front monitor photo detector IC (FMPDIC) as an example. The first light detection unit 45a acquires an RF signal for reproduction signal processing (including servo processing), and the second light detection unit 45b acquires a power monitor signal PM for APC control. Although not shown, each of the first light detection unit 45a and the second light detection unit 45b includes a light receiving element, a current-voltage conversion unit, and an amplification unit. Further, as will be described in detail later, the second light detection unit 45b of the present embodiment has a sample and hold circuit that samples and holds the power monitor signal PM output from the amplification unit and acquires the power monitor voltage PD.

  The laser light emitted from the semiconductor laser 41 passes through the lens 43a and the beam splitter 42, is reflected by the mirror 44a toward the optical disc OD side, is condensed by the lens 43b, and irradiates the optical disc OD. The reflected light reflected by the optical disk OD passes through the lens 43b, is reflected by the mirror 44a to the beam splitter 42 side, is reflected by the beam splitter 42 to the mirror 44b side, and is further reflected by the mirror 44b and is reflected by the first light detection unit. Incident at 45a. The first light detection unit 45a converts this incident light into an electric signal, amplifies it, and acquires an RF signal. The RF signal is transmitted to the recording / reproducing signal processing unit 50 via the flexible substrate 51.

  A part of the laser light emitted from the semiconductor laser 41 is reflected by the beam splitter 42 toward the second light detection unit 45b and enters the second light detection unit 45b. The second light detection unit 45b converts the incident light into an electric signal and amplifies it to obtain the power monitor signal PM, and further samples and holds the power monitor signal PM to obtain the power monitor voltage PD. The power monitor voltage PD is transmitted to the APC control unit 58 of the recording / reproduction signal processing unit 50 via the flexible substrate 51.

[Recording / Signal Processing Unit]
The recording / reproduction signal processing unit 50 includes an RF amplification unit 52, a waveform shaping unit 53 (waveform equalizer; Equalizer), and an AD conversion unit 54 (ADC; Analog to Digital Converter). The recording / reproduction signal processing unit 50 includes a clock reproduction unit 55, a write clock generation unit 56, a digital signal processing unit 57 composed of a DSP (Digital Signal Processor), and an APC control unit 58 (Automatic Power Control). Is provided.

  The RF amplifier 52 amplifies a minute RF (high frequency) signal (reproduced RF signal) read by the optical pickup 14 to a predetermined level. The waveform shaping unit 53 shapes the reproduction RF signal output from the RF amplification unit 52. The AD conversion unit 54 converts the analog reproduction RF signal output from the waveform shaping unit 53 into digital reproduction RF data Din.

  The clock recovery unit 55 includes a data recovery type phase synchronization circuit (PLL circuit) that generates a clock signal synchronized with the reproduction RF data Din output from the AD conversion unit 54. The clock recovery unit 55 supplies the recovered clock signal to the AD conversion unit 54 as an AD clock CKad (sampling clock), and also supplies it to other functional units.

  The digital signal processing unit 57 includes, for example, a data detection unit and a demodulation processing unit as a function unit for reproduction. The data detection unit performs processing such as PRML (Partial Response Maximum Likelihood) and detects digital data from the reproduction RF data Din.

  The demodulation processing unit demodulates the digital data sequence and performs digital signal processing such as decoding digital audio data and digital image data. For example, the demodulation processing unit includes a demodulation unit, an error correction code (ECC) correction unit, an address decoding unit, and the like, and performs demodulation / ECC correction and address decoding. The demodulated data is transferred to the host device via the interface unit.

  The write clock generator 56 generates a write clock for modulating data when recording on the optical disc OD based on a reference clock supplied from a crystal oscillator or the like. The digital signal processing unit 57 includes an ECC encoding unit and a modulation processing unit as recording functional units. The digital signal processing unit 57 generates recording data, and further generates a light emission timing signal of each power level corresponding to the write strategy.

  The APC control unit 58 of the recording / reproducing signal processing unit 50 has a function of controlling the light emission power of the semiconductor laser 41 to be constant based on the power monitor voltage PD, and the laser power instruction voltage PW is changed to the drive current control unit 47 of the optical pickup 14. To supply. During the recording / reproducing operation of the optical disk OD, APC is generally performed to adjust the laser emission power. APC is, for example, temperature dependent on the light emission characteristics of the semiconductor laser 41, and the light emission power can change even with the same drive current. Therefore, the relationship between the current and the light emission amount is calculated, and the predetermined light emission amount is It is to adjust the obtained drive current.

  During the recording operation, the APC monitors the light emission waveform with the light receiving element, samples and holds it at the timing when the level of the mark portion and the space portion of the monitoring waveform is settled, and obtains the power monitor voltage PD. The power monitor voltage PD is transmitted to the APC control unit 58, and the laser power instruction voltage PW is sent to the drive current control unit 47 so as to obtain a predetermined light emission amount, thereby adjusting the drive current.

  The recording / reproducing apparatus 1 records the digital data output from the information source on the optical disc OD with the laser light emitted from the semiconductor laser 41, and reproduces the recorded information on the optical disc OD. The drive current controller 47 combines the recording pulse corresponding to the write strategy and the laser power instruction voltage PW for APC control to generate a recording waveform, amplifies the recording waveform, and drives the semiconductor laser 41.

<Signal interface problems and countermeasure principle>
2 to 2C are diagrams for explaining the basic principle of the problem of the signal interface and the countermeasure technique. FIG. 2 is a diagram illustrating an example of a laser driving method to which the write strategy technique is applied. 2A to 2C are diagrams illustrating a first comparative example to a third comparative example of the signal interface method when the semiconductor laser 41 is driven by applying the write strategy technique.

  As an optical disk recording method, when information is recorded on an optical disk medium, recording is performed by a so-called light intensity modulation method in which a mark / space is formed on the recording medium by a change in intensity of light power. In order to perform recording with few errors, the intensity change of the optical power uses not the recording data itself but a waveform as shown in FIG. 2, for example.

  In the multi-pulse method, a recording clock is divided to emit pulses. In this example, there are three power levels: Cool, Erase, and Peak. The castle method is mainly used in high-speed recording, and does not emit pulses in units of recording clocks, but raises the laser power at the beginning and end of the mark. In this example, there are four power levels, cool, erase, peak, and overdrive (Over Drive), which are increased compared to the multi-pulse system. The timing of each edge is adjusted in units smaller than the channel clock interval (Tw). For example, Tw / 40, Tw / 32, Tw / 16, etc. The idea of the light emission pattern is called recording compensation (write strategy technique), and the recording compensation circuit (write strategy circuit) generates the timing of each edge according to the recording data.

  In each of the following embodiments, a castle method is applied as a laser emission waveform unless otherwise specified. This is because the castle method is common for high-speed recording. However, the mechanism of each embodiment to be described later can be applied to a multi-pulse system. This is because the castle method and the multi-pulse method are different from each other only in the setting value of the power level at each pulse timing, and are common in the point that “the recording power is divided into pulses and controlled to a multi-value level”.

  On the other hand, as shown in FIGS. 2A to 2C, for example, the laser drive system 3 of the optical disk apparatus is divided into an optical pickup 14 (optical head) on which a semiconductor laser 41 and optical components are mounted, and a drive substrate on which a control circuit is mounted. ing. Since the optical pickup 14 is movable according to the radius of the optical disk OD, both are connected by the flexible substrate 51.

  In the first comparative example shown in FIG. 2A, the write strategy circuit 290X (light emission waveform pulse generation unit) is mounted on the drive substrate. In this case, a write strategy signal (also referred to as a recording pulse signal or a laser drive timing signal) for instructing the light emission timing corresponding to each power level and a laser power instruction voltage PW to the laser drive circuit 200X mounted on the optical pickup 14 from the drive substrate. Will be sent. The laser drive circuit 200X includes a light emission waveform generation unit 203 that generates a light emission waveform by synthesizing the write strategy signal and the laser power instruction voltage PW. The light emission waveform generation unit 203 causes the semiconductor laser 41 to emit light by generating a drive current by increasing or decreasing the power according to the laser power instruction voltage PW.

  Focusing on the APC control system, the detailed description of each part is omitted, but the power monitor circuit 300A on the optical pickup 14 side (corresponding to the second light detection unit 45b in FIG. 1A) is a current signal photoelectrically converted by the light receiving element 310. Is converted into a voltage signal to generate a power monitor signal PM. The power monitor signal PM is sent as a feedback signal for APC to the APC control unit 58 side as a differential signal (PM_P, PM_N). On the drive board side, the APC control unit 58A samples and holds the values of the writing period (mark position) and bias period (space position) of the power monitor signal PM to obtain the power monitor voltages PD_1 and PD_2. Based on the power monitor voltages PD_1 and PD_2, the APC control unit 58A obtains the optimum recording output level of the semiconductor laser 41, generates a laser power instruction voltage PW for maintaining the emission power of the semiconductor laser 41 constant, and generates an emission waveform. To the unit 203.

  In the first comparative example, the write strategy signal sent from the write strategy circuit 290X has timing information finer than the channel clock. However, the following problems associated with the recent increase in recording speed are problematic. The first point is that the number of transmission lines of the recording system increases as the power level increases. For example, in the figure, 4 to 5 channels corresponding to LVDS (Low Voltage Differential Signal) are shown. Second, it is difficult to accurately transmit the write strategy signal due to the frequency characteristic degradation (transmission band degradation) caused by the flexible substrate 51. This makes it impossible to accurately transmit the write strategy signal interval, which hinders improvement in recording speed. Further, as shown in FIG. 2A (2), edge shift due to intersymbol interference occurs in the shortest pulse (for example, about 1T).

  The power monitor signal PM is obtained by detecting laser light corresponding to the write strategy signal sent from the write strategy circuit 290X. Therefore, the power monitor signal PM also has a problem caused by the flexible substrate 51, like the write strategy signal. As shown in FIG. 2A (3), due to the frequency characteristics of the flexible substrate 51, the power monitor signal PM is deteriorated and it is difficult to accurately transmit it. In addition, delay variation occurs, and there is a problem that the sampling gate cannot be opened due to the shortening of the pulse due to the high speed.

  In the second comparative example shown in FIG. 2B, the write strategy circuit 290Y (light emission waveform pulse generation unit) is mounted not on the drive substrate but on a laser drive circuit 200Y including a circuit similar to the laser drive circuit 200X of the first comparative example. ing. The write strategy circuit 290Y generates a timing signal for controlling the optical power from the recording clock and the recording data. The timing signal is a unit smaller than the channel clock interval (Tw) and is generated for each power level, and the power level and the timing are associated one to one. A write strategy circuit 290Y for realizing this includes a phase synchronization circuit, a memory, an address encoder, and a timing generation circuit. The phase synchronization circuit generates a multiphase clock for generating a unit smaller than the channel clock interval (Tw). The memory stores level information. The address encoder determines the recording data length and generates a memory address. The timing generation circuit converts timing information read from the memory into a timing signal in accordance with the recording data length.

  Focusing on the APC control system, detailed description of each part is omitted, but in the second comparative example, the writing and holding values of the power monitor signal PM are sampled and held not on the drive substrate side but on the optical pickup 14 side. Then, the sampled and held power monitor voltages PD_1 and PD_2 are supplied to the APC control unit 58B. In this configuration, power monitor voltages PD_1 and PD_2 are sent to the APC controller 58 via the flexible substrate 51 as feedback signals for APC.

  In the second comparative example, the recording system signal transmitted by the flexible substrate 51 becomes a recording clock and recording data, and the problem of strategy transmission in the first comparative example is solved. For example, the number of LVDS channels for write strategy transmission is reduced, and both the recording clock and the recording data are signals in units of channel clocks, so that they are not easily affected by the transmission characteristics of the flexible substrate 51. In the APC control system, the sample hold unit 330 is mounted on the power monitor circuit 300B on the optical pickup 14 side so that transmission at the power monitor voltage PD is possible, and the power monitor signal PM is transmitted by the flexible substrate 51. The problem of the first example is solved. However, since the write strategy circuit 290Y includes a phase synchronization circuit, a memory, an address encoder, and a timing generation circuit, the laser drive circuit 200Y has a large scale, and there is a problem that power consumption increases and a problem of heat generation occurs.

  In the third comparative example shown in FIG. 2C, the write strategy circuit 290X is arranged in the recording / reproduction signal processing unit 50 as in the first comparative example, and the sample hold unit 330 is arranged in the power monitor circuit 300B as in the second comparative example. It is arranged. In this case, the recording system has the same problem as the first comparative example. In addition, the sampling pulse SP for sample hold is generated by the sampling pulse generation unit 400X attached to the write strategy circuit 290X, and the sampling pulse SP is transmitted to the sample hold unit 330 via the flexible substrate 51. Therefore, an increase in the number of flexible wirings and signal degradation of the sampling pulse SP due to flexible transmission become new problems. Furthermore, considering that LVDS is supported for high-speed transmission of the sampling pulse SP, the sample hold unit 330 needs to make the input circuit for the sampling pulse SP compatible with LVDS, which increases the number of terminals. .

  As described above, in the first to third comparative examples, the number of signal transmissions and the transmission band decrease or the write strategy circuit 290 is arranged in the laser driving circuit 200 in the recording signal transmission and the APC control signal transmission. There are difficulties in terms of circuit scale.

<Signal interface: System configuration>
3 to 3B are diagrams for explaining the signal interface method of the present embodiment. FIG. 3 is a diagram showing a system configuration (first example) for realizing the signal interface system of the present embodiment. FIG. 3A is a diagram showing a system configuration (second example) for realizing the signal interface system of the present embodiment. FIG. 3B is a diagram for explaining the basic principle of the laser driving method of this embodiment to which the write strategy technique is applied.

  In the laser drive system 3 of the present embodiment, as a technique for solving the problems of the number of transmissions and the transmission band, a mechanism that can solve the problem without increasing the circuit scale of the laser drive circuit as much as the second comparative example is adopted. . Preferably, a mechanism capable of solving the problems of the first to third comparative examples in the generation / transmission technique of the APC control signal and the sampling pulse SP while considering the application of the write strategy technique. .

  In the application of the write strategy technique, the basic idea of the technique is to first store the power level information (recording waveform control signal pattern) of laser emission at each timing when the write strategy technique is applied. The first transmission signal including information defining the reference pulse acquisition timing indicating the switching timing of the space and mark repetition, and the information specifying the acquisition timing of the switching pulse indicating the switching timing of the laser emission level The second transmission signal including is used. The first transmission signal and the second transmission signal are treated as the write strategy signal (recording pulse) in FIGS. 1 and 1A.

  A reference pulse and a plurality of switching pulses are generated using two types of pulse signals, the recording pulse control signal pattern is set to the initial level by the reference pulse, and then the write strategy technology is applied according to the recording waveform control signal pattern for each switching pulse. Switch to each emission power level. Then, every time a reference pulse is generated, the same processing as described above is performed again. Such a method is referred to as a sequential method in this specification.

  In the present embodiment, with respect to the recording system, transmission is performed while reducing the types of signal lines based on the signal interface system similar to that of the first comparative example in which the write strategy circuit 290 is arranged on the drive substrate side. The first example shown in FIG. 3 is a configuration example focusing only on the signal interface in the application of the write strategy technology. The second example shown in FIG. 3A is a configuration example that also pays attention to a method for generating and transmitting an APC control signal and a sampling pulse SP.

  In the first example illustrated in FIG. 3, the drive board includes a sequential transmission signal generation unit 500 at the subsequent stage of the write strategy circuit 290. The transmission signal generation unit 500 generates a first transmission signal and a second transmission signal based on a write strategy signal (for example, 4 to 5 ch) from the write strategy circuit 290. The first transmission signal includes information defining the acquisition timing of the reference pulse indicating the switching timing of space and mark repetition. The second transmission signal includes information defining the acquisition timing of the switching pulse indicating the switching timing of the divided drive signal. The transmission signal generator 500 supplies the first and second transmission signals to the laser drive circuit 200 via the flexible substrate 51.

  The laser drive circuit 200 on the optical pickup 14 side includes a pulse generation unit 202 that matches the transmission signal generation unit 500 of the digital signal processing unit 57, a light emission waveform generation unit 203, and a power monitor circuit 300. The pulse generator 202 generates a reference pulse and a switching pulse based on the first and second transmission signals transmitted through the flexible substrate 51. The light emission waveform generation unit 203 generates a current signal according to the recording waveform control signal pattern using the reference pulse and the switching pulse. The power monitor circuit 300 photoelectrically converts a part of the laser light emitted from the semiconductor laser 41, samples and holds it, acquires the power monitor voltage PD as a feedback signal for APC control, and sends it to the APC control unit 58.

  In the second example shown in FIG. 3A, the write strategy circuit is arranged on the fixed circuit board side, and the sampling pulse SP is generated on the optical pickup 14 side based on a signal that defines a light strategy light emission power pattern (waveform control signal pattern). Generate. That is, the sampling pulse SP is generated on the optical pickup 14 side based on the laser drive timing signal received by the laser drive circuit 200 that does not include the write strategy circuit 290 (light emission waveform pulse generation unit).

  The sampling pulse generation unit 400 includes a sampling pulse pattern storage unit 430 that stores setting information (pulse pattern) when generating the sampling pulse SP based on the write strategy signal. The sampling pulse generator 400 may be arranged in either the laser drive circuit 200 or the power monitor circuit 300, or may be arranged separately from the laser drive circuit 200 or the power monitor circuit 300. The sampling pulse generator 400 generates sampling pulses SP_1 and SP_2 based on the LVDS-compatible write strategy signal (2-3 ch) transmitted from the recording / reproduction signal processor 50 via the flexible substrate 51.

  As shown in FIG. 3B (2), in the sequential method, two types of input signals, a reset signal RS as a first transmission signal and an edge signal ES as a second transmission signal, are used as reference pulses. A reset pulse RP and an edge pulse EP as a switching pulse are generated.

  The first transmission signal (reset signal RS) is the same as the start edge (the edge pulse EP1 in FIG. 3B (1)) of the recording waveform control signal pattern in the laser drive circuit 200Y of the second comparative example having a built-in write strategy circuit. It is a signal indicating an edge. The second transmission signal (edge signal ES) is a signal indicating the same edge as that obtained by synthesizing other edge timings (edge pulses EP2, EP3, EP4, and EP5 in FIG. 3B (1)).

  As shown in FIG. 3B (3), information on each light emission power level indicating a recording waveform control signal pattern is stored in order in each register of the memory circuit. Based on the reset pulse RP, information on the reference power level is read out. Information on the light emission power level at each timing following the information on the reference power level is sequentially read based on the edge pulse EP.

  That is, the laser drive circuit 200 includes a sequential access memory with a reset function that operates at high speed, and holds each power level information in the order of reading. Then, each time the switching pulse (edge pulse EP) is generated, the light emission power level information is selected and read sequentially from the next of the reference power level information. Further, regardless of which light emission power level is selected, the information on the head area (reference power level information) is read at the timing when the reference pulse is generated by the reset function of the reference pulse (reset pulse RP).

  As shown in FIG. 3B, among the edge pulses EP1 to EP5 that define the recording waveform control signal pattern generated by the write strategy circuit 290, the edge pulse EP1 corresponds to the reset pulse RP. Therefore, the transmission signal generator 500 generates the reset signal RS based on the edge pulse EP1. Further, since the edge pulses EP2 to EP5 correspond to the edge pulse EP, the transmission signal generation unit 500 generates the edge signal ES based on the edge pulses EP2 to EP5.

  At this time, either the concept of defining the reset pulse RP with one edge of the reset signal RS or the concept of defining the reset pulse RP with both edges can be adopted. Similarly, either the concept of defining the edge pulse EP with one edge of the edge signal ES or the concept of defining the edge pulse EP with both edges can be adopted. The edge pulse EP is output more frequently than the reset pulse RP. Therefore, in this embodiment, a configuration defined by both edges of the edge signal ES is adopted at least for the edge pulse EP. As for the reset pulse RP, either the case where it is defined by one edge of the reset signal RS or the case where it is defined by both edges is taken.

  Hereinafter, in order to facilitate understanding of the mechanism of the present embodiment, the basic mechanism of the sequential method will be described first, and then the specific mechanism of the present embodiment will be described.

<Laser drive method: Basic of sequential method>
4 to 4D are diagrams for explaining a basic mechanism of a laser driving method employing a sequential method. FIG. 4 is a diagram showing a laser drive circuit (particularly corresponding to the drive current control unit 47 in FIG. 1A) that realizes the laser drive method of the basic configuration. FIG. 4A is a diagram for explaining the relationship between stored information and current switches in a memory circuit (light emission level pattern storage unit) used in the laser drive circuit having the basic configuration. 4B and 4C are diagrams for explaining the operation of the laser driving circuit having the basic configuration. FIG. 4D is a diagram illustrating register setting information of the memory circuit corresponding to the recording waveform control signal patterns shown in FIGS. 4B and 4C.

  In the basic configuration, one first transmission signal and one second transmission signal are supplied to the laser driving circuit 200 in the recording mode, and the semiconductor laser 41 is driven by the write strategy technique. As the first transmission signal, a reset signal RS in which the acquisition timing of the reference pulse indicating the switching timing of space and mark repetition is indicated by an edge is used. As the second transmission signal, an edge signal ES in which the switching pulse acquisition timing indicating the switching timing of the laser emission level is indicated by an edge is used.

[Circuit configuration: Basic configuration]
As shown in FIG. 4, a laser drive circuit 200V having a basic configuration includes a pulse generation unit 202 having a reset pulse generation unit 210 and an edge pulse generation unit 220, a light emission level pattern storage unit 230, a current source unit 240, a current switch unit 250, A laser driving unit 270 is provided. The reset pulse generator 210 is an example of a first pulse generator, and the edge pulse generator 220 is an example of a second pulse generator. The light emission level pattern storage unit 230 is an example of a second storage unit, and the second storage unit is also used as a light emission level pattern storage unit.

  Of the laser driving circuit 200V, the portion excluding the pulse generating unit 202 and the laser driving unit 270 corresponds to the recording waveform generating unit. The laser drive circuit 200V is supplied with the reset signal RS as the first transmission signal and the edge signal ES as the second transmission signal from the transmission signal generation unit 500 provided in the digital signal processing unit 57 on the drive board side. The

  The pulse generation unit 202 generates a reset pulse RP and an edge pulse EP using the reset signal RS and the edge signal ES. For example, the reset pulse generator 210 generates the reset pulse RP based on the reset signal RS. The edge pulse generator 220 generates an edge pulse EP based on the edge signal ES. That is, the generation timing of the reset pulse RP is synchronized with the edge of the reset signal RS, and the generation timing of the edge pulse EP is synchronized with the edge of the edge signal ES. Here, it is assumed that both the reset pulse RP and the edge pulse EP are active H pulse signals.

  The reset pulse generation unit 210 includes an edge detection circuit 212 which is an example of a first edge detection unit. The edge pulse generation unit 220 includes an edge detection circuit 222 which is an example of a second edge detection unit. As the edge detection circuits 212 and 222, for example, a known circuit such as a NAND (or AND) gate, a NOR (or OR) gate circuit, a gate circuit such as an inverter or an EX-OR gate may be used. For example, when a non-inverted logic gate is used as a delay element and the input pulse signal and the output of the delay element are input to the EX-OR gate, both edges can be detected with active H. When an inverting logic gate is used as a delay element, when the input pulse signal and the output of the delay element are input to the AND gate, the rising edge can be detected with active H, and when the input pulse signal is input to the NOR gate, the falling edge can be detected with active H. .

  The reset pulse generation unit 210 detects a rising edge or a falling edge (here, a rising edge) of the input reset signal RS by the edge detection circuit 212 to generate a reset pulse RP, and stores a light emission level pattern. It supplies to the part 230 (refer FIG. 4B). As a modification, the reset pulse RP may be generated by detecting both rising and falling edges of the reset signal (see FIG. 4C).

  The edge pulse generation unit 220 detects both rising and falling edges of the input edge signal ES by the edge detection circuit 222, generates an edge pulse EP, and supplies it to the light emission level pattern storage unit 230. One reset pulse RP may be generated per one cycle of space and mark, but a plurality of edge pulses EP need to be generated. Therefore, by generating edge pulses EP from both edges of the edge signal ES, The frequency of the edge signal ES is kept low.

  The light emission level pattern storage unit 230 stores power level information (recording waveform control signal pattern) of laser emission at each timing when the write strategy technique is applied. For example, the light emission level pattern storage unit 230 includes a plurality of registers 232_1 to 232_k (collectively referred to as a register set 231) and read switches 234_1 to 234_k provided at the outputs of the registers 232_1 to 232_k.

  The register set 231 functions as a main storage unit. The output lines of the registers 232_1 to 232_k and the corresponding read switches 234_1 to 234_k are a plurality that can set a multi-value level of laser power when the write strategy technique is applied. The number of multilevel levels and the number of output lines of the registers 232_1 to 232_k and the read switches 234_1 to 234_k may be the same, or may be different by using a decoder. In the basic configuration, the number of multilevel levels is the same as the number of output lines of the registers 232_1 to 232_k and the number of read switches 234_1 to 234_k.

  In accordance with the recording waveform control signal pattern, the light emission level pattern storage unit 230 sequentially registers information on each light emission power level and information defining the switching mode of the current switch unit 250 corresponding to the initial level of the recording waveform control signal pattern. 232_1 to 232_k. An example of the recording waveform control signal pattern will be described later. The reset pulse RP is supplied from the reset pulse generator 210 to the control input terminal of the first-stage read switch 234_1 connected to the first-stage register 232_1 that holds the initial level information. The edge pulse EP is commonly supplied from the edge pulse generator 220 to the control input terminals of the read switches 234_2,..., 234_k connected to the registers 232_2,. Read switches 234_2,..., 234_k are sequential switches that sequentially select the outputs of the registers 232_2,.

  In the recording mode, the light emission level pattern storage unit 230 turns on / off each current switch of the current switch unit 250 based on the reset pulse RP, the edge pulse EP, and the power level information stored in the register 232. Outputs the current switching pulse SW. Specifically, the light emission level pattern storage unit 230 uses the power level information (particularly, the current switching pulse SW for controlling the current switch unit 250 in this example) stored in the registers 232_2,. Read in order. Then, at the timing of the reset pulse RP, the reading is returned to the register 232_1 that stores the initial level (reference level) information.

  The current source unit 240 includes a reference current generation unit 242 and a current output type DA conversion unit 244 (IDAC). The reference current generator 242 outputs digital reference current values corresponding to each power level of the multi-value in the recording mode and the read in the reproduction (reading) mode in the emission pulse waveform of the semiconductor laser 41 as the emission level pattern. Generated based on information in the storage unit 230. For example, current information corresponding to each light emission power level is set as multi-bit digital data in the light emission level pattern storage unit 230, and each reference current generation unit 242 corresponding to each light emission power level captures the current information.

  The DA converter 244 converts the current information (digital data) generated by the reference current generator 242 to analog and outputs the analog information. Each DA converter 244 is supplied with a laser power instruction voltage PW from the APC controller 58 via the flexible substrate 51. Each DA converter 244 adjusts the gain of DA conversion based on the laser power instruction voltage PW. The emission power of the semiconductor laser 41 is feedback controlled to a constant value corresponding to the laser power instruction voltage PW.

  In the recording mode, the current switch unit 250 sets the current switch 252 (Current SW) to any one or any combination (superimposition) of each power reference current converted into an analog signal by the DA conversion unit 244. I have. The current switch unit 250 controls the light emission power by turning on / off the current switch 252 based on a plurality of level information (specifically, the current switching pulse SW) read from the light emission level pattern storage unit 230.

  In this example, four levels of cool, erase, peak, and overdrive are used as the multilevel levels in the recording mode (see FIGS. 4A and 4B). reference). Correspondingly, the reference current generator 242 includes separate reference current generators 242C, 242E, 242P, and 242OD that generate four levels of reference currents, and a read reference current generator 242R. . The DA converter 244 includes DA converters 244C, 244E, 244P, 244OD, and 244R in order to convert each reference current generated by the reference current generator 242 into an analog signal. The current switch 252 also includes 252C, 252E, 252P, 252OD, and 252R, respectively.

  As the reference currents generated by the reference current generator 242, for example, as shown in FIG. 4A, different Ic, Ie, Ip, and Iod corresponding to the four values of cool, erase, peak, and overdrive are used. . In accordance with this adopted configuration, the output pattern information of the current switching pulse SW for controlling the current switch 252 is also stored in the light emission level pattern storage unit 230. In the recording mode, four types of current switching pulses SW_1 to SW_4 are output from each register 232 of the light emission level pattern storage unit 230 in order to control the quaternary level. In this example, reference currents Ic, Ie, Ip, and Iod are supplied to the corresponding current switches 252C, 252E, 252P, and 252OD separately for cool, erase, peak, and overdrive. Therefore, one current switch 252 may be turned on by activating any one of the four types of current switching pulses SW_1 to SW_4.

  The laser driving unit 270 includes a laser switching circuit 272 and a driver circuit 274. As an example of the laser switching circuit 272, three inputs -1 for switching three systems of a first semiconductor laser 41_1 for a CD system, a second semiconductor laser 41_2 for a DVD system, and a third semiconductor laser 41_3 for a next generation DVD system. It has an output type switch. The driver circuit 274 includes a first driver circuit 274_1 that drives the first semiconductor laser 41_1, a second driver circuit 274_2 that drives the second semiconductor laser 41_2, and a third driver circuit 274_3 that drives the third semiconductor laser 41_3. The laser driver 270 corresponds to semiconductor lasers 41_1, 41_2, and 41_3 for three types of recording media, CD, DVD, and next-generation DVD, and switches the semiconductor laser 41 depending on the recording medium.

  With such a configuration, the laser drive circuit 200V generates a multi-value power emission waveform to which the write strategy technique is applied by a combination of a bias current for supplying a threshold current of the semiconductor laser 41 and a plurality of current pulses. Yes. In a laser power control system (APC control system) (not shown), the multi-value power is controlled so that the laser power of the semiconductor laser 41 becomes a light emission waveform of this multi-value power.

[Operation: Basic configuration]
As shown in FIGS. 4B and 4C, the data input for writing is assumed to be non-return zero data NRZIDATA. The space length is 2T, and the mark length is 2T or more (2T, 3T, 4T, and 5T are illustrated in the figure). The maximum speed signal is 2T repetition.

  When the write strategy technique is applied, in this example, in each space length 2T, the cool level (Cool) is set at 1T in the first half, and the erase level (Erase) is set at 1T in the second half. When the mark length is 2T, the erase level is set to 1T in the first half, and the overdrive level is set to 1T in the second half. When the mark length is 3T, the erase level is set at the first 1T, the overdrive level (O.D.) is set at the second 1T, and the peak level (Peak) is set at the third 1T.

  When the mark length is 4T, the erase level is set at the first 1T, the overdrive level is set at the second 1T, the peak level is set at the third 1T, and the overdrive level is set at the fourth 1T. When the mark length is 5T, the erase level is set at the first 1T, the overdrive level is set at the second 1T, the peak level is set at the third 1T, the peak level is set at the fourth 1T, and the overdrive level is set at the fifth 1T. That is, when the mark length is 5T, the peak level is maintained at the 3rd to 4th 2T, and the transition is made to the overdrive level at the 5th 1T thereafter.

  Regardless of the mark length, the erase level is maintained at 2T from the second half of the space to the first mark, and transitions to the overdrive level at 1T thereafter. Each emission power level has a relationship of O.D.> Peak> Erase> Cool.

  Corresponding to such a recording waveform control signal pattern, cool level information is stored as an initial level in the first-stage register 232_1 as shown in FIG. 4D. Erase level is stored in the second register 232_2, overdrive level is stored in the third register 232_2, peak level is stored in the fourth register 232_2, and overdrive information is stored in the fifth register 232_5. To do.

  One reset signal RS and one edge signal ES are used as input pulse signals. A reset pulse RP is generated based on a rising edge or a rising edge and a falling edge of one reset signal RS. An edge pulse EP is generated based on both edges of one edge signal ES. And each power level information memorize | stored in each register | resistor 232_1-232_5 of the light emission level pattern memory | storage part 230 is read in order from a head area (this example is cool). For example, when the reset pulse RP is active H, the read switch 234_1 is turned on to read the power level information of the first-stage register 232_1. Thereafter, every time the edge pulse EP becomes active H, the read switches 234_2 to 234_5 having the sequential switch configuration are sequentially turned on to read the power level information of the registers 232_2 to 232_5 in order.

  For example, when recording at a mark length of 4T or a mark length of 5T, if all the power level information is read in order, the laser emission power is switched in the order of cool → erase → overdrive → peak → overdrive.

  Depending on the mark length of the non-return zero data NRZIDATA, all levels are not output. For example, when recording with a mark length of 2T, it is necessary to transition the power from overdrive to cool. In this case, by supplying a reset signal RS so that the reset pulse RP becomes active H at a timing immediately after overdrive to be cool, cool information is read after overdrive. Similarly, at the time of recording with a mark length of 3T, the reset signal RS may be supplied so that the reset pulse RP becomes active H at the timing immediately after the peak to be cooled so that the power transitions from the peak to cool.

<Laser Drive Method: First Embodiment>
5 to 5F are diagrams illustrating the first embodiment of the sequential method. FIG. 5 is a diagram illustrating a configuration example of the transmission signal generation unit 500A of the first embodiment. FIG. 5A is a diagram for explaining the operation of the transmission signal generation unit 500A of the first embodiment. FIG. 5B is a diagram illustrating the laser drive circuit 200A of the first embodiment. 5C and 5D are diagrams illustrating the operation of the laser driving circuit 200A according to the first embodiment. FIG. 5E is a diagram for explaining register setting information of the memory circuit corresponding to the recording waveform control signal pattern shown in FIGS. 5C and 5D. FIG. 5F is a diagram for explaining edge transition direction detection of a comparative example with respect to edge continuous detection according to the present embodiment.

  In the first embodiment, in the recording mode, one first transmission signal and N (N is a positive integer of 2 or more) second transmission signals are supplied to the laser driving circuit 200A, and the write strategy technique is used. The semiconductor laser 41 is driven. Although the number of signal lines increases, in order to enable high-speed transmission, the number of second transmission signals is set to N, and the timing is transmitted at the 2N edge of each rising edge and falling edge, thereby reducing the transmission band. The function to reduce is realized. By transmitting a plurality of second transmission signals including information defining the acquisition timing of the switching pulse, it is possible to more easily solve the problem of the transmission band and cope with high-speed recording.

  In addition, information should be given as to whether or not the transition timing of the second transmission signal immediately before and immediately after the transition timing of the first transmission signal is the same among the “N second transmission signals”. Thus, information transmission other than information on the transition timing itself of the second transmission signal is enabled. Whether or not the transition timing of the second transmission signal immediately before and after the transition timing of the first transmission signal depends on the same one of the “N second transmission signals” will be described below. It is also referred to as whether the edges of the second transmission signal before and after the transmission signal are continuous or non-continuous. Information other than timing information is transmitted by adding information for memory switching to indicate whether the edges before and after the reset are continuous or discontinuous. As “information other than information on the transition timing itself of the second transmission signal”, specifically, it may be used as information for switching a plurality of types of power level patterns. That is, it is applied when the power level such as the peak level or the overdrive level is changed according to the recording data length (space length or mark length).

  As a circuit configuration, the laser drive circuit 200A on the optical pickup 14 side is provided with a storage unit that stores a power level pattern (level information pattern). The storage unit selectively stores a plurality of sub-storage units (each referred to as a sub-storage unit) for storing different patterns and one of the power level patterns stored in each of the plurality of sub-storage units. Assume that a main memory is provided. For example, the power level pattern of one of the secondary storage units is stored in the main storage unit, and at the same time, one reset signal RS for reading the reference level of the repetitive pattern is used, and the edge signal for sequentially reading the subsequent levels Use N ES.

  The N edge signals ES have information for switching a plurality of types of power level patterns in combinations of the edge timings. The information is decoded by the laser drive circuit 200A and the power level is switched. Specifically, among the N edge signals ES, when the edges of the same edge signal ES are continuous across the edge of the reset signal RS, the power level pattern stored in the other sub storage unit is changed. Store in the main memory. For this reason, in this embodiment, it is determined whether the edges of the edge signal ES immediately before and after the edge of the reset signal RS are the same edge signal ES (referred to as edge continuous detection of the edge signal ES).

  Hereinafter, the description will be made centering on differences from the basic configuration with N = 2.

[Circuit Configuration: First Embodiment]
As illustrated in FIG. 5, the transmission signal generation unit 500A on the drive board side includes an RS flip-flop 510 and a D flip-flop 512 in order to generate the reset signal RS. The non-return zero data NRZIDATA is input to the R input terminal of the RS flip-flop 510, and the edge pulse EP1 is input to the S input terminal. The non-inverting output terminal Q of the RS flip-flop 510 is connected to the clock input terminal CK of the D-type flip-flop 512. The inverting output terminal xQ of the D-type flip-flop 512 is connected to the D input terminal to constitute a 1/2 frequency dividing circuit.

  By doing so, the non-inverting output terminal Q of the RS flip-flop 510 becomes active H in synchronization with the rising edge of the edge pulse EP1, and becomes inactive L in synchronization with the rising edge of the non-return zero data NRZIDATA. The output pulse at the non-inverting output terminal Q of the RS flip-flop 510 is supplied to the clock input terminal CK of the D-type flip-flop 512 and is divided by two.

  If the output pulse at the non-inverting output terminal Q of the RS flip-flop 510 is the reset signal RS, the reset pulse RP is defined at the rising edge. If the output pulse at the inverting output terminal xQ of the RS flip-flop 510 is the reset signal RS, the reset pulse RP is defined at the falling edge. If the output pulse at the non-inverting output terminal Q or the inverting output terminal xQ of the D-type flip-flop 512 is the reset signal RS, the reset pulse RP is defined at both edges. Therefore, when the system configuration is such that the reset pulse RP is defined by one edge of the reset signal RS, the D-type flip-flop 512 is not necessary.

  The transmission signal generator 500A includes a 4-input type OR gate 520, a NOR gate 521, a D-type flip-flop 522, and AND gates 523P and 523N in order to generate edge signals ES_1 and ES_2. Further, the transmission signal generation unit 500A includes a light emission level pattern selection signal generation circuit 524, an AND gate 525, and D-type flip-flops 526 and 527.

  Edge pulses EP <b> 2 to EP <b> 5 are supplied to the input terminals of the OR gate 520. The output terminal of the OR gate 520 is connected to one input terminal of the NOR gate 521 and one input terminal of the AND gates 523P and 523N. The output terminal of the NOR gate 521 is connected to the clock input terminal CK of the D-type flip-flop 522. In the D-type flip-flop 522, the inverting output terminal xQ is connected to the D input terminal so that a 1/2 frequency dividing circuit is configured. In the D-type flip-flop 522, the inverting output terminal xQ is connected to the other input terminal of the AND gate 523N, and the non-inverting output terminal Q is connected to the other input terminal of the AND gate 523P.

  The output terminal of the AND gate 523P is connected to the clock input terminal CK of the D-type flip-flop 526. The D-type flip-flop 526 is configured such that the inverting output terminal xQ is connected to the D input terminal to form a ½ frequency divider, and the edge signal ES_1 is output from the non-inverting output terminal xQ as will be described later. The The output terminal of the AND gate 523N is connected to the clock input terminal CK of the D-type flip-flop 527. The D-type flip-flop 527 is configured such that the inverting output terminal xQ is connected to the D input terminal to form a 1/2 frequency dividing circuit, and the edge signal ES_2 is output from the non-inverting output terminal xQ as will be described later. The

  The light emission level pattern selection signal generation circuit 524 has a recording data length determination result input to the input terminal, and an output terminal connected to one input terminal of the AND gate 525. An edge pulse EP 1 is input to the other input terminal of the AND gate 525. The output terminal of the AND gate 525 is connected to the other input terminal of the NOR gate 521.

  The light emission level pattern selection signal generation circuit 524 outputs a light emission level pattern selection signal PS to the output terminal in accordance with the recording data length determination result determined by the address encoder. The correspondence between the recording data length determination result and the light emission level pattern can be arbitrarily set. The edge pulse EP1 is output to the output terminal of the AND gate 525 in accordance with the light emission level pattern selection signal PS. When the light emission level pattern selection signal PS is at L level, the non-inverting output terminal Q and the inverting output terminal xQ of the D-type flip-flop 522 are L, H in synchronization with the falling edge of any one of the edge pulses EP2 to EP5. Changes in order. When the light emission level pattern selection signal PS is at the H level, the non-inverting output terminal Q and the inverting output terminal xQ of the D-type flip-flop 522 are L, H in synchronization with the falling edge of any one of the edge pulses EP1 to EP5. Changes in order.

  The AND gate 523P selectively outputs the edge pulses EP2 to EP5 output from the OR gate 520 to the D-type flip-flop 526 when the output of the non-inverting output terminal Q of the D-type flip-flop 522 is at the H level. The AND gate 523N selectively outputs the edge pulses EP2 to EP5 output from the OR gate 520 to the D-type flip-flop 527 when the output of the inverting output terminal xQ of the D-type flip-flop 522 is H. In synchronism with the rising edge of the edge pulse selected by the AND gate 523P, the non-inverting output terminal Q and the inverting output terminal xQ of the D-type flip-flop 526 change in order of L and H. In synchronism with the rising edge of the edge pulse selected by the AND gate 523N, the non-inverting output terminal Q and the inverting output terminal xQ of the D-type flip-flop 527 change in order of L and H. If the output pulse at the non-inverting output terminal Q and the inverting output terminal xQ of the D-type flip-flop 526 is the edge signal ES_1, the edge pulse EP_1 is defined at both edges. If the output pulse at the non-inverting output terminal Q and the inverting output terminal xQ of the D-type flip-flop 527 is the edge signal ES_2, the edge pulse EP_2 is defined at both edges.

  In principle, the edge signals ES_1 and ES_2 are logically inverted alternately based on the edge pulses EP2 to EP5. However, when the light emission level pattern selection signal PS is at the H level, the D-type flip-flop 522 inverts the output even with the edge pulse EP1, so that the logic inversion is performed immediately before the transition timing after the edge pulse EP1, instead of alternating. Is logically inverted first. When the light emission level pattern selection signal PS is at the H level, the edges of the same edge signals ES_1 and ES_2 are continuous across the edge of the reset signal RS corresponding to the edge pulse EP1, and the power level pattern is switched. The information is held in the edge signals ES_1 and ES_2.

  As shown in FIG. 5B, the laser drive circuit 200A (pulse generation unit 202A) of the first embodiment generates a selection pulse MC in addition to the reset pulse generation unit 210A and the edge pulse generation unit 220A. A third pulse generator). Similarly to the basic configuration, the reset pulse generator 210A detects the edge of the reset signal RS and generates the reset pulse RP. For example, the edge detection circuit 212 detects either one of the rising edge and falling edge (here, rising edge) of the input reset signal RS and generates the reset pulse RP (the corresponding timing chart is shown in FIG. 5C). As a modification, the edge detection circuit 212 may detect both rising and falling edges of the reset signal RS to generate the reset pulse RP (corresponding timing chart is FIG. 5D). Similar to the basic configuration, the reset pulse RP is supplied to the control input terminal of the read switch 234_1, and also has a function of a selection pulse for switching a plurality of types of power level patterns.

  The edge pulse generator 220A generates an edge pulse EP based on the two edge signals ES_1 and ES_2 as the second transmission signal. Therefore, the edge pulse generation unit 220A includes two edge detection circuits 222_1 and 222_2 and a logic gate 224 that is an example of a pulse synthesis unit. The edge detection circuit 222_1 detects both edges of the edge signal ES_1 and generates an edge pulse EP_1. The edge detection circuit 222_2 detects both edges of the edge signal ES_2 and generates an edge pulse EP_2. The logic gate 224 generates an edge pulse EP by logically synthesizing the edge pulses EP_1 and EP_2 output from the edge detection circuits 222_1 and 222_2. The edge pulses EP_1 and EP_2 are assumed to be active H pulse signals. Correspondingly, as the logic gate 224, an OR gate that takes the logical sum of the edge pulses EP_1 and EP_2 is used.

  The selection pulse generation unit 280A has a continuous edge detection function for determining whether the edges of the edge signal ES immediately before and after the edge of the reset signal RS are the same edge signal ES. The selection pulse generator 280A selects the selection pulse MC based on the edge signals ES_1 and ES_2 after the continuation when the edge of the edge signal ES_1 is continuous or the edge of the edge signal ES_2 is continuous across the edge of the reset signal RS. Is generated. Similar to the reset pulse RP, the selection pulse MC is also used to switch among a plurality of types of power level patterns.

  As a specific configuration, the selection pulse generation unit 280A includes two determination signal generation units 286_E and 286_R, and three logic gates 287_1, 287_2, and 287_3. The discrimination signal generation unit 286_E has a discrimination pulse DEP and its inverted signal xDEP that make active H from the fall of the edge pulse EP_1 generated by the edge detection circuit 222_1 to the fall of the edge pulse EP_2 generated by the edge detection circuit 222_2. Is generated. The determination signal generation unit 286_R generates a determination pulse DRP that makes active H from the rising edge of the reset pulse RP generated by the edge detection circuit 212 to the falling edge of the edge pulse EP generated by the logic gate 214.

  As the logic gate 287_1, a 3-input type AND gate that takes the logical product of the edge pulse EP_1, the discrimination pulse DEP, and the discrimination pulse DRP is used. As the logic gate 287_2, a 3-input type AND gate that takes the logical product of the edge pulse EP_2, the discrimination pulse xDEP, and the discrimination pulse DRP is used. As the logic gate 287_3, a two-input type OR gate that takes a logical sum of the logic gates 287_1 and 287_2 is used, and its output is set as a selection pulse MC. Unlike the reset pulse RP, the selection pulse MC does not have a function as a reference pulse indicating the switching timing of space and mark repetition, and has only a selection function of the register set 231.

[Memory Circuit: First Embodiment]
As shown in FIGS. 5C and 5D, the recording waveform control signal pattern differs from the basic configuration, and the overdrive level differs according to the mark length. For example, overdrive level 1 (OD1) and peak level (Peak1) are used as the first power level pattern when the mark length is 2T and 3T, and overdrive level 2 ( OD2) and peak level (Peak2). Each light emission power level has a relationship of OD1>Peak1>OD2>Peak2>Erase> Cool. In this example, the erase levels are the same in the first and second power level patterns, but they may be different such as Erase1 and Erase2 (Erase1> Erase2).

  In order to vary the overdrive level according to the mark length, the light emission level pattern storage unit 230 of the first embodiment includes a register set 231_0 that functions as a main storage unit, register sets 231_1 and 231_2 that function as sub storage units, and storage information. A control unit 236 is included. The register sets 231_1 and 231_2 store two types of recording waveform control signal patterns separately according to a level information register input instruction from a main control unit (not shown). The register set 231_0 corresponds to the basic register set 231. Based on the reset pulse RP and the selection pulse MC, the storage information control unit 236 reads any storage information of the register sets 231_1 and 231_2 and causes the register set 231_0 to hold it.

[Operation: First Embodiment]
As shown in FIGS. 5C and 5D, since one reset signal RS and two edge signals ES_1 and ES_2 are used as input pulse signals, there are a total of three input pulse signals. A reset pulse RP is generated based on the reset signal RS, and a selection pulse MC is generated when the edges of the same edge signals ES_1 and ES_2 are transitioned across the reset pulse RP. Incidentally, the first example shown in FIG. 5C is a mode in which only the rising edge of the reset signal RS is used to generate the reset pulse RP, and the second example shown in FIG. 5D uses both edges of the reset signal RS. Thus, the reset pulse RP is generated.

  As shown in FIG. 5E, when the reset pulse RP is active H, the storage information control unit 236 reads the storage information of the register set 231_1 and sets it in the register set 231_0. When the selection pulse MC is active H, the storage information control unit 236 reads the storage information of the register set 231_2 and sets it in the register set 231_0. That is, the storage information control unit 236 rewrites the information in the register set 231_0 to the corresponding power level pattern at the timing when the reset pulse RP and the selection pulse MC become active H. Further, similarly to the basic configuration, the reset pulse RP is supplied to the read switch 234_1 of the light emission level pattern storage unit 230. Hereinafter, the basic configuration is the same. For example, the level is returned to the cool level by the reset pulse RP, and then each level other than the cool level is sequentially read by the edge pulse EP.

  As in the first embodiment, two types of power level patterns can be switched by using two second transmission signals (edge signals ES_1 and ES_2). Thereby, the laser emission power level can be changed according to the mark length. Two edges reduce the transmission band per line to support high-speed recording. Furthermore, by using two edges, it is possible to detect continuous edges. With this edge continuation information, another power level pattern can be selected without increasing the number of resets. Further, by sandwiching the reset edge between successive edges, the edge interval at the edge continuous portion does not become the shortest edge interval of the output. The transmission band per transmission signal does not deteriorate, and high-speed recording is possible. However, since the selection pulse MC is synchronized with the next edge pulse EP of the reset pulse RP, the selection pulse MC is generated after the reset pulse RP (after the cool level is output) and cannot have two patterns of cool levels.

[Contrast with other configurations]
Although not shown, if only the high-speed recording is supported without adopting a mechanism for switching a plurality of types of power level patterns, whether the edges of the second transmission signal before and after the first transmission signal are continuous or discontinuous. Need not be represented by N second transmission signals. This method is referred to as a high-speed recording compatible method. Further, if only a mechanism for switching a plurality of types of power level patterns without adopting high-speed recording is adopted, the number of second transmission signals is one, and a plurality of types are used using N first transmission signals. It may be possible to change the power level pattern. This method will be referred to as a multiple power level compatible method. For example, when two reset signals RS_1 and RS_2 are used, a reset pulse RP_1 is generated from the reset signal RS_1, a reset pulse RP_1 is generated from the reset signal RS_2, and both the reset pulse RP and the reset pulse RP_2 are active H It is conceivable to generate the reset pulse RP_3 at the same time. By generating three reset pulses RP using the two reset signals RS_1 and RS_2, it is possible to switch the three power level patterns.

  In addition, a configuration in which a high-speed recording compatible method using a plurality of second transmission signals (edge signals ES) and a multiple power level compatible method using a plurality of first transmission signals (reset signals RS) may be combined. it can. This method will be referred to as a simple combination method. For example, based on high-speed transmission using one reset signal RS and two edge signals ES, a system corresponding to a plurality of power levels is further used using a plurality of reset signals RS. Since the effects of the high-speed recording compatible system and the multiple power level compatible system can be enjoyed, the effects of the first embodiment can be obtained.

  However, in the simple combination method in which the high-speed recording compatible method and the multiple power level compatible method are simply combined, in order to realize high-speed transmission with N edge signals ES and to have a plurality of power level patterns, at least The reset signal RS must be increased by one, and N edge signals ES and a plurality of reset signals RS are required. On the other hand, in the first embodiment, information for switching a plurality of types of power level patterns is provided at the transition timing of the N edge signals ES, so that only one reset signal RS is required. The first embodiment can realize both high-speed recording and multiple power levels with fewer input signals than the simple combination method.

  Further, when the first power level pattern is distinguished from the second power level pattern and the second power level pattern is read out, the edge continuity is always detected, so that an erroneous edge continuation occurs due to a sudden error. However, the error will only occur in that pattern and will not propagate after that. An error is a missing edge or incorrect edge generation. A pattern in which an edge is lost or erroneously generated becomes an error, but returns to the top level by the reset pulse RP, and therefore does not propagate thereafter. This is due to the fact that in the edge continuous detection function of the present embodiment, the order of edges does not matter.

  FIG. 5F shows an edge transition direction detection function that considers the order of edges. In this example, the case of having the timing of rising edge signal ES_1 → rising edge signal ES_2 → falling edge signal ES_1 → falling edge signal ES_2 is called forward transmission, rising edge signal ES_1 → edge signal ES_2 The case of having the following timing: falling edge → edge signal ES_1 falling → edge signal ES_2 rising timing is referred to as reverse transmission. The forward direction and the reverse direction are detected, and the first power level pattern is selected in the forward direction and the second power level pattern is selected in the reverse direction. When edges are accidentally continued due to a sudden error, the forward and reverse directions are reversed, and thereafter the first and second power level patterns are reversed and the error is propagated. .

  On the other hand, in the case of continuous edge detection according to the present embodiment, there is no error propagation because the first power level pattern is selected with discontinuous edges and the second power level pattern is selected with continuous edges. However, when compared with the high-speed recording method, the circuits on the output side and the receiving side that perform sequential transmission are complicated. Further, when compared with the multiple power level compatible method, for example, when two edge signals ES are used, a mechanism for switching two power level patterns instead of three is used. Also, in the multiple power level compatible method, the cool level can be provided separately, whereas in the first embodiment, only one cool level can be provided.

<Laser Drive Method: Second Embodiment>
6 to 6B are diagrams for explaining the second embodiment of the sequential method. FIG. 6 is a diagram illustrating a configuration example of the transmission signal generation unit 500B of the second embodiment. FIG. 6A is a diagram for explaining the operation of the laser drive circuit 200B of the second embodiment. 6B is a diagram for explaining register setting information of the memory circuit corresponding to the recording waveform control signal pattern shown in FIG. 6A. The laser drive circuit 200B may have the same configuration as the laser drive circuit 200A of the first embodiment. This point is the same in other embodiments unless otherwise noted.

  The second embodiment is an application example to a land / groove recording method. On the recording surface of a recording medium that takes a so-called land / groove recording method, there is an information recording portion comprising a guide groove portion called a groove region and a portion called a land region (between grooves) located between adjacent groove regions. Is formed. The land area and the groove area are alternately switched every round following the tracking operation by the optical pickup, and are treated as if they were one continuous track. However, in the recording operation, the write strategy is switched, that is, the power level pattern is switched depending on the difference in structure between the land area and the groove area.

  In order to increase the recording speed, the write strategy must be switched instantaneously. In the laser driving circuit 200B of the comparative example incorporating the write strategy circuit, the write strategy information for the land area and the strategy information for the groove area are stored in the internal storage unit, and which information is to be used. A terminal is provided for switching.

  In the method using the dedicated terminals, the number of terminals such as the laser driving circuit 200B increases, and the package becomes large. In addition, the timing transmission and the land / groove switching signal are separate transmission paths, and the timing transmission is a differential LVDS transmission. The land / groove switching signal is used to avoid an increase in signal lines. Single CMOS transmission is common and transmission is different. For these reasons, in the method using the dedicated terminal, skew between signals is likely to occur, and it is difficult to accurately control the switching timing.

  To cope with this, in the transmission signal generation unit 500B of the second embodiment, the light emission level pattern selection signal generation circuit 524 is removed based on the transmission signal generation unit 500A of the first embodiment, and one input of the AND gate 525 is performed. Input the land / groove switching signal LG at the end. The land / groove switching signal LG is a signal indicating whether the writing information transmitted at that time is information written in the land area or information written in the groove area.

  For example, the first power level pattern for the groove area and the second power level pattern for the land area are switched every round as shown in FIG. 6A. As shown in FIG. 6B, a first power level pattern for the groove area is set in the register set 231_1, and a second power level pattern for the land area is set in the register set 231_2. When the land / groove switching signal LG is at the L level, the first power level pattern for the groove area set in the register set 231_1 is read out only by the reset pulse RP. When the land / groove switching signal LG is at the H level, the selection pulse MC is also used to switch to the second power level pattern for the land area set in the register set 231_2. Here, the term “using selection pulse MC” is taken into consideration that the information (cool level in this example) set in the register set 231_1 is always read by the reset pulse RP.

  As described above, in the second embodiment, not only high-speed recording is possible, but also the power level pattern corresponding to each of the groove area and the land area is set using the edge continuous detection function of the edge signal ES. Can do. It is possible to select two types of power level patterns for the groove area and the land area without preparing a control line for level switching. Since there is no need to provide a dedicated terminal for level switching, the package area does not increase, and the power level pattern in the land area and the power level pattern in the groove area can be switched. Also, the land area and groove area switching signals are multiplexed on the three transmission lines that transmit the timing information, and there is no timing skew due to the difference between the transmission lines and the transmission system, so the switching timing is accurately controlled. Can do.

<Laser Drive Method: Third Embodiment>
7 to 7B are diagrams for explaining the third embodiment of the sequential method. FIG. 7 is a diagram illustrating a configuration example of a transmission signal generation unit 500C of the third embodiment. FIG. 7A is a diagram illustrating the operation of the laser drive circuit 200C of the third embodiment. FIG. 7B is a diagram for explaining register setting information of the memory circuit corresponding to the recording waveform control signal pattern shown in FIG. 7A.

  The third embodiment is an application example for switching power level patterns in CAV recording and ZCLV recording. In high-speed recording, CAV (Constant Angular Velocity) recording that records data while rotating the optical disk OD at a constant rotational speed, or an appropriate radial position so that the rotational speed of the optical disk OD does not increase at the inner periphery. The zone is divided by CLV (Constant Linear Velocity) in the zone, and ZCLV (Zone CLV) recording is performed so that the outer peripheral zone has a higher linear velocity. In these recording methods, the recording linear velocity increases from the inner periphery toward the outer periphery, and the optimum recording power and light emission pattern differ depending on the recording linear velocity, so that these are sequentially switched.

  In the laser drive circuit 200B of the comparative example with a built-in write strategy circuit, a power level pattern corresponding to CAV recording or ZCLV recording is stored in the internal storage unit, and a dedicated terminal is used to determine which power level pattern is used. It will be provided and switched. As in the case of land / groove switching described in the second embodiment, the method using dedicated terminals increases the package size. Skew between signals is likely to occur, and it is difficult to accurately control the switching timing.

  To cope with this, the transmission signal generation unit 500C of the third embodiment removes the light emission level pattern selection signal generation circuit 524 from the transmission signal generation unit 500A of the first embodiment and connects it to one input terminal of the AND gate 525. The circumferential position power level pattern switching signal LP is input. It may be considered that the land / groove switching signal LG of the second embodiment is replaced with the circumferential position power level pattern switching signal LP. The transition of the logical level of the circumferential position power level pattern switching signal LP is a signal indicating the switching timing of the recording power and the light emission pattern corresponding to the recording position in the circumferential direction of the optical disc OD in CAV recording and ZCLV recording.

  Similar to the second embodiment, different power level patterns are stored in the two register sets 231_1 and 231_2, and which one is selected and used is determined by using the continuous / non-continuous information of the edge of the edge signal ES. Thereby, the recording power and the light emission pattern can be switched following the recording linear velocity that changes depending on the recording position in CAV recording or ZCLV recording.

  Here, in the case of CAV recording or ZCLV recording, since the recording speed changes sequentially, unlike the first and second embodiments, the two power level patterns are not used alternately. Based on the transition of the logic level of the circumferential position power level pattern switching signal LP, when recording is performed using one power level pattern, the other power level pattern is rewritten to switch the recording power or light emission pattern. Use a mechanism to prepare for timing. The recording power can be instantaneously switched to the other power level pattern.

  However, there are the following restrictions in relation to the mechanism of the present embodiment in which pattern switching is performed with a selection pulse MC acquired by edge continuous detection. First, when recording is performed using the power level pattern of only the register set 231_1, the power level pattern of the register set 231_2 can be rewritten. When the register set 231_2 is used, the register 232_1 of the register set 231_1 is also used to set the cool level. Therefore, when the power level pattern of the register set 231_2 is used, the cool setting information of the register set 231_1 Switching is not possible.

  Therefore, for the register set 231_1, a power level pattern other than cool is rewritten. Specifically, the register set 231_1 is rewritten except for cool, and all the register sets 231_2 are rewritten. When the selection pulse MC becomes H level and the register set 231_2 is other than cool, the cool of the register set 231_1 is output, but other than the cool of the register set 231_1 is not output (= the memory is not accessed). It is possible to rewrite power level patterns other than 231_1 cool.

  In addition, by rewriting power information as multi-bit digital data stored in the light emission level pattern storage unit 230 by register input, it is possible to change not only the level pattern but also power. Similar to the level pattern, the power information corresponding to the unused register set is rewritten to prepare for the switching of the register set. Specifically, the power information of overdrive level OD_2 and peak level Peak_2 is rewritten at the timing when register set 231_1 is used, and the power information of overdrive level OD_1 and peak level Peak_1 is rewritten when register set 231_2 is used. .

  In the configuration of the register set 231_1, when one memory is physically considered, when the write and read cannot be used at the same time, it is possible to use physically different memories for cool and other purposes. You only have to deal with it.

  As described above, in the third embodiment, not only high-speed recording is possible, but also a power level pattern corresponding to CAV recording or ZCLV recording can be set using the edge continuous detection function of the edge signal ES. . Each power level pattern can be selected according to the disk recording position for CAV recording or ZCLV recording without preparing a control line for level switching. Since there is no need to provide a dedicated terminal for level switching, there is no increase in the package area, and each power level pattern can be switched according to the disk recording position. In addition, the switching signal of the power level pattern for CAV / ZCLV recording is multiplexed on the three transmission lines that transmit the timing information, and there is no timing skew due to the difference between the transmission line and the transmission method. It can be controlled accurately.

<Laser Drive Method: Fourth Embodiment>
8 to 8B are diagrams for explaining the fourth embodiment of the sequential method. FIG. 8 is a diagram illustrating a configuration example of the transmission signal generation unit 500D of the fourth embodiment. FIG. 8A is a diagram for explaining the operation of the laser drive circuit 200D of the fourth embodiment. FIG. 8B is a diagram for explaining register setting information of the memory circuit corresponding to the recording waveform control signal pattern shown in FIG. 8A.

  The fourth embodiment is an example applied to recording power adjustment called OPC (Optimum Power Calibration). Recordable optical discs have different optimum recording powers due to the effects of differences in characteristics among manufacturers and variations in individual characteristics. The optimum recording power also depends on the optical disc device, such as the light beam emission timing (recording strategy) and the light beam spot shape. Therefore, when recording / reproducing information on a writable optical disc, in order to optimize the recording power, a trial writing is performed in the trial writing area of the optical disc before the actual signal is recorded. The optimum recording condition suitable for reproducing and examining the reproduced signal for recording is determined. A series of processes for determining the optimum recording power by the trial writing is called OPC (recording power adjustment), and the trial writing area is called an OPC area. The OPC area is defined by the standard of each optical disc.

  In OPC, test data is written on the OPC area while changing the recording power step by step, the test data recorded in the OPC area is reproduced, and an optimum recording power value satisfying a predetermined evaluation index is obtained. decide. As the test data, a random pattern that repeats the longest mark at random from the shortest mark according to the modulation rule for the basic clock period T of the modulation rule is generally used.

  In the comparative example laser drive circuit 200B with a built-in write strategy circuit, a power level pattern corresponding to OPC is stored in the internal storage unit, and which of the power level patterns is used is provided with a dedicated terminal for switching. Will do. As in the case of land / groove switching described in the second embodiment and CAV / ZCLV recording described in the third embodiment, the method using a dedicated terminal increases the package and causes a skew between signals. This makes it difficult to accurately control the switching timing. Further, if the writing is stopped and the setting is rewritten every time the recording power is switched, it is not necessary to use a dedicated switching terminal. However, this method deteriorates the efficiency of OPC.

  To cope with this, the transmission signal generation unit 500D of the fourth embodiment removes the light emission level pattern selection signal generation circuit 524 from the transmission signal generation unit 500A of the first embodiment, and connects it to one input terminal of the AND gate 525. Input OPC power level pattern switching signal OPC. It can be considered that the power level pattern switching signal LP of the third embodiment is replaced with the OPC power level pattern switching signal OPC. The transition of the logic level of the OPC power level pattern switching signal OPC is a signal indicating the recording power switching timing when test data is recorded in the OPC area in the OPC process.

  In order to efficiently switch the recording power by OPC, different power level patterns are stored in the two register sets 231_1 and 231_2 as in the second embodiment, and which of the edge signals ES to select and use is stored. Determine using edge continuous / non-continuous information. Thereby, the recording power of the test data for OPC can be changed stepwise.

  In OPC, the recording power of the test data is changed in stages (the recording power changes sequentially), so that the two power level patterns are not used alternately. This is similar to the case of CAV / ZCLV recording in the third embodiment. When recording is performed using one power level pattern, the other power level pattern is rewritten to prepare for the timing of switching the recording power. Since the recording power can be instantaneously switched to the other power level pattern, the efficiency of OPC is not deteriorated.

  However, there are the following restrictions in relation to the mechanism of the present embodiment in which pattern switching is performed with a selection pulse MC acquired by edge continuous detection. First, when recording is performed using the power level pattern of only the register set 231_1, the power level pattern of the register set 231_2 can be rewritten. When the register set 231_2 is used, the register 232_1 of the register set 231_1 is also used to set the cool level. Therefore, when the power level pattern of the register set 231_2 is used, the cool setting information of the register set 231_1 Switching is not possible. This is the same as in the third embodiment.

  Thus, in the fourth embodiment, not only high-speed recording is possible, but also a power level pattern for changing the recording power stepwise in OPC using the edge continuous detection function of the edge signal ES is set. can do. The recording power for OPC can be selected without preparing a control line for level switching. Since it is not necessary to provide a dedicated terminal for level switching, the recording power (power level pattern) can be switched without increasing the package area. Further, the switching signal of the power level pattern for OPC is multiplexed on the three transmission lines for transmitting the timing information, and the timing skew due to the difference between the transmission line and the transmission method does not occur, so the switching timing is accurately controlled. be able to.

<Laser Drive Method: Fifth Embodiment>
9 to 9F are diagrams for explaining the fifth embodiment of the sequential method. FIG. 9 is a diagram illustrating a configuration example of the transmission signal generation unit 500E of the fifth embodiment. FIG. 9A is a diagram illustrating a power level pattern for APC. FIG. 9B is a diagram illustrating the operation of the transmission signal generation unit 500E of the fifth embodiment. FIG. 9C is a diagram illustrating a laser drive circuit 200E according to the fifth embodiment. 9D and 9E are diagrams for explaining the operation of the laser drive circuit 200E of the fifth embodiment. FIG. 9F is a diagram for explaining register setting information of the memory circuit corresponding to the recording waveform control signal pattern shown in FIGS. 9D and 9E.

The fifth embodiment is an example applied to the case where light emission power adjustment called APC is performed.
The accuracy of adjusting the laser emission power by APC increases as the frequency of sampling the monitoring waveform and obtaining the power monitor voltage PD increases. However, as the recording operation increases in speed, the light emission time of the mark portion and the space portion is shortened. With a short mark or a short space, the monitored waveform is not settled at a specified level, and sample hold cannot be performed. Furthermore, sampling has become difficult even with the longest T of the standard.

  Therefore, a method has been considered in which APC adjustment accuracy is improved by performing APC with a light emission pattern that can be sampled in the APC region. A high-density, large-capacity recordable optical disc is divided into a large number of areas by a prescribed information recording unit (RUB: recording unit block), and an APC area is provided in a part of the information recording unit. The APC area is an area that is standardized as an area capable of recording not related to information recording.

  A castle strategy is used in the information recording area corresponding to high-speed recording, but there is a method of using a block strategy in the APC area in order to lengthen the light emission time at the same light emission level as the light emission pattern in the APC area. The light emission pattern in the block strategy is shown in FIG. 9A. The light emission in the block strategy in the APC area is intended to facilitate sampling for APC, and it is not necessary to record on the recording medium correctly, and good recording cannot be expected.

  In order to switch the light emission pattern in the APC region, a method using a dedicated terminal is also conceivable, but there are problems of an increase in package area and switching timing accuracy. This is a problem common to the second to fourth embodiments.

  As illustrated in FIG. 9, the transmission signal generation unit 500E of the fifth embodiment removes the light emission level pattern selection signal generation circuit 524 from the transmission signal generation unit 500A of the first embodiment, and inputs one of the AND gates 525. An information recording area / APC area switching signal JA is input to the end. The power level pattern switching signal LP / OPC power level pattern switching signal OPC in the third and fourth embodiments is replaced with an information recording area / APC area switching signal JA. The logic level of the information recording area / APC area switching signal JA is a signal indicating whether the light emission pattern transmitted at that time is the light emission pattern of the information recording area or the light emission pattern of the APC area.

  As shown in FIG. 9C, the laser drive circuit 200E of the fifth embodiment is not different from the laser drive circuit 200A of the first embodiment in configuration. The difference is that the power level handled is different from that of the first embodiment, and therefore the reference current generator 242 and DA converter 244 of the current source unit 240 and the reference of the reference current I are changed for them. It is in.

  In order to efficiently switch the light emission patterns of the information recording area and the APC area, the light emission patterns (power level patterns) of the information recording area and the APC area are included in the two register sets 231_1 and 231_2 as in the second embodiment. ) Is memorized. Then, which one is selected and used is determined by using the continuous / non-continuous information of the edge of the edge signal ES. Thereby, the light emission pattern can be appropriately selected in each of the information recording area and the APC area. Since switching to the other light emission pattern can be performed instantaneously, there is no inconvenience when switching from the information recording area to the APC area or from the APC area to the information recording area.

  Here, the problem is how to switch between the castle type power level pattern in the information recording area and the block strategy type power level pattern (L / H binary) in the APC area. This is because the castle type cool level set in the register set 231_1 is read by the reset pulse RP, and the block strategy pattern set in the register set 231_2 is read by the selection pulse MC thereafter. Related to that.

  First, it is conceivable to make the L level of the block strategy system the same as the cool level of the castle system. In this case, the selection pulse MC is required when the H level of the block strategy method is set. However, in this case, as a matter of course, there is no freedom in setting the L level of the block strategy method.

  Therefore, in this embodiment, as shown in the lowermost part of FIG. 9A, when switching to the block strategy pattern, the castle cool level is set for a moment and the selection pulse MC is immediately output to set the block strategy L level. I will do it. Unlike the basic block strategy type power level pattern, it becomes a special block strategy type power level pattern that falls to the L level after falling to the cool level once, but the mark space area in the APC area is sufficiently long and the space is settled. There is almost no impact.

  FIG. 9B, FIG. 9D, and FIG. 9E show timing charts when switching from the castle type power level pattern in the information recording area to the block strategy type power level pattern in the APC area.

  For example, the operation on the transmission signal generation unit 500E side is shown in FIG. 9B. In FIG. 9B, the edge pulses EP1 to EP5 are output in the order of EP1 → EP2 → EP3 → EP4 → EP5 regardless of whether the period is a castle period or a block strategy period.

  The operation on the laser drive circuit 200E side is shown in FIGS. 9D and 9E. Incidentally, the first example shown in FIG. 9D is a mode in which the reset pulse RP is generated using only the rising edge of the reset signal RS, and the second example shown in FIG. 9E uses both edges of the reset signal RS. Thus, the reset pulse RP is generated. 9D and 9E, it is assumed that the last overdrive of the castle strategy is the edge pulse EP_2.

  In the block strategy, the reset pulse RP is issued before the L level, and the cool level read from the register set 231_1 is set. Immediately thereafter (about 1T or less), an edge pulse EP_2 is output, thereby causing the same edge to continue across the reset pulse RP. As a result, the selection pulse MC is output at the timing of the edge pulse EP_2 and switched to the register set 231_2, so that the L level of the block strategy is set. Next, the H level is set by the edge pulse EP_1.

  Thereafter, the same level is returned to the cool level read from the register set 231_1 by the reset pulse RP, and the same edge is continued with the reset pulse RP sandwiched immediately after the edge pulse EP_1 is issued for edge continuation. As a result, the selection pulse MC is output at the timing of the edge pulse EP_1 and switched to the register set 231_2, so that the L level of the block strategy is set. Further, the H level is set by the edge pulse EP_2.

  In other words, by adding a cool level to the basic block strategy pattern, it becomes a strategy that was reset when the first overdrive of the castle strategy was output, and the 2T space 2T mark shown in FIG. 3B The light emission waveform is the same as in FIG. As shown in FIG. 9B, in the period of the block strategy system, the transmission signal generation unit 500E repeats the edge pulse EP1 (corresponding to a reset signal RS (not shown)) and the edge pulses EP2, EP3 (corresponding to edge signals ES_1 and ES_2). .

  As described above, in the fifth embodiment, not only can the castle method be applied to the information recording area by using the edge continuous detection function of the edge signal ES, but also high-speed recording is possible, and the block strategy of the APC area A light emission pattern can be set. The light emission pattern can be selected without preparing a control line for switching the light emission pattern when switching from the information recording area to the APC area. Since it is not necessary to provide a dedicated terminal for switching the light emission pattern, the package area does not increase and the light emission pattern (power level pattern) can be switched. In addition, the switching signal of the light emission pattern is multiplexed on the three transmission lines that transmit the timing information, and the timing skew due to the difference between the transmission line and the transmission method does not occur, so that the switching timing can be accurately controlled. .

<Laser Drive Method: Sixth Embodiment>
10 to 10D are diagrams for explaining the sixth embodiment of the sequential method. FIG. 10 is a diagram for explaining a first setting example of the sampling pulse SP. FIG. 10A is a diagram illustrating a second setting example of the sampling pulse SP. 10B to 10D are diagrams illustrating register setting information of the sampling pulse pattern storage unit 430 in the sixth embodiment.

  The sixth embodiment is an application example in the system configuration of the second example shown in FIG. 3A (that is, a configuration that also pays attention to APC control signals and sampling pulse SP generation / transmission techniques).

  First, in order to facilitate understanding of the mechanism of the sixth embodiment, first, an example of a basic mechanism of a method for generating and transmitting the sampling pulse SP when the sequential method is used will be described. A mechanism of the sixth embodiment will be described.

[Sampling pulse setting: First example]
The first setting example shown in FIG. 10 sets a sampling pulse SP_1 for a mark. The laser emission waveform has four power levels: cool, erase, peak, and overdrive. Among these, the power level for forming the mark can be considered as peak and overdrive, and the power level for forming the space can be considered as cool and erase.

  For example, the sampling pulse SP_1 for the mark supplied to the sample hold circuit 332 starts from a certain edge for forming a mark, and the delay time, pulse width from there, and the whole for delay compensation up to the sample hold circuit 332 Create a delay time.

  Here, a description will be given of a case where the sampling pulse SP_1 samples and holds a peak level having a relatively wide width between the peak forming the mark and the overdrive. Since the sampling pulse SP_1 is used to sample and hold the peak level of the power monitor signal PM, the timing is set so that the power monitor signal PM can be sampled after it has settled from the overdrive level to the peak level. Therefore, it is preferable to generate the peak level based on the start position because it is not affected by the space width. In setting the timing for sampling the peak level, compensation for the signal band and delay of the signal path from the pulse generation unit 202 to the sample hold circuit 332 is considered.

  For example, when the castle method is applied, as shown in FIG. 10, the peak level start timing T12 is set to the starting edge (reference edge) for sampling the peak level. Starting from the reference edge T12, a rising delay time TD1_1 (T12 to T13) that defines the rising timing T13 of the sampling pulse SP_1 is set. The rise delay time TD1_1 is set in consideration of the time during which the power monitor signal PM input to the sample hold circuit 332 settles from the overdrive level to the peak level.

  Further, starting from the rising timing T13, a pulse width PW1 (T13 to T14) that defines the active H period of the sampling pulse SP_1 and a pulse delay time TD1_2 (T13 to T15) until the active pulse H actually becomes active are set. . The pulse delay time TD1_2 is set in consideration of compensating for the difference between the delay time of the sampling pulse and the delay time of the power monitor signal PM in the signal path from the pulse generator 202 to the sample hold circuit 332. The delay time of the sampling pulse is a time required until the sampling pulse is input from the pulse generator 202 through the sampling pulse generator 400 to the sample hold circuit 332. Further, the delay time of the power monitor signal PM means that the semiconductor laser 41 emits light from the pulse generation unit 202 through the light emission waveform generation unit 203, and the light enters the light receiving element 310 and the current-voltage conversion unit 313 and the variable gain type. This is the time required for input to the sample hold circuit 332 via the amplifier 315. As a result, the sampling pulse SP_1 rises after “TD1_1 + TD1_2” has elapsed from the timing T12, and falls after the pulse width PW1 has elapsed.

  In the case of a short mark with a short mark length, the setting is made so that the mark sampling pulse SP_1 is not generated. For example, the period from the reference edge T12 to the overdrive start timing T14 at the end of the peak level is set in the sampling pulse output determination setting period DET1. When the sampling pulse output determination setting period DET1 does not reach a predetermined value, the sampling pulse SP_1 is not output. For example, in a waveform that requires 10 ns for stabilization from the overdrive level to the peak level in the power monitor signal PM, the correct peak level can be sampled and held by setting the rise delay time TD1_1 to 10 ns or more. At this time, the sampling pulse output determination setting period DET1 is set to 10 ns, so that the sampling pulse SP_1 is not generated in a pulse having a peak level width of 10 ns or less.

[Sampling pulse setting: 2nd example]
In the second setting example shown in FIG. 10A, a sampling pulse SP_2 for space is set. The laser emission waveform has the same power level as in FIG.

  The generation of the sampling pulse SP_2 for space is the same as that for the mark as follows. In other words, the sampling pulse SP_2 for the space is generated by setting a delay time, a pulse width, and an overall delay time for delay compensation up to the sample hold circuit 334 from a certain edge for forming the space. To do.

  Here, the case where the sampling pulse SP_2 samples and holds an erase level having a relatively wide width between cool and erase forming a space will be described. Since the sampling pulse SP_2 is used to sample and hold the erase level of the power monitor signal PM, the timing is set so that the power monitor signal PM can be sampled after being settled from the cool level to the erase level. Therefore, it is preferable to generate with reference to the start position of the erase level because it is not affected by the mark width. In setting the timing for sampling the erase level, compensation for the signal band and delay of the signal path from the pulse generation unit 202 to the sample hold circuit 334 is considered.

  For example, when the castle method is applied, as shown in FIG. 10A, the start timing T32 of the erase level is set to the start edge (reference edge) for sampling the erase level. Starting from the reference edge T32, a rising delay time TD3_1 (T32 to T33) that defines the rising timing T33 of the sampling pulse SP_2 is set. The rise delay time TD3_1 is set in consideration of the time for the power monitor signal PM input to the sample hold circuit 334 to settle from the cool level to the erase level. Further, starting from the rising timing T33, the pulse width PW3 (T33 to T34) for defining the active H period of the sampling pulse SP_2 and the pulse delay time TD3_2 (T33 to T37) until the active pulse H actually becomes active are set. . The pulse delay time TD3_2 is set in consideration of compensating for the difference between the delay time of the sampling pulse and the delay time of the power monitor signal PM in the signal path from the pulse generator 202 to the sample hold circuit 334. In this way, the sampling pulse SP_2 rises after “TD3_1 + TD3_2” has elapsed from the timing T32, and falls after the pulse width PW3 has elapsed.

  In the case of a short space with a short space length, the setting is made so that the sampling pulse SP_2 for space is not generated. For example, the period from the reference edge T32 to the overdrive start timing T35 at the end of the erase level is set in the sampling pulse output determination setting period DET3. When the sampling pulse output determination setting period DET3 does not reach a predetermined value, the sampling pulse SP_2 is not output. For example, in a waveform that requires 10 ns for stabilization from the cool level to the erase level in the power monitor signal PM, the correct erase level can be sampled and held by setting the rise delay time TD3_1 to 10 ns or more. At this time, the sampling pulse output determination setting period DET3 is set to 10 ns, so that the sampling pulse SP_2 is not generated for a pulse whose erase level width is 10 ns or less.

[Sampling pulse switching]
As described in the fifth embodiment, sampling for APC becomes difficult for a short mark or a short space due to high speed. On the other hand, in the sampling pulse setting example described above, it is possible to set so that sampling pulses are not generated for short marks and spaces shorter than the specified length. This mechanism allows selection only for long marks and spaces exceeding the specified length. Sampling is possible.

  In the first and second examples of setting the sampling pulse, whether or not the sampling pulses SP_1 and SP_2 are generated is specified by the values of the sampling pulse output determination setting periods DET1 and DET3. Therefore, basically, it is not absolutely necessary to prepare two pieces of setting information. However, as the significance of switching the setting of the sampling pulse, for example, the following two points can be considered.

1) If a signal that does not output the sampling pulse SP is put on the input signal, the sampling pulse generator 400 does not need to measure the sampling pulse output determination setting period DET1 for determining the output, and the sampling pulse generator 400 Simplify.

2) When the level pattern of the short mark is switched with continuous edges, the amount of change in power from overdrive OD1 to peak peak and overdrive OD2 to peak peak (Peak is the same power) changes and the settling time also differs. Therefore, it is necessary to vary the rising position (rising delay time TD1_1) and falling position (pulse delay time TD1_2) of the sampling pulse SP.

  Here, 1) is switching only for sampling pulse setting, and 2) is premised on the combined use of power level pattern switching and sampling pulse setting switching.

  In addition, when the mark is short, the rise delay time TD_1 is set short and sampling is performed immediately after the monitoring waveform signal is settled. When the mark is long, the rise delay time TD_1 is set long and the monitoring waveform signal is sufficiently settled. It is possible to sample at timing. In this way, APC can be performed without lowering the sampling frequency even if the speed is increased. In this case, in order to change the rise delay time TD_1 between the short mark and the long mark, it is necessary to switch the setting information of the sampling pulse SP.

  In these cases, in order to switch the setting information of the sampling pulse SP, a method using a dedicated terminal can be considered, but there are problems of an increase in package area and switching timing accuracy. This is a problem common to the second to fifth embodiments.

  In order to deal with this, in the sixth embodiment, the setting information of the sampling pulse SP is switched using the continuous / non-continuous information of the edge of the edge signal ES. The configuration on the transmission signal generation unit 500 side is the same as that of the transmission signal generation unit 500A of the first embodiment.

  On the side of the sampling pulse generator 400, a mechanism for storing two types of setting information with different sampling pulse output determination setting periods DET1 and DET3 is provided. One setting is to generate sampling pulse SP regardless of mark length or space length (DET1, DET3 is set to be long), and the other is set to not generate sampling pulse SP for short marks or short spaces that are less than the specified length (DET1, DET3) Is a short setting). Alternatively, one can set the rise delay time TD_1 short when the mark is short and sample immediately after the monitored waveform signal settles, and the other set the rise delay time TD_1 long and monitor when the mark is long Sampling is performed at a timing when the waveform signal is sufficiently settled.

  As a basic idea, an idea of preparing a plurality of register sets 231 for switching the power level pattern is adopted. At this time, there are also two power level patterns, and the light emission pattern may be changed according to the mark length and the space length, or only the setting of sampling pulse generation may be changed.

  In this embodiment, since the register set 431 is switched using the reset pulse RP and the selection pulse MC generated at the space timing as triggers, the settings for mark sampling and space sampling are switched in conjunction with each other. That is, since the setting of mark sampling and space sampling is switched according to the pair of mark length and space length, the settings of mark sampling and space sampling are switched in conjunction with each other.

  For example, FIG. 10B is a first example in which both the setting information of the sampling pulse SP and the power level pattern are switched. FIG. 10C is a second example in which only the setting information of the sampling pulse SP is switched and the power level pattern is not switched.

  In any configuration, the sampling pulse pattern storage unit 430 of the sampling pulse generation unit 400 generates setting information (DET @, TD @ _1, PW @, TD @ when generating the sampling pulses SP_1 and SP_2 based on the write strategy signal. _2). The sampling pulse pattern storage unit 430 is an example of a second storage unit and is different from the light emission level pattern storage unit 230.

  The sampling pulse pattern storage unit 430 includes a register set 431_0 that functions as a main storage unit, register sets 431_1 and 431_2 that function as sub storage units, and a storage information control unit 436. The register set 431_0 includes a plurality of registers 432_1 to 432_k. Although this is not shown, the same applies to the register sets 431_1 and 431_2.

  The register sets 431_1 and 431_2 are set information (DET @, TD @ _1, PW @, TD @ _2) when the sampling pulses SP_1 and SP_2 are generated in response to a sampling pulse setting information register input instruction from a main control unit (not shown). ) Is stored separately. The register set 431_0 corresponds to the register set 231_0. The storage information control unit 436 corresponds to the storage information control unit 236, and reads out the storage information of one of the register sets 431_1 and 431_2 based on the reset pulse RP and the selection pulse MC and causes the register set 431_0 to hold it. The sampling pulse generator 400 reads the information in each register 432 of the register set 431_0 and generates sampling pulses SP_1 and SP_2 according to the values.

  As described above, in the sixth embodiment, the setting information of the sampling pulse SP can be switched using the edge continuous detection function of the edge signal ES. The setting information of the sampling pulse SP can be selected without preparing a control line for switching the setting information. Since there is no need to provide a dedicated terminal for setting information switching, there is no increase in the package area, and the setting information of the sampling pulse SP can be switched. In addition, the switching signal of the setting information of the sampling pulse SP is multiplexed on the three transmission lines that transmit the timing information, and there is no timing skew due to the difference between the transmission line and the transmission method, so the switching timing is accurately controlled. can do.

  In this example, the selection pulse MC generated using the edge continuous detection function of the edge signal ES is used for memory switching of the sampling pulse pattern storage unit 430, but this is not essential. For example, when two reset signals RS_1 and RS_2 are used, a reset pulse RP_1 is generated from the reset signal RS_1, and a reset pulse RP_1 is generated from the reset signal RS_2. Then, regardless of the configuration on the light emission level pattern storage unit 230 side, they may be used for memory switching as selection pulses as in the third example shown in FIG. 10D.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above embodiment, two edge signals ES_1 and ES_2 are used, and two types of power level patterns are switched depending on whether the edge of the edge signal ES before and after the reset is continuous or non-continuous (edge continuous detection). This is just an example. The number of edge signals ES may be three or more. In this case, if the edge of one edge signal ES (that is, the edge pulse EP) continues, the pattern is switched to another pattern, and if the edge is discontinuous, the normal operation is performed. For example, in the case of three edge signals ES_1, ES_2, and ES_3, when the normal operation is EP_1 → EP_2 → RP → EP_3 → EP_1, and EP_1 → EP_2 → RP → EP_2 → EP_3 → EP_1, RP → EP_2 At the time of reading another pattern.

  DESCRIPTION OF SYMBOLS 1 ... Recording / reproducing apparatus, 3 ... Laser drive system, 14 ... Optical pick-up, 41 ... Semiconductor laser, 47 ... Drive current control part, 48 ... Recording waveform production | generation part, 49 ... Laser drive part, 50 ... Recording / reproduction signal processing part 58 ... APC control unit, 200 ... laser drive circuit, 202 ... pulse generation unit, 203 ... light emission waveform generation unit, 210 ... reset pulse generation unit (first pulse generation unit), 220 ... edge pulse generation unit (second pulse) Generation unit), 230 ... light emission level pattern storage unit, 280 ... selection pulse generation unit (third pulse generation unit), 290 ... write strategy circuit, 300 ... power monitor circuit, 400 ... sampling pulse generation unit, 430 ... sampling pulse pattern Storage unit, 500 ... transmission signal generation unit, 524 ... light emission level pattern selection signal generation circuit

Claims (15)

A first pulse generation unit that generates the reference pulse by detecting the edge of the first transmission signal indicating information defining the acquisition timing of the reference pulse indicating the timing of switching between space and mark repetition;
The switching pulse is detected by detecting the edge of the second transmission signal indicating the information that defines the acquisition timing of the switching pulse indicating the switching timing of the divided power levels of the light emission waveforms of the space and the mark. A second pulse generator for generating
Among the power level information of the light emission waveform, reference level information that is level information of the position of the reference pulse is output for each reference pulse, and other level information following the reference level information is sequentially output for each switching pulse. A light emission waveform generator that
A light emission level pattern storage unit for storing a recording waveform control signal pattern indicating level information about the light emission waveform;
A plurality of sub storage units that store a plurality of different setting information, a main storage unit that selectively stores any setting information stored in the plurality of sub storage units, and the plurality of sub storage units A second storage unit comprising a storage information control unit that selects and stores any setting information stored in the main storage unit;
A laser drive device comprising: The first pulse generation unit is configured to generate the reference pulse by detecting one edge of the first transmission signal with a set of the space and the mark as one unit.
The second pulse generation unit is configured to generate the switching pulse by detecting edges of the plurality of second transmission signals,
A third pulse that generates a selection pulse based on the switching pulse immediately after the reference pulse when each of the switching pulses immediately before and after the reference pulse is based on the same edge of the second transmission signal. A generation unit;
The storage information control unit is stored in the plurality of sub storage units based on the reference pulse acquired by the first pulse generation unit and the selection pulse acquired by the third pulse generation unit. The laser driving device according to claim 1, wherein any setting information is selected and stored in the main storage unit. The second storage unit is also used as the light emission level pattern storage unit,
At least one of the plurality of sub storage units stores a recording waveform control signal pattern indicating level information about the emission waveform,
The light emission waveform generation unit reads, for each reference pulse, reference level information that is level information of a position of the reference pulse among power level information for each of the light emission waveforms stored in the main storage unit, The laser driving apparatus according to claim 1, wherein other level information following the reference level information is sequentially read for each switching pulse. The laser driving device according to claim 3, wherein each of the plurality of sub storage units stores a recording waveform control signal pattern indicating level information about the light emission waveform. One of the two sub storage units stores a recording waveform control signal pattern indicating level information about the emission waveform corresponding to the land area of the recording medium,
The laser driving apparatus according to claim 3, wherein the other of the two sub storage units stores a recording waveform control signal pattern indicating level information about the light emission waveform corresponding to a groove area of a recording medium. 4. The laser driving device according to claim 3, wherein each of the two sub storage units stores a recording waveform control signal pattern indicating level information about the light emission waveform according to a circumferential position of the recording medium. 4. The laser driving device according to claim 3, wherein each of the two sub storage units stores a recording waveform control signal pattern indicating level information about the light emission waveform in accordance with a set value of OPC recording power adjustment. The laser driving apparatus according to claim 6 or 7, wherein the setting information of the other of the two sub storage units is rewritten during a period when one of the two sub storage units is not used. One of the two sub storage units stores a recording waveform control signal pattern indicating level information about the light emission waveform for performing information recording in an information recording area in a recording medium,
The other of said two sub-storage parts memorize | stores the recording waveform control signal pattern which shows the level information for performing APC light emission power adjustment in the area | region for APC light emission power adjustment of a recording medium. Laser drive device. The laser driving apparatus according to claim 9, wherein the other of the two sub storage units stores a recording waveform control signal pattern according to a block strategy system as level information for performing the APC emission power adjustment. A sample-and-hold unit that samples and holds an electrical signal based on laser light emitted from the laser element;
A sampling pulse generator for sampling and holding the electrical signal based on the edge of the light emission waveform based on the reference pulse and the switching pulse and supplying the sampling pulse to the sample hold unit;
With
The light emission waveform generation unit reads, for each reference pulse, reference level information that is level information of the position of the reference pulse among power level information for each of the light emission waveforms stored in the light emission level pattern storage unit. The other level information following the reference level information is sequentially read for each switching pulse,
The second storage unit is also used as a sampling pulse pattern storage unit that stores setting information that defines a pulse pattern of the sampling pulse,
The plurality of sub storage units store a plurality of different setting information defining a pulse pattern of the sampling pulse;
The laser driving device according to claim 1, wherein the sampling pulse generation unit generates the sampling pulse based on the setting information stored in the main storage unit. A laser element;
A drive unit for driving the laser element;
An optical member for guiding laser light emitted from the laser element;
A light emission waveform pulse generation unit that generates a plurality of pulse signals that define a light emission waveform that is a combination of drive signals having different levels with respect to spaces and marks, based on a recording clock and recording data;
Based on a plurality of pulse signals generated by the light emission waveform pulse generation unit, a first transmission signal indicating information that defines an acquisition timing of a reference pulse indicating a switching timing of the space and the mark repeatedly with an edge; A transmission signal generation unit that generates a second transmission signal indicating an edge with information defining the acquisition timing of the switching pulse indicating the switching timing of the light emission waveform;
Pulse generation comprising a first pulse generation unit that generates the reference pulse based on an edge of the first transmission signal and a second pulse generation unit that generates the switching pulse based on an edge of the second transmission signal And
Among the power level information of the light emission waveform, reference level information that is level information of the position of the reference pulse is output for each reference pulse, and other level information following the reference level information is sequentially output for each switching pulse. A light emission waveform generator that
A light emission level pattern storage unit for storing a recording waveform control signal pattern indicating level information about the light emission waveform;
A plurality of sub storage units that store a plurality of different setting information, a main storage unit that selectively stores any setting information stored in the plurality of sub storage units, and the plurality of sub storage units A second storage unit comprising a storage information control unit that selects and stores any setting information stored in the main storage unit;
A first mounting unit on which the laser element, the driving unit, the optical member, the pulse generation unit, the light emission waveform generation unit, the light emission level pattern storage unit, and the second storage unit are mounted; and the light emission waveform pulse A transmission member for transmitting a signal interposed between the generation unit and the second mounting unit on which the transmission signal generation unit is mounted;
Optical device with The second storage unit is also used as the light emission level pattern storage unit, and stores a recording waveform control signal pattern indicating level information about the light emission waveform in at least one of the plurality of sub storage units,
The light emission waveform generation unit outputs, for each reference pulse, reference level information that is level information on the position of the reference pulse among power level information for each of the light emission waveforms stored in the main storage unit, The optical device according to claim 12, wherein a light emission waveform is generated by sequentially outputting other level information subsequent to the reference level information for each switching pulse. The first mounting unit includes a photoelectric conversion unit that converts laser light emitted from the laser element into an electric signal, a sample hold unit that samples and holds an electric signal obtained by the photoelectric conversion unit, and the electric A sampling pulse generation unit that generates a sampling pulse for sampling and holding a signal based on an edge of the light emission waveform and supplies the sampling pulse to the sample hold unit is further mounted,
The second mounting unit generates a laser power instruction signal for setting the power level of the laser light to an appropriate level based on the sample hold signal obtained by the sample hold unit, and sends the laser light instruction signal to the emission waveform generation unit. A supply APC control unit is further installed,
The second storage unit is also used as a sampling pulse pattern storage unit that stores setting information that defines a pulse pattern of the sampling pulse.
The plurality of sub storage units store a plurality of different setting information defining a pulse pattern of the sampling pulse;
The optical device according to claim 12 or 13, wherein the sampling pulse generation unit generates the sampling pulse based on the setting information stored in the main storage unit. A laser element;
A drive unit for driving the laser element;
An optical member for guiding laser light emitted from the laser element;
A first pulse generation unit that generates the reference pulse based on a first transmission signal that indicates the timing for obtaining a reference pulse indicating the timing for switching between repetition of space and mark, and switching of the light emission waveform A pulse generation unit including a second pulse generation unit that generates the switching pulse based on a second transmission signal indicating an edge with information defining the acquisition timing of the switching pulse indicating the timing;
Among the level information of the light emission waveform, reference level information that is level information of the position of the reference pulse is output for each reference pulse, and other level information subsequent to the reference level information is sequentially output for each switching pulse. A light emission waveform generator;
A light emission level pattern storage unit for storing a recording waveform control signal pattern indicating level information about the light emission waveform;
A plurality of sub storage units that store a plurality of different setting information, a main storage unit that selectively stores any setting information stored in the plurality of sub storage units, and the plurality of sub storage units An optical unit comprising: a second storage unit including a storage information control unit that selects and stores any setting information stored in the main storage unit.

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