JP2005122817A - Optical information recording device and semiconductor circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase accuracy in a recording position on a medium and that for setting a sampling pulse, and to speed up a transfer rate in an optical disk recording device. <P>SOLUTION: Two systems of recording signals (100, 102) and synchronous clocks (101, 103) are outputted from a controller LSI (11), one system is fed to a laser driver LSI (5), and the other is fed to an analog front end LSI (10). Delay in the two systems of recording signals can be independently adjusted inside the controller LSI. A sample hold pulse generation circuit is provided inside the analog front end LSI. The recording signals and the synchronous clocks use an interface having a small amplitude of 2V or less. As a result, positioning precision at a recording position on a medium is improved, and recording operation can be speeded up. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to optical recording of information on a recording medium such as an optical disk, and more particularly to information recording by irradiating a recording medium with a laser beam whose light intensity is modulated with a pulse-like signal.

  An optical information recording / reproducing apparatus irradiates a recording film of an information recording medium with a light beam, forms recording marks such as drilling pits, phase change pits, dye pits or magnetic domains on the recording film, records information, and records information. Information is reproduced using reflected light from the medium. Along with the high density recording on the recording medium, it is required to form marks (or bits) recorded on the surface of the information recording medium, for example, with a length of 0.5 μm or less, and recording is performed in order to realize this mark formation. There is a need for power control in which power is pulse-divided (multi-pulsed) and the level is changed to multiple values (for example, ternary or quaternary). For example, as disclosed in Patent Document 1, a configuration in which a multi-pulse circuit that generates a multi-pulse from a recording signal is provided on an optical pickup or inside a laser drive circuit has been proposed.

  In the CD-R recording apparatus, when recording information, optimization control of laser power during recording called OPC (optimum power control) is performed. OPC is a power control method in which an area for trial writing in which user data is not recorded is provided in a predetermined area of the disk, recording is performed while changing the power, and the optimum power value is obtained from the waveform of the reflected light amount during recording. Furthermore, in a power control method called ROPC (running optimum power control), the amount of reflected light is measured even during recording of user data, and is compared with the amount of reflected light during OPC by test writing. Based on the comparison result, the writing power is changed during user data recording to compensate for changes in mark formation conditions due to temperature fluctuations of the drive.

  In an optical disc, a run length limiting code, which is a code that limits the number of consecutive zeros and the number of ones, is used as a modulation method for recording on a medium, and a self-clocking operation using a clock synchronized with reproduced data is enabled. Yes. For example, in the DVD standard, both the mark length and space length are 3T to 14T (T: unit of recording bit) by using the NRZI conversion that inverts the run length limit code and the pulse signal at every rising edge or falling edge. Period). For example, in an optical disk using a phase change material or an organic dye as a recording film, a strong laser beam is irradiated with a mark and a laser beam intensity is reduced with a space. Also, the mark has a low reflectance and the space has a high reflectance. In the mark formation process at the time of recording, the mark formation start timing is almost close to a space state and the amount of reflected light is large. As the mark formation proceeds, the amount of reflected light decreases. When the amount of reflected light is monitored by OPC or ROPC, a method of AD-converting an electrical signal corresponding to the amount of reflected light by sample-holding using a pulse signal at a predetermined timing in the mark formation process is employed. Although the amount of reflected light changes during the mark formation process, if the sample hold pulse is generated with sufficient timing accuracy, the variation between the information of the reflected light amounts obtained by a plurality of marks can be reduced.

  An optical disc is generally provided with an APC (auto power control) circuit that controls the laser power so that the laser power during playback is converted into an electrical signal, compared with the target level, and the difference is canceled. It is used. In recent years, there are cases where the same method is used for controlling the recording power. The laser power at the time of recording is strong at the timing of mark formation, weak in space, and not uniform. Also in this case, the laser power intensity signal is sampled and held using a pulse signal corresponding to the mark formation timing or space timing, this signal is compared with a target reference signal, and servo control is performed so as to cancel the signal. In this case, since the electrical signal corresponding to the mark or space of the emitted light is sampled and held, the level fluctuation due to the deviation of the sample timing position within the mark formation timing is small compared to the reflected light used at the time of OPC.

  In addition to the above, since the servo signal and WOBBLE signal obtained from the reflected light during recording are also modulated by the recording data, the signal level varies greatly between the mark portion and the space portion. Further, as described above, since the reflectance changes in the process of forming the mark portion, the signal level also varies depending on the timing position of the same mark portion during recording. Recently, a method in which such a servo signal or WOBBLE signal is once sampled and held in either a mark portion or a space portion and then sent to a subsequent servo circuit or WOBBLE detection circuit has begun to be used.

  Patent Document 2 describes a technique for optimizing laser power during data recording on an optical disk. That is, the laser light emitted from the semiconductor laser is detected by a photodetector, and the light intensity is sampled and held by a predetermined sample pulse. The laser power is optimized according to the sample hold result. At this time, the timing of the sample pulse can be set according to the response time of the propagation path of the laser emission light.

  In a general optical disk, a spiral or concentric information track is provided on the disk surface, and information is recorded / reproduced by irradiating a laser beam along the information track. The information track is divided into units called sectors in order to facilitate management of recording data, and an address is given to each. Data formats of recordable optical disks can be roughly divided into two types.

  One is a sector format in which an address portion and a data portion are separated, and this corresponds to a magneto-optical disk, DVD-RAM, or the like standardized by ISO / IEC10089 or the like. Since the address portion is completely separated, address reproduction and data recording can be performed in a time division manner without affecting each other even during recording. In addition, a buffer area called a Gap area is usually provided at the boundary between the address part and the data part, and the recording apparatus can perform laser power control in any sector during recording using the Gap area during data recording. Is possible.

  The other is a sector format in which the address portion and the data portion are not separated in a time division manner, and this corresponds to CD-R, CD-RW, DVD-R, DVD-RW, and the like. Since there is no separated address part, data can be recorded continuously, and the recording density (format efficiency) can be increased accordingly. On the other hand, it is necessary to simultaneously reproduce addresses while recording data, and laser power control must also be performed during data recording.

JP 2001-43531 A

JP 2001-357529 A

  In the optical disk drive apparatus described above, high-speed recording has been progressing in recent years. In the optical disk drive, when the recording transfer rate of recording data is increased, the rotation speed of the recording medium is increased with respect to the basic rotation speed at the same ratio as the ratio of the desired recording transfer rate to the basic recording transfer rate. The mark length per bit on the medium is kept constant to ensure medium compatibility. Among optical discs currently on the market, for example, an optical disc recording / playback drive called DVD-R is rotated at, for example, four times the basic rotational speed, and the bit rate of recorded data is increased to four times the basic speed. I am letting. The 1T period is around 38 ns (nanoseconds) in the case of the basic rotational speed, but around 9.6 ns at the time of quadruple speed recording. If the speed is further increased to about 16 times in the future, the 1T period becomes 2.4 ns. At 16 × speed, the recording mark passing time is 7.2 ns for 3T and 26.4 ns for 11T.

  Since the speed of the recording mark is shortened by such an increase in speed, the pulse width of the pulse signal for sampling the electrical signal corresponding to the emitted light or reflected light during recording by OPC / ROPC or APC is reduced. For example, a sample pulse of 1T width is 2.4 ns at 16-times speed, and in this case, it is difficult to transfer by a conventional low voltage transistor-transistor logic (LVTTL) or the like. In recent years, transmission of small amplitudes such as LVDS (low voltage differential signaling) has increased, but it is considered that restrictions such as having to take differential interfaces will occur. In addition, when differential transfer is performed, when a plurality of sample pulses are transmitted from the controller LSI to the analog front end LSI, both terminals of the controller LSI and the analog front end LSI are increased. Further, when a large number of high-frequency sample signals are transmitted on the substrate, the substrate noise increases.

  Further, when the 1T cycle is shortened, the signal transmission delay on the substrate and the delay time due to circuit processing become relatively large with respect to the 1T cycle, and consequently the mark length and space length. Such a delay varies with temperature and voltage, and also varies with each optical disk drive and every LSI, thereby degrading the positioning accuracy of the recording position on the medium. In addition, the timing setting accuracy of the sample pulse described above is affected.

  An object of the present invention is to make it possible to easily keep the sample timing of laser light detection optimum.

  Another object of the present invention is to improve the reliability of data recording on a recording medium such as an optical disk.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] An optical information recording apparatus according to the present invention performs information recording by irradiating a recording medium with a laser beam based on a recording signal, and comprises a laser light source, a drive circuit for the laser light source, A first sample hold circuit that samples and holds an emitted light signal obtained by detecting laser light emitted from a laser light source, and a reflected light signal obtained by detecting reflected light of the laser light emitted to the recording medium A sample hold timing generation circuit that determines a sample hold timing of the first sample hold circuit and a sample hold timing of the second sample hold circuit based on the recording signal, Programmable setting of the delay of the recording signal supplied to the sample hold timing generation circuit ; And a delay circuit. From the above, with respect to the difference in delay time between the response system that drives the laser light source with the recording signal and the response system that drives the laser light source with the recording signal to emit laser light and sample it, the first Depending on the setting of the delay amount by one delay circuit, it becomes easy to match the relationship between the recorded information and the sampled information to a desired state. If a second delay circuit capable of programmably setting the delay of the recording signal supplied to the laser light source driving circuit is provided, it becomes even easier. The adjustment range of the delay time of the two delay circuits can be widened, and the adjustment becomes easy even when the circuit delay time fluctuates due to temperature change or power supply fluctuation. As a result, it is possible to easily keep the sample timing of laser light detection optimum, and it is possible to contribute to improving the reliability of data recording on a recording medium such as an optical disk.

  The delay time by the first delay circuit refers to the time difference obtained by comparing the timing of the recording mark obtained by the reflected light from the disk being recorded and the timing of the pre-pit signal obtained from the reflected light. Can be determined. The delay time by the second delay circuit generates a sample signal from a recording signal having a specific mark length inside the analog front end unit, and samples and holds an electric signal corresponding to the reflected light from the disc at the timing of this sample signal. It can be determined with reference to the sampled and held value.

  As a desirable mode of the present invention, there is provided a control register for designating a delay amount by the first delay circuit and a delay amount by the second delay circuit. It is easy to set the delay time in a programmable manner.

  [2] A semiconductor circuit device according to the present invention is a device used in an optical information recording apparatus that records information by irradiating a recording medium with a laser beam based on a recording signal, and a laser emitted from a laser light source. A first sample and hold circuit that samples and holds an emitted light signal obtained by detecting light; and a second sample that holds a reflected light signal obtained by detecting reflected light of a laser beam irradiated on the recording medium. A sample hold circuit; a sample hold timing generation circuit for determining a sample hold timing of the first sample hold circuit and a sample hold timing of the second sample hold circuit based on the recording signal; and a supply to the sample hold timing generation circuit A first delay circuit capable of programmably setting a delay of the recording signal to be recorded; A. Similarly to the above, with respect to the difference in delay time between the response system that drives the laser light source with the recording signal and the response system that drives the laser light source with the recording signal to emit laser light and sample it, Depending on the setting of the delay amount by the first delay circuit, it becomes easy to match the relationship between the recorded information and the sampled information to a desired state. If a second delay circuit capable of programmably setting the delay of the recording signal supplied to the laser light source driving circuit is provided, it becomes even easier. As a specific form of the present invention, a small amplitude interface for receiving the recording signal differentially is provided.

  [3] A semiconductor circuit device according to the present invention is a semiconductor circuit device used in an optical information recording apparatus for recording information by irradiating a recording medium with a laser beam based on a recording signal, which is read from the recording medium. Supplied to an interface circuit for transferring the output data to the outside, a modulation circuit for modulating a recording signal to be recorded on the optical disc, and a sample hold timing generation circuit for determining the sample hold timing of the sample hold circuit However, the first delay circuit capable of programmably setting the delay with respect to the recording signal modulated by the modulation circuit is provided in one semiconductor chip.

  As a specific form, it has a second delay circuit in which a delay can be set in a programmable manner with respect to the recording signal modulated by the modulation circuit supplied to the driving circuit of the laser light source for emitting the laser light. . Also, a control register for designating a delay amount by the first delay circuit is provided. In addition, it has a small amplitude interface for differentially sending the modulated recording signal to the modulation circuit.

  [4] An optical information recording apparatus according to the present invention is an optical information recording apparatus that records information by irradiating a recording medium with a laser beam based on a recording signal, and includes a laser light source and driving of the laser light source. A circuit, a first sample hold circuit that samples and holds an emitted light signal obtained by detecting the laser light emitted from the laser light source, and a reflected light of the laser light applied to the recording medium are obtained. At least one of second sample and hold circuits that sample and hold the reflected light signal; a sample and hold timing generation circuit that determines a sample and hold timing of the at least one sample and hold circuit based on the recording signal; and the sample and hold timing First delay circuit capable of programmably setting a delay of a recording signal supplied to the generation circuit , Having a second delay circuit can be set to a programmable delay of a recording signal supplied to the driving circuit of the laser light source.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to improve the accuracy of the recording position on the recording medium and the setting accuracy of the sample pulse.

<< First Embodiment >>
FIG. 1 shows an example of an information recording / reproducing apparatus according to an embodiment of the present invention. The optical disk 1 is held by a spindle motor and rotates. Examples of the recording film forming the optical disc 1 include a magneto-optical recording film, a phase change recording film, and an organic dye film. The information recording / reproducing apparatus forms a semiconductor laser 4 that emits a laser beam 106 for recording / reproducing information and an optical system that forms a laser beam 106 from the semiconductor laser 4 as a light spot of about 1 micron on a disk surface (see FIG. PD6 (photo detector) as a light detector for performing light spot control such as information reproduction, autofocus, track tracking, etc. using the reflected light 108 from the optical disc 1, and light-current by the PD6 And an IV converter 8 for converting the converted current into a voltage. Also, a sample hold (S / H) circuit 18 that samples and holds the output of the IV converter 8, an AD converter 20 that performs AD (analog to digital) conversion on this value, and an output of the AD converter 20 are received. A system control unit 12 configured to provide at least an MPU (micro processing unit) 28 and a MEM (memory) 29, and to control the entire optical disk drive; a binarization circuit 14 that binarizes the reflected light voltage 111; PLL (phase locked loop) 15 for generating a synchronous clock, decoding of NRZI (non return to zero inverted) conversion, decoding of run length limited code (run length limited code), and ECC, if necessary (Error correction code) A data reproduction circuit 16 for reproducing user data by performing correction, etc., and an interface for transferring user data to an external device or device The count value is corrected by the circuit 17, the ID reproduction circuit 22 that reproduces the ID number corresponding to the position information of the data on the disk embedded in the reproduction data 122, and the ID detection timing signal 127 output from the ID reproduction circuit, A sector counter 23 that counts in synchronization with recording units on the medium such as sectors and blocks, and user data to be recorded sent from the interface circuit 17 are subjected to modulation processing such as ECC code addition, run-length encoding, NRZI conversion, and the like. The modulation circuit 117 that outputs the modulation data 117 synchronized with the count value 121 and the recording clock 118 synchronized therewith, the delay circuit 25 that delays the modulation data 117 by the delay time instructed by the system control unit 12, and the system control similarly. And a delay circuit 26 for delaying by a delay time according to an instruction from the unit 12. That. Further, the information recording / reproducing apparatus can record the pulse signal corresponding to the timing corresponding to the mark of the recording signal 102 from the recording signal 102 obtained by delaying the modulation data 117 and the recording clock 103 synchronized therewith, or the timing of the space of the recording signal 102. S / H signal generation circuit 21 that generates a pulse signal corresponding to the above, PD 7 that converts the light emitted from the semiconductor laser 4 into a current, an IV converter 9 that converts the output of PD 7 into a current-voltage, and this output The S / H circuit 19 samples and holds the output light voltage 112 of the output light by the output light sample pulse 116 output from the S / H signal generation circuit 21. The output light sample hold signal 114 output from the S / H circuit 19 is sent to the laser drive LSI 5. The laser drive LSI 5 incorporates a multi-pulse generation circuit that generates a multi-pulse signal by modulating the timing of a recording mark of the recording signal 100 in a pulse shape using a recording clock, and a semiconductor corresponding to the peak of the multi-pulse signal. The level of the laser drive current 105 output to the laser 4 is switched between two or more values. The value of the laser drive current 105 is servo-controlled so that the emitted light sample hold signal 114 becomes a specified level. The multi-pulse generation circuit and the current drive function of the semiconductor laser 4 are provided in a laser drive LSI 5. Although the method for servo-controlling the laser power is not shown in FIG. 1, the laser drive current 105 of the semiconductor laser 4 is reduced so that the difference between the emitted light sample hold signal 114 and the target voltage value is taken and the error is reduced. What is necessary is just to make it increase / decrease.

  The recording / reproducing apparatus described above is divided into an optical pickup unit 2 and a circuit board 3, and an FPC (flexible printed circuit) board is disposed on the optical pickup 2, on the FPC board, the laser drive LSI 5 described above, The circuit board 3 includes an AFE LSI (analog front end large scale integrated circuit) 10, a controller LSI 11, and a system control unit 12. The semiconductor laser 4, PD 6, PD 7, and IV converters 8 and 9 are included. The optical pickup unit 2 and the circuit board 3 are connected by a cable. The AFELSI 10 includes a binarization circuit 14, a PLL 15, an S / H circuit 18, an S / H circuit 19, an AD converter 20, and an S / H signal generation circuit 21. The controller LSI 11 includes a data reproduction circuit 16, an ID reproduction circuit 22, a sector counter 23, an interface circuit 17, a modulation circuit 24, a delay circuit 25, and a delay circuit 26. Although not described in detail here, the system control unit 12 includes a MEM 29 that includes a program memory that holds an operation program of the MPU 28, a RAM that serves as a work memory of the MPU 28, and the like. The system control unit 12 controls the AFE LSI 10 and the controller LSI 11 via the MPU 28 bus and control port. As the circuit board disposed in the optical pickup unit 2, it is preferable to use an FPC board, but a general circuit board may be used. The optical pickup unit 2 can be moved by a sled motor 13 and can irradiate an arbitrary track on the disk 1 with a light spot. The laser drive LSI 5, the analog front end LSI 10, the controller LSI 11, and the system control unit 12 are each formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon.

  As the binarization circuit 14, as shown in the DVDRAM standard established by the DVD forum, ID portions are arranged as prepits at regular intervals on the track, and user data is recorded in a period from one ID to the next ID. In such a case, the reflected light voltage 111 is binarized as shown in FIG. 1, and the binarized data is subjected to PLL, and the data reproduction circuit 16 and the ID reproduction circuit 22 arranged in the controller LSI 11 are used. Data and ID are demodulated respectively. Further, when the ID is recorded as a pit in the land portion adjacent to the recording track (groove) as shown in the DVD-R standard established by the same DVD forum, the reproduction of user data is slightly different from FIG. ID information recorded as land prepits by the binarization circuit 14, PLL 15, and data reproduction circuit 16 shown in FIG. 1 is provided with a known land prepit detection circuit inside the AFELSI 10, and this binarized prepit is provided. The controller LSI 11 is provided with an ID reproduction circuit that decodes the ID information by the prepit according to a certain rule, the ID information is reproduced from the prepit signal, and the count value is corrected by the reproduction timing signal to thereby adjust the timing of the sector counter 23. ID (i) by pre-pits arranged on lands on the optical disk 1 dentfication). Furthermore, as shown in the CD-R (compact disc recordable) standard, ID information may be recorded by changing the frequency or phase of WOBBLE (meandering or waviness of the recording surface). Is provided with a circuit for detecting and binarizing WOBBLE and a circuit for reproducing ID from this signal, and correcting the count value at the reproduction timing of this ID to synchronize the sector counter with the ID timing by WOBBLE. . As described above, the configurations of the binarization circuit 14, the PLL 15, the data reproduction circuit 16, and the ID reproduction circuit 22 are determined according to the standard of the target disc. As for sector synchronization, it is only necessary to have a function for reproducing user data on a track and an ID reproduction function, and the sector counter 23 can be synchronized with the timing of IDs on the medium. The detection result of the ID information may be used as a signal for correcting the sector counter 23, but the sector counter may be synchronized at a detection timing of a synchronization signal for reproducing the ID. The present invention uses part or all of the position information signal recorded in advance on the disc, such as recorded WOBBLE, land pre-pits, pre-pits alternately arranged on the same track as user data, and the sector counter 23 It is only necessary to synchronize the operation timing of the sector counter value 121 and, eventually, the change timing of the sector counter value 121.

  As a clock for the sector counter 23, an oscillator clock having a desired frequency may be used. In addition, if a signal obtained by multiplying or dividing the above-mentioned WOBBLE signal is used as a clock, the clock cycle changes following the rotational fluctuation caused by the motor that rotates the optical disk or the eccentricity of the disk. It is possible to take good timing with the position information on the medium. Although not shown in FIG. 1, an oscillator clock may be used as the modulation circuit clock, but a clock generated from WOBBLE may be used as described above. When the delay circuit 25 and the delay circuit 26 are constituted by shift registers, a clock is required. However, if the same clock as the modulation circuit is used as the recording clock 118, the recording clock 101, and the recording clock 103, the circuit configuration is simplified. .

  As the S / H circuit 18 and the S / H circuit 19, for example, a switched capacitor circuit composed of an analog switch and a capacitor may be used.

  FIG. 2 shows an example of the S / H signal generation circuit 21 shown in FIG. Shift registers 40a to 40o that capture and shift the recording signal 102 with the recording clock 103, and mark length (laser beam irradiation length with strong intensity) or space length (laser beam irradiation with strong intensity) based on the output values of the shift registers 40a to 40o. A pulse width detection circuit 42 that detects the length), a pulse generation circuit 41 that outputs a pulse signal corresponding to the timing of the recording mark or space from the output values of the same shift registers 40a to 40o, and a pulse output from the pulse generation circuit 41 Is composed of selctors 43 and 44 for selecting. When the pulse width detection circuit 42 detects a pulse width having a specified width of 3T to 14T, it outputs a pulse width measurement value 126 indicating the width, and outputs 0 otherwise. The selectors 43 and 44 select and output a sample pulse that changes at a timing corresponding to the width indicated by the pulse width measurement value 126 from the output of the pulse generation circuit 42. Reference numerals 115 and 116 denote selected and output sample pulses. The selectors 43 and 44 are supplied with a control signal 125 from the system control unit 12 so that the timing of the sample pulses 115 and 116 can be adjusted. For example, it is possible to control such that the sample timing is cysted in the latter half of the reproduction pulse by the settling time of the reproduction pulses 111 and 112.

  FIG. 3 shows an operation time chart of FIG. 1 and FIG. FIG. 3 illustrates a case where the values obtained by NRZI conversion in the controller LSI 11 are output as the recording signal 102 and the recording signal 100. In FIG. 3, if the write timing 506a on the disk is, for example, the position shown in the figure, the corresponding modulation data 117 is output earlier than the write timing 506a on the disk as the modulation data output timing 129. The modulation data 117 is delayed by Tw1 by the delay circuit 26 and sent to the laser drive LSI 5 mounted on the optical pickup 2. A multi-pulse is generated inside the laser drive LSI 5 and a laser drive current 105 is output. The laser beam 106 is emitted with a laser beam intensity 110 corresponding to this current with a delay of Tw2, and the mark 120 on the track is formed with a delay of Tw3. The By switching the delay time Tw1 according to an instruction from the system control unit 12, the writing position can be matched with the writing timing 506a on the disk. Switching of the delay time Tw1 is instructed to the delay circuit 26 by the control signal 27.

  Further, the reflected light voltage 111 corresponding to the recording mark 120 formed in FIG. 3 is output with a delay of Tw4. On the other hand, the modulation data 117 is delayed by Ts1 by the delay circuit 25 and sent to the S / H signal generation circuit 21 built in the AFELSI 10. The pulse width detection circuit 42 decodes the outputs of the shift registers 40a to 40o and outputs a pulse width measurement value 126. For example, when detecting a 6T length mark, as shown in FIG. 3, the pulse width detection circuit 42 detects that 40h to 40o coincides with 01111110, so that a flip-flop (not shown) inside the pulse width detection circuit 42 is shown. 2), the value “6” is stored, and when 40n and 40o become “0, 1” by the subsequent shift operation, “0” is latched in the flip-flop. The output value of the flip-flop is set to “6” only during the 6T pulse period of the shift register 40o, and is set to “0” at other timings. Similarly, the pulse width detection circuit 42 decodes the values of 40h to 40o corresponding to the marks of 3T to 14T, and values 3 to 14 are supplied to the flip-flops inside the pulse width detection circuit 42 corresponding to the marks. When 40n, 40o becomes "0, 1", "0" is latched in the flip-flop, and this is output as the pulse width measurement value 126, so that the "H" period of the shift register 40o During this period, the pulse width measurement value 126 holds the value of the pulse width, and “0” is output during the “L” period.

  For example, since the pulse width of a 3T pulse is short, it is difficult to set the timing of sample and hold. In particular, when the time of 1T is several ns or less, it becomes difficult to accurately set the timing of sample and hold with respect to, for example, a 3T reflected light pulse. It is desirable to set a sample hold pulse for a mark or space of a predetermined length or longer. In the S / H signal generation circuit 21 of FIG. 2, the sample hold timing may be set according to the value of the pulse width measurement value 126. For example, a sample pulse may not be output for a mark having a predetermined length or less. The delay time of the S / H signal generation circuit 21 requires a mark / space length measurement time when the mark length or the space length is detected and the timing corresponding to this can be freely set. A time equivalent to or longer than the longest mark / space length to be measured is required.

  Although not shown here, as another example of the S / H signal generation circuit 21, for example, a sample pulse is output with a delay of, for example, 2T for a mark of 4T or more, and the end of the sample is at the end of the mark portion of the reflected light For example, in the case of timing setting such as 1T before, if a 3-stage shift register is provided and 1T is delayed per stage, it is sufficient to take an AND of the third stage and the input signal. The signal is delayed by 2T with respect to the rise of the output signal of the stage and is 1T before the fall. That is, the sample hold signal is virtually delayed by 1T. Thus, although depending on the circuit configuration of the S / H signal generation circuit 21, a circuit delay of 1T to the maximum mark length / space length or more occurs.

  In addition, as a multi-pulse generation circuit built in the laser drive LSI 5, for example, a shift register that alternately shifts in the normal phase and reverse phase of the 1T cycle synchronous clock is provided, and multi-pulses can be generated easily from the decoded value of the output. it can. However, on the other hand, as shown in Japanese Patent Laid-Open No. 2001-43531, a PLL circuit is provided in the laser drive circuit unit, and this PLL circuit is oscillated at a period sufficiently faster than the 1T period in synchronization with the recording clock. A method for correcting the width of each pulse with high accuracy has been proposed. The circuit configuration of the laser drive LSI becomes complicated and the circuit delay time of the signal may increase.

  Further, recently, with the aim of increasing the transfer rate, the optical disk recording / reproducing apparatus has been increased in speed. For example, in the DVD-R standard standardized by the DVD Forum, a 4 × speed recording / reproducing apparatus has begun to be commercialized, and when the speed is further increased to about 16 × speed, the 1T cycle becomes 2.4 ns. In addition to the delay time set in units of clocks, the delay time of the logic gate and the delay time of the input / output buffer cannot be ignored. The recording signal includes a synchronization error with the medium of the sector counter 23, a delay of the transmission path connected to the optical pickup of the recording signal 100, a delay inside the laser drive LSI 5 including the multi-pulse generation circuit, and a rise time of the current of the laser drive LSI 5. It is desirable that the recording signal 100 be output from the delay circuit 26 earlier than the recording timing on the medium by a time including all of the delay due to the delay due to the semiconductor laser 4 and the delay until the mark is formed on the optical disk from the semiconductor laser 4. . In the present invention, the modulated data 117 is output earlier than the write timing on the medium by the delay time described above. These delay times include transmission line delays, gate delays, and the like, and are affected by LSI process variations and environmental conditions. It is desirable that a sufficient margin is included in the time for advancing the modulation data 117 including these variations. As a delay time switching range of the delay circuit 26, at least a range in which these variations can be corrected can be set by an instruction by the signal 27 from the system control unit 12. The circuit configuration of the delay circuit 26 may be a selector circuit that switches the outputs of a plurality of stages of delay circuits using passive elements or logic gates, or the outputs of the shift register according to instructions from the system control unit.

  As a configuration of the controller LSI 11, it is desirable to be able to deal with various peripheral circuits. Similarly to the description with respect to the recording signal 100, as the recording speed on the optical disc 1 increases, the gate delay, the transmission path delay, and the like become relatively large as the mark length / space length decreases. Therefore, it is necessary to improve the timing setting accuracy for the 116 sample pulse signals. In the present invention, the recording signal delay circuit 25 is provided inside the controller LSI, the operation delay time of the output buffer of the controller LSI 11 in the transmission path of the modulation signal 102, the delay time of the S / H signal generation circuit 21, and the reflected light sample pulse. 115 until the reflected light voltage 111 reaches the input terminal of the S / H circuit 18 from the sum of the transmission delay to the S / H circuit 18 input terminal and the timing of the recording position on the optical disk including the delay of the transmission path. More than the value obtained by subtracting the delay time, the modulation data 117 is output earlier. Similarly to the description of the path that passes through the recording signal 100, the transmission path delay and gate delay vary due to temperature / semiconductor process variations, and the sector counter 23 is affected by temperature variations in the reproduction system delay. The relative relationship with the medium varies. The modulation data 117 is output earlier than the maximum delay time including these variations. The delay time switching range of the delay circuit 25 can be set over an adjustment range in which these variations can be corrected, and the reflected light sample pulse can be set at a predetermined position of the corresponding mark. The circuit configuration of the delay circuit 25 may be a selector circuit that switches the outputs of a plurality of delay circuits using passive elements or logic gates, or the outputs of the shift register according to instructions from the system control unit.

  FIG. 11 shows an example of the delay circuits 25, 26, 204, and 205. The output of the serial delay element DEL is selected by a selector SEL comprising an AND gate AND and an OR gate OR. Selection control for the selector SEL is determined by the delay control data 27 loaded in the delay control register REG. In the delay control data 27, the bit corresponding to the position of the AND gate AND to be selected is set to “1”, and the other bits are set to “0”. The delay control data 27 is supplied from the system control unit 12. The delay control register REG may be disposed in the system control unit 12. Although only the configuration of the modulation signal 117 is shown in FIG. 11, the same configuration may be applied to the recording clock 118, the sample pulse 255, and the sample pulse 256.

  The recording signal 102 and the recording signal 100 shown in FIG. 1 can be converted into modulation data 117 which is a common signal. That is, in such a case, the delay time from the recording signal 100 to the recording timing on the optical disc 1, the delay from the recording signal 102 to the input terminal of the S / H circuit 18 or 19, and the mark / space on the optical disc 1 The modulation data 117 is output earlier than the difference between the S / H circuits 18 and 19 whichever is longer, the delay circuit 25 is provided in the AFELSI 10, and the delay circuit 26 is provided in the laser drive LSI 5. Correct it. However, when the delay circuits 25 and 26 are configured as shift registers, in general, the controller LSI 11 mainly integrates logic circuits higher than the AFE LSI 10 side, so it is desirable to provide the controller LSI 11 side. In addition, a timing adjustment function corresponding to the delay circuits 25 and 26 is provided on both the controller LSI 11 side, the AFE LSI 10 and the laser drive LSI 5, and coarse timing adjustment is performed on the controller LSI 11 side, and fine adjustment is performed on the AFE LSI 10 and the laser drive LSI 5. It may be performed on the side.

  When the delay circuits 25 and 26 are provided on the AFELSI 10 and the laser drive LSI 5 side, the modulation data 117 output from the modulation circuit 24 and the recording clock 118 synchronized therewith are shared by the controller LSI 11 to the AFELSI 10 and the laser drive. Although it is sent to the LSI 5, it is preferable to provide two systems as output terminals of the controller LSI 11 for each connection destination from the viewpoint of reduction of reflection and ease of termination.

  Further, when the 1T period is increased to about several ns, the timing setting of the reflected light sample pulse 113 and the emitted light sample pulse with respect to the reflected light voltage 111 and the emitted light voltage 112 is performed even if correction is performed by the delay circuits 25 and 26. Accuracy deteriorates. It is desirable to set the sample pulse in consideration of the accuracy reduction. For example, when sampling the mark timing, the sample pulse is set to be delayed from the leading edge by about 1T to 2T in addition to at least the stabilization time of the reflected light voltage 111 and the outgoing light voltage 112, and from the trailing edge by about 1T to 2T. It is desirable to reset at a fast timing.

  Further, although the example of FIG. 1 has been described by taking the case of recording with multi-pulses as an example, rectangular recording pulses or other shapes may be used. Further, when recording with multi-pulses as shown in FIG. 1, the reflected light voltage 111 and the emitted light voltage 112 rapidly change in a pulse shape within the same mark, so that the signal after applying a band-pass filter or a low-pass filter. However, it is necessary to set the delay time of the delay circuit 25 in consideration of the delay time of these filter circuits.

  As described above, in the present invention, the sample hold signal generation circuit 21 is provided in the AFELSI 10. Since the sample pulse signal is generated from the recording signal 102 inside the AFELSI 10, only the recording signal 102 and the recording clock 103 are required as signal input terminals from the controller LSI 11 for controlling the sample circuits 18 and 19 for the emitted light and the reflected light. Even if a differential small-amplitude differential interface such as LVDS (low voltage differential signaling) is used for these, four are sufficient. Further, by providing the S / H signal generation circuit 21 in the AFELSI 10, any number of sample pulse signals can be generated without being restricted by the number of terminals. On the other hand, if the sample hold signal generating means is not provided in an LSI including many analog circuits such as a laser drive LSI or AFELSI, but provided in a controller LSI in which logic circuits can be mounted in a highly integrated manner, for example, a 1T cycle is obtained. If it is about several ns, it becomes difficult to send a sample pulse of about 1T to 3T width from the controller LSI to the AFELSI by LVTTL (low voltage transistor-transistor logic). Then, a small-amplitude interface such as LVDS (low voltage differential signaling) is indispensable, and further, there is a need for differential transfer. Conventionally, there are many configurations and LSI products in which about 2 to several sample pulse signals are usually sent directly from the controller LSI to the AFELSI. As the recording speed increases in this way, a differential interface with a small amplitude of sample pulses If about 10 are required, not only will the number of LSI terminals constituting the system increase, but it will also cause substrate noise.

  Furthermore, if the recording speed of DVD-R, etc. will shift to 8 × or 16 × in the future, the current CLV (constant linear velocity) recording method will change to a recording method such as CAV (constant angular velocity) recording or partial CAV recording. It is thought that it will shift. In the CLV recording method currently used in optical disk recording devices such as DVD-R (digital video disk-recordable), the length of the recording mark unit on the disk is made constant regardless of the inner and outer circumferences, while the disk is rotated. By doing so, the time for the light spot to pass through the recording mark as a unit is also constant, and the mark formation condition by the transfer of heat generated by the semiconductor laser irradiation is kept constant. The length of a track for one rotation of the inner periphery of an optical disc such as a DVD-R is about half of the outer periphery. In the case of the CLV recording method, the rotation speed is fast on the inner periphery and is rotated slowly on the outer periphery. However, if the double speed is further improved by the CLV method, the speed is limited at the inner periphery where the rotation is fast due to the limitations of the rotation control system including the spindle motor and the disk. Although it may be possible to use an expensive motor or neglect compatibility, it is not realistic. As a speed improvement measure in such a case, a CAV recording method in which the disk is rotated at a constant angular velocity is used. In the CAV recording method, the inner and outer circumferences are rotated at the same angular velocity. Therefore, if the rotation speed of the innermost circumference of the CLV is the same as that of the CAV, the outer transfer rate is higher in the CAV recording method, so the average transfer rate is improved. To do. In recent years, it is also used in recording devices such as CD-R / CD-RW.

  When such a CAV recording method is used, the 1T period of the outer peripheral part is about half of the inner peripheral part, and the period of the recording clock also changes correspondingly. Therefore, the gate delay and the delay time of the transmission path are set to 1T period. The converted delay time is not constant on the inner and outer circumferences. When the delay circuit 25 and the delay circuit 26 are configured such that a plurality of shift registers and a plurality of outputs are input to the selector circuit and are selected by the control signal 27 of the output of the system control unit 12, one cycle of the recording clock. Alternatively, the time corresponding to 0.5 period using both forward and reverse phases is a timing adjustment unit. Even if the timing is corrected accurately using the delay circuits 25 and 26 on the inner circumference, the 1T period is about half on the outer circumference, and a fixed gate delay or transmission path delay time that is not correlated with the 1T period. Minutes appear large in terms of 1T period. In order to cope with this, the track on the disk is divided into a predetermined number of areas in the radial direction, the delay time information of the delay circuits 25 and 26 for each area is stored in the MEM 29, and from the MEM 29 according to the area. Corresponding delay time information may be read, and the delay times of the delay circuits 25 and 26 may be set based on the information. The MEM 29 is preferably a rewritable nonvolatile memory such as a flash memory.

<< Second Embodiment >>
Next, a second embodiment of the present invention will be described. First, an example of an optical disk suitable for the second embodiment will be described with reference to FIGS. FIG. 10 is a diagram viewed from a direction perpendicular to the recording surface of the optical disk. Grooves 501 and lands 502 are alternately arranged on a spiral as shown in FIG. FIG. 9 shows a cross-sectional view of the optical disk of FIG. 10. The light spot 106 is irradiated from the side shown in the figure, and the light spot 106 tracks the track of the groove 501 in accordance with the rotation of the disk. Land pre-pits 503 are arranged in the land portion 502, and ID information is recorded by a combination of the intervals of the land pre-pits 503. The specific pits in the land pre-pit 503 group and the 14T mark (or space) of the synchronization signal in the recording signal recorded in the groove 501 are recorded so as to be synchronized. There is no 14T mark (or space) other than the sync signal portion of the recording mark. Details of the mark / land prepit are described in the DVD-R / RW standard created by the DVD Forum, and the land prepit can be easily reproduced from a tracking error signal by a known push-pull method or the like. Further, the groove 501 and the land 502 may meander as shown in FIG. Such a meandering track is generally called WOBBLE, and a WOBBLE signal is reproduced from a tracking error signal by a push-pull method or the like and a PLL is applied to this signal, so that a clock synchronized with a position on the track can be easily obtained. Can be generated. 9 and 10 is an example suitable for the second embodiment shown in FIG. 4, but the first embodiment, another third embodiment to be described later, and the fourth embodiment. For these embodiments, the present embodiment can be used regardless of the presence or absence of the land pre-pit 503. However, when there is no land pre-pit, the ID information by the WOBBLE modulation method is used. It is desirable that changing ID information is recorded in advance. Note that a clock reproduced from the land pre-pit or WOBBLE is positioned as a medium timing.

  A second embodiment of the present invention is shown in FIG. Circuits other than the AFELSI 10a and the system control unit 12a in FIG. 4 are the same as those in FIG. 1, and the configuration in FIG. 4 is replaced with the AFELSI 10 and the system control unit 12 in FIG. That is, the reflected light voltage 111, the emitted light voltage 112, and the emitted light sample hold signal 114 in FIG. 4 are connected to the optical pickup 2 in FIG. 1, and the reproduction data 122, the reproduction data synchronization clock 123, the recording signal 102, and the recording clock 103 are It is connected to the controller LSI 11 of FIG. The binarization circuit 14, the PLL 15, the S / H circuit 18, the S / H circuit 19, the AD converter 20, and the S / H signal generation circuit 21 in FIG. 4 may be the same circuit as in FIG. The S / H signal generation circuit 21 in FIG. 4 may be the same as the S / H signal generation circuit 21 in FIG. 2, but in the configuration in FIG. 4, the pulse width measurement value 126 can be output to the 14T timing gate generation circuit 60. In FIG. 1, signals are connected from the system control unit 12 to the controller LSI 11 and the laser drive LSI 5, but these are not shown in FIG. 4, but may be connected from the system control unit 12a in the same manner.

  Hereinafter, the second embodiment of the present invention will be described in detail with reference to FIG. In the AFELSI 10a of FIG. 4, the binarization circuit 14, the PLL 15, the S / H circuit 18, the S / H circuit 19, the AD converter 20, and the S / H signal generation circuit 21 operate in the same manner as in FIG. Description is omitted. In FIG. 4, an LPP detection circuit 51 that newly detects a land pre-pit 503 (abbreviation: LPP) from a push-pull tracking error signal, a binarization circuit 55 that binarizes the reflected light voltage 111, and this output. A 14T detection circuit 56 that detects a pulse width of the mark and outputs a detection pulse when the pulse width is 13T or 14T or more, and a gate signal for the mark width measurement value 126 to 14T that is a count value of the mark pulse width from the recording signal 102 14T timing gate generation circuit 60 to be generated, AND gate 52 that takes AND of 14T detection timing gate 159 and LPP detection pulse 160, AND gate 53 that takes AND of 14T detection timing gate 159 and 14T detection signal, and AND gate 52 The counter starts at the output pulse timing of Constituted by the counter 54 to hold the count value at the pulse timing of the output of the over bets 53, the system control unit 12a for correcting the recording timing controller LSI11 with reference to the count value 164 of the counter 54. When applied to an optical disc in which ID information is recorded in land prepits as shown in FIG. 9, although not shown in FIG. 4, in addition to the binarization circuit 14 and the PLL 15, an LPP detection pulse 160 is sent to the controller LSI 11. An ID detection circuit that detects the ID from the LPP may be provided, and the timing of the sector counter 23 may be corrected at this detection timing.

  The operation timing of the configuration of FIG. 4 will be described with reference to FIG. Although not shown in FIG. 4, a case where, for example, the controller LSI 11 and the optical pickup 2 in FIG. 1 are connected as the peripheral circuit in FIG. 4 will be described. The sector counter 23 is a counter that operates in synchronization with the timing on the medium (optical disk) surface, and generates modulation data 117 in synchronization with the count value 121 of this counter. A 14T mark (or space) is output to the modulated data 117 in the vicinity of the LPP. The modulation data 117 is output as the recording signal 100 in the delay circuit 26 with a delay of Tw1, for example. The laser beam 106 is emitted with a delay of Tw 2 from the recording signal 100, and its intensity is indicated by the laser beam intensity 110. The 14T recording mark 505 is formed on the groove 501 with a delay of Tw3 from the laser beam (intensity) 110. The reflected light voltage 111 is further outputted with a delay of Tw4 and is binarized. When this pulse width is 13T or 14T or more, a 14T detection pulse 161 is outputted. On the other hand, a tracking error signal is generated from the reflected light voltage 111 by, for example, a push-pull method, and the LPP detection pulse 160 is obtained with a delay of Tlpp time from the medium timing by slicing this signal at a predetermined level. On the other hand, the same 14T mark is output to the recording signal 102 with a delay of Ts1 from the modulation data 117. As for the 14T mark length, the S / H signal generation circuit 21 detects the pulse width and outputs the value “14” to the pulse width measurement value 126. The pulse width measurement value 126 is output with a delay of Ts2 with respect to the recording signal 102, the pulse width measurement value 126 is decoded by “14” to generate a 14T timing pulse 167, and the 14T timing pulse 167 is delayed by T14t. A 14T timing gate 159 is generated. When the LPP detection pulse 160 is detected during the “H” period of the 14T timing gate 159, the counter 54 is cleared and started simultaneously. When the 14T detection pulse 161 is detected during the “H” period of the 14T timing gate 159, the counter is stopped. Let The count value 164 held at the timing of the 14T detection pulse 161 indicates the timing difference between the LPP detection pulse 160 and the 14T detection pulse 161. In the example of FIG. 5, the difference of 7T is measured.

  In FIG. 5, recording is performed on the disc so that the land pre-pits 503 correspond to the intermediate positions of the 14T recording marks 505. Tw4 and Tlpp are the delay times of the reflected light, and the delay time can be adjusted to some extent by matching the wiring length and circuit configuration. The LPP detection pulse 160 is centered in the 14T timing pulse 167 of the reflected light binary signal 166. The timing should come. In order to distinguish the 14T mark from other 3 to 11T marks, the amount of deviation from the LPP detection pulse 160 is measured using a 14T detection pulse 161 that outputs a pulse signal when the mark width is 13T or 14T or more. To detect the write position deviation. If the amount of deviation indicated by the count value 164 is greater than “7”, it indicates that the 14T detection pulse 161 is delayed, and the delay time of the delay circuit 26 may be adjusted to reduce Tw1 by the necessary time. Further, when the deviation amount indicated by the count value 164 is smaller than “7”, it indicates that the 14T detection pulse 161 is advanced, and the delay time of the delay circuit 26 may be adjusted to increase Tw1 by a necessary time.

  As described above, according to the second embodiment, it is possible to adjust the recording position in the optical disc provided with the LPP. Further, when dust adheres to the optical disk or there is a defect in the recording film, the LPP detection pulse 160 or the 14T detection pulse 161 may not be detected or may be detected at an incorrect position. For such a problem, the system control unit 12a may measure the count value 164 a plurality of times, check the validity of the value, or process the averaged value as an acquired value. It is also possible to provide a function for storing the AD conversion value in the storage means or an averaging circuit, which can be referred to from the system control unit 12a. Although the timing at which the system control unit 12a acquires the count value 164 is not shown in FIG. 4, for example, the 14T detection pulse 161 is input as an interrupt signal to the system control unit 12a and the count value 164 is referenced at this timing. You may make it do. Further, there is a case where the circuit delay fluctuates due to a temperature rise or the like in the middle of recording, and the delay time of the delay circuit 26 may be changed when the count value 164 is checked every predetermined time and the value changes. The land pre-pit has been described above as an example, but in the present embodiment, the reflected light during the formation of a specific recording mark during recording and the timing of the corresponding pre-pit are compared to detect the amount of writing position deviation and detect this. Any pre-pit shape or arrangement may be used. The example of FIG. 4 is an example in which the prepit corresponds to the center of the 14T recording mark, but the front-rear relationship between the prepit and the recording mark may be arbitrary. In other words, if the specifications are such that the pre-pits and the recording marks correspond to each other with a fixed time relationship, the relative time between the two may be measured and corrected if the time is different from the expected time. In the example of FIG. 4, the shift amount between the specific recording mark and the prepit timing is detected. However, there is a case where a track is meandered on a disk called WOBBLE. The ID is recorded by modulating the WOBBLE meandering period, frequency, phase, and the like. WOBBLE can be easily converted into an electrical signal in the same manner as a push-pull tracking error signal. This WOBBLE detection signal may be used instead of the pre-pit timing signal to detect the amount of deviation from the corresponding specific mark. For example, if there is a timing relationship between the edge of the WOBBLE and the specific mark, the amount of deviation between them may be measured. Further, when a predetermined modulation is applied to the WOBBLE, the amount of deviation between the detection timing of the specific pattern of the WOBBLE or the specific width and the timing of the specific mark may be measured.

  There is a disc provided with a test area in which user data is not recorded in a specific area on the disc, and is used for, for example, OPC. By recording in such an area and detecting the deviation amount of the writing position by the above-described method and correcting it, the deviation amount of the writing position at the start of recording can be suppressed to a small value. In addition, when the test area is used, the writing position deviation can be detected by detecting the deviation amount between the specific mark of the reflected light and the pre-pit during reproduction after recording in the test area. A method of correcting the positional deviation amount may be employed. In the example of FIG. 4, the 14T mark is detected from the recording signal 102 and the 14T timing gate 159 is generated. However, a function equivalent to this function may be provided on the controller LSI 11 side. Further, a 14T timing gate may be generated by decoding the sector counter 23. The 14T timing gate 159 in FIG. 4 is a signal for preventing erroneous detection, and it is only necessary to mask the timing at which the LPP detection pulse 160 and the 14T detection pulse 161 do not exist as accurately as possible. For the LPP detection pulse 160 and the 14T detection pulse 161, It may be provided individually or may be omitted if the system is low in noise.

  Further, although the reflected light voltage 111 is connected as an input signal of the binarization circuit 55, when the skew due to the optical path difference between the emitted light voltage 112 and the reflected light voltage 111 and the circuit variation is small, the reflected light voltage 111 is When connected to the binarization circuit 55, the counter 54 can obtain information similar to the write position deviation. When the S / N of the reflected light is poor, the emitted light voltage 111 can be used.

<< Third Embodiment >>
A third embodiment of the present invention will be described with reference to FIG. Circuits other than the AFELSI 10b and the system control unit 12b in FIG. 6 are the same as those in FIG. 1, and the configuration in FIG. 6 is replaced with the AFELSI 10 and the system control unit 12 in FIG. That is, the reflected light voltage 111, the emitted light voltage 112, and the emitted light sample hold signal 114 in FIG. 6 are connected to the optical pickup 2 in FIG. 1, and the reproduction data 122, the reproduction data synchronization clock 123, the recording signal 102, and the recording clock 103 are It is connected to the controller LSI 11 of FIG. Further, the binarization circuit 14, the PLL 15, the S / H circuit 18, the S / H circuit 19, and the AD converter 20 in FIG. 6 may be the same as those in FIG. The S / H signal generation circuit 203 in FIG. 6 is different from the S / H signal generation circuit 21 in FIG. 1 and will be described later with reference to FIG. 7, but can output a sample pulse group of 250a to 250g. Other than that, the configuration is almost the same as that of the S / H signal generation circuit 21. The sample pulses 250a to 250g are connected to the S / H circuits 200a to 200g, respectively, and sample and hold the reflected light voltage at respective timings 250a to 250g. The sample pulse 255 output from the S / H signal generation circuit 203 is the same signal output as the reflected light sample pulse 111 in FIG. 1, and the delay circuit 204 to which this is input is input from 0 to a predetermined time by the control signal 254 from the system control unit 12b. The delay time can be set at predetermined time intervals. When the delay time is set to 0 by the control signal 254, the output signal 251 of the delay circuit 204 is a pulse output with substantially the same timing as the reflected light sample pulse of FIG. Further, the sample pulse 256 output from the S / H signal generation circuit 203 is the same signal output as the output light sample pulse 112 in FIG. 1. In the delay circuit 205 to which the sample pulse 256 is input, the sample pulse 256 starts from 0 by the control signal 253 from the system control unit 12b. The delay time can be set at predetermined time intervals between the predetermined times. When the delay time is set to 0 by the control signal 253, the output light sample pulse 252 output from the delay circuit 205 is a pulse output having substantially the same timing as the output light sample pulse 116 of FIG. Selector circuits 201 and 202 for selecting the reflected light sample and hold signal 113 and the output signals of the sample and hold circuits 200a to 200g based on the control signals 259 and 260 of the output of the system control unit 12b, and AD for AD conversion of the outputs of the selector circuit 202 A converter 20 is provided. The AD conversion value 257 can be referred to by the system control unit 12b. Note that the delay circuits 204 and 205 have the significance of finely adjusting both delay times when the reflected light sample pulse and the emitted light sample pulse are generated from the common recording signal 102.

  The operation of the embodiment of FIG. 6 will be described using the time chart of FIG. A case where, for example, the controller LSI 11 and the optical pickup 2 in FIG. 1 are connected as peripheral circuits of the AFE LSI 10b and the system control unit 12b in FIG. 6 will be described. The sector counter 23 is a counter that operates in synchronization with the timing on the medium surface, and the modulation data 117 is generated in synchronization with the count value of this counter. The modulation data 117 is delayed by Tw1 by the delay circuit 26 shown in FIG. 1, and the recording signal 100 is output. Further, a recording mark 504 is formed on the disk with a delay by the delay time (Tw2 + Tw3) of the laser drive LSI 5 and the semiconductor laser 4. The reflected light voltage 111 is input to the AFELSI 10b with a delay of Tw4. In response to this, the delay circuit 25 delays the recording signal 102 by Ts1. As described in the first embodiment, the recording signal 102 is delayed by Ts2 by the pulse width detection function in the S / H signal generation circuit 203 or the like. The sample pulses 250a to 250g are generated as waveforms obtained by shifting the 1 CLK width pulse of the recording clock 103 by 1 CLK from the timing delayed from the recording signal 102 by Ts2. In the sample and hold circuits 200a to 200g, V1 to V7 of the reflected light voltage 111 corresponding to the timing of the sample pulse are held by the sample pulses 250a to 250g. V1 to V7 are switched using the selector circuits 201 and 202 in FIG. 6 and input to the AD converter 20, respectively. By switching the selector 201 and the selector 202, the system control unit 12b can acquire the AD conversion values 257 of V1 to V7, and can obtain an outline of the reflected light voltage 111, and obtain the timing of the reflected light voltage 111. Is possible. As a means for obtaining the timing of the reflected light voltage 111, for example, by utilizing the fact that the voltage value suddenly increases from V4 to V5, the rising of the reflected light voltage 111 is detected, and reflected at a predetermined delay from this rising timing. The optical sample pulse 251 may be delayed using the delay circuit 204. The recording signal 102 is delayed by an input buffer of the AFELSI 10b and a gate delay in the S / H signal generation circuit 203, and the reflected light voltage 111 is also delayed by the PD 109, the IV converter 8 and the like. In this embodiment, the reflected light sample hold pulse 251 is reflected by the reflected light voltage by measuring the skew of both input signals of the S / H circuit 18 by sample-holding using the S / H circuits 200a to 200g having the same configuration. 111 can be set with high accuracy.

  In the example of FIG. 6, a plurality of sample pulses 250a to 250g at a plurality of timings are used to sample and hold signals at a plurality of S / H circuits 200a to 200g at this timing. Only one / H circuit may be provided, and the pulse timing of this sample pulse may be slightly shifted every measurement time, and information on V1 to V7 in FIG. 7 may be acquired from the measurement results of each time.

<< Fourth Embodiment >>
FIG. 8 shows a fourth embodiment of the present invention. Circuit blocks having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The laser drive circuit 5a in FIG. 8 has the same function as the laser drive LSI 5 in FIG. 1, and the connections between corresponding circuit blocks including the laser drive circuit 5a are the same as those in FIG. The configuration of FIG. 8 differs from FIG. 1 in that at least a delay circuit 25, a delay circuit 26, an S / H signal generation circuit 21, an S / H circuit 18, an S / H circuit are provided in the laser drive LSI 5c disposed in the optical pickup 2c. The circuit 19, the AD converter 20, and the laser drive circuit 5a are provided, and the delay circuits 25 and 26 built in the controller LSI 11 in FIG. 1 are arranged on the laser drive LSI 5c side in FIG. As shown in FIG. 8, the IV converters 8 and 9 may be provided inside the laser drive LSI 5c. Further, the binarization circuit 14 and the PLL 15 may be a single LSI, or the binarization circuit 14 and the PLL 15 may be provided as an analog function inside the controller LSI.

  According to the fourth embodiment, the modulation data 117 and the recording clock 118 are sent from the controller LSI 11c to the laser drive LSI, the S / H signal generation circuit 21 and the S / H circuits 18 and 19 are provided inside the laser drive, and the recording speed is set. When the signal becomes high, only the recording data 118 synchronized with the modulation data 117 and the modulation data 117 is transferred from the controller LSI 11c to the laser drive LSI 5c. A high frequency signal such as the emitted light sample pulse 116 is generated inside the laser drive LSI 11c. As a result, the number of high-speed signal lines in the recording system can be limited to at most two, and noise can be reduced. Of course, the higher the read / write speed of the optical disc, the better is to use a small amplitude interface such as LVDS (low voltage differential signaling) for the modulation data 117 and the recording clock 118 synchronized with the modulation data 117, and send it further differentially. Further, in FIG. 1, a circuit path from the recording signal 102 to the reflected light sample pulse and the emitted light sample pulse is provided in the AFE LSI 10, and a circuit path from the recording signal 100 to the laser drive current 105 is provided in the laser drive LSI 5. It is difficult to adjust the delay and skew. In FIG. 8, there are a path from the recording data 117 to the reflected light sample pulse 115 and the emitted light sample pulse 116 via the recording signal 102, and a path from the recording data 117 to the laser drive current 105 via the recording signal 100. The same laser drive LSI 5c and the same semiconductor chip are provided to facilitate delay time and skew adjustment. In particular, in the present invention, among the two paths, the recording data 117 connected to the laser driver on the optical pickup 2c is transferred as a common signal from the controller LSI 11c on the circuit board 3c, which is difficult to adjust the skew. Originally, the reflected light sample pulse 115, the emitted light sample pulse 116, and the laser drive current 105 are generated inside the laser drive LSI 5c. The optical pickup 2c is movable so that the laser spot position on the disk can be moved. The optical pickup 2c is connected to the circuit board 3c by a cable, so that the transmission path becomes relatively long and the transmission delay becomes large. The reflected light sample pulse 115, the emitted light sample pulse 116, and the laser drive current 105 are generated by using the path between the circuit board 3c having a large delay time and the optical pickup 2c as a common path for the same recording data 117, thereby generating the reflected light. The setting accuracy of the optical sample pulse 115 and the outgoing light sample pulse 116 can be improved.

  According to each of the embodiments described above, the reflected light voltage 111 and the emitted light voltage 112 of the laser light modulated by the recording signal can be sampled and held with high precision at the timing of the recording mark or the space portion. The transfer rate can be increased.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  In the first, second, and fourth embodiments described above, the reflected light sample pulse 115 and the emitted light sample pulse 116 are generated in the S / H signal generation circuit 21, and in the third embodiment, the S / H signal generation circuit 203 is generated. The delay circuit 204 and the delay circuit 205 generate the reflected light sample pulse 251 and the emitted light sample pulse 252 to generate the sample hold signal used for OPC / ROPC and APC. However, the present invention is not limited to this. The reflected light voltage 111 is modulated by a recording signal during data recording, and the level fluctuates greatly. For example, a servo signal and a WOBBLE reproduction signal can be easily reproduced from a tracking error signal by, for example, a known push-pull method, but the reflected light is modulated and fluctuated during recording. In recent years, a method has been proposed in which during recording, a signal that becomes the basis of a servo signal or WOBBLE reproduction signal is sampled and held at the timing of a recording mark to reduce these fluctuations. Even in such a case, if the present invention is applied, the timing of sample and hold can be set with high accuracy. In the embodiment, an example is described in which sample-holding is performed at the timing of a recording mark during recording. However, sample-holding may be performed in a space portion during recording. For example, sample holding may be performed in the space portion of the emitted light voltage 112, and APC may be applied to the laser power in the space portion during recording. Alternatively, the reflected light voltage 111 may be sampled and held in a space portion, and a servo signal or a WOBBLE signal may be generated based on the sample and hold signal. In the reflected light voltage 111, the reflectivity decreases and the voltage level decreases in the recording mark formation process at the timing of the recording mark during recording, but this does not occur in the space portion. For example, if the recording signal 102 in FIG. 1 is inverted and input to the S / H signal generation circuit 21 as a sample-and-hold signal generating means in the space portion, a sample-and-hold signal in the space portion can be easily generated. The present invention can be applied to any case where the mark portion and the space portion being recorded are sample-held, and the use of the sample pulse is, for example, OPC / ROPC / APC / servo signal generation / WOBBLE signal generation. Can be used for other purposes.

  In the first to fourth embodiments, the operation at the time of data recording is mainly described. However, a data reproducing circuit may be provided together. Although not shown, in the present invention, when a reproducing circuit is provided, the recording signal and the recording clock may be stopped. For example, in the configuration of FIG. 1, a gate circuit that stops the recording signal 102, the recording clock 103, the recording signal 100, and the recording clock 101 according to an instruction from the system control unit 12 may be provided in the output stage of the controller LSI 11. If the signals 100 to 103 change at a high frequency during reproduction, noise may be generated in the reproduction signal, and the present invention may be provided with a function of stopping these signals. It is obvious that the recording signals 100 and 102 are stopped at the time of reproduction. However, in the example of FIG. 1, the S / H signal generation circuit 115 is provided in the AFELSI 10 and the recording clock synchronized with the recording signal is also transferred to the AFELSI 10. Since this can be stopped, noise during reproduction can be reduced. In particular, there are many cases in which an analog playback function is built in the AFELSI 10, and the noise reduction effect by stopping the clock is great. It is more preferable that the recording clock 101 transferred to the laser drive LSI 5 can be stopped. The gate circuit to be stopped is preferably provided at the output stage of the controller LSI, but it may be inside the AFELSI 10, inside the laser drive LSI 5, or some other place. In short, means for stopping the recording signal and the recording clock may be provided to reduce noise during reproduction. Also, a configuration has been proposed in which prepits called IDs and recording areas are alternately arranged on the same track as represented by the DVDRAM standard established by the DVD Forum. During prepit reproduction of the ID portion, the recording clock and recording data are stopped, and the recording clock and recording data can be output in the recording area. Also in the second to fourth embodiments, the present invention may be provided with a function of stopping the recording clock together with the recording signal during reproduction.

1 is a block diagram showing a configuration of an optical disc recording apparatus according to a first embodiment of the present invention. It is a block diagram showing an example of the S / H signal generation circuit of a 1st embodiment of the present invention. It is a timing diagram of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the analog front end LSI of the 2nd Embodiment of this invention. It is a timing diagram of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the analog front end LSI of the 3rd Embodiment of this invention. It is a timing diagram of the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the optical disk recording device of the 4th Embodiment of this invention. It is sectional drawing of the optical disk which can apply this invention. It is a figure of the optical disk which can apply this invention. It is explanatory drawing which illustrates the logic structure of the delay circuit which delays a memory signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Optical disk 2 Optical pick-up 3 Circuit board 4 Semiconductor laser 5 Laser drive LSI
6,7 Photo detector (abbreviation: PD)
8,9 IV converter 10 Analog front-end LSI (abbreviation: AFELSI)
10a Analog front-end LSI (abbreviation: AFELSI)
10b Analog front-end LSI (abbreviation: AFELSI)
11 Controller LSI
12 System Control Unit 12a System Control Unit 12b System Control Unit 13 Thread Motor 14 Binary Circuit 15 PLL
DESCRIPTION OF SYMBOLS 16 Data reproduction circuit 17 Interface circuit 18, 19 S / H circuit 20 AD converter 21 S / H signal generation circuit 22 ID reproduction circuit 23 Sector counter 24 Modulation circuit 25, 26 Delay circuit 27 Delay control data 40a-40o Shift register 41 Pulse generation circuit 42 Pulse width detection circuit 43, 44 Selector 51 LPP detection circuit 52, 53 AND gate 54 Counter 55 Binarization circuit 56 14T detection circuit 60 14T Timing gate generation circuit 100 Recording signal 101 Recording clock 102 Recording signal 103 Recording clock 104 Control signal 105 Laser drive current 106 Laser light 107 Emission light 108 Reflected light 109 Reflected light detection current 110 Emission light detection current 111 Reflected light voltage 112 Emission light voltage 113 Reflected light sample hold signal 14 Emission light sample hold signal 115 Reflected light sample pulse 116 Emission light sample pulse 117 Modulation data 118 Recording clock 120 Mark on track 121 Count value 122 Reproduction data 123 Reproduction clock 124 AD conversion value 125 Control signal 126 Pulse width measurement value 127 ID Detection timing signal 151 Control signal 159 14T timing gate 160 LPP detection pulse 161 14T detection pulse 164 Count value 165 Control signal 166 Reflected light binary signal 167 14T timing pulse 200a to 200g S / H circuit 201, 202 Selector circuit 203 S / H signal generation circuit 204, 205 delay circuit 250a-250g sample pulse 251 reflected light sample pulse 252 outgoing light sample pulse 253, 2 4 control signals 255, 256 sample pulse 257 AD conversion value 258 control signals 259 and 260 control signal 2c optical pickup 3c circuit board 5a laser drive circuit 5c laser drive LSI
11c Controller LSI
12c System control unit 13c Thread motor 501 Groove track 502 Land track 503 Land pre-pit 504 Recording mark 505 14T mark 506 Writing timing on the disk Tw1 to Tw5 delay time Ts1, Ts2 delay time Tsr, Tso delay time T14t delay time

Claims (14)

An optical information recording apparatus for recording information by irradiating a recording medium with a laser beam based on a recording signal,
A laser light source;
A drive circuit for the laser light source;
A first sample hold circuit that samples and holds an emitted light signal obtained by detecting laser light emitted from the laser light source, and a reflected light signal obtained by detecting reflected light of the laser light emitted to the recording medium At least one of the second sample and hold circuits that sample and hold
A sample hold timing generation circuit for determining a sample hold timing of the at least one sample hold circuit based on the recording signal;
A first delay circuit capable of programmably setting a delay of a recording signal supplied to the sample hold timing generation circuit,
An optical information recording apparatus, wherein the at least one sample hold circuit and the sample hold timing generation circuit are provided on one semiconductor chip. 2. The optical information recording apparatus according to claim 1, further comprising a second delay circuit capable of programmably setting a delay of a recording signal supplied to the laser light source driving circuit. 2. The optical information recording apparatus according to claim 1, further comprising a control register for designating a delay amount by the first delay circuit. 3. The optical information recording apparatus according to claim 2, further comprising a control register for designating a delay amount by the first delay circuit and a control register for designating a delay amount by the second delay circuit. A semiconductor circuit device used in an optical information recording apparatus for recording information by irradiating a recording medium with laser light based on a recording signal,
A first sample-and-hold circuit that samples and holds an emitted light signal obtained by detecting laser light emitted from a laser light source, and a reflected light signal obtained by detecting reflected light of the laser light emitted to the recording medium At least one of the second sample and hold circuits that sample and hold
A sample hold timing generation circuit for determining a sample hold timing of the at least one sample hold circuit based on the recording signal;
A semiconductor circuit device comprising: a first delay circuit capable of programmably setting a delay of a recording signal to be supplied to the sample hold timing generation circuit. 6. The semiconductor circuit device according to claim 5, further comprising a second delay circuit capable of programmably setting a delay of the recording signal supplied to the driving circuit of the laser light source. 6. The semiconductor circuit device according to claim 5, further comprising a drive circuit for the laser light source. 6. The semiconductor circuit device according to claim 5, which is mounted on an optical pickup provided with a laser light source. 6. The semiconductor circuit device according to claim 5, further comprising a small amplitude interface for receiving the recording signal differentially. A semiconductor circuit device used in an optical information recording apparatus for recording information by irradiating a recording medium with laser light based on a recording signal,
An interface circuit for transferring data read from the recording medium to the outside; a modulation circuit for modulating a recording signal to be recorded on the optical disc;
One first delay circuit capable of programmably setting a delay with respect to the recording signal modulated by the modulation circuit supplied to the sample hold timing generation circuit for determining the sample hold timing of the sample hold circuit A semiconductor circuit device comprising: 2. A second delay circuit capable of programmably setting a delay with respect to a recording signal modulated by the modulation circuit supplied to a driving circuit of a laser light source for emitting the laser light. Item 11. The semiconductor circuit device according to Item 10. 11. The semiconductor circuit device according to claim 10, further comprising a control register for designating a delay amount by the first delay circuit. 11. The semiconductor circuit device according to claim 10, further comprising a small-amplitude interface for sending the modulated recording signal to the modulation circuit in a differential manner. An optical information recording apparatus for recording information by irradiating a recording medium with a laser beam based on a recording signal,
A laser light source;
A drive circuit for the laser light source;
A first sample hold circuit that samples and holds an emitted light signal obtained by detecting laser light emitted from the laser light source, and a reflected light signal obtained by detecting reflected light of the laser light emitted to the recording medium At least one of the second sample and hold circuits that sample and hold
A sample hold timing generation circuit for determining a sample hold timing of the at least one sample hold circuit based on the recording signal;
A first delay circuit capable of programmably setting a delay of a recording signal supplied to the sample hold timing generation circuit, and a second delay circuit capable of programmably setting a delay of a recording signal supplied to the driving circuit of the laser light source, An optical information recording apparatus comprising:

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