JP2007087543A - Optical disk drive and its writing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of generating the optimum write start timing in an optical disk drive which detects a synchronizing signal from a wobble signal to record it on DVD+R/RW, etc. <P>SOLUTION: The wobble signal read out from a recording medium is reproduced, and wobble data, channel clock and wobble clock are demodulated from this wobble signal to generate the synchronizing signal from the demodulated wobble clock and wobble signal, and a delay synchronizing signal is generated, which is obtained by delaying the synchronizing signal for the defined delay period from a starting edge of the demodulated wobble clock, then such optical disk drive is obtained that the data is written to the recording medium earlier by at least the defined delay period than the write start timing decided by the delay synchronizing signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an optical disc apparatus for writing on a writable recording medium such as DVD + R / RW and a writing method thereof.

  A meandering groove called wobble is formed on a DVD + R / RW recording medium. In this wobble, a physical address on the disc multiplexed with predetermined modulation and information on the disc are recorded. These pieces of information are extracted as a wobble detection signal by rotating the disk with a spindle motor, irradiating a laser beam, detecting the reflected light with a pickup (see Patent Document 1). The wobble detection signal is demodulated to demodulate the wobble clock, channel clock, and address information.

  FIG. 6 shows a wobble detection signal detected from the wobble recorded on the disc and wobble data obtained by demodulating the wobble detection signal. The wobble detection signal is composed of two types of sine waves whose phases are inverted by 180 ° with the wobble clock as a unit. Data “1” and data “0” are assigned to these two types of different sine waves, and wobble data is configured with 8 data as unit information. FIG. 6A shows a synchronization signal composed of a pattern with wobble data “11110000”. FIG. 4B shows the data “1” with the wobble data pattern “10001100”, and FIG. 4C shows the data “0100” with the wobble data “10000011”. Yes.

  The frequency of the wobble clock is 817.5 KHz, and its period is 1223.2 nsec. One cycle of the wobble clock corresponds to the data length of one wobble data. Therefore, a wobble signal can be extracted or a physical address can be extracted by a detection circuit using a wobble clock. The channel clock is obtained by multiplying the wobble clock by 32. For example, when writing on a DVD + R / RW recording medium at 1 × speed, the frequency of the channel clock is 26.16 MHz, and one period (1T) is 38.23 nsec.

  On the other hand, the writing position to be written on the recording medium is determined in units of 1T of the channel clock with reference to the wobble synchronization signal, and the allowable accuracy of the writing start position is defined as ± 5T of the channel clock. As described above, the period of the wobble synchronization signal is extremely long compared to the channel clock. Therefore, if the wobble clock is applied as it is to the timing of the write start position, it may be difficult to manage the timing of the write start position.

  In particular, when a synchronization signal is detected using a wobble clock, an indefinite delay amount due to the clock tree is included in the wobble clock inside the LSI. For this reason, the detected synchronization signal also includes an uncertain delay amount, which deteriorates the write start position accuracy.

FIG. 7 is a conceptual diagram showing a clock tree inside an LSI that performs data processing. The clock tree is a tree configured to adjust the delay time from the start point of the clock to the clock terminal of each sequential element so that a plurality of sequential elements connected to a certain clock can perform synchronous communication. FIG. 7 shows a case where the wobble data 101 is processed in synchronization with the wobble clock 100 by the combinational circuit 106 or the combinational circuit 108. When the wobble data 101 is processed by each combinational circuit 106 or 108 via the flip-flops 105, 107, and 109, a delay time occurs until the wobble clock 100 reaches the flip-flops 105, 107, and 109. Since this delay time is affected by the layout and wiring of LSI elements, the delay time is not constant among the elements. In order to avoid this problem, the delay time due to the layout and wiring of the LSI is predicted in advance, and a buffer 102 as a delay circuit is inserted between the clock terminal and the wobble clock generation circuit to obtain the required number of stages. A countermeasure is adopted in which the variation due to the delay of 100 is corrected, and the flip-flops 105, 107 and 109 are driven in synchronization with the wobble clock 100.
JP 2005-38559 A

  The delay of the wobble clock actually depends on variations in the LSI manufacturing process. Therefore, there is a problem that the clock delay amount cannot be determined unless the LSI element is actually created. This variation in delay becomes a problem particularly when writing at high speed. For example, assume that the amount of delay due to the clock tree is 6 nsec. When writing at a quadruple speed of DVD + R / RW, the cycle of the channel clock is 9.6 nsec, so it is within 1T. However, at 16 × speed, the channel clock period is 2.4 nsec, and the variation due to the delay amount is 2T or more. This imposes great restrictions on the factors that cause other variations.

  In order to avoid an indefinite delay due to the circuit arrangement and wiring as described above, it is conceivable to use a channel clock having a short cycle as an operation clock for performing signal processing. However, in this case, all the sequential elements must be enabled sequential elements having a period 32T as an enable signal, which increases the circuit scale and increases the current consumption. .

  In order to solve the above problems, the present invention has taken the following measures.

  A wobble signal reproduction amplification circuit that reproduces and amplifies a wobble signal read from a writable recording medium, and a period obtained by demodulating the wobble clock and wobble data from the amplified wobble signal and multiplying the wobble clock A wobble signal demodulating circuit for generating a channel clock having a period of T, a synchronizing signal detecting circuit for detecting a synchronizing signal from the demodulated wobble data and the wobble clock, the synchronizing signal delayed for a predetermined period, and the generated A synchronization signal delay circuit for generating a delay synchronization signal synchronized with the channel clock, and a write start timing to the recording medium for a period nT (n is an integer value of 0 or more) than a write start timing determined by the delay synchronization signal ) Decided to start early in the fixed delay period A write start position determining circuit that was an optical disc apparatus equipped with.

  In the present invention according to claim 2, the optical disc apparatus according to claim 1, wherein the fixed delay period is longer than the predetermined period.

  In the present invention according to claim 3, the synchronization signal detected based on the wobble clock is delayed for an indefinite period from a start edge of the wobble clock, and the fixed delay period is at least the indefinite period and the predetermined period. The optical disk apparatus according to claim 1 or 2, wherein the optical disk apparatus is longer than a period including the period.

  In the present invention according to claim 4, the synchronization signal delay circuit receives the demodulated wobble clock, and the delay synchronization signal uses the synchronization signal input from the synchronization signal detection circuit as the detection of the synchronization signal. 4. The optical disc apparatus according to claim 1, wherein the optical disk apparatus is a delayed synchronization signal that is delayed at least by the definite delay period from a start edge of a wobble clock used in the above.

  In this invention which concerns on Claim 5, the said synchronizing signal delay circuit has a delay amount selection circuit which can set arbitrarily the integer value n of the period nT which is the said fixed delay period. The optical disk device described in the item is used.

  In the present invention according to claim 6, the wobble data and the wobble clock are demodulated from the wobble signal read from the writable recording medium, and the wobble clock and the wobble data are generated by multiplying the wobble clock. A synchronization signal is generated, a delay synchronization signal synchronized with the channel clock is generated by delaying the synchronization signal for a predetermined period, and a write start timing to be written to the recording medium is determined by the write start timing determined by the delay synchronization signal The optical disk writing method for writing to the recording medium is started earlier by a period of nT (n is an integer value of 0 or more) having at least a period T which is the period of the channel clock.

  In the present invention according to claim 7, the optical disk writing method according to claim 6, wherein an integer value n of the period nT can be set.

  According to the present invention, a wobble clock can be used without using a channel clock as a synchronization signal. Therefore, a channel clock having a high frequency is input to each circuit element and an enable signal is detected from the channel clock. There is no need to use an element, the circuit area does not increase, and an increase in current consumption can be prevented.

  Furthermore, even if an indefinite delay occurs in the synchronization signal detected from the wobble clock after the clock tree, the maximum value of the indefinite delay time is predicted in advance, and the start timing is set to be larger than this maximum value delay period. A fixed delay period synchronized with the clock is set to delay the synchronization signal, and the write start timing for writing to the recording medium is determined in consideration of the fixed delay period. Therefore, it is possible to determine the write start timing to write on the recording medium without using an uncertain delay time without using a high-frequency channel clock for all the sequential elements, and to improve the accuracy of the writing position on the recording medium. Can be improved.

  Embodiments of the present invention will be described below.

  A guide groove is provided on a writable recording medium made of the optical disc 1, and a wobble that slightly snakes is formed in the guide groove. In this wobble, multiplexed information is recorded. The wobble on the recording medium is irradiated with laser light, the reflected light is converted into an electric signal, and the wobble signal reproduction amplification circuit 5 reproduces it as a wobble signal. A wobble clock and a channel clock obtained by multiplying the wobble clock from the reproduced wobble signal and wobble data are demodulated by the wobble signal demodulation circuit 6. The demodulated wobble clock is a clock before the clock tree, and can correspond to a physical position on the recording medium and data recorded at the position. Accordingly, wobble data can be processed in units of wobble clocks.

  The synchronization signal detection circuit 7 detects a synchronization signal from the wobble data and the demodulated wobble clock. The detected synchronization signal includes an indefinite indefinite time based on the clock tree. Therefore, if it is attempted to determine the write start timing for the recording medium based on this synchronization signal, the position of the data to be written on the recording medium becomes uncertain and the position cannot be determined.

  The synchronization signal delay circuit 8 receives the synchronization signal including the indefinite delay, and generates a delayed synchronization signal obtained by delaying the input synchronization signal for a predetermined period. In this case, the period nT (n is an integer value greater than 0) elapses with reference to the start edge of the wobble clock before the clock tree used to detect the synchronization signal. Synchronize with the channel clock after. In this way, the delay synchronization signal having the start edge is generated after the fixed delay period of the period nT from the start edge of the wobble clock before the clock tree. As a result, even if an indefinite delay has occurred in the synchronization signal, a delayed synchronization signal is generated with a fixed delay period for canceling the uncertain indefinite period.

  The write start position determining circuit 9 receives this delay synchronization signal, and starts writing so that the write start position to the recording medium determined based on the delay synchronization signal, that is, the write start timing, starts at least earlier than the above-described definite delay time. Determine timing. As a result, even if the synchronization signal includes an indefinite delay due to the clock tree, the timing for starting writing to the recording medium can be determined with high accuracy without being affected by the indefinite delay. .

  The fixed delay period nT is set at least longer than a predetermined period in which the synchronization signal is intentionally delayed. Further, in order to increase the accuracy of the write start position, it is set to be equal to or longer than the period obtained by adding the maximum value extension period by the preset clock tree and the predetermined period delayed intentionally. In this setting, the positional relationship from the wobble signal demodulation circuit 6 to the synchronization signal detection circuit 7, the wiring to be routed, the circuit configuration of the synchronization signal detection circuit, and the like are taken into consideration. Further, it is possible to configure the delay amount selection circuit 14 capable of arbitrarily setting the integer value n so that the integer value n can be arbitrarily selected from the outside.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a functional block diagram showing the optical disc apparatus of the present embodiment.

  An optical disk 1 that is a writable recording medium is rotated by a spindle motor 2. Reflected light including information multiplexed in the wobble recorded by irradiating the optical disk 1 with laser light is detected by the pickup 3. The detected signal is reproduced and amplified by the wobble signal reproduction amplifier circuit 5 to generate a wobble signal. A rotation control signal is detected from the generated wobble signal and applied to the servo 4 to control the rotation of the spindle motor 2. The regenerated and amplified wobble signal is demodulated by the wobble signal demodulation circuit 6 to generate a wobble clock, a channel clock, and wobble data.

  The synchronization signal detection circuit 7 receives wobble data and a wobble clock, and detects address information, a synchronization signal periodically included in the wobble signal, and the like. As already described, the detected synchronization signal includes an indefinite indefinite period. Therefore, the synchronization signal delay circuit 8 generates a delay synchronization signal obtained by adding a predetermined delay time to the synchronization signal from the synchronization signal detection circuit 7. The delay synchronization signal is generated in synchronization with the channel clock. This is because the accuracy of the write start timing to the recording medium is defined in units of 1T which is one cycle of the channel clock.

    The write start position determination circuit 9 receives the delay synchronization signal generated by the synchronization signal delay circuit 8, and determines the write start timing for the optical disc 1 as a recording medium based on the delay synchronization signal. When determining the write start timing, the write start timing is generated at least earlier than the predetermined fixed delay period as the write start timing determined by the delay synchronization signal. By making the writing start timing earlier in such a period, the indefinite indefinite period is removed and recording is performed with minimal variation in the synchronization signal or address physically recorded on the optical disc 1. Is possible.

  The fixed delay period is set to be larger than these maximum values in consideration of the maximum delay period of the synchronization signal predicted from the clock tree and the variation of the delay period included therein. In addition, the delay synchronization signal is synchronized with the channel clock in order to determine the reference time of the fixed delay period. For example, the delay synchronization signal is raised in synchronization with the rising edge of the channel clock. In this way, the write start timing can be determined with an accuracy within 1T. The wobble clock before the clock tree demodulated by the wobble signal demodulating circuit 6 has a time deviation from the position of the synchronization signal recorded on the optical disc 1 which is a recording medium. However, this temporal deviation is a time difference that can be determined in advance. Therefore, it is necessary to determine the write start timing in consideration of this time difference.

  The write start position determination circuit 9 outputs a write start timing signal that starts writing at least earlier in the fixed delay period to the write strategy generation circuit 10 in accordance with a control signal input from the system controller 20, and the write strategy generation circuit 10 Write data is output to the laser driver 11 and writing to the optical disc 1 as a recording medium is started.

  FIG. 2 is a timing chart for explaining an indefinite delay period and a definite delay period by the clock tree.

  The uppermost stage represents a channel clock having a cycle of 1T, and is a short cycle clock obtained by multiplying the wobble signal demodulation circuit 6 by the wobble clock.

  The next stage represents the wobble clock generated by the wobble signal demodulation circuit 6 before the clock tree. The wobble clock starts at time To, and the start edge is synchronized with the rising edge of the channel clock. The period of the wobble clock is 32T, and the synchronization signal and address information are read in units of 8 periods of the wobble clock, that is, 256T. The time To can be made to correspond to the position of the synchronization signal recorded on the optical disc 1 which is a recording medium.

  The next stage represents the wobble clock signal after the clock tree. After the clock tree, it is affected by circuit layout, wiring, etc., so it contains an indefinite delay time. This indefinite delay is represented by an indefinite period δT.

  The next stage represents the synchronization signal detected by the synchronization signal detection circuit 7. This synchronization signal is detected by a wobble clock including an indeterminate indefinite period δT, and is therefore delayed by a period of To to δT.

  The lowermost stage represents a delayed synchronization signal obtained by delaying the detected synchronization signal by a synchronization signal delay circuit 8 for a predetermined period. This delay synchronization signal starts in synchronization with the rising edge of the channel clock 6T after the start edge of the wobble clock before the clock tree. Therefore, in the present embodiment, n = 6 and 6T is set as the fixed delay period. This fixed delay period of the delay synchronization signal is a delay period set in advance with reference to the wobble clock before the clock tree. Therefore, even if the indefinite period δT due to the clock tree cannot be determined unless the LSI is actually manufactured due to variations in the LSI manufacturing process, the maximum period of δT is predicted in advance, and By delaying the synchronization signal for a slightly longer period, it is possible to generate a delay synchronization signal that is not affected by indefinite irregular intervals. Further, as will be described later, this fixed delay period can be arbitrarily set in the synchronization signal delay circuit 8.

  In the above-described embodiment, the delay synchronization signal is synchronized with the rising edge of the channel clock. However, it is of course possible to synchronize with the falling edge of the channel clock by shifting the phase by 180 °. As a result, the delay synchronization signal can be determined with an accuracy within 1T which is at least the cycle of the channel clock.

  FIG. 3 is a block diagram of the synchronization signal delay circuit 8 that generates the delay synchronization signal described in FIG. The synchronization signal detection circuit 7 inputs the wobble data demodulated by the wobble signal demodulation circuit 6 and the wobble clock after the clock tree, and outputs a synchronization signal. For this reason, this synchronization signal includes an indefinite period δT.

  A flip-flop (hereinafter referred to as FF) 12-1 inputs the wobble clock demodulated by the wobble signal demodulation circuit 6 to the data terminal D, inputs the channel clock to the clock terminal CL, and starts wobble clock. The rising edge is delayed from the terminal Q by about 1T, which is the period of the channel clock. The FF 12-2, FF 12-3, FF 12-4, and FF 12-5 repeat the operation of sequentially delaying 1T. Therefore, a wobble clock delayed by 5T is output from the terminal Q of the FF 12-5. The AND circuit 13 inputs an output from the terminal Q of the fifth-stage FF 12-5 and an output obtained by inverting the output from the terminal Q of the sixth-stage FF 12-6, and generates an enable signal for the FF 12-7. . This enable signal consists of a pulse having a period of 1T synchronized with the rising edge of the wobble clock delayed by 5T appearing at the terminal Q of the fifth stage FF12-5.

  The FF 12-7 receives the synchronization signal at the data terminal D, the channel clock at the clock terminal, and the enable signal from the AND circuit at the enable terminal, and generates a delayed synchronization signal. The FF 12-7 starts the FF operation in synchronization with the enable signal, and delays the channel clock by 1T. Therefore, the synchronization signal detected by the synchronization signal detection circuit 7 is output from the terminal Q of the FF 12-7 as a delayed synchronization signal delayed for a total period of 6T delayed by 1T from the rising edge of the enable signal.

  In the above embodiment, the delay is performed in six stages (period 6T). However, indefinite indefinite period δT due to the clock tree is considered, and an arbitrary definite delay period that can sufficiently cancel this can be determined. .

  FIG. 4 is a timing chart showing the write start timing in the write start position determination circuit 9. For ease of understanding, in this timing chart, there is a time shift between the position of the synchronization signal recorded on the recording medium and the corresponding wobble clock demodulated by the wobble signal demodulation circuit. Appears as not.

  From the top of the figure, the synchronization signal recorded on the optical disc 1 as a recording medium, the synchronization signal including the indefinite indefinite period δT detected by the synchronization signal detection circuit 7, and the delay synchronization output from the synchronization signal delay circuit 8 The signal and the write start timing output from the write start position determining circuit 9 are shown.

  With respect to the synchronization signal recorded on the optical disc 1 which is a recording medium, the synchronization signal output from the synchronization signal detection circuit 7 includes an indefinite delay of the indefinite period δT. The start timing of the synchronization signal recorded on the optical disc 1 corresponds to the rising edge of the wobble clock generated in the wobble signal demodulation 6. The synchronization signal delay circuit 8 generates a delay synchronization signal delayed from the rising edge of the wobble clock by a fixed delay period of the period nT. The write start position determination circuit 9 supplies the write strategy generation circuit 10 with the write start timing earlier than the write start timing determined by the delay synchronization signal by a fixed delay period. As a result, data can be written to the optical disc 1 without being affected by the delay of the indefinite period δT.

  Note that the write start timing can be set to a period longer than the fixed delay period in units of the period T. In practice, there is a time difference between the synchronization signal recorded on the optical disc and the corresponding wobble clock demodulated by the wobble signal demodulation circuit 6. Therefore, the definite delay period is set in consideration of this time difference.

  FIG. 5 shows a circuit block diagram of the synchronization signal delay circuit 8 capable of arbitrarily setting the fixed delay period. The difference from the synchronization signal delay circuit 8 shown in FIG. 3 is that a delay period is selectively set between the FF 12-1 to FF 12-6 for delaying the wobble clock and the final stage FF 12-7 for delaying the synchronization signal. This is because a delay amount selection circuit 14 is provided.

  The FF 12-1 inputs a wobble clock to the data terminal D and a channel clock to the clock terminal CL, and outputs the wobble clock from the terminal Q with a delay of about 1T. In each stage from FF12-2 to FF12-6, a wobble clock delayed by 1T is output from the terminal Q. The output from each terminal Q of FF12-2 to FF12-5 is input to the switching circuit 15-1. The output from each terminal Q of FF12-3 to FF12-6 is input to the switching circuit 15-2. Each of the switching circuits 15-1 and 15-2 receives a delay amount selection signal, outputs FF12-2 and FF12-3, outputs FF12-3 and FF12-4, outputs FF12-4 and FF12-5, and FF12. One of the outputs of −5 and FF12-6 is selected as a pair and output to the AND circuit 13. The AND circuit 13 inputs an inversion of the input signal and the output signal of the FF, and outputs an enable signal to the enable terminal of the FF 12-7.

  The FF 12-7 receives the synchronization signal at the data terminal D, the channel clock at the clock terminal, and the enable signal from the AND circuit at the enable terminal, and generates a delayed synchronization signal. The FF 12-7 starts the FF operation in synchronization with the enable signal and delays the channel clock by 1T. Therefore, the synchronization signal detected by the synchronization signal detection circuit 7 is output from the terminal Q as a delayed synchronization signal delayed by 1T from the rising edge of the enable signal. As a result, when the output of the n-th FF is selected by the delay amount selection signal, a fixed delay period of period nT can be given to the delay synchronization signal.

  Although the above example shows the case where each output of the 6-stage FF is selected, the number of stages can be set according to the maximum delay time after the clock tree.

It is a functional block diagram which shows the structure of the optical disk apparatus in this Embodiment. It is a timing chart for demonstrating the delay period in this Embodiment. It is a functional block diagram which shows the structure of the synchronizing signal delay circuit in this Embodiment. It is a timing chart for demonstrating the start timing in this Embodiment. It is a functional block diagram which shows the structure of the synchronizing signal delay circuit in this Embodiment. It is a timing chart figure which shows the data contained in the conventionally well-known wobble detection signal this. It is a conceptual diagram which shows the delay by a clock tree.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Optical disk 2 Spindle motor 3 Pickup 4 Servo 5 Wobble signal reproduction amplification circuit 6 Wobble signal demodulation circuit 7 Synchronization signal detection circuit 8 Synchronization signal delay circuit 9 Write start position determination circuit 10 Write strategy generation circuit 11 Laser drivers 12-1 and 12- 2, 12-3, 12-4, 12-5, 12-6, 12-7 Flip-flop 13 AND circuit 14 Delay amount selection circuit 15-1, 15-2 switching circuit 20 System controller

Claims (7)

A wobble signal reproduction amplification circuit for reproducing and amplifying a wobble signal read from a writable recording medium;
A wobble signal demodulation circuit that demodulates a wobble clock and wobble data from the amplified wobble signal and generates a channel clock having a period of a period T obtained by multiplying the wobble clock;
A synchronization signal detection circuit for detecting a synchronization signal from the demodulated wobble data and wobble clock;
A synchronization signal delay circuit for delaying the synchronization signal for a predetermined period and generating a delay synchronization signal synchronized with the generated channel clock;
Write start position determination circuit for determining that the write start timing to the recording medium is started earlier than the write start timing determined by the delay synchronization signal for a fixed delay period of period nT (n is an integer value of 0 or more). And an optical disc device.   The optical disc apparatus according to claim 1, wherein the fixed delay period is longer than the predetermined period.   The synchronization signal detected based on the wobble clock is delayed for an indefinite period from a start edge of the wobble clock, and the fixed delay period is longer than at least a period obtained by adding the indefinite period and the predetermined period. The optical disc device according to claim 1 or 2.   The synchronization signal delay circuit inputs the demodulated wobble clock, and the delay synchronization signal is obtained by inputting the synchronization signal input from the synchronization signal detection circuit from the start edge of the wobble clock used for detection of the synchronization signal. 4. The optical disk apparatus according to claim 1, wherein the optical disk apparatus is a delay synchronization signal delayed at least by the fixed delay period.   5. The optical disc apparatus according to claim 1, wherein the synchronization signal delay circuit includes a delay amount selection circuit capable of arbitrarily setting an integer value n of a period nT that is the fixed delay period.   Demodulate wobble data and wobble clock from a wobble signal read from a writable recording medium, multiply the wobble clock to generate a channel clock, generate a synchronization signal from the wobble clock and the wobble data, and generate the synchronization signal. Is delayed for a predetermined period to generate a delay synchronization signal synchronized with the channel clock, and the write start timing to be written to the recording medium is at least a period of the channel clock from the write start timing determined by the delay synchronization signal An optical disk writing method in which writing is started on the recording medium, starting early in a period of nT (n is an integer value of 0 or more) with T as a unit. The optical disc writing method according to claim 6, wherein an integer value n of the period nT can be set.

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