JP2008310893A - Laser driver circuit and optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the influence of noises on an analog control signal by suppressing an increase in the number of wiring lines on a flexible board. <P>SOLUTION: The laser driver circuit is provided with a write strategy circuit 603 for receiving a clock and recorded data to output a switching control signal 623, drivers 616 to 619 having driving current values independently set, for receiving the switching control signal to output a recording current waveform or a reproducing current waveform, registers 605 to 608 for receiving a power set value of a laser diode 624 to store it, DACs 609 to 611 for converting the power set value into an analog power set value signal to output it, a sample holding circuit for receiving a power monitor signal to output the monitor signal in association with recorded data, and power control circuits 613 to 615 for deciding a driving current value based on the monitor signal and the analog power set value signal to output it to a current driver. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a laser driver circuit and an optical disc apparatus.

  In a CD-R / RW or recordable DVD device, information recording on an optical disk medium is realized by intensity-modulating laser light focused on a recording layer of the optical disk by an objective lens.

  In general, a region irradiated with high-intensity laser light is a region called a mark, and a region irradiated with low-intensity laser light is a region called a space. The optical characteristics of these two regions It is recorded as binary information by the difference.

  The intensity-modulated light emission waveform has a waveform called a multi-pulse composed of a plurality of pulses deviated from the recording clock by a certain time. This waveform is not the input data pattern itself consisting of “0” and “1”, but a waveform that has been subjected to complicated waveform generation processing, and is called a strategy waveform.

  In addition, when performing processing called pattern-corresponding recording compensation in the strategy processing, the input data pattern, that is, the length of the mark to be recorded and the length of the space before and after it are recorded in order to improve the recording mark accuracy Depending on the combination, the edge positions of the leading and trailing pulses constituting the multi-pulse are shifted in minute time in real time.

  Here, in many recordable optical disc apparatuses, a circuit having a recording waveform generation processing function, that is, a strategy function is arranged on the main substrate side, and the drive waveform after the waveform generation processing is transferred from the main substrate through the flexible substrate. Recording was performed by transmitting to a laser driver circuit provided in a pickup head (hereinafter referred to as PUH).

  However, as the recording speed increases, signal degradation may occur when the write strategy waveform is transmitted from the main board through the flexible board, and unnecessary radiation of high-frequency components may be received from the flexible board. In order to avoid such a phenomenon, for example, as described in Patent Document 1 described later, the recording data before the recording waveform generation processing is transmitted to the PUH side, and the recording waveform is transmitted to the laser driver circuit provided on the PUH side. It is shifting to a configuration in which a circuit having a generation function is mounted.

  In recording waveform processing, generally, recording data in NRZI format (signals “1” and “0” corresponding to the recording mark length and space length appear alternately) are serially transferred in synchronization with the recording clock, The input data pattern of the recording data is detected. Then, according to the detected pattern, the edge shift position from the reference clock stored in advance in the memory is called, and the pulse edge position of the multi-pulse is changed in real time.

  Along with the built-in strategy function in the laser driver circuit, the laser signal is multiplied in the laser driver circuit by multiplying the clock input from the outside, and the clock signal is multiplied in the circuit. The frequency of the input clock signal can be lowered.

  By the way, in order to record and reproduce data stably, it is necessary to always obtain a constant laser power. However, the current-output power characteristic (hereinafter referred to as the IL characteristic) of the laser has temperature dependency, and the ambient temperature condition, the heat generation of the laser itself during recording, and the heat generation of ICs around the PUH are increased. As a result, a phenomenon called so-called IL shift occurs in which the output power decreases due to temperature rise even with the same current.

  In other words, it is assumed that the IL characteristic at a certain temperature Temp1 has a laser threshold current Ith1, and the current change / light emission power slope is α. When the temperature rises to Temp2, the laser threshold current shifts to Ith2, and the slope changes to β.

  In order to eliminate such influences, it is essential to perform feedback control so that a part of the laser emission is optically branched, the output power is directly monitored, and the monitor signal is always constant. Is called auto power control (hereinafter referred to as APC).

  A conventional laser driver circuit with a built-in write strategy function performs APC by feedback control between a PUH having a built-in strategy function and a main board on which a DSP (Digital Signal Processor) is mounted.

  The APC circuit in such a conventional laser driver circuit with a built-in write strategy controls the change of the bias current / the gradient of the light emission power and the bias current with analog signals. The DSP, controller, and APC circuit mounted on the main board and the laser driver circuit (Laser Diode Driver, hereinafter referred to as LDD) mounted on the PUH side are electrically connected via the flexible board. .

  Such a conventional laser driver circuit has the following problems. An analog control signal output from the APC circuit via the flexible substrate from the main substrate side is sent to the PUH to control the laser diode. Conversely, a power monitor value as an analog signal indicating the emission intensity of the laser diode is sent from the PUH side to the main board side.

For this reason, many wirings for control signals are required on the flexible substrate, and there is a problem that the number of wirings increases. In addition, signal lines for transmitting clocks, recording data, etc. in the recording mode are arranged close to the wiring for the analog control signal described above, and the analog control signal is affected by disturbance noise to operate the circuit. There was a problem of disturbing.
Japanese Patent Laid-Open No. 2001-291261

  An object of the present invention is to provide a laser diode circuit capable of suppressing an increase in the number of wirings on a flexible substrate and reducing the influence of noise on an analog control signal, and an optical disk apparatus using the same.

A laser diode circuit according to an aspect of the present invention is provided with a waveform generation circuit that is supplied with a clock and recording data and outputs a switching control signal, and a driving current value is set independently of each other, is supplied with the switching control signal, and is turned on. A plurality of current drivers that output a recording current waveform or a reproduction current waveform under controlled off /
The same number as the current driver, a power setting register for storing a power setting value of a laser diode, and the power setting value provided as many as the power setting register and output from the power setting register, respectively. Is converted into an analog power set value signal and output, and a power monitor signal for monitoring the light emission power of the laser diode is given, and the monitor signal is sampled or held in conjunction with the recording data A sample-and-hold circuit that outputs the same number as the current driver, and based on the monitor signal output from the sample-and-hold circuit and the analog power set value signal output from the digital / analog converter circuit The driving power of the current driver To determine the value, characterized in that it comprises a power control circuit that outputs to the current driver.

  An optical disc device according to an aspect of the present invention is provided with a clock and recording data, and a waveform generation circuit that outputs a switching control signal, a driving current value is set independently of each other, the switching control signal is applied, A plurality of current drivers that are controlled to be turned off and output a recording current waveform or a reproduction current waveform, a power setting register that is provided in the same number as the current drivers and that is given a power setting value of a laser diode, and the power setting A digital / analog conversion circuit that is provided in the same number as the register for converting the power setting value output from the power setting register to an analog power setting value signal and outputs the analog power setting value signal to the corresponding current driver as the driving current value; A power monitor signal for monitoring the light emission power of the laser diode An analog / digital conversion circuit that converts the digital monitor signal to an external output and determines the drive current value of each of the current drivers based on the digital monitor signal, and sets the power setting value to the power And a controller for outputting to the setting register.

  As described above, according to the laser diode circuit and the optical disc apparatus of the present invention, it is possible to suppress an increase in the number of wires on the flexible substrate and reduce the influence of noise on the analog control signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(1) Embodiment 1
FIG. 1 shows a configuration of a laser driver circuit and an optical disk apparatus including the laser driver circuit according to Embodiment 1 of the present invention.

  In the first embodiment, a DSP, a controller, and an APC circuit are mounted on a main board (not shown), and an LDD 601 mounted on the PUH side is electrically connected via a flexible board. The LDD 601 incorporates a write strategy circuit 603 having a recording or reproduction waveform generation function called a write strategy.

  The LDD 601 includes a serial interface circuit SIF 602, a strategy setting register 627, a write strategy circuit 603, a phase-locked loop (hereinafter referred to as PLL) circuit 604 for multiplying an externally input clock to generate an internal recording clock, APC block 699, DAC 612, 4-channel current driver circuit having registers 605-608, digital / analog converters DACs 609-611 for setting light emission power and drive current, and APC circuits 613-615, each independently The peak driver 616, the erase driver 617, the read driver 618 and the bottom driver 619, the analog input terminal AIN 626, the connection terminals 628 to 630, and the switching terminal 63 that can set the drive current value. , And a laser drive terminal 633.

  A power monitor signal obtained by detecting the intensity of light emitted from a photodiode circuit (hereinafter referred to as PDIC) 625 is input to the analog input terminal AIN 626 as an analog signal AIN. The other terminals of the external capacitors CBW1 622, CBW2 621, and CBW3 620 for APC band control, each having one end grounded, are connected to the connection terminals 628 to 630, respectively.

  A recording / reproduction switching signal RW for switching the recording mode / reproduction mode is input to the switching terminal 631. The laser drive terminal 633 is connected to the anode terminal of a laser diode 624 whose cathode terminal is grounded.

  In the reproduction mode, only the read driver 618 operates in a constantly on state to output a direct current and is supplied to the laser diode 624 via the output terminal 633.

  In the recording mode, except for the read driver 618, a three-channel current driver circuit including a peak driver 616, an erase driver 617, and a bottom driver 619 operates. Then, the write strategy circuit 603 supplied with the recording clock WCLK from the main substrate side adds the current by a combination of high-frequency on / off switching synchronized with the recording clock WCLK, and generates a recording current waveform to output the output terminal. 633.

  As shown in FIG. 2, the reproduced waveform is a waveform obtained by modulating the optical power of DC output, which is referred to as read power, having a relatively small amount of light, for the purpose of reducing laser noise, which is referred to as high-frequency superposition. It has become.

  In the recording mode, as shown in FIG. 3, a current driving waveform 802 called a multi-pulse synchronized with the recording clock WCLK 801 is used based on the recording data WDATA 801. The current drive waveform 802 is configured by combining three peak levels, erase levels, and bottom levels.

  The switching control signal for switching on / off switching of the drivers 616 to 619 when generating the current driving waveform 802 is combined with the peak signal 804, the erase signal 805, and the bottom signal 806 which is always on in FIG. Generated. In this example, the three-level recording current drive waveform 802 has been described. However, four-level and five-level recording waveforms may be generated and used.

  Here, the switching control signal 623 that defines the ON / OFF switching timing in each of the drivers 616 to 619 shown in FIG. 1 is generated by the write strategy circuit 603 that performs waveform generation processing.

  The SIF 602 is an interface circuit controlled by a general three-wire system (SCLK, SDATA, SEN), activated by a serial enable signal SEN, and synchronized with the serial clock signal SCLK to record speed and media type. The serial data SDATA corresponding to the data is input to the SIF 602, and the recording waveform is set in the strategy setting register 627 so that the optimum recording waveform is obtained.

  The SIF 602 sets data in the registers 605 to 608 for setting the light emission power and the drive current value. Here, the register (P) 605, the register (E) 606, the register (R) 607, and the register (B) 608 are registers for setting peak power, erase power, read power, and bottom power, respectively.

  Among the registers 605 to 608, the output values of the registers 605 to 607 are converted into power setting values (target values) as analog signals by the DACs 609 to 611, respectively. Further, although not shown, other than the light emission power and the drive current value, for example, a condition setting of the PLL, the internal state of the LDD 601 and the like may be provided and set similarly. Note that the bottom power certified in the register 608 is directly converted into a drive current value by the DAC 612 without being converted into a target value because it does not have an APC circuit.

  In the write strategy circuit 603, a switching control signal 623 for switching on / off of each of the drivers 616 to 619 based on the recording waveform set in the strategy setting register 627 and the input recording data WDATA; A sample timing signal 1013A input to a sample hold circuit (to be described later) in the APC circuits 613 to 615 and a switching control signal 1013B for switching on / off of the switch are generated and output.

  The output currents of the drivers 616 to 619 are summed and output from the output terminal 633. The laser diode 624 is driven by this output, and light having a power corresponding to the drive current value is emitted to record data.

  Part of the light output from the laser diode 624 is branched, received by the PDIC 625, and output as a power monitor signal converted from light to an electrical signal. As shown in FIG. 3, this signal has a PDIC output waveform 803 in which the edge is dull due to the response characteristic of the PDIC 625 and there is a delay with respect to the optical input. The analog input terminal 626 is input.

  The APC block 699 will be described with reference to FIG.

  In the APC block 699, the configuration of the three systems including peak, erase, and lead is common, and the configuration of the DAC 609, the DAC 651, and the APC circuit 613 connected to the peak driver 616 will be described as an example.

  The APC circuit 613 includes a sample hold circuit 1001, an APC comparison amplifier 1004, an operational amplifier 1005, a hold switch 1006, a reset switch 1007, and a charge switch 1008, and is connected to the capacitor CBW 1 622 through a connection terminal 628. Here, a portion excluding the sample hold circuit 1001 from the APC circuit 613 corresponds to a power control circuit.

  A power monitor signal is input to the sample and hold circuit 1001 as an analog input signal AIN input from the analog input terminal 626 in FIG. The sample hold circuit 1001 takes in an analog value at a predetermined timing according to the sample timing signal 1013A, and outputs an AD monitor signal 1011.

  As described above, the power setting value is set in the register (P) 605 and converted into an analog value by the DAC 609. The power setting value having the analog value and the AD monitor signal 1011 having the analog value output from the sample hold circuit 1001 are input to the APC comparison amplifier 1004 and compared. The comparison result is applied to the capacitor CBW1 622 via the connection terminal 628 when the hold switch 1006 is on. When the reset switch 1007 is turned on, the output terminal of the APC comparison amplifier 1004 is grounded.

  On the other hand, the initial current value at the start of the APC feedback loop is set in the DAC 651. An initial value current setting value having an analog value output from the DAC 651 is supplied to the operational amplifier 1005 and amplified. When the charge switch 1008 is turned on, the capacitor CBW1 622 is charged according to the amplified value.

  Further, the output terminal of the APC comparison amplifier 1004 and the output terminal of the operational amplifier 1005 are connected via the hold switch 1006 and the charge switch 1008, and are connected to the input terminal of the driver 616.

  Here, the hold switch 1006, the reset switch 1007, and the charge switch 1008 are analog switches for setting an APC state in which an APC feedback loop is formed, a hold mode, a reset mode, and a charge mode. The / off state is as shown in FIG.

  Regarding the DAC 610, the DAC 652 and the APC circuit 614 connected to the other erase driver 617, and the DAC 611, the DAC 653 and the APC circuit 615 connected to the read driver 618, the DAC 609, the DAC 651 and the APC circuit 613 connected to the peak driver 616 described above. The description is omitted.

  The operation of the APC block 699 having the above configuration will be described below.

  The power monitor signal input from the analog input terminal AIN is selectively sampled to a light intensity level at a specific timing by the sample and hold circuit 1001 and output as an AD monitor signal 1011. FIG. 6 shows an example of the sample timing of the light intensity waveform output from the erase driver 617 during recording.

  The light intensity waveform is a multi-pulse waveform in which a plurality of irradiation levels are mixed. In order to detect the same level of power, the sample timing signal 1013A input to the sample hold circuit 1001 is written by the write strategy circuit 603 by each driver 616. Are generated in conjunction with a switching control signal 623 that defines timing for controlling on / off switching of ˜619.

  The APC comparison amplifier 1004 compares the AD monitor signal 1011 after the sample hold and the power set value signal 1012 output from the DAC 609. When the AD monitor signal 1011 is larger than the APC power set value, the AD monitor signal 1011 acts in the direction of discharging the external capacitor CBW1010 (in the direction of decreasing the voltage applied to the capacitor CBW1010). Conversely, when the light intensity signal is smaller than the power set value, it acts in the direction of charging the external capacitor CBW1010 (in the direction of increasing the voltage applied to the capacitor CBW1010).

  A drive current set value signal 1015 having a voltage value charged in the capacitor CBW 1010 has a drive current set value to be given to the drivers 616 to 618, and is given to the drivers 616 to 618 to control increase / decrease in output current. An APC feedback loop is formed.

  As described with reference to FIG. 5, the external capacitor CBW1010 is provided with three analog switches (hold switch 1006, reset switch 1007, charge switch 1008), and various modes (APC state, hold mode, reset). Mode, charge mode). The relationship between various modes and on / off of each switch is as shown in the truth table in FIG. Here, switching control signals (A), (B), and (C) for controlling on / off switching of the switches 1006 to 1008 are switching control signals output from the write strategy circuit 603 shown in FIG. 1013B.

  Normally, in the APC state, the APC feedback loop is formed with only the hold switch 1006 turned on. The APC feedback loop is formed to follow the temperature fluctuation, and the control band is as low as several KHz or less. For this reason, the capacity of the capacitor CBW 1010 is relatively large, such as 0.01 μF to 1 μF, and is an external component via the connection terminal 1009. Since the capacity is large, it takes a certain time to charge the capacitor CBW 1010 from the ground voltage to a desired voltage.

  For example, when the APC feedback loop is activated when the driving current set value signal 1015 output from the capacitor CBW 1010 starts with the ground voltage at the time of switching between the reproduction mode and the recording mode, the switching point from the reproduction mode to the recording mode. Therefore, it takes about several tens of microseconds to settle to a stage where desired light emission power can be obtained. During this time, the light emission power is not stable and only low accuracy is obtained.

  Therefore, in the first embodiment, a charge switch 1008 is provided in the APC block 699 to charge the capacitor CBW1010. When only the charge switch 1008 is turned on, the charging mode is set, and the drive current set value signal 1015 is equivalent to the initial value current set value output from the DAC 651.

  First, the drive current setting value signal 1015 is set to a predetermined voltage value in the charging mode with the corresponding driver among the drivers 616 to 618 being switched off. By turning off the charge switch 1008 at the same time as turning on the hold switch 1006 and starting the operation of the APC feedback loop, it is possible to shorten the time until a predetermined light emission power is stably obtained.

  Next, a case where switching between the recording mode and the reproduction mode is performed in a short time will be described.

  In the playback mode, only the read driver 618 is operating, and the other drivers 616, 617, 619 are not operating and are always in the off state. At this time, an APC feedback loop of read driver 618 → laser diode 624 → PDIC 625 → analog input terminal AIN 626 → APC circuit 615 → read driver 618 is formed.

  The APC circuit 613 included in the APC system using the peak driver 616 is in a hold state, and the capacitor CBW1 622 holds a voltage corresponding to the drive current value.

  Similarly, the APC circuit 614 included in the APC system using the erase driver 617 is also in the hold state, and the capacitor CBW2 621 holds a voltage corresponding to the drive current value.

  At the time of switching from the reproduction mode to the recording mode, the hold switch 1006 in the APC circuit 615 included in the APC system using the read driver 618 is turned off to set the drive current setting value in the reproduction mode to the end of the APC feedback loop. The previous drive current value, that is, the voltage value of the capacitor CBW3 620 is held.

  In the recording mode, the read driver 618 does not operate, the peak driver 616, the erase driver 617, and the bottom driver 619 are in an operating state, and a recording current is output, but in the playback mode, the capacitors CBW1 622 and CBW2 621 are output. The held voltage value is used as the initial value of the output current.

  In the recording mode, the hold switches 1006 in the APC circuit 613 and APC circuit 614 are turned on, and an APC feedback loop is started. However, the current as the initial setting value output from the DAC 651 is output until the control band is sufficiently entered.

  Similarly, in switching from the recording mode to the reproduction mode, by turning off the respective hold switches 1006 in the APC circuit 613 and the APC circuit 614, the driving current setting value in the recording mode is the driving current value immediately before the end of the APC feedback loop. That is, the voltage values of the capacitors CBW2 621 and CBW1 622 are held.

  According to the first embodiment, it is possible to form an APC feedback loop using an analog signal in a closed state on the PUH side by three components of the laser diode 624, the PDIC 625, and the LDD 601. As a result, APC can be realized without using a flexible substrate, and noise resistance is improved particularly during recording. Furthermore, an increase in signal lines on the flexible substrate can be prevented.

  Further, when switching between the recording state and the reproducing state, the initial value of the driving current value for the drivers 616 to 619 is set and held as the voltage value in the capacitors CBW1 622, CBW2 621, and CBW3 620 in advance, so that the APC At the start of the feedback loop, the drive current value can be raised to the target value at high speed. As a result, at the time of mode switching, a driving current can be output from the drivers 616 to 619 so that a desired light emission power can be obtained immediately after switching.

  Further, the comparison of the power monitor value output from the sample hold circuit 1001 and the power set value output from the DAC 609 in the comparison amplifier 1004 switches the charging and discharging of the capacitors CBW1 622, CBW2 621, and CBW3 620. . By adjusting the capacities of these capacitors, the bandwidth of the APC feedback loop can be controlled.

(2) Embodiment 2
A laser driver circuit and an optical disk apparatus including the laser driver circuit according to Embodiment 2 of the present invention will be described with reference to FIG.

  The second embodiment is different from the first embodiment in that an analog / digital converter (ADC) block 1213 is arranged inside the LDD 1201. As an input signal of the ADC block 1213, at least one of the AD monitor signal 1011, the power set value signal 1012, and the drive current set value signal 1015 is provided in each APC circuit 1214 to 1216 and shown in FIG. It can be one signal or all.

  The digital data 1233 that is input to the ADC block 1213 and converted into a digital signal is output as serial data SDATA to the outside of the DDC 1201 via the SIF 1202, and is given to a controller on the main board via a flexible board (not shown). . Other configurations are the same as those in the first embodiment, and a description thereof will be omitted.

  Here, as described above, the AD monitor signal 1011 has the value of the power monitor signal after sampling in the sample hold circuit 1001. The power setting value signal 1012 is a target APC power setting value, and the driving current setting value signal 1015 is a signal having the driving current setting value of the corresponding driver among the drivers 1217 to 1219.

  For example, the actual light emission power and the drive current set value can be monitored by comparing the value of the AD monitor signal 1011 and the value of the drive current set value signal 1015 in the controller on the main board. Thereby, on the main substrate side, it is possible to know the state of the IL curve shift of the laser diode 1225, whether it is in an overcurrent state, and the like.

  Further, it is possible to know whether or not an abnormality has occurred in the APC feedback loop by comparing the AD monitor signal 1011 and the power set value signal 1012 in the controller. When the APC feedback loop is operating normally, the values of the AD monitor signal 1011 and the power set value signal 1012 are substantially equal, and if there is a difference greater than the allowable value, it is abnormal. .

  As described above, according to the second embodiment, information on various analog signals in the APC block 1299 inside the LDD 1201 can be converted into digital data by the ADC 1213 and then transmitted to the main board side via the SIF 1202. As a result, the noise resistance is improved and the operation state in the APC block 1299 can be observed on the main board side without causing an increase in the number of wirings on the flexible board by transferring the serial data as SIF 1202. it can.

(3) Embodiment 3
FIG. 8 shows a configuration of a laser driver circuit and an optical disk device including the laser driver circuit according to the third embodiment of the present invention.

  On the main board 1330, a controller 1328 for performing various controls and a DSP 1329 for performing overall digital signal processing in the optical disc apparatus are mounted. On the other hand, a laser diode 1320, a PDIC 1321, and an LDD 1301 are provided on the PUH 1399 side. The LDD 1301 is not equipped with an APC block. The SIF 1302, the strategy setting register 1324, the write strategy circuit 1303, the PLL circuit 1304, the registers 1305 to 1308, the DACs 1309 to 1312, the ADC block 1313, the sample hold 1314, and the driver 1315 1318 is provided.

  In the first and second embodiments, the APC block is provided on the LDD side, and the driver drive current is controlled by the APC so that the set value having the digital value set in the register and output from the DAC is maintained. Do. On the other hand, in the third embodiment, the APC block is not provided in the LDD 1301, and the drivers 1315 to 1318 are directly operated with the set values output from the DACs 1309 to 1312 to supply a drive current to the laser diode 1320. The power monitor signal from the PDIC 1321 is input to the analog input terminal 1323 as an analog signal AIN, transmitted to the main board 1330 side via the SIF 1302 and the flexible board 1331, and the output values from the DACs 1309 to 1312 are maintained on the main board 1330 side. Control to be done.

  As in the first and second embodiments, the register (P) 1305, the register (E) 1306, the register (R) 1307, and the register (B) 1308 are respectively a peak driver 1315, an erase driver 1316, a read driver 1317, and a bottom. This is a register for setting each drive current value of the driver 1318, and data is written from the controller 1328 via the SIF 1302.

  The DACs 1309, 1310, 1311, and 1312 convert the outputs of the register (P) 1305, the register (E) 1306, the register (R) 1307, and the register (B) 1308 into analog drive current setting values, respectively, A drive current set value signal is given to 1316, 1317, and 1318. The drivers 1315 to 1318 to which the drive current setting value signal is given give the drive current to the laser diode 1320 to emit light.

  When the power monitor signal is output from the PDIC 1321, it is input to the sample hold circuit 1314 as the analog input signal AIN via the analog input terminal AIN 1323 as described above.

  The sample hold circuit 1314 has a 4-channel configuration corresponding to peak, erase, bottom, and read, and follows a switching control signal 1322 that controls on / off switching of the sample / hold generated by the write strategy circuit 1303. The power monitor signal is selectively sampled along the time direction, and analog signals corresponding to the peak level, erase level, bottom level, and read level are output to the ADC block 1313. The analog signal is converted into digital data 1325 by the ADC block 1313.

  The digital data 1325 is output to the outside of the LDD 1301 as serial data SDATA via the SIF 1302. Further, the digital data 1325 is given to the DSP 1329 via the flexible board 1331 and the controller 1328 on the main board 1330. The DSP 1329 monitors the light emission intensity value converted into a digital signal by the ADC block 1313 inside the LDD 1301, performs shift estimation based on the temperature of the IL curve of the laser diode 1320, and calculates a current value that provides an appropriate light emission intensity. .

  The current value obtained by the DSP 1329 is stored in the register (P) 1305, the register (E) 1306, the register (R) 1307, and the register (B) 1308 via the controller 1328, the flexible substrate 1331, and the SIF 1302 on the LDD 1301 side. Rewrite the current drive current setting value.

  As described above, in the third embodiment, the drive current setting value and the power monitor value in the analog signal form in the LDD 1301 are converted into digital data, and the DSP 1329 on the main board 1330 is used for monitoring via the flexible board 1331. By transmitting, an APC feedback loop is formed.

  If an APC feedback loop is formed in the form of digital data only with a DSP, the load on the DSP side increases. On the other hand, if an APC feedback loop is formed only in the LDD using an analog signal, the DSP is not involved in the control and the load is small. However, the APC feedback loop may oscillate when a malfunction occurs in the LDD.

  In the third embodiment, an APC feedback loop is formed in the form of an analog signal in the LDD, and then the drive current set value and the power monitor value are converted into digital data and monitored by the DSP, whereby both types of APC are used. A feedback loop can be formed for optimization.

(4) Embodiment 4
A laser driver circuit and an optical disk device including the laser driver circuit according to the fourth embodiment of the present invention will be described with reference to FIG.

  When switching between the recording mode and the reproduction mode, a predetermined time is required to switch the gain of the PDIC 1426. Therefore, the fourth embodiment is characterized in that the APC feedback loop is not turned on until this time elapses.

  In the recording mode, only the read driver 1419 is kept off, and the other peak driver 1417, erase driver 1418, and bottom driver 1420 are turned on or off. Further, the light emission intensity of the laser diode 1425 in the recording mode is relatively higher than that in the reproduction mode.

  On the other hand, in the playback mode, only the read driver 1419 is turned on, and the other drivers 1417, 1418, and 1420 are all turned off. At this time, the emission intensity of the laser diode 1425 is lower than that in the recording mode.

  Therefore, in the fourth embodiment, a recording / reproduction switching timing circuit 1416 is provided in the LDD 1401 to delay the switching timing between the recording mode and the reproduction mode by a predetermined number of clocks. When a recording / reproduction switching signal RW1432 is input to the recording / reproduction switching timing circuit 1416 from the main board (not shown) to the recording / reproduction switching timing circuit 1416 via the input terminal 1430, the recording / reproduction switching timing circuit 1416 is delayed for a predetermined time. A switching signal 1434 is output and output to the APC circuits 1413 to 1415. This state switching signal 1434 controls switching of three switches in the APC circuits 1413 to 1415 in place of the switching control signals 1013B and 1227B output from the write strategy circuits 603 and 1203 in the first embodiment. It corresponds to a thing.

  Until the state switching signal 1434 is input, the APC circuits 1413 to 1415 do not perform the APC feedback loop operation. As a result, the hold switch 1006 shown in FIG. 5 inside the APC circuits 1413 to 1415 controlled by the switching control signal 1424 for controlling the on / off switching of the drivers 1417 to 1420 and the delayed state switching signal 1434. There is a time difference in the timing for switching on / off the reset switch 1007 and the charge switch 1008.

  That is, there is a time difference between switching of mode setting (APC state, hold state, reset state, charge state) in the APC circuits 1413 to 1415 and switching of the drivers 1417 to 1420 on / off.

  In the recording mode and the reproduction mode, the emission intensity differs by about 10 to 20 times at the maximum. For this reason, the PDIC 1426 has a gain switching function for switching the conversion coefficient of optical / electrical signal conversion in a plurality of stages, and switches between the reproduction mode and the recording mode.

  FIG. 10 shows a change in the state of the APC circuits 1413 to 1415 and a change in the level of the power monitor signal 1431 output from the PDIC 1426 when the reproduction state is switched to the recording state in accordance with the recording / reproduction switching signal RW1432.

  When the recording / reproduction switching signal RW1432 changes from the low level to the high level at the time t1, and the mode is switched from the reproduction state to the recording state, the APC circuit 1415 is switched from the APC state to the hold state at the time t1. Along with this, the read driver 1419 is turned off at time t1 in synchronization with the change in the level of the recording / playback switching signal RW1432, and switches from the APC state to the hold state in which the drive current set value is held in the capacitor CBW3 1421. .

  In the reproduction mode, both the APC circuits 1413 and 1414 are in the off state, and the erase driver 1418 and the peak driver 1417 are off and in the hold state.

  Immediately after the level of the recording / reproduction switching signal RW1432 changes and switches from the reproduction state to the recording state at time t1, the peak APC circuit 1413 and the erase APC circuit 1414 maintain the hold state. In accordance with this, the peak driver 1417 and the erase driver 1418 output drive currents based on the drive current set values held in the capacitors CBW1 1423 and CBW2 1422 to the laser diode 1425, respectively.

  Thereafter, the APC circuits 1413 and 1414 shift from the hold state to the APC state in conjunction with the state switching signal 1434 at time t3.

  The gain switching of the PDIC 1426 is instantaneously performed in conjunction with the level change of the state switching signal RW1432 at the time point t1. However, in the PDIC 1426, after the mode is switched at the time t1, the output level rises at the time t2, and a certain delay time is required until the time t3 when the output level is stabilized.

  From the time point t2 to the time point t3, the output level of the PDIC 1426 changes transiently, and an incorrect power monitor signal 1431 is output. The state switching signal 1434 to be given to the APC circuits 1413 and 1414 is set so that the timing of the state switching in the APC circuits 1413 and 1414 is later than the gain switching response time in the PDIC 1426. As a result, the hold state can be maintained during the period when the incorrect power monitor signal 1431 is output, and smooth APC feedback loop control from the reproduction mode to the recording mode becomes possible.

  FIG. 11 shows changes in the internal state of the APC circuits 1413, 1414, and 1415 and the level of the power monitor signal 1431 output from the PDIC 1426 when the recording mode is switched to the reproduction mode.

  At time t11, when the level of the recording / reproduction switching signal RW1432 changes to switch from the recording state to the reproduction state, the APC circuits 1413 and 1414 are turned off in synchronization with this switching timing, and accordingly the peak driver 1417 and erase The driver 1418 is turned off. The APC state in which the peak driver 1417 is on is switched to a hold state in which the drive current set value is held in the capacitor CBW1 1423. Similarly, the APC circuit 1414 is also turned off at time t11 and the erase driver 1418 is turned off, so that the APC state is switched to the hold state in which the drive current set value is held in the capacitor CBW2 1422. The APC circuit 1415 is off in the recording state, and the read driver 1419 is off and is in the hold state.

  Immediately after the level of the recording / reproduction switching signal RW1432 changes and switches from the recording state to the reproduction state at time t11, the read APC circuit 1415 maintains the hold state. As a result, a current based on the drive current setting value held in the capacitor CBW3 1421 is output from the read driver 1419.

  Thereafter, at time t13, the state shifts from the hold state to the APC state in synchronization with the state switching signal 1434 supplied to the APC circuit 1415. The gain switching of the PDIC 1426 is performed in conjunction with the switching timing of the recording / reproducing switching signal RW1432, but a certain time is required until the output level is stabilized.

Therefore, as shown in FIG. 11, the level of the power monitor signal 1431 from the PDIC 1426 fluctuates transiently and an incorrect signal is output. Therefore, the switching timing of the state switching signal 1434 applied to the APC circuit 1415 is set to be later than the response time required for the gain switching of the PDIC 1426. As a result, the hold state can be maintained during the period when the incorrect power monitor signal 1431 is output, and the smooth transition from the recording mode to the reproduction mode is possible. By adopting a simple configuration, the influence of the level fluctuation of the transient power monitor signal 1431 generated depending on the inherent gain switching delay of the PDIC 1426 when switching from the playback mode to the recording mode and from the recording mode to the playback mode. Without being received, it is possible to smoothly shift from the state in which the drive current set value is held to the APC feedback loop, and to obtain stable light emission power.

  Further, the response time required for the gain switching of the PDIC 1426 is a fixed time unique to each PDIC. The state switching timing signal 1434 generated by the recording / reproduction switching timing circuit 1416 and supplied to the APC circuits 1413 to 1415 can set a delay time in units of clocks according to the recording double speed by the SIF 1402, and is in an appropriate state. Switching timing can be realized.

(5) Embodiment 5
A laser driver circuit and an optical disk device including the laser driver circuit according to a fifth embodiment of the present invention will be described with reference to FIG.

  In the fifth embodiment, when the voltage accumulated in the capacitors 1621 to 1623 exceeds a predetermined value, the laser diode 1625 is caused to output a light emission power higher than necessary, and any error occurs. Has a function to judge. In order to realize such a function, an error detection circuit 1609 for determining whether or not the drive current set value is an abnormally large value is provided in the LDD 1601.

  The drive current setting values of the peak driver 1617, the erase driver 1618, and the read driver 1619 are input to the error detection circuit 1609, and when a preset threshold value, that is, a current value higher than this is detected, it is determined that there is an abnormality. Compare with the level you want. As a result, whether or not an abnormality has occurred, specifically, whether or not an overcurrent is flowing, is output from the error detection circuit 1609 as a “0” or “1” flag. This flag is read by the SIF 1602 and transmitted to the main board (not shown).

  Here, the drive current setting value corresponds to the terminal voltages of the terminals 1628, 1629, and 1630 to which the capacitors CBW1 1623, CBW2 1622, and CBW3 1621 are connected. In the APC state, since the APC feedback loop always operates so that the power is always constant, the drive current set value varies depending on the surrounding environmental conditions and the like.

  However, the ADC block 1699 is built in the LDD 1601 and the drive current set value is constantly monitored because the DSP on the main board side (not shown) that controls the start of the operation of the ADC block 1699, data reading, etc. The burden will increase.

  Therefore, in the fifth embodiment, by adopting the above-described configuration, when an overcurrent occurs in the APC block 1699, the error detection circuit 1609 monitors, and the monitoring result is read out via the SIF 1602. Abnormalities can be detected in the DSP on the main board side without increasing the number of signal wirings on the flexible board.

  The above-described embodiments are merely examples, and the present invention is not limited thereto, and various modifications can be made within the technical scope of the present invention.

1 is a circuit diagram showing a configuration of a laser driver circuit and an optical disc apparatus according to Embodiment 1 of the present invention. Explanatory drawing which showed the optical output waveform at the time of the reproduction | regeneration mode in the laser driver circuit. Explanatory drawing which showed the optical output waveform at the time of the recording mode in the laser driver circuit. Explanatory drawing equivalent to the trial value table | surface which shows the relationship between the various modes and switch ON / OFF in the laser driver circuit. The circuit diagram which shows the structure of 1 system in the APC block in the laser driver circuit. FIG. 4 is an explanatory diagram showing sample timing of a light intensity waveform output from an erase driver during recording in the laser driver circuit. FIG. 5 is a circuit diagram showing a configuration of a laser driver circuit and an optical disk device according to a second embodiment of the present invention. FIG. 6 is a circuit diagram showing the configuration of a laser driver circuit and an optical disk device according to a third embodiment of the present invention. FIG. 6 is a circuit diagram showing a configuration of a laser driver circuit and an optical disk device according to a fourth embodiment of the present invention. FIG. 5 is an explanatory diagram showing a change in mode state inside the APC block and a change in the level of the output signal of the PDIC when the playback mode is switched to the recording mode in the laser driver circuit. FIG. 4 is an explanatory diagram showing a change in the mode state inside the APC block and a change in the level of the output signal of the PDIC when the recording mode is switched to the reproduction mode in the laser driver circuit. FIG. 6 is a circuit diagram showing a configuration of a laser driver circuit and an optical disk device according to a fifth embodiment of the present invention.

Explanation of symbols

601, 1201, 1301, 1401, 1601 Laser driver circuit (LDD)
602, 1202, 1302, 1402, 1602 Serial interface circuit (SIF)
603, 1203, 1303, 1403, 1603 Write strategy circuits 605 to 608, 1205 to 1208, 1305 to 1308, 1405 to 1408, 1605 to 1608 Registers 609 to 611, 651 to 653, 1209 to 1211, 1251 to 1253, 1309 to 1312, 1409-1412, 1451-1453, 1610-1612, 1651-1653 DAC
613-615, 1214-1216, 1413-1415, 1614-1616 APC circuits 616-619, 1217-1220, 1315-1318, 1417-1420, 1617-1620 Current drivers 620-622, 1010, 1221-1223, 1421 1423, 1621-1623 Capacitors 624, 1225, 1320, 1425, 1625 Laser diodes 625, 1226, 1321, 1426, 1626 Photodiode circuits (PDIC)
1001 Sample hold circuit 1330 Main board 1328 Controller 1329 DSP

Claims (5)

A waveform generation circuit which is supplied with a clock and recording data and outputs a switching control signal;
A plurality of current drivers that each independently set a drive current value, given the switching control signal, and controlled to be turned on / off to output a recording current waveform or a reproduction current waveform;
A power setting register that is provided in the same number as the current driver and stores a power setting value of the laser diode,
A digital / analog conversion circuit that is provided in the same number as the power setting register, converts the power setting value output from the power setting register to an analog power setting value signal, and outputs the analog power setting value signal;
A sample and hold circuit that receives a power monitor signal that monitors the light emission power of the laser diode, outputs a monitor signal by sampling or holding in conjunction with the recording data;
The drive current of the corresponding current driver is provided based on the monitor signal output from the sample and hold circuit and the analog power set value signal output from the digital / analog conversion circuit. A power control circuit that determines the value and outputs to this current driver;
A laser driver circuit comprising: The waveform generation circuit further outputs first and second switching control signals based on the recording data,
Each of the power control circuits is
A capacitor with one terminal connected to the connection terminal;
A first analog switch having one terminal connected to the connection terminal and controlled to be turned on / off by the first switching control signal;
A second analog switch having one terminal connected to the connection terminal and controlled to be turned on / off by the second switching control signal;
Based on the result of comparing the value of the power monitor signal sampled and held by the sample and hold circuit with the value of the analog power set value signal and having an output terminal connected to the other terminal of the first analog switch A comparison amplifier that charges and discharges the capacitor via the first analog switch;
An output terminal is connected to the other terminal of the second analog switch, an initial value current set value is given, and the voltage of the connection terminal becomes a voltage corresponding to the initial value current set value. An amplifier that charges and discharges the capacitor via an analog switch of
The charge mode for charging until the voltage of the connection terminal reaches a predetermined voltage by controlling on / off of the first and second analog switches by the first and second switching control signals; and The hold mode for holding the voltage of the connection terminal and the control mode for charging and discharging the capacitor so that the value of the power monitor signal matches the value of the analog power set value signal are switched, and the voltage of the connection terminal is switched. The laser driver circuit according to claim 1, wherein the drive current value of the current driver is determined based on the equation (1). An analog / digital conversion circuit that receives the power monitor signal sampled and held by the sample and hold circuit, performs analog / digital conversion, and outputs a digital power monitor signal;
3. The laser driver circuit according to claim 1, further comprising a serial interface circuit that outputs the digital power monitor signal to the outside in the form of serial data. Based on the timing at which the switching control signal switches on / off of the current driver, a state switching signal obtained by delaying a recording / reproduction switching signal given from the outside by a predetermined delay amount is used as the first and second controls. A recording / reproducing switching timing circuit for outputting as a signal;
4. The laser driver circuit according to claim 1, wherein on / off of the first and second analog switches is controlled based on the first and second control signals. A waveform generation circuit which is supplied with a clock and recording data and outputs a switching control signal;
A plurality of current drivers, each of which is independently set to a drive current value, given the switching control signal, and controlled to be turned on / off to output a recording current waveform or a reproduction current waveform;
A power setting register that is provided in the same number as the current driver and stores a power setting value of the laser diode,
Digital / analog provided as many as the power setting registers, converting the power setting values respectively output from the power setting registers into analog power setting value signals and outputting them to the corresponding current drivers as the driving current values A conversion circuit;
An analog / digital conversion circuit that receives a power monitor signal that monitors the light emission power of the laser diode, converts it to a digital monitor signal, and outputs the digital monitor signal;
A controller that determines the drive current value of each of the current drivers based on the digital monitor signal and outputs the power setting value to the power setting register;
An optical disc apparatus comprising:

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