TWI270822B - Battery activation circuit - Google Patents

Abstract

A system and method for selectively activating a device based on an activate command. A circuit, in low power mode, listens for an activate command. The activate command includes a preamplifier centering sequence, an interrupt signal, and an activate code. The circuit receives a signal that may or may not be an activate command, self-biases the signal based on the preamplifier centering in the preamp/gain control, then determines whether the interrupt signal is of the proper length in the interrupt circuit. If the interrupt is not the proper length, the process stops. If it is the proper length, the command is recognized as an activate command, and a data slicer compares the activate code to a prestored value. If the activate code matches the prestored value, the device is powered up. If they do not match, the device is not initiated.

Description

1270822 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD This invention relates to power saving circuits, and more particularly to a circuit that can be selectively activated to provide a power saving function. [Prior Art] Automatic identification ("AutcHD") technology is used to assist the machine in identifying objects and automatically acquiring data. The earliest Aut.丨D technology - that is, the bar code, the basin uses - the interval sequence of wide and narrow stripes, which can be translated by optical scanning. This technology is widely adopted and nearly globally accepted through the designation of the up-commodity bar code (upc). The 'unified commodity bar code is a standard set by an industry-wide group called the Unified Bar Code Association. It was officially announced in the festival year. Private: UPC is currently used in all the actual production of goods - 'and make the goods in the manufacturing, supply and lock-up tracking is extremely efficient. ~ 旦 f I exhaust: Of course, the operator needs to take the manual interrogation method to sweep two::: aunt a tagged item. This is the kind of sight and reliability limit of the manufacturer. In addition, the UPC bar code is only available: the product type information is encoded as a bar code, not a special product. The bar code on the milk carton will be the same as the other ones, so that ~, ^ calculate the object or individually check the product expiration date.目七包装箱箱条条条 _ has more than 40 kinds of 仏 仏. These printed labels are incorrect, and the county is ready to print. However, there may be situations such as printing errors, standing errors, and label errors. During the delivery process, these external labels are usually taken care of and transported, and they are lost. When receiving, usually the cargo pallet will cause the lower part to be damaged, and each box will be scanned into an enterprise system. The error rate of each checkpoint in the supply chain is 4-18%, thus generating one billion. The apparently problematic inventory, and only radio frequency identification ("RFID") can automatically combine software applications on the physical layer of the actual commodity to provide accurate tracking. The emerging RHD technology uses a radio frequency ("RF") wireless link with ultra-compact embedded computer chips to overcome bar code limitations. RFID technology enables physical items to be identified and tracked through these wireless "tags." Its function is like a bar code that automatically communicates with the reader without the need for manual line-of-sight scanning or separation of items. RFID promises to revolutionize the retail, pharmaceutical, military, and transportation industries. The advantages of RF丨D s over bar code are summarized in Table 1: Table one code RFID requires line of sight reading without line of sight to identify only readable readable/writable only bar code number can store data in tag bar code No. Fixed data can be updated at any time. Label can only identify the type of goods. It can identify a single item. Unidentifiable single item. If the barcode is damaged, it cannot be read. It can be forbidden. It can be used in a harsh environment. It can be used only once. Reusable cost. Low cost. /Value 1270822 As shown in FIG. 1, an RFID system 100 includes a tag 1, a reader 104 and an optical server (10). The tag 102 includes a C-chip and an antenna. The ic chip includes a digital decoder to execute the tag 1 〇 2 to receive computer instructions from the tag reader 104. The 丨c chip also includes a power supply line for fetching and regulating power from the RF reader; - _ to decode signals from the reader, a backscatter modulator; and a transmitter to transmit data back to read Machine; anti-collision agreement line; and at least enough memory to store its EPC code. The communication starts with the reader 104 transmitting a signal to find the label 1〇2. When the radio wave hits the tag 102' and the tag 102 acknowledges and responds to the signal of the reader, the reader 104 decodes the program data to In the label 1〇2, the information will be transmitted to the servo H 1Q6 for processing. By marking various items, the information about the nature and location of the product can be immediately and automatically known. Many impotence systems use reflection or "backscatter, radio frequency (RF) waves from the tag 102 to the reader] 〇 4. Because passive (Class-1 and Class-2) tags are available The reader signal gets all the power 'so the tag has power only in the beam of the reader 104. The EPC-allowed tag categories in the Automatic Identification Center are as follows:

Class-1 • Identification tag (RF user can be programmed 'maximum range 3 meters). Minimum cost (AIDC target: 5 points per unit US dollar down to 2 points per year - mega lot)

Class-2 • Memory tag (8-bit to 128 Mbits can be programmed, the maximum range is 7 8 1270822 3 meters) • Security and privacy protection • Low cost (AIDC target: 10 US dollars in 100 million units of bulk) ), ,,,

Class-3 • Battery label (256-bit to 64Kb). Self-powered backscatter (internal clock, detector interface support) • 1 〇〇 meter range

• General price (target · currently US$50, US$5 in two years, US$20 in a billion units)

Class-4 • Active label • Active transmission (allows the label to say the operating mode first) • Up to 30,000 meters range • Higher cost (target: US$10 in two years, US$30 in one billion units)

In the RHD system, passive receivers (ie ο.%) and (:|3 _2_2 sticks) can draw enough energy from the transmitted RF to provide power to the device, without the need for a battery. When the distance prevents the supply of the power supply in this way, an alternate power supply must be used. For these "alternating" systems (also known as active or semi-passive), the battery is the most common form of power supply, which can greatly increase the reading. Range, reliability with tag reading, because the tag does not need to be powered by the reader, the Class-3 tag only needs 1〇mV signal from the reader compared to the 50〇mV required for Class-1 operation. This 2,500:1 reduction in power requirements allows the ciass-3 tag to operate at distances of 8-1270822 100 meters or more, which is a significant difference from Class-1's distance of only about 3 meters. Early field trials have shown that passive short-range Class-1 and ciass-2 labels that are currently available are generally not suitable for label pallets and many different types of boxes. When these passive labels are "unfavorable with RF, materials such as metal( It is a soup pot), a metal foil (like a potato chip), or a conductive liquid (like a drink, shampoo). When used together, the problem is particularly serious. λ Someone can continue to read in a pile of boxes. The box label - this happens on the * bin or pallet. Existing passive tags are not suitable for use on large or fast moving objects such as trucks, cars, container trucks, etc.

Class-3 tags address these issues by placing battery and signal preamplifiers to increase the range. If the power consumption is well managed, the battery can last for several years, but if the power consumption is poorly managed, it may only be used for a few days, because the battery-powered system will coexist with the passive tag, so take care to reduce the power supply from the battery-powered system. Loss in the middle. If a Class-3 device continues to respond to an "other" device, such as an unwanted Class-1 command, the battery's power supply will drain very quickly. SUMMARY OF THE INVENTION The present invention includes a start-up circuit and a start-up command structure that enables a semi-actuated device (e.g., 'battery-powered) to detect a particular sequence of data to indicate device activation. If the device does not get the correct sequence, the received command will be ignored, thus saving power. The circuitry can be implemented, for example, in a radio frequency identification (RFID) tag' or any other device that requires limited power consumption. 8 1270822 According to one embodiment, a circuit of an activation device includes an interrupt circuit to determine whether an interrupt period of a received signal meets a predetermined multi-value or falls within a predetermined range, and thus can be recognized as a start command. A preferred start command preferably includes a preamplifier center alignment sequence, an interrupt period, and an enable code. The interrupt circuit outputs an interrupt signal if the interrupt period meets a predetermined value or falls within a predetermined range. A special data cutter compares the received start code with the stored value. If the received start code matches the stored value, the data cutter transmits a wake-up signal to activate the device. • The whai circuit preferably includes a self-biased amplifier that sets the bias point based on the 50% duty cycle waveform of the received clock synchronization sequence. This allows the circuit to set a bias point at the appropriate point to read the incoming start command (and subsequent transmissions) regardless of the presence of noise or signal strength variations. The V-pass filter rejects unwanted noise from the received signal. Preferably, the interrupt circuit includes a first pair of mirror inverters, each of which is tuned for use with a non-specific delay timing, and the first pair of mirror inverters _ between specific delay timings - The low period of the interrupt pulse. A second pair of mirror inverters is also provided, each inverter being tuned for use by an unspecified delay sequence, and the second pair of mirror inverters is operative to detect an interruption between specific delay timings. The high period of the pulse. Outputting the first door lock from the first pair of mirror inverters and storing the reverse, and outputting the first-flash lock embodiment from the second pair of mirror inverters and storing the reverse, and outputting the third flash from the first flash lock 11 cases were locked and stored. The igniting includes passing the gate. - The logic gate will receive the output from the second and third flash locks, and if the high pulse of the interrupt and the low 8 1270822 pulse fall in the delay sequence, the logic gate will output an interrupt signal. Preferably, the interrupt circuit includes - a first-mutual exclusive or (XQR) gate between the first pair of mirror inverters and the first flash lock, and a second between the second pair of mirror inverters and the second flash lock Two XOR gates. If the low period of the interrupt pulse is between the specific delay timing of the mirror-inverter, the output of the first x〇R gate is activated, and if the high period of the interrupt pulse is at the second pair of mirrors = The output of the second x〇R gate is activated when the device is between specific delay timings. Preferably, the interrupt circuit further includes a series of inverters between the first pair of mirror inverters and the third flasher, and a series between the second pair of mirror inverters and the second flash lock Inverter. «The gate can also receive the signal directly from the input, so the logic gate can therefore be a logic gate of 5 inputs. The circuit for activating the device may also include an adaptive timing circuit for controlling a data cutter, the adaptive timing circuit may include a trimmable reference oscillator, a phase locked loop oscillator (pll) , a calibration current mirror' or other similar circuit. • ▲ is used to initiate a general method such as an RFID tag device, preferably using a circuit as described above, including listening to a start command on a device; receiving a start command, and the start command includes a clock synchronization sequence, an interrupt cycle, And a start code; if the interrupt period meets a predetermined value or falls within a predetermined range /, the start code is analyzed; and if the start code meets the stored value in the shock, the device is activated, or if the start code and the pre-stored value If it doesn't match, it won't start the device. However, please note that the special boot code can also be implemented. For example, the -tag start code is all set to zero, and the tag will be used for any and 11 8 1270822. The startup code transmitted by the machine responded. Similarly, the tag can be set to respond to various codes. Alternatively, the reader can also issue a quick and continuous different activation code to initiate and communicate with various tag groups at the same time. The method can be performed by several RFID tags, and several tags are activated upon receipt of a particular boot command. Other features and advantages of the present invention will become more apparent from the detailed description of the invention. [Embodiment] The following is a description of the best embodiment of the present invention. The description herein is based on the general principles of the invention, and is not intended to limit the inventive concept of the invention. This invention is preferably implemented in a Class 3 or higher Class wafer, and Figure 2 illustrates a circuit diagram of a Class-3 wafer 200 in accordance with a preferred embodiment implemented in an RFID tag. This Class-3 wafer forms the core of an RFID chip and is suitable for many applications, such as pallets, packaging cartons, containers, vehicles, or any identification that requires more than 2 - 3 meters. As shown, the wafer 200 includes several industry standard circuits including a power generator and regulation circuit 202, a digital command decoder and control circuit 204, a detector interface module 206, and a C1V 2 interface communication protocol. Circuit 208, and a power source (battery) 210. A display drive module 212 can be added to drive a display. A battery enable line 214 is also presented as a wake-up trigger, and this circuit 12 -1270822 <RTIgt; Briefly, battery enable circuit 214 includes an ultra low power supply and a narrow bandwidth preamplifier that consumes only 5 〇 nA of electrostatic current. The battery enable circuit 214 also includes a self-timer interrupt circuit and uses the innovative 16-bit user to program the digital wake-up code. The battery enable circuit 214 consumes less power during its sleep state and is better protected against accidental and malicious false wake-up trigger events that would otherwise cause the Class-3 tag battery 210 to be depleted prematurely. A forward link AM decoder 216, using a simplified phase locked loop oscillator, requires an absolute minimum amount of wafer area. Ideally, the 5H circuit 216 requires only a minimum of series of reference pulses. The reverse political beam eliminator block 218 preferably increases the backscatter amplitude modulation depth to over 50%. A simple, Fowler_Nordheim direct permeation peroxide device 220 was used to simultaneously reduce the write and erase currents in the eepR〇m memory array to less than 0.1 μM/π丨丨. The difference from all current Rf:丨D is that this method allows the label to be specified to operate at the maximum range, even if it is executed during the write and erase operations. Wafer 200 is also integrated into a highly simplified, yet highly efficient, secure encryption circuit 222. Only four connection pads (not shown) are required to enable the wafer 2 to function: Vdd to battery, ground, plus two antenna pins to support multi-element multi-directional steering antennas. Detectors for monitoring temperature, vibration, and swaying can be attached to the core chip by an industry standard 丨2C interface. A very low cost Class-2 security device can be created by simply removing or removing wake-up modules, preamplifiers, and 丨F modules from the C|ass_3 chip 13 8 core. The battery activation circuit 214 described herein is used to communicate between two devices, one of which wants to activate or enable a receiving device through a radio frequency (RF) medium, when the circuit diagram is expected to be used in an RFID system. In the meantime, it is by no means meant to be limited only to the industry. This disclosure describes a preferred description of the RFID and the starting circuit of the specific embodiment, but by no means is meant to be limited to this technology. As a result, any system that requires an entity (eg, a transmitter) to alert another entity (eg, a reader) is suitable for this concept regardless of the media used (eg, RF, 丨R, cable, etc.) ). In order to reduce current consumption and increase the life of the battery power, a Class-3 (or higher) device can be used for startup. This "start," instruction consists of three parts of "instructions", the first part is clock synchronization, the second part is interrupt, and the last part is a digital user-initiated instruction code. These three parts conceptually generate a startup agreement. Although it is not necessary to actually follow these three processing steps, the steps or methods must be adequately removed from the "other normal" traffic, so that it can decrypt the start command in the other eight of the Class_1 or ciass_3 devices. The basic features of the "start" command are: gossip 7 • clock spin up or sync • an interrupt 'which causes the instruction to start with a sequence from the "positive f' (for example, timing in a forward communication protocol) The full difference of violations can be synchronized. A start code can allow for possible selection or general startup. Figure 3A shows a preferred structure for the -instruction command letter, which shows four stages: preamplifier center alignment 3〇2, interrupt coffee, same as 1270822 step 305, and data sampling 306. The circuits and descriptions of each stage of instruction 300 are detailed below; however, the basic principles are presented in summary form. When not in the start mode or at the initial start point, all devices will "listen" to the incoming signal as a start command. It is desirable to consume very little power on the listening sequence, and the power consumption is directly related to the battery life (and therefore may also be related to the device life). When a start command is received and processed, the circuit start portion is as much as the completed start command sequence. First, the device receives a preamp center alignment sequence (PreAmp Centering) 302. The center alignment preferably includes a 6 KHz 50% duty cycle waveform number. Again, the use of 6 KHz sound is specific to the preferred approach and does not represent all possible synchronization methods. This center alignment is used to compile all subsequent instructions at this stage. By transmitting the "some numbers" of the pulses, the receiving device (tag) has sufficient time to adjust its sampling threshold, which will allow the receiver to distinguish between logical high and low values (1 and 0). The next program is an interrupt period 304, which preferably includes a 2 KHz 50% duty cycle waveform. By observing the interrupt period, the receiver (tag) will know that it has received a well-formed "start". instruction. The next program is a sync signal 305 which is used to synchronize an adaptive clock circuit (see Figure 11). Here, the clock circuit will wait until the device detects the appropriate interrupt period 304. The clock circuit then uses the sync signal 305 to set the period. In this way, the oscillator 412 8 15 1270822 (see Figure 4) does not need to be constantly operating for proper tuning. The device should then shift its focus to the decoding of the subsequent received block, which is the digital start code (data sample) 3〇6. The digital start code 306 is a 50% duty cycle signal (+Bu 1%) based on an F2F modulation communication protocol, and it allows the transmitter (reader) to select the desired start in the -Class-3 mode. The total number of receivers (labeled), which is presented in 16-bit units, which allows 216 = 65536 possible code values, and the actual number of possible codes is reduced to 彳. The • OOOO(hex) value is used to select all devices regardless of the preprogrammed startup code. Fig. 3B shows another preferred configuration of the -start command signal 〇〇. However, its waveform is simpler. For example, the 'preamplifier center alignment and sync-P knife will no longer be needed. Note that if there is a need for the center of the preamp, it can be displayed as the "mode, as indicated by the ® 3B. This "mode, preferably a series of all 0's, for example 16 〇. Instead of transmitting signals of different symbols (eg 2, 4, 5 • > 8KHZ in Figure 3A), only two symbol signals are used, In this example, the symbols are 2KHZ (logic 1) and 8KHZ (logic 0), and the 2KHZ symbol is also used as an interrupt. Since only two symbols are used, the current circuit can be simplified, in fact, no clock is needed at all. Synchronization. This also reduces the power required, and the same 'operation can be more powerful, because it is easier to distinguish two symbols than four. One of the f costs will not use all possible combinations. Available, and the number of 0 does not meet all possible applications, but enough for 16 8 !27 〇 822 for most use. Another advantage is that the incoming signal can be asynchronous, in other words, by rising At the edge of the clock, the device can read the asynchronous spread of the data. Since the next data signal can immediately follow a shorter period (for example, 8 ΚΗζ symbol), the overall signal will be more time efficient. For example, four Combine a 2 ΚΗζ symbol (single 1) with 8 ΚΗζ marks (four 0s) in the same time period. By using the four-to-one method, there is no need to adapt the shock absorber, eliminating the need to use many additional circuits. Also retains approximately 5〇% of the duty cycle. In operation, ## can be transmitted as a continuous stream. A repeating pattern of 8ΚΗζ streams (combination of 0) or other selected series can be transmitted to allow for concentration The receiving device will listen to an interrupt signal, such as a logic 1 in this embodiment (as shown in [1] of Figure 3). When any logic is encountered, the device will continuously stream incoming data. A stored start command is compared. If the next bit sequence matches the start command, the device wakes up (as described below). If one of the bits in the sequence does not match, the device resets to find the next logic. 1, and start monitoring the bit sequence after the next logic, so, for example, if the third bit is 彳, the device will know that this is not the correct start command, but will reset, and Start listening again for interrupts. In this real snippet, the device is expected to receive the code after the sixth bit (the next "彳" in the sequence). However, the code will not match and the device will reset again. In the implementation of this invention, the user should carefully select the code that does not cause unintentional activation, and does not intend to start the time.

17 • 1270822 Rarely occurs. Please note that the code can be scheduled to avoid unintentional activation of the subscription and designation, which also applies to the previously correctly interrupted bits. Please note that the start command 300 can be transmitted several times to ensure that the code tag is activated. At the same time, several different start commands can be continuously transmitted to initiate multiple tags.

As will be appreciated by those skilled in the art, the following lines will function with the signals described in the reference of Figure 3A. The following devices, when used with one of the signals shown in Figure 3B, do not require certain parts of the device (e.g., voltage controlled oscillators (Fig. 11), clock segments (Fig. 12), data cutters [ Figure 13], DAC [Fig. 14]). The system block diagram of the method for performing the preferred start function is shown in Figure 4. The system shed is found at the front end of the -RF|D tag device, and the incoming L 遽 is received by the antenna 402 and transmitted to A wave-blocking detector, the wave-sealing and measuring device 4〇4 provides a band-pass chopping and amplifying function 35, and the system of the amplification stage & 406 is also set when the phase is adjusted by the clock. The preamplifier "large|^ and 406 gain control has a self-produced circuit (discussed as

B), which allows the circuit to self-adjust the signal threshold to account for any noise in the signal. The following areas of the slave process collect the filtered and amplified signals, and the i test meets the entry information and the start command. In the interrupt circuit 408, the observation into the 1st signal and the interruption period • Φ ^ m4J ratio h ' so that the observed signal conforms to the 雳, η success, an interrupt signal is transmitted to the power oscillating benefit and data cutter Section, disk rm . . 5 Do not have a number to enter the start of the stone horse. During the boost cycle, the oscillating test 4 is used to adjust the vc 〇 (voltage controlled oscillator) 412 from a "preset, value to the desired value during the action. This required value can be stored. In the latch, the VCO is turned off to save power. The data cutter section 414 is used to observe the start command and compare the received value with the stored value of the tag. If the value matches, the tag (device) transmits a "wake up" "Signal and turn the tag into a fully activated state (battery-powered). Subsequent circuits use a "current mirror" which, when checking the function of the current mirror, acts to limit the amount of current consumed in the operation or logic function. 5 shows the use of a current mirror 5〇〇 to create a low power inverter. The current mirror is a device used to regulate the current in an integrated circuit; it remains fixed regardless of the load. The two central transistors 502, 504 A typical inverter is included. By placing a logic voltage or a high voltage at the input, the bottom transistor 504 is placed in the active region and drives the output signal to a logic or low voltage level. If a low voltage (logic 〇) is placed on the input signal, the top transistor 502 will turn on, thus driving the output signal to a high voltage (logic 1). When turning on a transistor and turning off other transistors When switching, there is a problem. When the two transistors are turned on at the same time, it will drive the current to ground. This will be a very large current drop and a large amount of battery power will be used. By adding the main current mirror, the two transistors 5 〇 6, 508 is used to limit the amount of current flowing through the inverter. Figure 6 shows an example of a current mirror 6 依据 according to an embodiment. From Figure 6 'the transistor Q1 is connected, thus having a fixed current flow The actual action is like a forward biased diode, and the current is determined by the resistor R1. It is important to have Ql in the circuit to replace a regular diode because the two transistors Will match, so the two branches of the circuit will have similar characteristics. The second transistor Q2 will change its own impedance, so all the impedance on the second branch of the circuit will be the same as on the first branch. The same resistance, regardless of the load resistance R2. Since the total impedance at each branch is the same and is connected to the same power supply Vs+, the amount of current on each branch is the same. The heart value can be changed to flow through R2 as needed. Since R2 can be changed at any time, and the current flowing through it remains the same, the current mirror is not only a current regulator, but also a fixed current source, which is also the method used in integrated circuits. The first part of the communication protocol is the antenna and wave seal detection sections 402, 404. This circuit 700 is shown in Figure 7. There are several parts on the circuit 700, and two important items come from the antenna 402: first The item is the information presence signal, and the second item is the RF transmission power. The transmission power is processed separately, and then the information (signal) is filtered by a low-pass filter. From this area, the signal is sent to the amplification and Self-biasing circuit 406, as shown in FIG. The first portion of the circuit 406 is a high pass filter which combines the low pass filter of the previous stage to produce a band pass filter. As shown in Figure 9, this bandpass region 900 is approximately 7 kHz and has a 12 db/octivate drop on both sides. This bandpass filter is used to eliminate most of the unwanted noise. The advantage of these two stage amplifiers is that they allow for regulation and self-biasing of the output signal. A signal will enter from the left as shown in Figure 8 and then be filtered by the electric 1276022 container resistor (RC) circuit. It allows filtering of unwanted signals (high pass). Since the feedback configuration allows for self-biasing, the signal then enters the operational amplification design, and background-related noise causes the bias point to move from an optimal position to a point beyond the farther range. Since the signal is a 5〇% duty cycle waveform (50% high and 50% low), the threshold will move to the average and concentrate on the desired bias point. If noise is received, the resistor will bleed some 彳5 saying that 'hunting is 50% of the forced duty cycle, and the DC level will always seek a relay point between the two signals, causing itself to concentrate on the received signal. Regardless of the amount of noise or the strength of the signal, and although the unwanted noise may actually fall within the range allowed by the bandpass filter, the noise will not show the characteristics of a 50% duty cycle waveform, if the waveform is not 5〇%, the bias point will actually move to the appropriate level. If a noise signal is received, so that the amplifier also receives a very unbalanced high voltage non-50% duty cycle, the bias point will move to a lower input voltage (the same argument exists in the opposite case and Lower input voltage). In this embodiment, it displays one of the 5 〇 % duty cycles within the bandpass filter. The "real" signal is presented to the preamplifier input, which can have a different voltage threshold. By allowing several cycles to occur, the 5〇% duty cycle will adjust the bias point, lowering or boosting the voltage level to accommodate the “real” signal as an output against the “noise” signal (background, interference, or other preamplifier) It should be a 1V rms digital "input, to the next segment, which is the interrupt circuit and the start code circuit. At this point, the circuit has assisted in tuning the clock, and the threshold has been Setting. Now, it is necessary to identify an interrupt having a specific low period 21 -1270822 and a specific high period, and if the low period and the high period fall within a predetermined range, the circuit knows to look for the start code. As shown in FIG. 1A, the output of the preamplifier 4〇6 will enter the digital input voltage on the left hand side of the interrupt circuit as shown in FIG. 10, and then it will pass a weak feedback latch 1〇〇2. , it will maintain the digital value until the input changes. The next segment (mirror inverter) 1 〇〇 4 will meet the low and high cycle time and accompany the interrupt cycle, this interrupt cycle will correspond to the previous start command The second parallel segment includes two inverters 〇〇6, 1Q08, 1〇1〇, 1012, which are limited by a high period and a low period delay period of the interrupt interval. The upper half captures or matches the low period of the interrupt pulse, while the lower half captures the high period of the pulse. The two parts of the pattern show a boundary between 12 and 2 ms, which is transparent. Mirror inverters 1〇〇6, 1008, 1010, 1012 are produced. These inverters 1〇〇6, 1〇〇8, 1〇1〇, 1012 mothers all contain a current mirror to limit the current drain Each of the inverters 1006, 1008, 1〇1, and 2 are calibrated for use with a particular delay sequence. An inverter (within each half of the circuit) is tuned to 12 〇ps. The others are tuned to 2 ms so that the delay can be between these intervals. The interrupt interval is formally set to 256, which is the periodic timing between 2 and 120 με; it has -135卟 to + 1 74 ms tolerance pulse interval. The mirror inverters 1006, 1〇〇8, 101〇, 1〇12 are similar to the one shown in Figure 5. However, to complete The long-delay timing required (for example, 2ms) provides several unique features. The width of the 1270822 channel of the P-Side transistor (5〇2 of Figure 5) is minimized (for example, 〇·6μΓΤ1) The channel length of the p-side transistor is extended (for example, 2 〇) to further reduce the current flow. Because the length of the long channel increases the critical value, the current will be slower, making it difficult for the current to turn on the transistor. The transistor will have more capacity due to its size, which will make the signal weaker. To further extend the timing delay, the mirror transistor driven by the mirror voltage (5〇6 and 5〇8 in Figure 5) will increase. The mirror transistor is also asymmetric, and the p-Side mirror transistor has a channel size similar to that of the P side transistor. However, the mirror transistor will be

Set to mV2 1 〇s above the critical value only. Note that the N_s丨• Mirror transistor (508 of Figure 5) is optional because the N_sjde transistor (504 of Figure 5) is a full-scale device and can be switched very quickly. Because the mirror inverter is used as a sequential circuit, it has a very large capacity, and the signal will then be in the wrong area for a long time, that is, a slow ramp. In order to make the edge of the current boundary or filtered signal sharper, half of the output of each of the inverters 1〇〇6, 1〇〇8 in the upper half will enter the mutual exclusion or (XOR) gate 1014. +, then go through several stages of the inverter to reach - pass ~" 〇 18. Each "stage" will sharpen the edges of the signal, amplify and clear the signal to provide _ fast transfer time F represents a fast mirror reverse signal. Please note that Μ represents a mirror inverter. The same process is also true in the lower half of the lower half of the figure. Through several inverters, the high cycle limit then passes through the -x〇R gate 1〇彳6 and reaches the pass gate 1020. The upper and lower passes through the gates 1〇18 and 忉汕2 can be used as the closing so that the n different points are the upper channel; 23 the outer pass gate 1022 to allow a shift register to synchronize the clock and the order. Since the low time will be one half clock cycle ahead of the high time, the low valid signal must be maintained for this extra time to align with the high cycle valid signal. The mutex or gates 1014, 1016 are then used to select the active portion of the interrupt protocol. Since the clock of the active period falls between 12 〇 μ5 and 2 ms cycles, the output of the mirror inverters 1006, 1008 will initiate the output of the xqr gate 1 〇 14 to derive the true result. This signal is sequentially captured by gate 1018 with the correct polarity and is used synchronously as a latch. If the sequence of interrupt agreements is "valid, then the logic (eg, reverse) gate 1 〇 24 output will go low, therefore, an interrupt output signal will be generated, which has five inputs: Four are from the mirror invertor 1〇〇6, 1〇〇8, 1〇1〇, 1〇12 output and an output from the feedback latch 1002. This interrupt output signal is then transmitted to the final block 11〇 〇, as shown in Fig. 11, which is the second half of the starting circuit 4〇〇 shown in Fig. 4. This section includes four separate blocks; a free running pulse 彳2, a voltage control The pulse 412, the data cutting and comparison block 414, and a 6-bit digit to the analog converter 1104. In Fig. 12, the pattern of the clock circuit 12 is shown in Fig. 12, and Fig. 12 is divided into two parts. - is the voltage control clock 412, and the second is the free running clock 1102 'which contains two transistors that are combined to provide a shocker configuration. Due to the nature of the configuration 'it will provide - free The oscillating reference is communicated to the interrupt circuit. The second half of Figure 12 handles the voltage control clock 412. The three basic inputs into the circuit, the first one is the reference voltage, the second is the reset, and the last one is the _ self-correcting self-biased clock input, -1270822 which is used to combine the input data to correct The clock edge is connected to the incoming signal. The frequency control input is from the digital to analog converter 11〇4 and is used to adjust the voltage control clock segment 412. By boosting or lowering the collocation. The speed of the device is variable. This adjustment affects the mirror inverters 1202, 1204 to accelerate or reduce the oscillating speed, and then the output is used as a reference for the data cutting area. Because there is also a need to adjust the clock cycle to correctly The alignment correction enters the data signal, and a self-correcting self-bias input is also used to adjust the edge of the clock. If the logic is placed on this input, it turns on the upper transistor and turns off the lower transistor (input to the mirror) Then, the logic 1 is placed on the clock reference output. The result is that the opposite can also be true. If the logic is placed on this input, the upper transistor will be turned off. Open the lower transistor. This will determine the logic clamp; the pulse reference output. The last input is the interrupt input, which can be used to reset the clock circuit, stop the oscillation and thus save power. In a very similar way 'When a logic 1 is used from a self-correcting self-biased input, the interrupt/reset input is also true. The advantage of this configuration is that the oscillator only needs to operate when the interval is adjusted. Finally, a pass gate is used to adjust the interrupt/reset value (not shown in the figure for clarity). The pass gate function is selected from the self-correcting input or voltage control clock input. The gate is output to the data cutting section as the selection clock. Fig. 13 shows the adaptable data cutting section 414. This area is 414 曰, enters the M stream stream decoding, and then determines the incoming f2F data encoding. Whether the pre-programmed startup code value inside the symbol. The data input is from the amplification and 25 • 1270822 bandpass filter stage block 406 and operates through the pass gate 1302. From the pass gate 1302 from the voltage controlled oscillator timing, the data value is maintained by a weak feedback latch 1304. A counter 1306 is clocked in conjunction with each data input transition at the edge of the clock. This counter 1306 is used to process the 16-bit EEPROM 1308. The counter 1306 is reset from the interrupt portion of the receiving communication protocol. After the interrupt, the counter 1306 begins processing subsequent EEPROM addresses. These EEPROM addresses hold the "boot code" for this device. At each clock interval, a comparison between the incoming data input value and the stored value of the activation code is completed. If there is a non-conformity, the mutex or gate 1310 will set a segment of the 16-bit cumulative register 1312, which will avoid the wake-up signal decision in sequence. If there is no error, the 16-bit cumulative register 1312 has no segment setting, and will determine the match signal, and then further counter limit will be detected when it reaches the end, and when it occurs, it will be determined. Comply with the completion signal. The coincidence completion signal defines the output of either or all of the R gates 1314. If 〇R gate 1314 is asserted, then the output of the wake-up signal is also asserted. Two values may result in a wakeup; a match to store the boot code or a special code, such as all 〇. This devaluation is used in an attempt to match the boot code from any reader. For example, all thresholds can direct all tags in response to all readers, thus providing interoperability of tags in different environments. Note that a special startup code may be a sequence of values other than all 〇, such as all 1, or a second sequence of 〇, may require additional logic and/or memory to identify and/or conform to these other value.

26 1270822 The last section is the digit to analog converter 11〇4 as shown in Figure 14. The basic operation of this region 1104 is to optimize the voltage control clock 4彳2. This is done by the VCO 412 using a fixed "tuning" stored in the RQM 1402, which is done as the initial starting operation. This value is generally set to 24, which will select the weighted or appropriately sized battery. The crystal is supplied with a fixed voltage to the VCO 412. By adjusting the active transistor, the voltage turn is corrected to go up or down. This correction can be done by a 6-bit counter 彳4〇4. During the calibration cycle, the speed of VC〇4彳2 is increased or decreased by turning on or off different combinations of transistors. The clock to the counter is from VCO 412, and the reset of the counter comes from the filtering and amplification stage 406. The operation is amplified and output. This adjustment occurs in the initial stage of the start command. From Figure 3, we find that the first part of the start command is a 6 KHz tuning cycle, which is used for adjustment in counter 1404. The calibration period of the value, and thus the value of the transistor, has been turned on, which will adjust the value of the "Frequency Control" signal in sequence. Figures 15A-B show a preferred embodiment of the interrupt circuit 408 andAn illustrative interrupt command signal 1500. The interrupt circuit 4〇8 detects a start command signal 1500, similar to that shown in Figure 3B. However, in this circuit 4〇8, four (or more) data paths are presented. To detect an "interrupt cluster" 1502 in the incoming signal, wherein the interrupt cluster is a series of symbols recognized by the circuit as an interrupt. Here, the interrupt cluster is a data 1-1. Again, when Upon detection of the appropriate interrupt cluster, the circuit then compares the subsequent received start command 1504 and matches it to the value stored in the device. 12 8 1270822 Regarding the start command signal 1500 shown in Figure 15A, preferably The start command portion 1504 of the 1500^ 1500 does not contain any two consecutive sequences. In a 16-bit code 1504, there are approximately one million possible combinations, and in a 32-bit code 1504, There are about 400 million possible combinations. The first part of the circuit is one of the detectable interrupt clusters. The interval detection circuit 1505. The data path A detects the first rising edge of the interrupt cluster 15〇6, at the delay. time( After 250 and 1 ms), Y represents mirror invertors 1508, 1510 in response to rising edge 彳5〇6. First mirror inverter 1508 will slowly respond to the first rising edge, for example, within 256, and second The inverter will take longer to respond, for example, 1 ms. The two actions combine to produce a negative pulse 1512 (due to the inverter) in response to the positive clock edge 1506. The pulse will go low and For 250μκ] ms, the signal will be clocked through the remaining logic like a shift register after the initial sampling. In this embodiment, the data will be latched by several logic ones, for example The first enabled gate 1514 will drop at 50G with Na_Logic. This signal then passes through additional latches, inverters and registers and finally reaches a logical AND gate. The other latches in data path A will similarly respond to the first latch 1514, except those that are marked with "§," on the falling edge. The body path B function is substantially the same as the data path A, with the exception of The 疋 mirror reverser will respond to the first drop edge 1516, as in the delay time, after the f is not. The other difference is that the data path B has fewer logical parts because it responds to the edge 1516 in time. It will be later. 28 -1270822 is the same in > Feeds C and D. The end result is that the signal from each negative path will arrive at the interrupt gate 1518 (AND gate) at the same time. If the interrupt cluster is correct, then The inputs to the interrupt gate 1518 are all 1 'including the input along line 1520 (as a result of rising edge 彳 522). When all 1 are input to the interrupt gate 1518, the interrupt gate 1518 outputs a pulse. A 5-bit counter 1524 is activated and a latch 1526 is set. At this point, circuit 408 will know to look for a 32-bit enabler code 1504, which can be reset on the rising edge of the clock using a one-cycle detector circuit 1530. Timing 'and a comparison line 1532 for comparing the start command with a pre-stored value. The period detector circuit 153 only cares about the length of the symbol (eg, rising edge to rising edge, or falling edge to falling edge). It is less important to have the correct duty cycle. When the incoming signal is low to high on the rising edge, it will pass through a first inverter 1534 and a second inverter 1538, and the first and third latches 1536 will be turned on at the same time. 1552. The signal is stored on a capacitor 1540 via a first latch 1536, which in turn enters a delay circuit 1542 and is coupled to a P device 1544. The delay circuit 1542 outputs a predetermined time. A pulse, such as 250 μ5, activates transistor 1546 and allows data to be stored in capacitor 1504 to enter a second latch 1548. The second latch 1548 opens at the falling edge and allows the signal to reach NOR gate 1550, where Will be compared with the stored start command. Now go to the comparison circuit, when an interrupt signal from the AND gate 1518 receives 29 1270822, the counter 1524 will start. A memory 1554 storage A predetermined start code is fed from the memory 1554 to the NOR gate 1550 under the control of the counter 1524. Since the counter 1524 and the third latch 1552 are on the same clock signal, the NOR gate can be used with the correct timing. To compare the stored code sequence with the incoming data sequence. If the incoming code matches the stored code, a second AND gate 1560 outputs a start pulse to wake up the tag. Again, as previously described, if the interrupt is met and subsequently When the start command is 0, the circuit also knows to start. As mentioned earlier, in some instances, the tag may have to detect multiple codes, such as a public activation code, a private activation code, a code for a particular category tag or item, and a specific code for the tag. For example, a hierarchical structure can also be used where one code starts all tags in the warehousing, another code initiates the purge replenishment tag, and the third code is specific to each tag. Those skilled in the art will appreciate that there are many options for designers and users when multiple codes are available. In order for a plurality of codes to be usable, portions of the start command comparison portion 1532 of the circuit can be copied (to other code stored in the memory), as will be appreciated by those skilled in the art. At the same time, it should be noted that circuit 408 is self-timer and line 1520 provides a clock signal to counter 1524 which uses the input voltage as the clock signal. Thus, the circuits 408 shown in Figures 10 and 15 are both self-timer circuits (when the clock is not present). Therefore, two methods have been shown to detect an interruption under the clock signal that does not need to be presented. One familiar with the prior art will appreciate that other circuit designs can be used to implement the invention. While the various specific embodiments have been described above, it is to be understood that they are presented Therefore, the scope and scope of a preferred embodiment should not be limited to any specific embodiments described above, but only to the scope of the following claims and their dependents. BRIEF DESCRIPTION OF THE DRAWINGS In order to further understand the nature and advantages of the present invention, and the preferred mode of use, the following detailed description should be read in conjunction with the accompanying drawings. Figure 1 is a system diagram of an RFID system. Figure 2 is a system diagram for performing an integrated circuit (IC) chip within an RFID tag. FIG. 3A is a description of a startup command in accordance with an embodiment. Figure 3B is an illustration of a startup command in accordance with another embodiment. 4 is a startup circuit diagram in accordance with an embodiment. Figure 5 is a circuit diagram of a mirror inverter in accordance with an embodiment. 6 is a circuit diagram of an exemplary current mirror in accordance with an embodiment. Figure 7 is a circuit diagram of an antenna and a wave seal detection section of the start-up circuit of Figure 4, in accordance with an embodiment. Figure 8 is a circuit diagram of a self-biased preamplifier of the startup circuit of Figure 4, in accordance with an embodiment. Figure 9 illustrates the bandpass region of the signal filtered by the high and low pass filters of the startup circuit.

31 1270822 FIG. 10 is an interrupt circuit diagram of the startup circuit of FIG. 4 in accordance with an embodiment. Figure 11 is a circuit diagram of a voltage controlled oscillator and data cutter of the start-up circuit of Figure 4 in accordance with an embodiment. Figure 12 is a circuit diagram of the clock segment of Figure 11 in accordance with an embodiment. Figure 13 is a circuit diagram of the data cutting section of Figure 11 in accordance with an embodiment. Figure 14 is a circuit diagram of a digital to analog converter of the Figure according to an embodiment.

Figure 15A is an illustration of a startup command in accordance with an embodiment. Figure 15B is a circuit diagram of an interrupt circuit of the start-up circuit of Figure 4, in accordance with an embodiment. [Main component symbol description] 100 RFID system 1〇2 tag 104 reader 106 optical server 200 Class-3 chip 202 power generator and adjustment circuit 204 digital command decoder and control circuit 206 detector interface module 208 C1V 2 interface communication protocol circuit 210 power supply (battery) 212 display drive module 214 battery start line 32 8 1270822 216 forward link AM decoder 218 backscatter amplitude modulator block 220 Fowler-Nordheim direct through peroxide device 222 Security Encryption Circuit 300 Startup Command Signal 302 Preamplifier Center Alignment Sequence 304 Interrupt Period 305 Synchronization Signal 306 Digital Activation Code 400 System 402 for Performing a Better Startup Function Method Antenna 404 Wave Seal Detector 406 Preamplifier, Amplification And self-biasing circuit, amplification and bandpass filter stage block, filtering and amplification stage 408 interrupt circuit 410 oscillator tuner 412 voltage control oscillator, voltage control clock 414 data cutting section, data cutting and comparison Section 500 Current Mirror 502 Transistor 504 Transistor 506 Transistor, Mirror Transistor 508 Transistor Mirror transistor 600 Current mirror 700 Circuit 900 Bandpass region 1002 Feedback latch (§) 33 1270822 1004 Mirror inverter 1006 Current mirror inverter 1008 Current mirror inverter 1010 Current mirror inverter 1012 Current mirror reversal 1014 Mutually exclusive or gate 1016 mutually exclusive or gate 1018 through gate 1020 through gate 1022 through gate

1024 Logic Gate 1100 Final Block 1102 Free Running Clock 1104 6-Bit Digit to Analog Converter 1200 Clock Circuit 1202 Mirror Inverter 1204 Mirror Inverter 1302 Pass Gate 1304 Feedback Latch 1306 Counter

1308 16-bit EEPROM 1310 Mutually exclusive or gate 1312 16-bit cumulative register 1314 OR gate

1402 ROM 1404 6-bit counter 1500 interrupt command signal, start command signal 1502 interrupt cluster 1504 start command, start code, capacitor 8 34 -1270822 1505 interval detection circuit 1506 first rising edge 1508 mirror inverter 1510 mirror inverter 1512 Negative pulse 1514 First enable gate, first latch 1516 First drop edge 1518 Break gate (AND gate) 1520 Line 1522 Rising edge

1524 5-bit counter 1526 latch 1530 period detector circuit 1532 compare line, start command compare portion 1534 first inverter 1536 first latch 1538 second inverter 1540 capacitor 1542 delay circuit 1544 P device 1546 transistor 1548 Second Latch 1550 NOR Gate 1552 Third Latch 1554 Memory 1560 Second AND Gate 35

Claims (1)

* 1270822 X. Patent application scope: 1. A battery starting circuit for starting device, the circuit comprising: an interrupt circuit for determining whether an interruption period of one of the received signals meets a predetermined multi-value ' or falls within a predetermined range If the interrupt period meets the predetermined value or falls within the predetermined range, the interrupt circuit outputs an interrupt signal; and a data cutter for comparing the received start code with a stored value, if the received start code is in accordance with the storage Value, the data cutter will send a wake-up signal to activate the device. 2. The circuit of claim 1, wherein the circuit is used in a radio frequency identification (RFID) tag. 3. The circuit of claim 2, further comprising a self-bias amplifier </ RTI> which sets a bias point based on a 5 〇 duty cycle waveform of the center sequence of the preamplifier. V 4. = Circuitry as claimed in item j of the patent application, wherein further steps include a band-of-sense wave machine to exclude unwanted noise from the received signal. 5. The circuit of claim </RTI> wherein the interrupt circuit comprises a logic gate having five inputs. 8. The circuit of claim 1, wherein the interrupt circuit comprises: a first pair of mirror inverters - each of the reverse H is calibrated to provide a different specific delay timing 'first For the mirror inverter side - the low period of the interrupt pulse is between the specific delay timing; a second pair of mirror inverter 'per-inverter is tuned to provide different specific delay timing use' The second pair of mirror inverters will be side-interrupted pulses between the high-cycle ant-specific delay timings; , - the first latch, sampling and storing the wheel from the first pair of mirror inverters. - the second latch , sampling and storing the wheel from the second pair of mirror inverters. 36 8 1270822 one: the latch 'sampling and storing the wheel from the first latch; and the second _ _,, its 7 · as applied When the circuit-to-mirror inverter described in item 6 of the patent scope is between the specific delay timing of the first-off mR:=: wide _ dry-out, then the output of the first job is "started, if The high period of the interrupt pulse is When there is a specific delay between the timings, the two XOR closed rounds will be activated. The circuit of claim 6, further comprising a series of inverters between the first mirror reverser and the third latch. 9. The circuit of claim 6 wherein the step further comprises a series of inverters between the second mirror reverser and the second latch. The circuit of claim 6, wherein the flash lock comprises a pass. 11. The circuit of claim 6 wherein the logic gate also receives an output from a feedback flash lock for storing a value associated with the interrupt pulse. 12. The circuit of claim i, further comprising an adaptive timing circuit to control the data cutter. 13. If the circuit described in the scope of the patent application is further including an adaptive timing circuit for starting and adjusting - the clock of subsequent processing, the round-out value of the adaptive timepiece circuit is stored in -flash In the lock, when the value of the adaptive sequential circuit is stored in the flash lock, the adaptive sequential circuit is turned off. 14. The circuit of claim 2, wherein the received signal is a start command comprising a preamplifier center alignment sequence, an interrupt period, and a start code. 37 8 1270822 15. 1 is used to start the battery of the device, the circuit includes: · a predetermined majority of the predetermined interrupt circuit to determine whether the interrupt cycle of the received signal meets the value 'or The injection cycle meets the predetermined value or the finalization 'interrupt circuit will output-cap health; 1 financial interface _ number, the axis _ sequence circuit Τ enable and __ clock for later processing; and one to adjust Calibration device for school adaptive timing circuits. 16. The circuit of claim 15, further comprising a pair of receiving activation code and a stored value, and if receiving the activation code and the stored value 2Y, the data cutter transmits a wake-up signal to activate the device. . 17. A circuit for identifying an interrupt, the circuit comprising: a first pair of mirror inverters, each of the inverters being tuned for use with a specific delay timing, the first pair of mirrors The comparator measures the low-cycle delay between the interrupt pulses; in the second-pair mirror inverter, each of the inverters is tuned to provide a specific delay Timing uses '帛 二 对 对 对 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Locking, sampling and storing the output from the second pair of mirror inverters; a second latching, sampling and storing the output from the first latch; and a logic gate receiving the second and third flash locks The output, where the output from the logic idle represents the successful identification of an interrupt. 18. The circuit of claim 17, wherein the further step comprises a first -X0R gate between the first-to-mirror inverter and the first-flash lock, and a second pair of mirrors 38. (D • 1270822 :?:= The second X0R is closed between the two flash locks, where if the low cycle of the interrupt pulse = ^ is the timing of the mirror, the first job is 19. = a is activated, If the _ _ _ _ is the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - Implemented in the no-identification (RFID) tag. 2. The circuit described in claim 17 is used as a pass-through. 1. The circuit of claim 17, wherein the logic gate also receives an output from an inverse lock for storing a value associated with the burst pulse. The circuit of claim 17, further comprising a series of inverters between the first pair of mirror inverters and the third flash lock. The circuit of claim 17, further comprising a series of inverters between the second pair of mirror inverters and the second question lock. 24 - a method for starting a device with a circuit, the method comprising: - listening to a start command on the device; Receiving the start command, the start command includes a preamplifier center alignment sequence, an interrupt period, and an activation code; if the interrupted Zhouqihe-predetermined value or falls within the apology, the aging initialization code; and if The activation code matches the stored value in the device and the device is activated. 25. The method of claim 24, wherein the method is implemented as a wireless RID tag. 26. The method of claim 24, wherein the method is executable by a different RFID tag, and upon receipt of a particular activation command, a plurality of tags are activated. 39 8 -1270822 27_ The method of claim 4, wherein the method can be implemented in a green device. 28. The method of claim a, wherein the special activation code directs the device to respond All inquiry settings. 29. The method of claim 24, wherein the device is responsive to a plurality of activation codes. The method of claim 24, wherein the preamplifier center alignment sequence is a 50. % work cycle waveform. 31. The method of claim 24, wherein the interrupt circuit is determined to determine whether the interrupted ant is in conformity or falls within the care, and the circuit package is reversed, each of which The inverters are tuned to provide different specific delays for use, the first pair of mirrors are just reversed—whether the ramp of the interrupt pulse is between the special delay timings; the second pair of mirror inverters, Each inverter is tuned to provide a different specific delay 2 using 'the second pair of mirrors is just back-tested—whether the high period of the interrupt pulse is between a particular delay timing; a first flash lock, sample touch Save the output from the first-to-mirror inverter, · a second _, sample the output from the second _ reverse ;; - the third f- Ι lock' sample and store the round from the first question lock Between the and the logic, the output from the second and third _ is received, which is from the input of the logic-interrupt signal. One uses the soft method described in the 31st patent application scope, in which the logic also receives the output of the anti-language lock from the value of the library accompanying pulse. 32. 33. A method of using a boot code to activate a device, the method comprising: receiving a boot code on the device; comparing the boot code with a pre-stored value; if the boot code meets a pre-stored value, the device is activated; If the boot code does not match the pre-stored value, the device will not be booted. 34. The method of claim 33, wherein the method is implemented as a radio frequency identification (RFID) tag. 35. The method of claim 33, wherein the method is executable by a plurality of RF|D tags, and when a particular start command is received, a plurality of tags are activated. 36. The method of claim 33, wherein the method is performed by a plurality of RHD private tags, the tag being responsive to a plurality of readers when receiving a particular activation code. 37. The method of claim 33, wherein a specific activation code activates all devices. 38. The method of claim 33, wherein a particular activation code bypasses the startup circuit. 39. The method of claim 33, further comprising synchronizing a clock and confirming - indicating an interrupted period of the start command, wherein the start code is received as part of the start command. 40. The method of claim 53, wherein the initiating circuit compares the activation code with a pre-stored value and activates the device if the activation code meets a pre-stored value. 41. The method of claim 33, wherein the activation code is a part of a start command, and the start command further comprises a preamplifier center alignment sequence and an interrupt period 'the start code is not It will be compared to the pre-stored value unless the interruption period falls within a predetermined range. -1270822 42. The method of claim 33, wherein the activation code is received as part of a stream of data symbols, wherein only two symbol signal types are present in the stream of data symbols. . 43. A method of using a boot code to initiate a device, the method comprising: receiving a stream of a symbol; attempting to acknowledge a symbol or combination of symbols as an interrupt; comparing a received symbol after an acknowledged interrupt a sequence and a pre-stored value; if the received symbol sequence after the interrupt meets the pre-stored value, at least a portion of the device is enabled; and - if the received symbol sequence after the interrupt does not conform to the pre- At least some of the devices will not start when the value is stored. 44. The method of claim 43, wherein the method further comprises: stopping the comparison and repeating the method when the determined sequence does not conform to the pre-stored value. 45. The method of claim 43, wherein only two types of symbol signals are present in the stream of data symbols. 46. The method of claim 43, wherein the stream of symbols is asynchronous. #4? The method of claim 46, wherein only two types of symbol signals are present in the stream of data symbols, wherein the first type of the symbol signal has four times the signal of the symbol The duration of the second type. 48. A method of initiating a plurality of selected devices, the method comprising: transmitting a plurality of different activation commands to a remote device, each remote device analyzing the startup command to determine whether the activation command is to be included in the device The activation code of the value in the special find; and if the start code meets the stored value in the device, the device is activated. 42 8 'l27〇822 49. The method of claim 48, further comprising communicating with the activation device at the same time. 5. A method of initiating a plurality of selected devices, the method comprising: receiving a data stream by a sequence of data symbols; detecting a particular symbol cluster from the data stream; wherein the symbol cluster is in a data stream A related data sequence is identified, wherein the symbol contains two or more symbols, wherein the symbol cluster does not appear in the associated data sequence as the φ-identification characteristic of the symbol cluster. The method of claim 50, wherein the symbol cluster is an interruption. The method of claim 50, wherein the symbol cluster initiates an alignment of consecutive data streams. 53. If the method of patent application 帛5〇 is applied, the data sequence of 纟中曙 is a start-up code. 54. The method of claim 5, wherein the symbol in the data stream is based on two symbol types related to a continuous interval basis, wherein the symbol type is _ 疋 another symbol type Continue to rely on the _ part, and its towel has enough difference between the symbols to distinguish one symbol type from another symbol type. 55. A method of encoding data using a duration parameter, the method comprising: generating a data stream of two symbol types related to a duration interval, wherein one of the symbol types is another symbol type One part of the duration, and there is enough difference between the 7 tigers to distinguish one symbol type from another symbol type. 56. The method of claim 55, wherein the partial relationship is an integer. 43 8 1270822 57. The method of claim 55, wherein the partial relationship is not an integer.