TWI437497B - Selective rf device activation - Google Patents

Abstract

Systems and methods for activating one or more devices are disclosed. According to one embodiment, the device listens for an activate code, the activate code having a length field and a mask field, the mask field including a mask value, the length field specifying a length of the mask field to a final bit of the mask value. Upon receiving the activate code, the length field is compared to a stored length value for determining whether the length field meets a predefined criterion. If the length field meets the predefined criterion, an address of the activate value is loaded (if an address field is present) and the appropriate bits (mask value) of the mask field are compared to a stored activate value. An activate signal is generated if the mask value matches the stored activate value. The activate signal can be used to activate additional circuitry including the entire device.

Description

Selective radio frequency component starting system and method

This invention relates to the initiation of radio frequency (RF) tags, and more particularly, the invention relates to the functional activation of RF tags and other electronic RF devices.

Automatic identification ("Auto-ID") technology is used to assist the machine in automatically identifying objects and extracting data. One of the earliest automatic identification techniques is the bar code, which uses an interleaved sequence of widths and narrow stripes to allow an optical scanner to be digitally decoded. This technology is widely used and is nearly universally recognized as a Universal Product Code ("UPC") - a standard managed by a joint industry organization called the Unified Coding Committee. Formally adopted in 1973, UPC is one of the most common symbols of all manufactured goods today, and has been extremely efficient in tracking goods through the manufacture, supply and distribution of various commodities.

However, the bar code still requires an operator to scan each tag item separately using a scanner to complete the manual inquiry. This direct processing has inherent limitations in speed and credibility. In addition, the UPC bar code only allows manufacturers and product type information to be encoded into the bar code without a unique item number. The bar code on a milk carton is identical to any other milk carton, so it is difficult to calculate the number of items or individually check their expiration date.

Currently, cartons are marked with bar code labels. These printed labels have more than 40 "standard" designs, which may cause printing errors, soiling, misplacement and marking errors. These external labels are often damaged or lost during shipping. When accepting objects, the pallets must typically be disassembled and each item box scanned into an enterprise system. The error rate of each ring node in the supply chain is 4-18%, which creates a significant problem of one billion yuan in inventory. Accurate tracking can only be provided by automatically linking the physical layer of the goods to the software application using a Radio Frequency Identification System ("RFID").

The new RFID technology uses a radio frequency ("RF") wireless link and ultra-compact embedded computer chips to overcome these bar code limitations. RFID technology allows actual objects to be identified and tracked via wireless "tags" that function as a bar code that automatically communicates with the reader without the need to manually scan or screen objects. RFID is expected to revolutionize the retail, pharmaceutical, military, and transportation industries.

The advantages of RFID overtaking barcodes are summarized in Table 1:

As shown in FIG. 1, an RFID system 100 includes a tag 102, a reader 104, and a selection server 106. The tag 102 includes an IC chip and an antenna. The IC chip includes a digital decoder that requires execution of the tag 102 to receive computer instructions from the tag reader 104. The IC chip also includes a power supply circuit for extracting and adjusting current from the RF reader; a sensor for decoding the signal from the reader; a backscatter modulator for returning data The transmitter to the reader; an anti-collision protocol circuit; and at least enough memory to store its EPC code.

Communication begins by transmitting a signal from a reader 104 to find the tag 102. When the radio wave touches the tag 102 and the tag acknowledges and responds to the signal from the reader, the reader 104 decodes the data into the tag 102. The information is then transmitted to a server 106 for processing, storage, and/or transmission to another computing device. By tagging different items, you can immediately and automatically learn about the status and location of your products.

Many RFID systems use reflected or "backscattered" radio frequency (RF) waves to transmit information from the tag 102 to the reader 104. Since the passive (category 1 and 2) tags can obtain the required power from the reader signal, the tag will only be powered within the beam of the reader 104.

The Automatic Identification Center EPC-compatible label category is described below: Category 1. Identification tag (RF users can be programmed, up to 3 meters). Lowest cost

Class 2. Memory tag (8-bit to 128M-bit can be programmed, up to 3 meters). Security and privacy protection. low cost

Category 3. Semi-active label. Battery label (256 bits to 64K bits). Self-powered backscatter (internal clock, sensor interface support). 100 meter range. General cost

Class 4. Active label. Active transmission (allows the label to identify the operating mode first). Up to 30,000 meters. higher cost

In an RFID system, where passive receivers (i.e., Class 1 and Class 2 tags) are capable of drawing sufficient energy from the transmitted RF to drive the device, no battery is required. In systems where the distance is such that the device cannot be driven in this manner, an alternate power source is required at this time. For these "alternative" systems (sometimes referred to as active or semi-passive), batteries are the most common type of power supply. It greatly increases the read range and the reliability of tag reading because the tag does not require power from the reader. Compared to a Class 1 tag that requires 500mV operation, the Type 3 tag only requires a 10mV signal from one of the readers to operate. This 2,500:1 reduction in power requirements is only about 3 meters compared to Class 1 labels, allowing Class 3 labels to operate at 100 meters or more.

Early field trials have shown that passive short-distance Class 1 and Class 2 labels currently available are generally not suitable for marking pallets and many types of boxes. The problem with these passive labels is when used on "RF-unsuitable" materials such as metal (eg soup cans), metal foils (eg potato chip bags), or conductive liquids (eg beverages, shampoos, etc.) ), the situation will be particularly serious. No one can continuously read the boxed labels in a pile of boxes - this often happens in a warehouse or pallet. Existing passive tags are also not suitable for marking large or fast moving items such as trucks, cars, and shipping containers.

Class 3 tags solve this problem by adding a range of integrated battery and signal preamplifiers. If the power consumption is well managed, the battery can last for several years, but if the power consumption is poorly managed, it may only be used for a few days. Because battery-powered systems (also known as active devices) coexist with passive devices, care must be taken to reduce power consumption from battery-powered systems. For example, a Type 1 RFID tag receives an operating power source (transmitted power source) from a reader. Class 3 RFID devices define a power source that requires sufficient distance to make it unusable. In addition, Class 3 devices must coexist in Class 1 environments and special care should be taken to manage battery power consumption from all active or semi-active devices. If a Class 3 device continually responds to unwanted Class 1 commands (these commands are for "other" devices), battery power will be exhausted very quickly.

Wake-up codes have been used in RFID systems to selectively "wake up" individual tags rather than other tags, thus saving battery life for unneeded tags and/or reducing the amount of semaphores received from a particular tag group. . Traditionally, the reader propagates a wake-up code, and each tag only needs to initiate a time sufficient to determine whether the code being transmitted matches the code stored in the tag's memory. If the code matches, the label will start completely. If the code does not match, the tag will either return to sleep or not respond further to the reader.

The use of wake-up codes has been shown to be effective in reducing overall battery drain in Class 3 devices. However, it is preferable to be able to remove all tags and receive a propagated wake-up code for analysis to determine whether the wake-up code corresponds to a particular tag. Therefore, it is preferable to add certain types of codes when receiving the wake-up code to indicate early whether to continue analyzing other wake-up code streams.

A system and method for activating one or more devices is disclosed. According to a specific embodiment, the device listens to a startup code having a length bar and a mask bar, the mask bar includes a mask value, and the length column specifies a mask column length to a mask value. One of the final bits. When the activation code is received, the length field is compared to a stored length value to determine if the length field meets the predetermined condition. If the length column meets the predetermined conditions, a start value address will be loaded (if the address field appears) and the appropriate bit (mask value) of the mask bar will be compared with a stored start value, if the mask value is The stored start value matches to generate a start signal that can be used to initiate additional circuitry.

According to another embodiment, the device listens to a startup code having a length bar and a mask bar, the mask bar includes a mask value, and the length column specifies a mask value in the mask bar. The location of the bit. The appropriate bit (mask value) of the mask bar is compared to a stored start value. When the final bit of the comparison mask bar is specified by the length column, the comparison is terminated. If the mask value matches the stored start value, an enable signal is generated that can be used to initiate additional circuitry.

In accordance with another embodiment, a method for activating a device includes receiving an activation code having an address bar and a mask bar, the mask bar having a mask value, wherein the address bar indicates within the mask column One of the mask values begins, and the mask value is compared to a start value stored on the device.

In accordance with another embodiment, a method for analyzing a start code having a length field and a mask bar includes receiving a length field, comparing the length field to a stored length value, and based on the length column and the storage length a result of comparing the values to determine whether the length column meets a predetermined condition; receiving a mask bar having a mask value, and if the length column meets a predetermined condition, the mask value of the mask column is stored The start value is compared and a start signal is generated if the received mask value matches the stored start value.

In accordance with another embodiment, a method for analyzing a boot code having a bitmap bar and a mask bar includes receiving an address and a mask bar, wherein the address bar indicates a location of the mask value in the mask bar . The mask value of the mask bar is compared to a stored start value, and a start signal is generated if the received mask value matches the stored value.

A system comprising an interrogator and a plurality of devices for communicating with an interrogator at a radio frequency, wherein a first branch of the device responds to a start command of a first length and a second leg of the device responds to a second length One of the startup instructions.

According to a specific embodiment, a circuit for selectively generating a start signal includes an interrupt circuit for determining whether an interrupt period of a received signal meets a plurality of predetermined values or falls within a predetermined range, if the interrupt period meets a predetermined schedule If the value falls within the predetermined range, the interrupt line will output an interrupt signal. A data comparison circuit compares a received activation code with a stored start value having a length field and a mask column, the length field specifying at least one of (i) the length of the mask column, and (ii) The final bit position of the mask value of the mask bar. If the received mask value matches the stored start value, the data comparison circuit generates an enable signal.

According to another embodiment, a circuit for analyzing a start code having a length field and a mask bar includes a data register for storing a start value, a length counter for receiving the length field, and a A comparison circuit for comparing at least a portion of the mask column with the startup value. If the mask bar portion meets the startup value, the data comparison circuit generates a start signal.

In accordance with another embodiment, a method of selectively activating a plurality of device sets includes transmitting a start code having a length field and a mask field, wherein the length field indicates which of the plurality of devices is to be processed Mask bar.

A method of selectively initiating a plurality of device sets includes transmitting a plurality of activation codes to a plurality of remote devices, wherein only one of the devices analyzes a particular activation code based on different sizes of the code.

Other features and advantages of the present invention will become apparent from the following detailed description.

The following description is by way of a preferred embodiment of the invention. This description is made to illustrate the general principles of the invention and is not intended to limit the inventive concepts set forth herein.

The following description describes the various systems and methods in which a variety of various boot or "wake-up" codes are used, but not just the wake-up tag, but also indicates which tag set should fully analyze the boot code.

Many types of devices may take advantage of the specific embodiments disclosed herein, including but not limited to radio frequency identification (RFID) systems and other wireless devices/systems; pacemakers; portable electronic devices; audio devices and other electronic devices; Smoke detectors, etc. In order to provide a structure and to assist in understanding the specific embodiments of the present invention, many of the descriptions will be presented in the context of one of the RFID systems of FIG. It should be noted that this is only by way of example, and the invention is not limited to RFID systems. Those skilled in the art will know how to apply the teaching here to the hardware and software of electronic devices. Examples of hardware include application-specific integrated circuits (ASIC), printed circuits, single-rock circuits, and reconfigurable hardware. Body, such as field programmable gate arrays (FPGAs). In addition, the methods disclosed herein can also be integrated into a computer program product, such as a computer-based optical disc containing software. Alternatively, the software can be downloaded or converted from another computing device to another device via a network, non-electrical memory device or the like.

A preferred embodiment of a particular embodiment of the invention is for use in a Class 3 or higher level wafer. In accordance with an illustrative embodiment, FIG. 2 shows a circuit layout of a type 3 wafer 200 that can be implemented in an RFID tag. This Class 3 wafer can form the core of an RFID wafer and is suitable for use in many devices, such as pallets, crates, containers, vehicles, or any identification that requires more than 2-3 meters. As shown, the wafer 200 includes several commercial standard circuits including a power generation and regulation circuit 202, a digital command decode and control circuit 204, a sensor interface module 206, a C1V2 interface protocol circuit 208, and a A power source (battery) 210 can also be added with a display driver module 212 to drive the display.

A battery enable circuit 214 is also shown as a wake-up trigger. The 214 circuit will be detailed below. Briefly, battery enable circuit 214 includes an ultra low power, narrow frequency preamplifier with ultra low power electrostatic current draw. The battery enable circuit 214 also includes a self-timer interrupt circuit and uses an innovative user-programmable digital wake-up code. The battery enable circuit 214 draws less power during its sleep state and can be better protected against accidental and malicious false wake-up trigger conditions that would otherwise cause the Type 3 tag battery 210 to exhaust the remaining power early. .

A battery monitor 215 can be used to provide power usage status within the monitoring device, and the collected information can be used to estimate the remaining useful life of the battery.

A forward coupled AM decoder 216 uses a simplified phase locked loop oscillator that requires a very small area of the chip. Preferably, circuit 216 requires only a minimum string of reference pulses.

A preferred backscatter modulator block 218 is to increase the backscatter modulation depth by more than 50%.

A memory component, such as an EEPROM, is also shown. In a specific embodiment, a pure Fowler-Nordheim direct tunneling oxygen device 220 is shown for simultaneously reducing write and erase currents in the EEPROM memory array. At 0.1μA/battery. Unlike any of the currently newly constructed RFID tags, it allows the design of the tag to operate at its maximum extent, even if the write and erase operations are being performed.

The module 200 can also incorporate a highly simplified, but highly efficient, secure encryption circuit 222, such as the US Patent No. 10/902,683, filed on July 28, 2004, entitled "SECURITY SYSTEM AND METHOD" As described in the application, this is incorporated herein by reference. Other security architectures, secret handshakes with readers, etc., can be used.

The wafer 200 requires only four connection pads (not shown) to function; Vdd is connected to the battery, ground, and two antenna wires to support the multi-element omnidirectional antenna. An inductor that monitors temperature, vibration, and tampering can be added by attaching an industry standard I2C interface to the core chip.

A very low cost Category 2 safety device can be constructed by simply removing or removing the preamplifier and/or removing the IF module from the Class 3 wafer core.

The battery activation circuit 214 described herein uses communication between two devices, one of which wants to transmit or activate a receiving device through a radio frequency (RF) medium. Although circuit use can be added to the RFID system, it does not mean that the industry is limited. A startup circuit is described herein, wherein the preferred description and the specific embodiments are related to RFID, but are in no way limited to the technology. Thus, any system that requires an entity (eg, a transmitter) to alert another entity (eg, a reader) can apply this concept regardless of the medium used (eg, RF, IR, cable, etc.) .

In the category 3 (and higher category) tabs, power management is also facilitated by separating the activated devices to conserve battery power. The selection criteria for starting or turning on the tag power supplies that need to be communicated will be saved as much as possible. When selecting a tag group located in a field, such as a Type 3 mode, the tag can be selectively activated, then accessed, and then returned to its hibernation (or other low power) state, while the next set of tags Can be selectively activated. In order to be able to initiate the selection process, a large number of existing tags are launched at once in the field instead of all the tags in the startup field, providing an optimal power management strategy.

In order to reduce current consumption and increase battery energy life, a starter or "start" command is used. According to a preferred embodiment, the activation command comprises three parts: the first part is clock synchronization, the second part is an interrupt (also called a violation), and the last part is a digital user. Start the instruction code. These three parts conceptually establish a start-up communication protocol. These steps must be combined to adequately separate the "other normal" or common flow from the combination to enable the resolution of other commands or noise from, for example, a Class 1, Class 2, or Class 3 device. Each of these three parts is referred to in Figure 3A of the annex. It should be noted that the number of bits, the number of cycles, the frequency, the position of the memory, etc. may vary depending on the purpose of the following description.

The startup diagrams described herein are also useful in all RF devices with or without a battery, and can be used as a secondary group for selective selection of individual or specific devices.

The basic feature of the "start" command 300 is one: Clock acceleration or synchronization area 302; An interrupt 304 can cause a synchronization instruction to be sufficiently different at the beginning to distinguish it from a "normal" instruction (eg, a clock violation in a forward communication protocol, or a bit that is considered by the device as an interrupt) "cluster"); A startup code 306 can allow for potential selection, all branching, or collective startup.

The circuit diagram and description of each stage of instruction 300 will be detailed below; however, the basic principles will now be presented in summary form.

When starting together, or in the non-start mode, all devices "listen" to the incoming signal of the start command. It is best to consume very little power when listening to the start command. Power consumption is directly related to battery life (and therefore may affect device life). When the start command is accepted and processed, part of the circuit is started and more sequences of start instructions are completed.

The clock synchronization region 302 of the start command 300 preferably includes a clock synchronization signal having an incoming frequency, such as 8 kHz. A sufficient clock cycle is required to allow the tag to be received to confirm and synchronize the incoming stream. The number of clocks entering the tag is preferably more than 4 cycles and less than 10 cycles, but may be more or less.

The next area is the interrupt or violation area 304, which preferably includes a two cycle of 50% duty cycle based on a 2 KHz entry rate, the interrupt will mark the beginning of the code area, which is the third part of the start command. By observing the interrupt portion 304, the receiver (tag) will know that it has received a "start" command. Correct reception of the interrupt portion 304 moves the tag from hibernation to code search. Preferably, a device (tag) is only maintained for a maximum period of time in the code search state, such as 1-5 ms, preferably 2 ms. If the tag is not moved to the ready or activated state within this time, the tag will automatically revert to hibernation.

The receiving device will hear the interrupt, in this embodiment a logical 1-1 sequence. When any logic 1-1 is encountered, the device will then process the following entry activation code 306. If a value in the next meta-sequence matches a value stored on the local receiving device, the device wakes up (as described below). If one of the elements in the sequence does not match, the device resets, looks for the next interrupt, and begins monitoring the sequence of bits after the next interrupt (here, logic 1-1). It should be noted that one of the logic 1-1 in the boot code portion 306 may cause the device to begin analyzing the incoming bit stream again. However, the code will reset the device again due to non-compliance. Therefore, when implementing this invention, it is possible to select a code that does not require analysis, and the analysis that is not required should be small. It should be noted that the code can be predetermined to avoid unwanted analysis being scheduled and assigned, which can be applied equally to the previous correct interrupt bit.

According to a specific embodiment, the activation code portion 306 can be divided into two parts: the first is to signal or the communication protocol, and the second is the instruction agreement. The signal is preferably described in two different frequencies, where 0 is a 2KHz tone and 1 is an 8KHz tone, and the second tone (others can be described as FQF for frequency, quadruple frequency) describes an instruction. When an internal scratchpad is met, the instruction moves the tag from a hibernation state to an active state (prepared state in the machine state). The start code segment is composed of a number of data streams, such as the packet 306 shown in Figure 3B.

As shown in FIG. 3B, three of the elements are (in the order in which the tags are received) a length 322, an address (optional) 324, and a mask 326. Each component will be detailed below. Again, the specific values used below are for illustrative purposes only and are illustrative of a functional embodiment. Those skilled in the art will appreciate that they can increase or decrease the value or length of the bit according to their personal preferences, and adjust the demand according to the consideration. Therefore, the entire instruction size can be changed. In addition, the length 322 and address 324 locations may be exchanged, ie, the address 324 may be received prior to the length 322, and other changes may include additional fields not shown in FIG. 3B, such as a terminator value (eg, logic 1 - 0-1-0) indicates the end of the length 322 or the address 324 field.

The length column 322 in this example contains 7 bits, and the length column 322 can include a length value, such as from zero to 2 ⁷ (or 128). The length value specifies the length of the mask column 326 from zero to the maximum length of the mask column 326, and therefore the position of the last bit in the mask value in the mask column, in this example, the maximum The mask length is 96 bits and the length field 322 is used together with a user-defined minimum mask length register (MML register) on the receiving device (tag). The MML register controls the minimum value available to the length column 322 at a particular location (e.g., user memory; 0x0000). The minimum mask length register is the minimum of the required bits for pairing the mask from the set starting point. If the value of the length field 322 is less than the MML register, the tag will ignore the other boot code 306 and remain in the hibernation state. If the MML register is set to zero, the length field 322 of the start code 306 must also be set to zero. In one variation, the mask length register can set a maximum or correct value to be compared to the value of the length column 322. In another variation, the length field 322 can indicate the length of the mask value in the mask bar, where the address field 324 indicates where the length begins.

One of the zero values (or other predetermined values) in the length field 322 can be used as a pairing for all devices in the field. A length value greater than the maximum mask length (eg, 96) causes the boot packet to be ignored, and thus the tag will revert to hibernation. If it is a zero-length value, neither the address nor the mask bar will exist, so the zero value of the boot code to a 7-bit field is reduced. If a zero value is found in the length column and the MML register allows a zero value to be used for the length, then all devices may transition from hibernation to startup preparation regardless of the address or mask column. In fact, if a legal zero value is found in the length column, the address and mask fields may not exist.

Address field 324 is optional and is also a 7-bit field in this example. It can be used in conjunction with the mask bar 326 to provide a compensation to 96-bit memory while remaining for use by the mask. If the length is set to 96, it is assumed that the address is a zero compensation, so the address bar will not be observed. If the length value is less than 96, the address can be applied as a compensation to the mask value received in the mask bar 326 to calibrate the data stored in the internal mask register. In other words, the associated mask value in the mask bar 326 will start somewhere instead of the starting point of the mask bar. If the combination of the length column and the address bar causes an overflow (an end value greater than the size of the 96-bit internal mask register), the tag will remain hibernated while ignoring the other incoming activation code 306 and waiting until Receive a new start preamble.

The mask bar is compared to the internal boot mask register, and the length and address are used as the number of bits to compare and start the comparison with the start compensation. The internal boot mask register is located, for example (user memory; 0x30). The receive mask value of the mask bar is compared on a one-bit-to-bit basis. If the bit that receives the mask value conforms to the internal boot mask register, the label is converted from a hibernation state to a boot-prepared state. If there is a flipping situation and the length of the comparison is not used up until the 96th bit of the mask is compared, the tag is interpreted as an error condition, ignoring the other incoming boot packets and maintaining the hibernation mode. This can happen if the address indicates a mask field 90 and the length field indicates a 10-bit mask. Because the mask bar ends at 96 bits, the mask ends when the 6-bit is compared, causing the handler to fail.

In another case, in order to avoid the failure of overturning, the mask can be ring-shaped. If the address and length columns cause overturning, the comparison of the mask bits will be initiated by the first bit of the mask. Come on. This can happen if the address indicates a mask field 90 and the length field indicates a 10-bit mask. Since the mask bar ends at 96 bits, the comparison flips over the end of the mask, so the comparison continues from the first mask bit to the fourth mask bit. Therefore, the comparison is performed in a ring pattern.

It should be noted that after the mask value, the mask bar will also include the "false" bit. Since the portion of the mask bar that needs to be compared with the startup mask register is defined by the length and address area, any extra bits after the portion do not affect the activation of the device, which can be tolerated as Startup codes for different tags have a common length. The activation code can be set at the beginning of the manufacturing process, or during the stylization phase, for example, tag initialization, regardless of the step, the device password can be set to restrict access to a particular function or tag memory location.

Some or all of the components of the boot code: length 322, address 324, and mask 326 may be programmed by the user at any stage during the use of the tag, including the above and post-initialization. Preferably, only the authorized person (including the person, the software, and the machine) can modify the activation code, and the authorization can be determined by presenting the correct password. In addition, the scope of the change may vary from user to user, for example, different passwords may allow for different levels of authorization, from very limited functionality to full access, and the ability to make any changes on the label.

The specific embodiments of the length column values are advantageous by the user as they provide considerable operational flexibility between different industries. For example, in the case of a platform door, where the tag will pass through the reader quickly, a shorter length is required. In the pharmaceutical or financial industry, where privacy and security considerations are important, a longer length provides greater security. Similarly, in a noisy or harsh environment, requiring a shorter code due to noise can result in fewer chances of failing to identify a bit. The longer the transmission, the more chances of being damaged by noise or environmental influences. The user knows the security mode and the environment in which the device is used, and can set the length, address, and/or mask to the most appropriate condition. In addition, these values can be changed as the device passes through a supply chain, thus providing better flexibility. The length, address, and/or mask values can also be locked, requiring a password to change them. Therefore, the specific embodiment of the present invention provides enhanced security, and the tag cannot communicate at all unless the tag is awakened. .

Note that the start command 300 can be transmitted several times to ensure that the code tag is activated, and several different start commands can also be continuously transmitted to launch multiple tags.

One advantage of the start command 300 of Figure 3 is that only two symbol signals are used instead of transmitting various symbol signals (e.g., 2, 4, 5, and 8 KHz). In this example, the symbols are 2KHz (logic 1) and 8KHz (logic 0). This 2KHz symbol is also used for interrupts.

Because only two symbols are used, the circuit diagram is very simple. In fact, there is no need for clock synchronization, which also reduces power requirements. Similarly, the operation will be stronger, and the two symbols will be easier to distinguish between the two symbols. One disadvantage is that not all possible combinations of 0 and 1 can be used. However, the number of combinations that can be used is still quite sufficient for most non-all possible applications.

Another advantage is that the incoming signal can be out of sync. In other words, by the clock falling (or rising) edge, the device can read out-of-sync intermittent timing data. Since the shorter period (for example, the 8KHz symbol) can be immediately connected by the next data signal, the overall signal is more time efficient. For example, four 8KHz symbols (four zeros) fit within the same period of a 2KHz symbol (one single 1). In addition, by using four-to-one, there is no need to automatically adjust the oscillator, which greatly eliminates the need for a large number of additional circuit diagrams, which also saves 50% of the duty cycle.

In operation, signals can be transmitted in a continuous stream. A repeat mode (0) 8 KHz stream, or other selected sequence can be transmitted to allow the device to center the signal.

3C shows the structure of the enable command signal 350 in accordance with another embodiment, showing four regions: preamplifier center 352, interrupt 354, sync 356, and data sample 358.

A preamplifier center sequence (preamplifier centered) 352 is first received by the device. The center preferably includes a number of 6KHz 50% duty cycle waveforms. Again, the use of a 6 KHz tone is specifically for the preferred method, but does not represent all possible synchronization methods. This center is used to interpret all subsequent instructions during this period. By transmitting a "some number" of pulses, the receiving device (tag) has sufficient time to adjust its sampling threshold. This allows the receiver to distinguish between high and low values of logic (1 and zero).

The next sequence is the Interrupt 354. It preferably includes a 2 KHz 50% duty cycle waveform.

The next sequence is a sync signal 356 which is used to synchronize an adjustment timing circuit. The timing circuit is not activated until the device detects the correct interrupt period 354. The timing circuit can then synchronize the signal 356 to set the period. In this way, the device oscillator (if displayed) does not need to be continuously operated so that it can be properly calibrated.

The device should then shift its attention to decoding a subsequent received field, the digital activation code (data sample) 358.

The digital start code 358 is based on a 50% duty cycle signal (+/- 10%) of an F2F adjustment protocol that allows the transmitter (reader) to select which set of receivers (tags) to be in the Type 3 mode. start up. The startup code will be displayed in 7-110 bits. A 16-bit mask column 326 value allows 2 ^{1 6} = 65536 possible code values. Perhaps the actual number of possible codes is minus one; the 0000 (hexadecimal) value is preferably used to select all devices, regardless of the pre-programmed startup code.

Referring to Figure 3A, a well-known prior art will understand that the following circuit diagram will work with a signal.

For example, the signal shown in Figure 3C may require additional device components, such as a VCO, a clock region, a data cutter, and/or a DAC. A device that can process the signal of Figure 3C has been described in the application of U.S. Patent Application Serial No. 11/007,973, filed on Dec. 8, 2004, the patent entitled "Battery Startup Circuit", incorporated herein by reference. reference.

A block diagram of a system 400 for implementing a preferred boot function method is shown in FIG. System 400 will be found at the front end of an RFID tag device (or other device) and the incoming signal will be received by antenna 402 and transmitted to a packet detector 404. Packet detector 404 provides bandpass filtering and amplification. The bias voltage in the amplification phase 406 is also set at the clock tuning phase. The amplification stage 406 preamplifier and gain control can have a self-biasing circuit to allow the circuit to self-adjust the signal threshold to calculate any noise in the signal.

The following areas are responsible for processing the collected filtered and amplified signals and attempting to pair the incoming information into the start command. In the interrupt circuit 408, the observation of the incoming information is compared to the interrupt period to pair the observed signals to the desired interrupt period. If successful, an interrupt signal will be sent to a data comparison area 410 alerting it to an incoming digital activation code. The data comparison area 410 is used to observe the start command and compare the received value with the stored value of the tag. If the values match, the tag (device) will be sent a "wake up" signal to bring the tag to a fully activated state (battery-powered).

Subsequent circuit diagrams use a "current mirror." When viewing the function of a current mirror, it is used to limit the amount of current drawn in an operational or logic function.

Figure 5 shows the use of a current mirror 500 to fabricate a low power inverter. A current mirror is a device used in an integrated circuit to regulate current so that it remains fixed regardless of the load. The central two transistors 502, 504 comprise a typical inverter. By placing logic, or a high voltage on the input, the bottom transistor 504 is placed into the startup region and drives the output signal to a logic 0 or low voltage level. If a low voltage (logic 0) is placed on the input signal, the top transistor 502 will turn on, driving the output signal to a high voltage (logic 1). A problem arises when switching from turning on the transistor and turning off other transistors, that is, the two transistors will start for a while at the same time, driving the current to ground. This is a large current drop and will use a lot of battery power.

By adding the current mirror principle, two additional transistors 506, 508 are used to limit the amount of current through the inverter.

In accordance with a specific embodiment, FIG. 6 shows an exemplary current mirror 600. From FIG. 6, the transistor Q ₁ is connected to a fixed current through and thus has its actual role like a forward biased diode, and the current is determined by the resistor R _1. It is very important to have Q ₁ in the circuit, replacing the general diode, because the two transistors will match, so the two branches of the circuit will have the same characteristics. The second transistor Q ₂ changes its own resistance so that the total resistance of the second branch in the circuit will be the same as the total resistance of the first branch, regardless of the load resistance R ₂ . Since all the resistors are the same in each branch and they are connected to the same supply V _{s +} , the current amount of each branch is the same.

The value of R ₁ can be changed by the amount of current passing through R ₂ , because R ₂ can be changed greatly, and the current through it remains the same, so the current mirror is not only a current regulator but also a fixed power source. It is also how it is used in integrated circuits.

The first portion of the protocol is the antenna and packet detection regions 402, 404, which are shown in FIG.

There are several parts in this circuit 700, two of which are from the antenna 402: the first is the information presence signal, and the second is the RF transmit power, the transmit power is processed separately, and the information (signal) is then The low pass filter filters and the signal is sent from this region to the amplification and self-biasing circuit 408, as shown in FIG.

The first portion of this circuit 406 is a high pass filter that combines with the low pass filter of the previous stage to create a band pass filter. As shown in Figure 9, the bandpass region 900 is approximately 7 kHz and has a 12 db/octivate drop on both sides. The bandpass filter is used to eliminate most unwanted noise.

The advantages of the two-stage amplifier allow for adjustment of the output signal and self-biasing. A signal enters from the left side of Figure 8 and is filtered by a resistive capacitor (RC) circuit. It allows filtering of unwanted signals (Qualcomm). The signal then enters the operational amplification design, allowing self-bias due to feedback settings. Noise associated with the background may cause the bias point to be moved from an optimal position to a point further away from the range. Because the signal is a 50% duty cycle waveform (50% high and 50% low), the threshold is shifted to the average and centered at the desired bias point. If noise is received, the resistor will draw some signals. By forcing the duty cycle to be 50%, the DC level will always seek an intermediate point between the two signals, causing it to automatically center on the received signal regardless of the amount of noise or signal strength. Although the unwanted noise may actually fall within the range allowed by the bandpass filter, the noise does not exhibit a 50% duty cycle waveform. If the waveform is not 50%, the bias point will actually move to the appropriate level.

If a noise signal is received and the amplifier receives a very unbalanced high voltage for a non-50% duty cycle, the bias point will move to a higher input voltage (the same dispute will exist in the opposite condition and a lower input) When the voltage is). In this case, one of the "actual" signals that exhibit a 50% duty cycle within the bandpass filter is presented to the preamplifier input, which may have different voltage thresholds. By allowing several cycles to occur, the 50% duty cycle will adjust the bias point, down or boost the voltage level to adjust the "real" signal to the opposite of the "noise" signal (background, interference or otherwise). The output of this preamplifier should be a 1V rms digital "input". These two areas are the interrupt circuit and the start code circuit.

At this point, the threshold has been set and now the interrupt needs to be recognized.

Interrupt circuit 408 in accordance with one embodiment is shown in FIG. The circuit 408 detects an interrupt having a particular low period and a high period. If the low and high periods fall within a predetermined range, the entire circuit 400 will know how to find the boot code.

The output of preamplifier 406 enters the left side of interrupt circuit 408 as shown in FIG. 10 as a digital input voltage. An attenuated feedback latch 1002 is then passed, which maintains the digital value until the input changes. The next region (of the mirror inverter) 1004 will meet the low and high cycle times associated with the interrupt cycle. This interrupt period corresponds to the second region before the start command.

Each of the parallel opposing regions includes two inverters 1006, 1008, 1010, 1012 that are limited by delaying the high and low periods of the interrupt interval. The upper half of the circuit captures or pairs the low period of the interrupt pulse, while the lower half captures the high period of the pulse. Both parts of the diagram show a 120μs and a 2ms limit to the signal. This occurs through the matching mirror inverters 1006, 1008, 1010, 1012. These inverters 1006, 1008, 1010, 1012 each include a current mirror to limit current draw. Each of these inverters 1006, 1008, 1010, 1012 will be "tuned" for use with a particular delay. One inverter (in each half of the circuit) is tuned for 120μ use, while the others are tuned for 2ms, which allows for delayed pairing between these intervals. The interrupt interval is typically set to 256μ, which is one cycle between 2ms and 120μs; a pulse interval of 256μs with a tolerance of -135μ to +1.74ms.

The mirror inverters 1006, 1008, 1010, 1012 are mirror inverters similar to those shown in FIG. However, to achieve the required long delay timing (eg, 2ms), several unique features are required, and the channel width of the P-side transistor (502 of Figure 5) is minimized (eg, 0.6 μm). The channel length of the P-side transistor is extended (eg, 20 μm) to further reduce the current passed therethrough. This current will be even slower because the long channel length will increase the critical value, making it more difficult to turn on the transistor. In addition, due to the size of the transistor, it is more bulky, resulting in a slower signal. To further extend the timing delay, the mirror transistor (506 and 508 of Figure 5) is added, which is driven by the mirror voltage. The mirror transistor is also asymmetrical, and the P-side mirror transistor has a channel size similar to that of a P-side transistor. However, the P-side mirror transistor will be set to only 10s above the threshold mV. Note that the N-side mirror transistor (508 of Figure 5) is optional because the N-side transistor (504 of Figure 5) is a full-scale device and converts quickly.

Because the mirror inverters are used as timing circuits, they have a very large capacity, and the signal will therefore be in the wrong area for a long time, that is, very slow to jump, to deepen the limit or filter the edge of the signal, in the upper half The output of each inverter 1006, 1008 enters a mutually exclusive or (XOR) gate 1014 and then passes through the stages of several inverters to reach a pass gate 1018. Each "stage" will deepen the edges of the signal, amplify and clean the signal to provide a signal that can quickly convert time. Note that an M represents a mirror inverter and an F represents a fast mirror inverter.

The bottom half of the figure is the same process that is really used to handle high cycles. The high cycle boundary then passes through an XOR gate 1016 again, through a number of inverters and to a pass gate 1020. Both the upper and lower half of the through gates 1018, 1020 are used as latches. One difference is that the upper half of the channel has an additional pass 1022 to allow a conversion register to be close to the synchronization timing and sequence. Since the low time will be about half a clock cycle before the high time, the low active signal must be maintained during this additional time to align with the high cycle effective signal. The dedicated OR gates 1014, 1016 are used to select the start portion of the interrupt protocol. Since the timing of the active period will fall between 120μs and 2ms, the output of the mirror inverters 1006, 1008 will initiate the output of the XOR gate 1014 to drive it accurate. The signal is captured in sequence with the correct polarity by the switch 1018 as a synchronized latch. If the sequence of interrupt agreements is "active", then the output of the logic (e.g., NAND) gate 1024 will go low, so an interrupt output will be signaled to have occurred. Logic gate 1024 has five inputs: four from the outputs of mirror inverters 1006, 1008, 1010, 1012 and one from the output of feedback latch 1002.

11A-B show another illustrative embodiment of interrupt circuit 408. The interrupt circuit 408 detects a start command signal similar to that shown in Figure 3A. In this circuit 408, four (or more) data paths are displayed to detect an "interrupt cluster" in the incoming signal, wherein the interrupt cluster is a series of symbols that the circuit recognizes as an interrupt. Here, in FIG. 3A, the interrupt cluster is a material 1-1. Once again, once the appropriate interrupt cluster is detected, the circuit then compares the subsequent received start commands and compares them with a value stored in the device.

Regarding the start command signal 1100 shown in FIG. 11A, it is preferable that the start designation portion 1104 of the signal 1100 does not contain any sequence of two consecutive ones. In a 16-bit code 1104, there may be approximately one million combinations. In a 32-bit code 1104, there may be approximately 4 billion combinations. In a 110-bit code 1104, there may be approximately hundreds. Billions of combinations. The result is that there should be enough possible bit combinations, but no consecutive ones are available for most or all of the possible start instructions 1100.

The first part of the circuit is an interval detection circuit 1105 for detecting interrupt clusters. Data path A detects the first rising edge 1106 of the interrupted cluster. The "r" after the delay time (250 μs and 1 ms) represents the mirror inverter 1108, which responds to the rising edge 1106.

The first mirror reflector 1108 will slowly respond to the first rising edge, for example, at 256 [mu]s. The second inverter responds with a longer time, for example 1 ms. These two actions together produce a negative pulse 1112 (due to the inverter) in response to the positive clock edge 1106. The pulse will go low for 250μs to 1ms, and once the information begins to be sampled, it will be clocked as if it were a conversion register through the rest of the logic. In this particular embodiment, the data will pass through a number of logical latches, for example, the first enable gate 1114 will fall at 500 μs to capture a logic one. The signal then passes through additional latches, inverters, and registers to finally reach a logical AND gate. The other latches in the data path A will likewise respond to the first latch 1114, except those on the falling edge. Capture the data.

The data path B operates substantially the same as the data path A method, with the exception being the mirror inverter responding to the first falling edge 1116, which is represented by "f" after the delay time. Another difference is that data path B has fewer logical elements because the edge 1116 it responds will be later in time.

This is also true for paths C and D. The end result is that the signal from each data path will arrive at interrupt gate 1118 (AND gate) at the same time.

If interrupt clustering is appropriate, all inputs to interrupt gate 1118 are 1, including inputs along line 1120 (due to rising edge 1122). When all of the 1s are input to the interrupt gate 1118, the interrupt gate 1118 outputs an interrupt signal.

It should also be noted that circuit 408 is self-timed. Line 1120 provides a timing signal to counter 1524 which uses the input voltage as the timing signal.

Therefore, the two circuits 408 shown in Figures 10 and 11 are self-timer circuits (due to no display timing). Therefore, two methods of detecting an interruption without displaying a time signal are displayed. Those skilled in the art will appreciate that other circuit designs can be used to implement various specific embodiments.

The interrupt output signal is then transmitted to block 1200 shown in FIG. 12, which is part of the data comparison area 410 shown in FIG. In block 1200, the entry enabler code is compared to a reference value ("start value") stored in a data buffer or other memory of the host device, and if the entry value matches the stored boot value, A start signal is generated.

As described above, the length information of the activation code (Fig. 3B) will arrive first, and the data will be clocked into the length counter 1202. If the length value is not 0, the address will be clocked into the address counter 1204. Circuit 1200 will now pre-predict the start value stored in data register 1206 to be compared to the mask bit. The storage bits from data register 1206 are selected for comparison by address counter 1204. In this example, comparator 1207 is a simple mutually exclusive-or (XOR) function (or prior art for comparing bits). The other suitable logic function is between the incoming data bit and the bit selected by the address counter 1204 through the 96x1 multiplexer (MUX) 1208. If the length counter 1202 has been counted down to zero and there is no alignment error, a start signal will be generated and the device will be activated. If a comparison error is detected, circuit 1200 will be reset. In a usage paradigm, the address bar value may indicate that the circuit begins to compare at bit 15 of the mask, and the length column may stop comparing at bit 60. The device will only change the power state if the mask bit 15-60 matches the stored start value.

One advantage of this design is that the data does not need to be stored anywhere or converted, but the address counter 1204 is stylized with values from the address bar. Data from the internal scratchpad will be transmitted one bit at a time and compared to the data received in the incoming. This removes the need for a 96-bit conversion register for incoming data.

The data comparison area 410 (Fig. 4) can also know how to start, if the interrupts match and the subsequent start command is a sequence of all zeros. It should be noted that a particular start code may be a sequence that is not all zeros, such as all 1, or a second sequence of ones and zeros. Additional logic and/or memory may be required to identify and/or align these other values, as will be appreciated by those skilled in the art.

In some instances, the tag may have to detect multiple codes, such as a public activation code, a private activation code, a code for a particular tag or item type, and a code specifying the tag. For example, a hierarchical structure can also be used where one code will initiate all tags in the warehousing, another code can initiate a cleaning supply tag, and a third code is assigned to each tag. Those skilled in the art will appreciate that when multiple codes are available, there are many options available to the designer and the user.

To be able to use multiple codes, a portion of the data comparison portion 410 of the circuit can be copied (for other codes stored in memory), as will be appreciated by those skilled in the art. 13 shows an example 1300 that includes the elements of FIG. 12, and a second address counter 1304, a second multiplexer 1308, a second mutex or device 1306, and a second data register 1302. Only one length counter 1202 is needed, however it can be copied. The incoming data will be analyzed and the mask will be compared to two stored boot codes, one from each code register 1206, 1302. If the entry code matches one of the stored values, a start command can be generated. It should be noted that in a relatively simple variation, a single address counter 1204 can simultaneously drive a multiplexer and other display devices.

Figure 14 shows a method 1400 for activating a device in accordance with an embodiment. In operation step 1402, the device will listen to a boot code. Preferably, the device will periodically listen to the boot code. However, since the power capture is minimal, it is preferable to continuously monitor. Once the activation code is received at operation 1404, the length field is compared to a stored length value at operation 1406 to determine if the length field meets a predetermined condition. If the length column meets the predetermined condition, an activation value address will be loaded in operation step 1408 (if the address field is displayed), and the appropriate bit (mask value) of the mask bar will be in operation step 1410 and Store the startup values for comparison. When the last bit of the comparison mask bar is specified by the length field, the comparison is terminated at operation 1412. If the mask value matches the stored boot value, an enable signal is generated at operation 1414, which may be used to initiate additional circuitry at operation 1416.

Example 1

In a retail store, an RFID tag reader is placed near the store exit. The field length is set to 0, so all tags will respond when in the range of a reader. Therefore, the reader will continue to transmit 0. If a tag responds, a security alert is initiated.

Example 2

In a retail store, a tagged item is located on the shelf and needs to reduce battery drain and avoid unauthorized access to the tag. The length value will be set to a number greater than 0. Different labels may have different lengths or different startup codes.

Example 3

In a supply chain, both the length bar and the mask bar are set small (eg, mask value length < 16 bits) and no address compensation enables fast identification of RFID tags. When entering a pharmacy, the tag is stylized with a number of bit masks (eg, mask value length > 64 bits) and the address bar is set to provide a 12-bit compensation. The length column of the result will have a value of 86 bits.

Example 4

In a warehousing, the minimum length value of the RFID tag stored in group A is set to 16 bits. The stored minimum length value of the RFID tag in group B is set to 32 bits. A start command will be transmitted with a 12-bit length column value, and no group response in group A or group B. A start command will be transmitted with a length field of 20 bits. The label in group A will analyze the startup code, while the label in group B will not. A start command will be transmitted with a length field of 40 bits. The tags in group A and group will analyze the activation code.

Example 5

In a supply chain, when a device (eg, an RFID tag) passes through the supply chain, different users (including entities and/or systems) will use different activation codes (or portions thereof). Authorized users at different stages of the supply chain will change the activation code by sending a password or the like. The device will now only respond to a specific activation code (otherwise it will remain asleep). When the device moves to another stage, subsequent users will receive the activation code from the previous user, and may include the password if the subsequent user has not yet obtained the password.

Although the specific embodiments have been described above, it should be understood that they are presented by way of example only and not limitation. Therefore, the breadth and scope of the preferred embodiments are not to be construed as limited

100. . . Radio frequency identification system

102. . . label

104. . . Reader

106. . . server

200. . . Wafer

202. . . Power generator and regulating circuit

204. . . Digital instruction decoding and control circuit

206. . . Sensor interface module

208. . . C1V2 interface agreement circuit

210. . . Power supply (battery)

212. . . Display driver module

214. . . Battery start circuit

215. . . Battery monitor

216. . . Forward link AM decoder

218. . . Backscatter modulator block

220. . . Fowler-Nordheim direct tunneling oxygen device

222. . . Secure encryption circuit

300. . . Start command

302. . . Clock acceleration or synchronization area

304. . . Interrupt

306. . . Startup code

306. . . Packet

322. . . length

324. . . Address

326. . . Mask

350. . . Start command signal

352. . . Preamplifier centered

354. . . Interrupt

356. . . Synchronization signal

358. . . Data sampling, digital start code

400. . . system

402. . . antenna

404. . . Packet detector

406. . . Magnification stage

408. . . Interrupt circuit, amplification and self-bias circuit

410. . . Data comparison area

500. . . Current mirror

502. . . Top transistor

504. . . Bottom transistor

506. . . Transistor

508. . . Transistor

600. . . Current mirror

700. . . Circuit

900. . . Band pass area

1002. . . Feedback latch

1004. . . Area of (mirror inverter)

1006. . . inverter

1008. . . inverter

1010. . . inverter

1012. . . inverter

1014. . . Mutual exclusion or gate

1016. . . XOR gate / mutual exclusion gate

1018. . . Switch

1020. . . Switch

1022. . . Additional pass

1024. . . Logic gate

1100. . . Start command signal

1102. . . Interrupt cluster

1104. . . The specified part of the start of the signal

1105. . . Interrupt the first rising edge of the cluster

1106. . . Interval detection circuit

1108. . . Mirror inverter

1110. . . Mirror inverter

1112. . . Negative pulse

1114. . . First enable gate

1116. . . First falling edge

1118. . . Interrupt gate

1120. . . line

1122. . . Rising edge

1200. . . Block

1202. . . Length counter

1204. . . Address counter, first address counter

1206. . . Data register, first data register

1207. . . Comparators

1208. . . Multiplexer, first multiplexer

1300. . . Block

1302. . . Second data register

1304. . . Second address counter

1306. . . Second mutual exclusion or device

1308. . . Second multiplexer

1400. . . method

1402. . . Steps

1404. . . Steps

1406. . . Steps

1408. . . Steps

1410. . . Steps

1412. . . Steps

1414. . . Steps

1416. . . Steps

1524. . . counter

In order to more fully understand the nature and advantages of the invention, and the preferred mode of use, the following detailed description should be taken in conjunction with the drawings.

Figure 1 is a system diagram of a radio frequency identification system.

2 is a system diagram for implementing an integrated circuit (IC) chip in an RFID tag.

3A is a diagrammatic illustration of a start command in accordance with an embodiment.

Figure 3B is a diagrammatic illustration of one of the activation codes in accordance with an embodiment.

Figure 3C is a diagrammatic illustration of a start command in accordance with another embodiment.

4 is a diagram of a start line in accordance with an embodiment.

Figure 5 is a circuit diagram of a mirror inverter in accordance with an embodiment.

6 is a circuit diagram of an exemplary current mirror in accordance with an embodiment.

7 is a circuit diagram of an antenna and packet detector portion of the startup circuit of FIG. 4 in accordance with an embodiment.

8 is a circuit diagram of a self-biased preamplifier of a start-up circuit of FIG. 4 in accordance with an embodiment.

Figure 9 illustrates a bandpass region for filtering signals by a high pass and low pass filter of the enable circuit.

10 is a circuit diagram of an interrupt circuit of the startup circuit of FIG. 4 in accordance with an embodiment.

Figure 11A is a diagrammatic illustration of a start command in accordance with one embodiment.

Figure 11B is a circuit diagram of the interrupt circuit of the start line of Figure 4 in accordance with an embodiment.

Figure 12 is a circuit diagram of a comparison circuit for comparing a start command with a stored value.

Figure 13 is a circuit diagram of a comparison circuit for comparing a start command with a multiple stored value.

14 is a flow chart of a method for activating a device, in accordance with an embodiment.

100. . . Radio frequency identification system

102. . . label

104. . . Reader

106. . . server

Claims (22)

A method for starting a selective radio frequency component, comprising: listening to a startup code; receiving a startup code, the activation code having a length column and a mask bar following the length column, the mask column including a mask value, and The length column includes a length value that specifies the length of a mask column to a specific number of bits of the final bit of a mask value, in other words, specifies the final bit of the mask value in the mask column. The position of the element; comparing the length value in a length column with a stored length value to determine whether the length column meets a predetermined condition; when the decision length column meets the predetermined condition, the mask value in the mask column is stored with a The startup value is compared; and when it is determined that the mask value meets the stored startup value, an additional circuit is activated; if the mask value is determined not to meet the stored startup value, the sleep state is maintained; wherein the predetermined condition is The length value in the length column is greater than or less than the stored length value; wherein the start code has an interrupt signal, further comprising detecting the interrupt signal, and executing the method when the interrupt signal is detected Wherein upon receiving the start code, start the mask value of the mask and the storage of the column lines in one yuan one yuan Comparative manner; and Wherein at least one field of the activation code is programmable, wherein authorization must be obtained prior to stylizing the at least one field. The method of claim 1, wherein the predetermined condition is that the length value of the length column is greater than the stored length value. The method of claim 1, wherein the predetermined condition is that the length value of the length column is not greater than the stored length value. The method of claim 1, wherein if the length column does not meet the predetermined condition, the mask value is not compared to the stored startup value, wherein the additional circuit is not activated. The method of claim 1, wherein the activation code further comprises a location bar, and the address bar is received before the mask bar, the address bar indicating the start command The starting position of the mask value in the mask bar. The method of claim 5, wherein the mask column is a predetermined length, and when the stored startup value is compared with the mask value, if the length column is deviated from the address column, Then this method will fail. The method of claim 5, wherein the mask column is an annular mask, and if the length column is deviated from the address column, the stored starting value is in a ring pattern and a mask. The bits in the column are compared. The method of claim 1, wherein the device is a radio frequency identification (RFID) tag, wherein a specific number of bits specifying a final bit of the mask value is the mask in the mask column The number of bit positions in the final bit of the value. The method of claim 8, wherein the RFID tag is a passive tag. The method of claim 8, wherein the RFID tag is an active tag. The method of claim 1, wherein the method is performed by a plurality of RFID tags, and only a part of the tags will receive the mask in the mask column when receiving a specific activation code. The cover value is compared to a stored start value. A selective radio frequency component activation system comprising: a plurality of RFID tags configured to perform the method of claim 1; and an RFID interrogator communicable with the RFID tags. The method of claim 1, wherein the activation code is preceded by a clock synchronization signal. The method of claim 1, further comprising changing the stored field value for subsequent communication. The method of claim 1, further comprising changing the stored value of the store for subsequent communication. The method of claim 1, wherein the authorization comprises a password verification. The method of claim 1, further comprising comparing the comparison when the final bit of the mask column is specified by the length column. The method of claim 1, further comprising maintaining a sleep state when the length column does not meet the predetermined condition. The method of claim 1, wherein the length column has a length value at least equal to one of: (i) a first bit from the length column to a bit of the final bit of the mask value. The number, (ii) the number of bits from the first bit of the mask bar to the last bit of the mask value. The method of claim 1, wherein the predetermined condition is that the number of specific bits defined by the length value of the length column specifies a number greater than or less than the stored length value. A radio frequency identification (RFID) tag comprising a circuit configured to perform the method of claim 1 and a memory for storing the stored activation value. The method of claim 1, wherein at least one field of the activation code is programmable, wherein authorization is required to prioritize the at least one field.