TWI270161B - Boat, batch type apparatus and wafer handling process using the boat - Google Patents

Boat, batch type apparatus and wafer handling process using the boat Download PDF

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Publication number
TWI270161B
TWI270161B TW92125464A TW92125464A TWI270161B TW I270161 B TWI270161 B TW I270161B TW 92125464 A TW92125464 A TW 92125464A TW 92125464 A TW92125464 A TW 92125464A TW I270161 B TWI270161 B TW I270161B
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Taiwan
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wafer
wafers
boat
slots
batch processing
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TW92125464A
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Chinese (zh)
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TW200512860A (en
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Huan-Shun Lin
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Promos Technologies Inc
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Abstract

A boat for a batch type apparatus is provided. A plurality of wafer slot is configured at the boat between a first end and a second end of the boat. The plurality of wafers are paralleled each other with their surface by putting them into the wafer slots. These spaces of the wafer slots are increased gradually from the first end to the second end of the boat. The boat can be configured in a vertical furnace. The first end of the boat is configured on the bottom of the furnace, and the second end of the boat is located on the top of the furnace. When the vertical furnace with the boat is used to perform a wafer handling process, the difference of electrical parameters and film's characteristics of the wafers in the same process can be reduced.

Description

12701611270161

發明所屬之拮術領域 本發明是有關於一種半導體裝置及製程,且特別是有 關於一種晶舟及使用此晶舟之批式處理(batch typ 及晶圓處理製程。 先前技術 爐管式反應器係為一種批式處理裝置,因此可以一次 ,大,的晶圓進行處理,其中爐管式反應器可應用於化學 氣相沉積(Chemical Vapor Deposition,CVD)製程與摻雜 (Doping)製程。在化學氣相沉積製程的應用上,主於 多晶矽、氧化矽以及氮化矽等材料的沈積,至於在摻雜製 程的應用上,例如是可以應用於金氧半電晶體之閘極多晶 石夕層的摻質預置等。爐管式反應器主要可分為水平式與垂 直式等兩種方式,由於垂直式爐管(Vertical Furnace)所 需之整體體積較小,因此在使用上已漸漸取代傳統水平式 爐管化學氣相沉積法,成為產業界中的主流。 第1圖係繪示習知一種垂直式爐管設備之剖面圖。請 參照第1圖,垂直式爐管設備至少包括升降底座〗〇 〇、爐管 102、氣體入口 1〇6、晶舟11〇、加熱裝置、加熱裝置 Z2、加熱裝置Z3、加熱裝置Z4以及加熱裝置Z5。爐管1〇2 的升降底座1 0 0上係配置有晶舟11 〇,且晶舟11 〇上具有多 個晶圓插槽(wafer slot),用以將晶圓水平地配置在晶舟 11 0上,且此些晶圓插槽係為等間距並可使配置於其中之 晶圓1 0 8的表面互相平行。而氣體入口 1 〇 6係配置在爐管 102的底部112,且加熱裝置Z1〜Z5係配置在爐管1〇2的外FIELD OF THE INVENTION The present invention relates to a semiconductor device and process, and more particularly to a wafer boat and batch processing using the same (batch typ and wafer processing process. Prior art furnace tube reactor It is a batch processing device, so it can be processed in one-time, large, and the furnace tube reactor can be applied to the Chemical Vapor Deposition (CVD) process and the Doping process. In the application of chemical vapor deposition processes, the deposition of materials such as polysilicon, yttrium oxide and tantalum nitride, as for the application of the doping process, for example, can be applied to the gate polycrystal of the MOS transistor. The dosing of the layer is preset, etc. The furnace tube reactor can be mainly divided into two types, horizontal and vertical. Since the vertical furnace tube (Vertical Furnace) requires a small overall volume, it has gradually been used. It replaces the traditional horizontal tube chemical vapor deposition method and becomes the mainstream in the industry. The first figure shows a cross-sectional view of a vertical furnace tube equipment. Please refer to Figure 1 The furnace tube equipment includes at least a lifting base 〇〇, a furnace tube 102, a gas inlet 1〇6, a boat 11〇, a heating device, a heating device Z2, a heating device Z3, a heating device Z4, and a heating device Z5. The lifting base 110 of the 2 is equipped with a boat 11 〇, and the wafer boat 11 has a plurality of wafer slots for horizontally arranging the wafer on the boat 110, and The wafer slots are equally spaced and the surfaces of the wafers 108 disposed therein are parallel to each other. The gas inlets 1 and 6 are disposed at the bottom 112 of the furnace tube 102, and the heating devices Z1 to Z5 are Arranged outside the furnace tube 1〇2

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1270161 五、發明說明(2) 壁,用以提供製程中爐管102内所需要的熱能。而製程中 所使用的反應氣體係由氣體入口 1 〇 6由底部11 2朝向頂部 114的注入至爐管1〇2内,以使反應氣體由爐管1〇2的底部 11 2流動、擴散至爐管丨〇2的中段部與頂部11 4,並流經過 晶圓108的表面。 在上述製程中,由於爐管102内的壓力不高,所以爐 管102中段部與頂部114的反應氣體濃度會遠少於在爐管 I 0 2底部11 2的反應氣體濃度,以致於愈往爐管1 〇 2的頂部 II 4,其沉積於晶圓1 〇 8上之薄膜的沉積速率愈低,因而造1270161 V. INSTRUCTIONS (2) Walls are used to provide the heat energy required in the furnace tube 102 in the process. The reaction gas system used in the process is injected into the furnace tube 1〇2 from the bottom portion 11 2 toward the top portion 114 from the gas inlet 1 〇 6 so that the reaction gas flows and diffuses from the bottom portion 11 2 of the furnace tube 1〇2 to The middle portion of the furnace tube 2 and the top portion 11 4 flow through the surface of the wafer 108. In the above process, since the pressure in the furnace tube 102 is not high, the concentration of the reaction gas in the middle portion and the top portion 114 of the furnace tube 102 is much smaller than the concentration of the reaction gas at the bottom portion 11 of the furnace tube I 0 2, so that the The lower the deposition rate of the film deposited on the wafer 1 〇8 at the top II 4 of the furnace tube 1 〇2, thus

成同批處理的晶圓1 〇 8沉積薄膜厚度不均的問題。習知^ 決晶圓與晶圓間厚度不均的方法,係藉由調整加熱袭置冗 〜Z5的功率’使加熱裝置Z1〜Z5所提供之熱能由:^ 1 Z5在加熱裝置Z1遞增’以提南爐官102内頂部114斑中^ 的溫度,進而增加薄膜在晶圓1 08表面上的沉積速率,又部 使同批處理的晶圓得到良好的膜厚均勻度。 …’以 題可以藉由調整不同位置 ,上述的晶圓處理製程仍 雖然晶圓之膜厚均勻度的問 之加熱裝置的溫度以克服,然而 存在著某些問題: 以在晶圓表 叫一〜识幼〜/〜衣枉马例,上述The problem of uneven thickness of deposited film 1 〇 8 deposited in the same batch. The method of determining the thickness unevenness between the wafer and the wafer is to adjust the heating power to the power of the Z5 to make the heat energy provided by the heating devices Z1 to Z5: ^ 1 Z5 is incremented in the heating device Z1' The temperature of the top 114 spot in the interior of the cooker 102 increases the deposition rate of the film on the surface of the wafer 108, which in turn gives the wafer of the same batch a good film thickness uniformity. ...the problem can be overcome by adjusting the temperature of the wafer processing process, although the film thickness of the wafer is uniform, but there are some problems: ~ 知幼〜/~衣枉马,, above

會使垂直式爐管内不同位置之晶圓的熱預算不同,耸> 批處理的晶圓間,位於頂部之晶圓與位於^ 二:導1 生相當大的電性差異。 -° 日日圓1 另外,以砷(As)對多晶矽閘極層的摻雜製程 於爐管1 02的底部11 2的反應氣體濃度較爐管的、、'頂例。’由The thermal budget of the wafers in different positions in the vertical furnace tube will be different, and the wafers at the top of the wafer will have a considerable electrical difference between the wafers at the top and the wafers at the top. - ° Japanese Yen 1 In addition, the doping process of arsenic (As) to the polysilicon gate layer is at the bottom of the furnace tube 102. The concentration of the reaction gas is higher than that of the furnace tube. 'by

1270161 五、發明說明(3) 之反應氣體濃度高,所以晶圓丨〇8上所摻 會由爐管1 0 2底部朝向爐其n ?馆邱、系 ’、 、濃又’ 管102底邱! Μ Μ θ 漸變小,並且靠近爐 : = 圓108上所摻之珅的濃度會遠大於靠近 02的頂。Η 14之晶圓1〇8。而晶圓1〇8在經過另一埶製 $後’摻有較多神的晶圓所測得之電阻值便會較摻有較少 申的晶圓所測得之電阻值低,同樣會造成電性差異較大的 問題。 在線寬較寬的半導體製程中,上述在沈積製程或是摻 雜製程所產生的電性差異可能尚在製程裕 window)可容許的範圍内,然而,隨著近年來在半導體元 件製程的持續縮小化,此晶圓間之電性差異的容忍裕度將 會隨之縮小,在此種情形下,習知製程之晶圓電性差異值 -將會超出新的製程容忍裕度,因而造成不良品的產生。 曼Jg内容1270161 V. Inventive Note (3) The concentration of the reaction gas is high, so the doping on the wafer 丨〇8 will be from the bottom of the furnace tube to the furnace, and the furnace will be closed. ! Μ θ θ has a small gradient and is close to the furnace: = The concentration of erbium doped on circle 108 is much greater than the top near 02. Η 14 wafers 1〇8. On the other hand, after the wafer 1〇8 is subjected to another $$, the resistance value measured by the wafer with more gods will be lower than that measured by the wafer with less application. Causes a large difference in electrical properties. In the wide-width semiconductor process, the above-mentioned electrical differences in the deposition process or the doping process may be within the allowable range of the process, however, as the process of semiconductor components continues to shrink in recent years. The tolerance of the electrical difference between the wafers will be reduced. Under this circumstance, the wafer's electrical difference value of the conventional process will exceed the new process tolerance margin, thus causing no The production of good products. Man Jg content

舟 因此 5 本發 明 之 g 的 就 是 在 提供 一— 種 晶 舟 及 使 用 此 晶 之批式 處 理 裝 置 及 晶 圓 處 理 製 程 J 可 以 縮 小 同 批 處 理 之 晶 圓間的 電 性 差 異 α 本發 明 提 出 種 晶 舟 5 適 用 於 晶 圓 批 式 處 理 裝 置 〇 其 中 ’於晶 舟 之 第 一一 端 部 至 第 二 端 部 間 j 具 有 複數 個 晶 圓 插 槽 ’且晶 圓 插 槽 係 使 配 置 於 其 中 之 晶 圓 表 面 互 相 平 行 〇 而 其 特徵在 於 晶 圓 插 槽 之 間 距 係 由 晶 舟 之 第 一 端 部 朝 向 第 二 端部逐漸增加。 此外,本發明提出一種批式處理裝置,至少包括晶舟 以及氣體入口。其中,晶舟之第一端部至第二端部間有複Therefore, in the present invention, the invention provides a seed boat and a batch processing device using the crystal and a wafer processing process J, which can reduce the electrical difference between the wafers of the same batch. The boat 5 is suitable for a wafer batch processing device, wherein 'the first end portion to the second end portion of the wafer boat has a plurality of wafer slots' and the wafer slot is configured to be disposed in the wafer The surfaces are parallel to each other and are characterized in that the distance between the wafer slots gradually increases from the first end of the wafer boat toward the second end. Furthermore, the present invention provides a batch processing apparatus comprising at least a boat and a gas inlet. Wherein, there is a complex between the first end and the second end of the boat

11741twf.ptd 第7頁 1270161 五、發明說明(4) 數個晶圓插槽,且晶圓插槽係使配置於其中之晶圓的表面 互相平行。而氣體入口係由第一端部朝向第二Z部提供氣 體,以使氣體與晶圓產生反應,其中晶圓插槽之間距係由 晶舟之第一端部朝向第二端部逐漸增加。 、另外,本發明更提出一種晶圓處理製程,適用於一批 式處理裝置。其中,此批式處理裝置至少具有晶舟以及氣 體入口。此晶舟之第一端部至第二端部間有複數個晶圓插 槽’且晶圓插槽係使配置於其中之晶圓的表面互相平行。 而氣體入口係由第一端部朝向第二端部提供氣體,以使氣 體與晶圓產生反應。而晶圓處理的製程至少包括先在晶舟 中配置晶圓,且晶圓的配置間距係由晶舟第一端部朝$第 二端部逐漸增加,再以批式處理裝置對晶圓進行處理。 由上述可知,上述之晶舟應用於批式處理裝置時,係 能夠藉由其晶圓插槽間距是沿著反應氣體的供應與流動、 擴散方向逐漸增加,因此可以縮小兩端部之反應速率的差 異’並藉此縮小兩端部之熱預算差異,從而進一步縮小同 一批晶圓的電性差異。 並且’藉由對此晶舟之晶圓插槽間距進行適當的調 正’還可以使此晶舟的晶圓置放量不至於減少太多,從而 維持應用此晶舟之批式處理裝置的產率。 尚且,本發明亦可以利用傳統的晶舟,將之應用於批 式處理裝置時,藉由將晶圓的置放間距沿著反應氣體的供 應與流動、擴散方向逐漸增加,同樣能夠使同批處理之晶 圓間之電性差異縮小,減少不良品的產生。11741twf.ptd Page 7 1270161 V. INSTRUCTIONS (4) Several wafer slots, and the wafer slots are such that the surfaces of the wafers disposed therein are parallel to each other. The gas inlet provides gas from the first end toward the second Z to react the gas with the wafer, wherein the distance between the wafer slots gradually increases from the first end of the wafer toward the second end. In addition, the present invention further proposes a wafer processing process suitable for a batch processing apparatus. Among them, the batch processing apparatus has at least a boat and a gas inlet. There are a plurality of wafer slots ′ between the first end and the second end of the wafer, and the wafer slots are such that the surfaces of the wafers disposed therein are parallel to each other. The gas inlet provides gas from the first end toward the second end to cause the gas to react with the wafer. The wafer processing process includes at least arranging the wafers in the wafer boat, and the arrangement pitch of the wafers is gradually increased from the first end of the wafer boat toward the second end portion, and then the wafer is processed by the batch processing device. deal with. As can be seen from the above, when the wafer boat is applied to a batch processing device, the wafer slot pitch can be gradually increased along the supply and flow of the reaction gas, and the diffusion direction can be reduced, thereby reducing the reaction rate at both ends. The difference 'and thereby narrow the thermal budget difference between the two ends, thereby further reducing the electrical differences of the same batch of wafers. And 'by properly adjusting the wafer slot spacing of the wafer boat' can also make the wafer placement of the wafer boat not to be reduced too much, thereby maintaining the production of the batch processing device using the wafer boat. rate. Furthermore, the present invention can also utilize a conventional wafer boat, and when it is applied to a batch processing device, the same batch can be made by gradually increasing the placement pitch of the wafer along the supply and flow and diffusion directions of the reaction gas. The difference in electrical properties between wafers processed is reduced, reducing the occurrence of defective products.

11741twf.ptd 第8頁 127016111741twf.ptd Page 8 1270161

為讓本發明之上述和其他 顯易懂,下文特舉一較佳實施 細說明如下: 目的、特徵、和優點能更明 例,並配合所附圖式,作詳 實施方次 一立第2圖係繪示本發明一較佳實施例的一種晶舟的剖面 示思圖。凊參照第2圖,晶舟2 〇 〇中包括多個晶圓插槽 (wafer slot)204、206以及2〇8,其中此些晶圓插槽&〇4、 206、208係使配置於其中的晶圓(未繪示)是以晶圓的表面 互相平+打’並且於晶舟2〇〇中,晶圓插槽之間距係由端部 202沿著垂直晶圓表面的方向朝向端部216逐漸增加。 於本實施例中,係將晶舟2〇〇從端部202至端部21 6區 分為第一部份218、第二部分220以及第三部分222。其中 第一部份218中具有多個晶圓插槽2 〇4,且晶圓插槽2〇4間 具有相同的間距,第二部分220中具有多個晶圓插槽2〇6, 且晶圓插槽2 0 6間具有相同的間距,而第三部分2 2 2中則係 具有多個晶圓插槽208,並且晶圓插槽2〇8間具有相同的間 距。In order to make the above and other aspects of the present invention obvious, the following detailed description of the preferred embodiments will be described as follows: The objects, features, and advantages can be more clearly illustrated, and The drawings illustrate a cross-sectional view of a wafer boat in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, the wafer boat 2 includes a plurality of wafer slots 204, 206, and 2〇8, wherein the wafer slots & 、 4, 206, 208 are configured The wafers (not shown) are such that the surfaces of the wafers are flush with each other and are in the wafer boat 2, and the distance between the wafer slots is from the end portion 202 in the direction of the vertical wafer surface toward the end. Department 216 is gradually increasing. In the present embodiment, the boat 2 is divided into a first portion 218, a second portion 220, and a third portion 222 from the end portion 202 to the end portion 21 6 . The first portion 218 has a plurality of wafer slots 2 〇 4, and the wafer slots 2 〇 4 have the same pitch, and the second portion 220 has a plurality of wafer slots 2 〇 6 and crystal The circular slots 206 have the same spacing, while the third portion 2 2 2 has a plurality of wafer slots 208, and the wafer slots 2〇8 have the same spacing.

此外,於本發明較佳實施例中,晶圓插槽2〇6之間距 21 2例如是可以設計為與習知之晶舟中的晶圓插槽間距相 同’且晶圓插槽204的間距210為晶圓插槽2〇6之間距21 2的 0 · 6倍’而晶圓插槽2 0 8之間距21 4則例如是晶圓插槽2 〇 6之 間距2 1 2的2倍。經由此種設計的話,既能夠符合使晶圓插 槽之間距由端部2 0 2沿著垂直晶圓表面的方向朝向端部2】6 逐漸增加的原則,同時又能夠使可置放的晶圓數不至於減In addition, in the preferred embodiment of the present invention, the distance between the wafer slots 2〇6 21 can be designed to be the same as the spacing of the wafer slots in the conventional wafer boat, and the spacing of the wafer slots 204 is 210. The distance between the wafer slots 2〇6 is 21·6 times and the distance between the wafer slots 20.8 is 21 times, for example, twice the distance between the wafer slots 2〇6 and 21.2. Through such a design, it is possible to conform to the principle that the wafer slots are gradually increased from the end portion 2 0 2 along the vertical wafer surface toward the end portion 2]6, and at the same time, the crystal can be placed. The number of circles is not reduced

1270161 五、發明說明(6) 少太多’因而能夠顧及產率(throughput)的要求。 雖然於上述之實施例中係將晶舟區分為三部分來作說 明,但本發明並不限定於此,由晶舟所區分之部分數以及 晶圓插槽間距,係可以依照實際製程所需來作調整。 第3圖係繪示配置有本發明之晶舟的一種批式處理裝 置之配置示意圖,於第3圖中,構件與第1圖相同者係使用 相同的標號並省略其說明。請參照第3圖,此批式處理裝 置例如是垂直式爐管反應器,至少包括晶舟2 〇 〇以及氣體 入口 106。晶舟200係以端部202在下,而端部216在上之方 向’配置於爐管1 〇 2的升降基座1 〇 〇上,用以將晶圓水平地 配置在其上的晶圓插槽中,以進行例如是化學氣相沈積製 程或是摻雜製程,且爐管1 0 2例如是石英管。而晶舟2 〇 〇之 第一部份21 8係位在爐管1 〇 2的底部附近,且晶舟2 〇 〇之第 三部份2 2 2係位在爐管1 〇 2的頂部附近。另外,氣體入口 1 06例如是氣體注入器,其係配置在爐管丨02的底部附近, 其中反應氣體的注入方向係由爐管1〇2的底部朝向爐管1〇2 的頂部11 4,以使反應氣體能夠由下往上流動、擴散並流 經晶圓的表面。 請繼續參照第3圖以詳細說明利用上述之批式處理裝 置對晶圓進行處理之製程。以化學氣相沈積製程為例,首 先係將晶圓204a、206a以及208a配置於晶舟200上的晶圓 插槽中,再將反應氣體自外界透過氣體入口 106注入,再 由爐管1 0 2的底部11 2往頂部11 4 (亦即是由晶舟2 0 0的端部 2 0 2朝向端部2 1 6 )流動、擴散並流經爐管1 〇 2内晶圓2 0 4a、1270161 V. INSTRUCTIONS (6) Too few 'and thus can take into account the requirements of throughput. Although the wafer boat is divided into three parts in the above embodiments, the present invention is not limited thereto, and the number of parts distinguished by the boat and the wafer slot spacing may be required according to actual processes. Make adjustments. Fig. 3 is a schematic view showing the arrangement of a batch processing apparatus in which the wafer boat of the present invention is arranged. In the third embodiment, the same reference numerals are used for the same members as in the first embodiment, and the description thereof will be omitted. Referring to Figure 3, the batch processing apparatus is, for example, a vertical furnace tube reactor comprising at least a boat 2 and a gas inlet 106. The wafer boat 200 is disposed with the end portion 208 in the upper direction, and the end portion 216 is disposed on the lifting base 1 of the furnace tube 1 〇 2 for inserting the wafer on which the wafer is horizontally disposed. In the tank, for example, a chemical vapor deposition process or a doping process is performed, and the furnace tube 102 is, for example, a quartz tube. The first part of the boat 2 21 21 8 is located near the bottom of the furnace tube 1 〇 2, and the third part of the boat 2 2 2 2 2 is located near the top of the furnace tube 1 〇 2 . In addition, the gas inlet 106 is, for example, a gas injector disposed near the bottom of the furnace tube 02, wherein the injection direction of the reaction gas is from the bottom of the furnace tube 1〇2 toward the top portion 11 of the furnace tube 1〇2, In order to allow the reaction gas to flow from bottom to top, diffuse and flow through the surface of the wafer. Please continue to refer to Figure 3 for a detailed description of the process for processing wafers using the batch processing apparatus described above. Taking a chemical vapor deposition process as an example, first, the wafers 204a, 206a, and 208a are disposed in a wafer slot on the wafer boat 200, and the reaction gas is injected from the outside through the gas inlet 106, and then the furnace tube 10 The bottom portion 11 2 of the second portion 2 2 flows toward the top portion 11 4 (that is, from the end portion 2 0 2 of the wafer boat 200 toward the end portion 2 1 6 ), diffuses and flows through the wafer 2 0 4a in the furnace tube 1 、 2,

11741twf.ptd 第10頁 1270161 五、發明說明(7) 2〇6a以及208a的表面’之後再由配置在爐管1〇2外壁的加 熱裝置Z1〜Z5提供爐管102内熱能,則所輸入的反應氣體 即會與晶圓204a、20 6a以及208a的表面產生化學反應,而 在其表面上形成薄膜。11741twf.ptd Page 10 1270161 V. INSTRUCTION DESCRIPTION (7) The surface of the 2〇6a and 208a' is then supplied with heat in the furnace tube 102 by the heating devices Z1 to Z5 disposed on the outer wall of the furnace tube 1〇2, and the input is The reaction gas chemically reacts with the surfaces of the wafers 204a, 20 6a, and 208a to form a thin film on the surface thereof.

口 、於上述之晶圓處理製程中,由於本發明係將晶舟2〇〇 區为為二部分,且晶圓相隔的間距係由端部2 〇 2往端部2 j 6 的方向逐漸增加。而反應氣體係經由氣體入口 1 〇 6注入並 f爐管102的底部112流至爐管1〇2的頂部114,因此,反應 氣體朝向爐管1 〇 2頂部的流速會加快,且因晶舟2 〇 〇之第一 :份2 1 8中的晶圓插槽間距較小,所以反應氣體與此處之 曰曰圓204a表面產生的反應速率較慢,而能夠提供爐管1〇2 頂部較高的反應氣體濃度。對於爐管1〇2的頂部而言,由 於晶圓的間距變寬,在氣體流速較快且濃度提高的情形 下,反應氣體水平進入晶圓間距的流量亦會增加。而且, 由於氣流與晶圓表面的邊界層變薄且濃度提高的情形下, 反應氣體垂直向下沈積的流量亦會隨之增加。而對於爐管 102的底^部而言,由於晶圓的間距變窄,上述反應氣體的 水平流量與垂直流量則會相對應的縮減,進而使得爐管内 之頂部與底部之反應氣體的沈積速率差距將會縮小。In the above wafer processing process, since the present invention has two regions of the wafer boat, the spacing between the wafers is gradually increased from the end portion 2 〇 2 to the end portion 2 j 6 . . The reaction gas system is injected through the gas inlet 1 〇 6 and flows to the bottom portion 114 of the furnace tube 1 〇 2 at the bottom portion 112 of the furnace tube 102. Therefore, the flow velocity of the reaction gas toward the top of the furnace tube 1 〇 2 is accelerated, and the wafer boat is accelerated. 2 〇〇 first: the spacing of the wafer slots in the portion 2 1 8 is small, so the reaction rate of the reaction gas and the surface of the circle 204a here is slow, and the top of the furnace tube 1 〇 2 can be provided. High reaction gas concentration. For the top of the furnace tube 1〇2, since the pitch of the wafer is widened, the flow rate of the reaction gas level entering the wafer pitch is also increased in the case where the gas flow rate is fast and the concentration is increased. Moreover, as the boundary layer between the gas stream and the wafer surface becomes thinner and the concentration is increased, the flow rate of the reaction gas vertically deposited downward also increases. For the bottom portion of the furnace tube 102, since the pitch of the wafer is narrowed, the horizontal flow rate and the vertical flow rate of the reaction gas are correspondingly reduced, thereby causing the deposition rate of the reaction gas at the top and the bottom in the furnace tube. The gap will narrow.

而^,因應爐管内之頂部與底部之反應氣體的沈積速 Ί】加熱器z 1〜z5的溫度梯度亦能夠縮小,從而 使得爐官頂部與底部之熱預算的差距能夠縮小,因此,就 沈積製程而言,係能夠使得同批處理之晶圓具有相同的薄 膜特性’並縮小晶圓間之電性差異。And ^, in response to the deposition speed of the reaction gas at the top and bottom of the furnace tube] the temperature gradient of the heaters z 1~z5 can also be reduced, so that the difference between the thermal budget of the top and bottom of the furnace can be reduced, therefore, deposition In terms of process, it is possible to have the same film characteristics of the same batch of wafers' and to reduce the electrical difference between wafers.

1270161 五、發明說明(8) 圓,位於爐管頂$1* *言’係能夠使得在同批處理之晶 質的強度差異之晶圓與位於爐管底部之晶圓其趨入摻 差異的目的。、,進而同樣能夠達成縮小晶圓間之電性 舟。在本發2 = ^圓^理製程並不限定使用上述之晶 以使用搭載習知之Τ::實之晶圓處理製程中’還可 t日日舟的批式處理裝詈以洁}、士 1 ί ^^ - ^ ^ /Λ Λ ^ 相曰同曰的;號ίϊ略;第4圖中’構件與第1圖相同者係使用 為第一π一,、說明。請參照第4圖,將晶舟11 〇區分 邱8口由刀、第二部分420以及第三部分422。於第一 2 中’晶圓1083例如是插人每—個晶圓插槽中,且 π奸描^ #二部分422中,晶圓1〇8〇:則例如是間隔二個晶 將晶圓108a、觀、驗依上述配置方式插 曰曰舟110後,再將反應氣體自外界透過氣體入口1〇6注 =二,由爐管102的底部112往頂部114(亦即是由晶舟位於 爐官底部的端部朝向位於爐管頂部的端部)流動、擴散並 流經爐官102内之晶圓l〇8a、l〇8b以及l〇8c的表面,之後 再由配置在爐管102外壁的加熱褒置Z1〜25提供爐管1〇2内 熱能,則所輸入的反應氣體即會與晶圓1〇8a、1〇8b以及 l〇8c的表面產生化學反應,而在其表面上形成薄膜。 於本實施例中,係在習知晶圓插槽間距相等之晶舟 11 0中’以上述之間隔若干晶圓插槽的方式置放晶圓,其1270161 V. INSTRUCTIONS (8) Round, located at the top of the furnace tube, $1* * 言' is the purpose of making the difference between the wafer strength difference between the same batch of crystals and the wafer at the bottom of the furnace tube. . Furthermore, it is also possible to achieve an electric boat that reduces the inter-wafer. In this issue 2 = ^ circle process is not limited to the use of the above-mentioned crystals to use the conventional Τ:: The actual wafer processing process can also be used in the day of the boat's batch processing equipment to clean}, 1 ί ^^ - ^ ^ /Λ Λ ^ The same as the same; number ί ϊ; in Figure 4 'the same as the first figure is used as the first π one, description. Referring to Fig. 4, the boat 11 is divided into a knife, a second portion 420, and a third portion 422. In the first 2, 'wafer 1083 is inserted into each of the wafer slots, for example, and in the second part 422, the wafer is 1〇8〇: for example, the wafer is separated by two wafers. 108a, observation, inspection according to the above configuration of the boat 110, and then the reaction gas from the outside through the gas inlet 1 〇 6 Note = two, from the bottom 112 of the furnace tube 102 to the top 114 (that is, located by the boat The end of the bottom of the furnace is flowing toward the end of the furnace tube, diffusing and flowing through the surfaces of the wafers 8a, 8b, 8b, and 8c in the furnace 102, and then disposed in the furnace tube 102. The heating devices Z1 to 25 of the outer wall provide heat energy in the furnace tube 1〇2, and the input reaction gas will chemically react with the surfaces of the wafers 1〇8a, 1〇8b and 10〇8c, on the surface thereof. A film is formed. In the present embodiment, the wafers are placed in the wafer boat 110 with the same pitch of the wafer slots, and the wafers are placed at intervals of a plurality of wafer slots.

11741twf.ptd 第12頁 1270161 五、發明說明(9) ,果係同樣能夠使得晶圓&間距是由晶舟! 1〇位於爐管底 ::1)2的端部朝向爐管頂部114的另一端部增加,進而同樣 月b夠達到使同批晶圓之電性差異縮小的目的。 同樣的’雖然於第4圖中係將晶舟區分為三部分來作 ,但本發明並不限定於此,自晶舟所區分之部分數及 八B曰圓間距,,係可以依照實際製程所需來作調整。 第5圖係繪不利用本實施例以及習知技術進行砷的摻 ,時,晶圓中砷的強度與晶圓放置位置的關係圖。請 :^多照第1圖及第5圖,習知技術中係將晶圓J Μ配置於 :個晶圓插槽内,所以晶圓1〇8係以等間距的方式排列於 晶舟11〇中,則配置於靠近爐管底部的晶圓1〇8中砷的強产 :如是4.7%,且配置於靠近爐管中段部的晶圓1〇8中砷ς =度例如是4·15 %,而配置於靠近爐管頂部的 再同時參照第4圖及第5圖,在砷的摻雜製程中,將晶圓月 =8a、l08b以及1〇8c變間距地配置在晶圓插槽ιΐ6内39, 晶圓1〇8a中砷的強度例如是4·55 %,且晶圓i08b中坤的 強度例如是4.46 %,而晶圓i〇8c中砷的強度例如是4 、 % ’如第5圖中之實線曲線所示。 · 曰。由第5圖可知,本發明第4圖之實施例中底部與頂部 晶,中的砷強度僅相差〇 · 4 %,而習知技術中底部與j ^ 申強度卻相差了〇.94 % ’因此可明顯得知7本部 a < a轭例與習知技術相較之下,係能夠將差異範圍广 小5 7 %,從而大幅地改善了習知技術中晶圓之 =縮11741twf.ptd Page 12 1270161 V. Invention Description (9), the fruit system can also make the wafer & spacing is by the boat! 1〇 The end of the bottom of the furnace tube: ::1) 2 increases toward the other end of the top 14 of the furnace tube, and thus the same month, the purpose of reducing the electrical difference of the same batch of wafers is achieved. Similarly, although in FIG. 4, the boat is divided into three parts, the present invention is not limited thereto, and the number of parts distinguished from the boat and the distance between the eight B and the circle may be in accordance with the actual process. Need to make adjustments. Fig. 5 is a graph showing the relationship between the intensity of arsenic in the wafer and the placement position of the wafer when the arsenic is doped without using the present embodiment and the conventional technique. Please: ^ Take the first picture and the fifth picture. In the prior art, the wafer J Μ is arranged in one wafer slot, so the wafers 1 〇 8 are arranged at equal intervals in the wafer boat 11 In the crucible, the strong production of arsenic in the wafer 1〇8 disposed near the bottom of the furnace tube: 4.7%, and disposed in the wafer 1〇8 near the middle portion of the furnace tube, the arsenic ς = degree is, for example, 4.15 %, and disposed near the top of the furnace tube, and referring to FIG. 4 and FIG. 5 simultaneously, in the doping process of arsenic, the wafer month=8a, l08b, and 1〇8c are spaced apart in the wafer slot. In ιΐ639, the intensity of arsenic in wafer 1〇8a is, for example, 0.455%, and the intensity of quinone in wafer i08b is, for example, 4.46%, and the intensity of arsenic in wafer i〇8c is, for example, 4, % ' The solid line curve in Figure 5 is shown. · Hey. As can be seen from Fig. 5, in the embodiment of Fig. 4 of the present invention, the intensity of arsenic in the bottom and top crystals differs by only 〇·4%, whereas in the prior art, the bottom and the j ^ intensity are different by 〇.94 % ' Therefore, it can be clearly seen that the 7th a < a yoke example can reduce the difference range by 5.7 % compared with the prior art, thereby greatly improving the wafer shrinkage in the prior art.

第13頁 衫雜強度 1270161 五、發明說明(10) 差異過大的問題。 第6圖係繪示本發明第4圖之實施例以及習知技術中加 …、裝置Z1〜Z5所提供的溫度大小,請同時參照第1圖及第6 圖在第1圖中,爐管102的底部112之加熱裝置π所提供 的溫度係為攝氏608· 5度,而爐管1〇2的頂部114之加熱^ 置ζι所提供的溫度係為攝氏653度,所以靠近頂部ιΐ4、的^加 熱裝置Ζ1與靠近底部的加熱裝置Ζ5相差攝氏445度。 二而’研同時參照第4圖及第6圖,在本實施例中,爐管 102的底部112之加熱裝置Ζ5所提供的溫度係為攝氏6〇8 5 J,而爐管102的頂部丨14之加熱裝置Z1所提供的溫度係為 攝氏634度,所以靠近頂部114的加熱裝置Z1與靠近底部 Π2的加熱裝置Z5只相差攝氏26·5度。相較於習知技術, 本發明之實施例係將加熱裝置21〜25之溫度差異縮小了4〇 %,能夠大幅地改善習知技術中熱預算差異過大所造成的 問題。 第7圖則係繪示利用本實施例以及習知技術進行摻雜 多晶矽的沈積製程時,晶圓經過另一熱製程驅入矽底材後 所呈現出來的電阻值與晶圓放置位置的關係圖。且由第6 圖可知,本發明之實施例中的晶圓間 技術中之晶圓間所受之熱預算均句,且摻雜濃 所以晶圓間的電阻值差異也會較習知技術之晶圓間的電阻 ,差異小。請同時參照第!圖及第7圖,靠近爐管ι〇2之底 W12的晶圓108所測得的電阻值為44〇 〇hm/s(iuare,且靠 近爐管1 02中段部的晶圓1 08所測得的電阻值為532Page 13 Shirt strength 1270161 V. Invention description (10) The problem of excessive difference. Fig. 6 is a view showing the temperature of the embodiment of Fig. 4 of the present invention and the addition of the devices Z1 to Z5 in the prior art, and referring to Fig. 1 and Fig. 6 in Fig. 1, the tube The heating device π of the bottom portion 112 of the 102 provides a temperature of 608 · 5 degrees Celsius, and the heating of the top portion 114 of the furnace tube 1 〇 2 provides a temperature of 653 degrees Celsius, so that it is close to the top ι 4 ^ The heating device Ζ1 is different from the heating device Ζ5 near the bottom by 445 degrees Celsius. 2, while referring to FIG. 4 and FIG. 6, in the present embodiment, the temperature of the heating device Ζ5 of the bottom portion 112 of the furnace tube 102 is 6 〇 8 5 J, and the top of the furnace tube 102 is 丨The heating device Z1 of 14 provides a temperature of 634 degrees Celsius, so the heating device Z1 near the top 114 and the heating device Z5 near the bottom Π2 differ only by 26.5 degrees Celsius. Compared with the prior art, the embodiment of the present invention reduces the temperature difference between the heating devices 21 to 25 by 4%, and can greatly improve the problems caused by the excessive thermal budget difference in the prior art. FIG. 7 is a diagram showing the relationship between the resistance value and the placement position of the wafer after the wafer is subjected to another thermal process to drive the substrate by using the present embodiment and the conventional technique for doping polysilicon. Figure. It can be seen from FIG. 6 that the thermal budget between the wafers in the inter-wafer technology in the embodiment of the present invention is uniform, and the difference in resistance between the wafers is also higher than that of the prior art. The resistance between wafers is small. Please refer to the same at the same time! In Fig. 7 and Fig. 7, the resistance value measured by the wafer 108 near the bottom W12 of the furnace tube ι2 is 44 〇〇/s (iuare, and is measured near the wafer 108 of the middle portion of the furnace tube 102). The resulting resistance is 532

第14頁 1270161 五、發明說明(11) ohm/square ’而靠近爐管102之頂部1H的晶圓1〇8所測得 的電阻值為570 ohm/square ’此晶圓間的電阻值差異範圍 係為130 ohm/square。然而,請同時參照第4圖及第7圖, 靠近爐管1 0 2之底部11 2的晶圓1 〇 8 a所測得的電阻值為4 8 2 ohm/square ’且靠近爐管102中段部的晶圓1〇礼所測得的 電阻值為511.5 ohm/scuiare,而靠近爐管1〇2之頂部114的 曰曰圓1 0 8 c所測付的電阻值為5 4 0 〇 h m / s q u a r e,此晶圓間的 電阻值差異範圍係為58 ohm/square。 由此可知’本發明第4圖之實施例係能夠將習知技術 中之晶圓電阻值的差異範圍縮小55 %,大幅地改善習知技 術中晶圓電性差異過大的問題,從而能夠避免在線寬要求 較小的製程中產生不良品。 踩合以上所述,本發明係提供一種晶舟,此晶舟應用 於批式處理裝置例如是垂直式熱爐管時,係能夠藉由其晶 圓插槽間距是由爐管底部向頂部(等同沿著氣體供應與流 動方向)逐漸增加,因此可以使同批處理之晶圓具有相同 的薄膜特性,並可改善習知技術中由於同批處理之晶圓所 文之熱預算不同,而導致晶圓間之電性差異太大的問題, 減少不良品的產生。 並且’藉由對此晶舟之晶圓插槽間距進行適當的調 整’還可以使此晶舟的晶圓置放量不至於減少太多,從而 維持應用此晶舟之處理裝置的產率。 而且,本發明亦可以利用傳統的晶舟,將之應用於批 式處理裝置例如是垂直式熱爐管時,藉由將晶圓的置放間Page 14 1270161 V. Description of the invention (11) ohm/square 'the resistance value measured on the wafer 1〇8 near the top 1H of the furnace tube 102 is 570 ohm/square 'The difference in the resistance value between the wafers The line is 130 ohm/square. However, please refer to FIG. 4 and FIG. 7 at the same time, the resistance value measured on the wafer 1 〇 8 a near the bottom 11 2 of the furnace tube 102 is 4 8 2 ohm/square 'and close to the middle of the furnace tube 102 The resistance value measured by the wafer 1 〇 51 is 511.5 ohm/scuiare, and the resistance value measured by the round hole 1 0 8 c near the top 114 of the furnace tube 1 〇 2 is 5 4 〇 hm / Square, the difference in resistance between the wafers is 58 ohm/square. Therefore, it can be seen that the embodiment of the fourth embodiment of the present invention can reduce the difference range of the wafer resistance values in the prior art by 55%, and greatly improve the problem that the wafer electrical difference is too large in the prior art, thereby avoiding Defective products are produced in processes where the line width is less demanding. According to the above description, the present invention provides a crystal boat which can be used in a batch processing apparatus such as a vertical hot tube tube by which the wafer slot pitch is from the bottom of the furnace tube to the top ( Equivalently increasing along the gas supply and flow direction, so that the same batch of wafers can have the same film characteristics, and can improve the thermal budget of the same batch of wafers in the prior art. The problem of too much electrical difference between wafers is to reduce the generation of defective products. Moreover, by appropriately adjusting the wafer slot pitch of the wafer boat, the wafer placement amount of the wafer boat can be prevented from being reduced too much, thereby maintaining the yield of the processing device using the wafer boat. Moreover, the present invention can also be applied to a batch processing apparatus such as a vertical hot tube by using a conventional wafer boat, by placing the wafers therebetween.

11741twf.ptd 第15頁 1270161 五、發明說明(12) 距是由爐管底部向頂部(等同沿著氣體供應與流動方向)、 漸增加,同樣能夠使同批處理之晶圓具有相同的薄棋遂 性,並縮小晶圓間之電性差異太大的問題,減少 、寻 產生。 良品的 雖然本發 限定本發明, 和範圍内,當 範圍當視後附 任何熟習此技藝者,在不脫 =非用以 可作些許之更動與潤饰,明之精神 之申請專利範圍所界定者本發明之保護 1270161 圖式簡單說^ -------- 圖。 圖是繪示習知之垂直式爐管反應器的剖面 第2圖是繪示本發明一較佳實施例的一種晶舟:面 第3圖是繪示本發明一較佳實施例的一種批式裝置配 置圖 配置Γ。圖是繪示本發明另一較佳實施例的一種批式裝置 第5圖係繪示利用本實施例以及習知技術進行砷 雜製程時,晶圓中砷的強度與晶圓放置位置的關係圖, 第6圖係繪示本實施例以及習知技術中加熱裝置ζι〜 Z5所提供之溫度的示意圖。 第7圖係繪示利用本實施例以及習知技術進行摻雜多 曰曰石夕的沈積製程時,晶圓經過另一熱製程後所呈現出來的 電阻值與晶圓放置位置的關係圖。 【圖式標示說明】 100 :基座 1 0 2 :爐管 106 :氣體入口 108 、 108a 、 l〇8b 、 108c 、 204a 、 206a 、 208a :晶圓 110 、 200 :晶舟 11 2 :爐管底部 11 4 :爐管頂部 2 0 2、2 1 6 :端部 2 04、20 6、208 :晶圓插槽11741twf.ptd Page 15 1270161 V. INSTRUCTIONS (12) The distance is gradually increased from the bottom of the furnace tube to the top (equivalent to the gas supply and flow direction), and the wafers of the same batch can have the same thin chess. It is ambiguous and reduces the problem of too much electrical difference between wafers, reducing and finding. The present invention is defined by the scope of the invention, and the scope of the invention is defined by the scope of the patent application. The protection of the present invention 1270161 is simple to say ^ -------- Figure. FIG. 2 is a cross-sectional view showing a conventional vertical tube reactor. FIG. 2 is a view showing a wafer boat according to a preferred embodiment of the present invention. FIG. 3 is a schematic view showing a batch type according to a preferred embodiment of the present invention. Device configuration diagram configurationΓ. The figure shows a batch device of another preferred embodiment of the present invention. FIG. 5 is a diagram showing the relationship between the intensity of arsenic in the wafer and the placement position of the wafer during the arsenic process using the present embodiment and the prior art. Figure 6 is a schematic view showing the temperatures provided by the heating devices ζι to Z5 in the present embodiment and the prior art. Fig. 7 is a graph showing the relationship between the resistance value exhibited by the wafer after another thermal process and the placement position of the wafer when the doping process is performed by the present embodiment and the conventional technique. [Description of Patterns] 100: Base 1 0 2 : Furnace tube 106: gas inlets 108, 108a, l〇8b, 108c, 204a, 206a, 208a: wafer 110, 200: boat 11 2: bottom of furnace tube 11 4 : Top of the tube 2 0 2, 2 1 6 : End 2 04, 20 6, 208 : Wafer slot

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11741twf.ptd 第18頁11741twf.ptd Page 18

Claims (1)

1270161 六、申請專繼® 、 一 - 1 · 一種晶舟,適用於一批式處理裝置,其中於該晶舟 之一第一端部至一第二端部之間具有複數個晶圓插槽,且 該些晶圓插槽係使配置於其中之複數個晶圓以該些晶圓的 表面互相平行,其中該些晶圓插槽之間距係由該晶舟之該 第^邰/cr著垂直該些晶圓表面的方向朝向該第二端部逐 漸增加。 2.如申請專例範圍第1項所述之晶舟,其中該晶舟係 由該第一端部朝向該第二端部的方向分為一第一部分、一 第二部分以及一第三部分,且位於該第二部分之每一該此 晶圓插槽之間距彼此相等,並且位於該第三部分之每一 ^ 些晶圓插槽之間距彼此相等。 Μ 3· —種批式處理裝置,至少包括: 、卜一晶舟,該晶舟之一第一端部至一第二端部之間具有 獲數個晶圓插槽,且該些晶圓插槽係使配置於其中之複數 個晶圓,該些晶圓的表面互相平行;以及 氣體入口,其中該氣體入口係由該第一端部朝向該 一端部提供一氣體,以使該氣體與該些晶圓反應, 其中該些晶圓插槽之間距係由該晶舟之該第一端部朝 向該第二端部逐漸增加。 4、·如申请專例範圍第3項所述之批式處理裝置,其中 f ^舟係由該第一端部朝向該第二端部的方向分為一第一 ,分、一第二部分以及一第三部分,且位於該第一部分之 每一該些晶圓插槽之間距彼此相等,並且位於該第二部分 之每一該些晶圓插槽之間距彼此相等,尚且位於該第三部1270161 VI. Application of Succession®, 1-1. A wafer boat suitable for use in a batch of processing apparatus, wherein there are a plurality of wafer slots between the first end and the second end of the wafer boat And the plurality of wafers disposed in the plurality of wafers are parallel to each other, wherein the distance between the wafer slots is determined by the first/cr/c of the wafer boat The direction perpendicular to the surface of the wafer gradually increases toward the second end. 2. The wafer boat of claim 1, wherein the wafer boat is divided into a first portion, a second portion, and a third portion from a direction in which the first end portion faces the second end portion. And each of the wafer slots located in the second portion are equidistant from each other, and each of the wafer slots located in the third portion are equidistant from each other. Μ 3·- batch processing device, comprising at least: a wafer boat having a plurality of wafer slots between a first end and a second end of the wafer boat, and the wafers The socket is configured to have a plurality of wafers disposed therein, the surfaces of the wafers being parallel to each other; and a gas inlet, wherein the gas inlet provides a gas from the first end toward the end portion to allow the gas to The wafers are reacted, wherein the distance between the wafer slots is gradually increased from the first end of the wafer boat toward the second end. 4. The batch processing apparatus according to claim 3, wherein the f ^ boat is divided into a first portion, a second portion and a second portion by the first end portion toward the second end portion. And a third portion, wherein each of the plurality of wafer slots in the first portion are equal to each other, and each of the wafer slots in the second portion are equal to each other, and are still located at the third portion unit 1270161 六、申請專利範圍 分之每一該些晶圓插槽之間距彼此相等。 5 ·如申請專例範圍第3項所述之批式處理裝置,其中 該批式處理裝置包括一垂直式熱爐管。 6 ·如申請專例範圍第5項所述之批式處理裝置,其中 該晶舟係以該第一端部配置於該垂直式熱爐管之底部,且 由該第一端部朝向該第二端部的方向係與由垂直式熱爐管 之底部朝向該由垂直式熱爐管之頂部的方向相同。 7 ·如申請專例範圍第5項所述之批式處理裳置,其中 該氣體入口係設置於該垂直式熱爐管之底部,且由該氣體 入口流出之氣體係由該垂直式熱爐管之底部朝向該垂直式 熱爐管之頂部流動。 、 8·如申請專例範圍第5項所述之批式處理裝置,其中 該晶舟由該垂直式熱爐管之底部朝向該垂直式熱爐管之頂 部的方向分為一下段部、一中段部以及一上段部,且位於 該下段部之每一該些晶圓插槽之間距彼此相等,並且位於 該中段部之每一該些晶圓插槽之間距彼此相等,尚且位於 該上段部之每一該些晶圓插槽之間距彼此相等。 ^ 9· 一種晶圓處理製程,適用於一批式處理裝置,其中 該批式處理裴置中至少具有: 一晶舟,其中於該晶舟之〆第一端部至一第二端部之 間係能夠用以配置複數個晶圓,且該些晶圓係以該些晶圓 的表面互相平行;以及 y ^ 一氣體入口,其中該氣體入口係由該第一端部朝向該 第 部提供一氣 /',以使該氟體與該些晶圓反應; 11741twf.ptd 第20貢 1270161 六、申請專利範圍 該晶圓處理製程至少包括: 於該晶舟中配置該此日皮由 #^ a # ^ ^ & —日日回,其中该些晶圓的配置間距 係由該日日甘之該第一端部翱A碎榮— u _抵六、_ # # Ζ 向第一舳部逐漸增加;以及 以該批式處理裝置對該些晶圓進行處理。 10.如申請專例範圍第9項所述之晶 該晶舟之該第-端部至該第一嫂邱之„::理I其中 奸描,日兮此曰m J 第一鈿部間更包括複數個晶圓 插槽且Μ二曰曰0係個別配置於該些晶圓插槽中。 Π·如申請專利範圍第10項所述之晶圓㈢ 豆 中該些晶圓插槽之間距係由哕曰冉之兮筮 山// /、 £ 1示田这日日丹之孩第一端部朝向該第 二端部逐漸增加。1270161 VI. Patent Application Range Each of the wafer slots is equal to each other. 5. The batch processing apparatus of claim 3, wherein the batch processing apparatus comprises a vertical hot tube. 6. The batch processing apparatus of claim 5, wherein the wafer boat is disposed at a bottom of the vertical hot tube with the first end, and the first end faces the first The direction of the two ends is the same as the direction from the bottom of the vertical hot tube to the top of the vertical hot tube. 7) The batch processing skirt according to item 5 of the application scope, wherein the gas inlet is disposed at the bottom of the vertical hot furnace tube, and the gas system flowing out from the gas inlet is from the vertical hot furnace The bottom of the tube flows toward the top of the vertical hot tube. 8. The batch processing apparatus of claim 5, wherein the wafer boat is divided into a lower section by a bottom of the vertical hot furnace tube toward a top of the vertical hot furnace tube, a middle portion and an upper portion, and each of the wafer slots located in the lower portion is equidistant from each other, and each of the wafer slots in the middle portion is equidistant from each other, and is located in the upper portion Each of the wafer slots is equal to each other. ^ 9· A wafer processing process suitable for a batch processing apparatus, wherein the batch processing apparatus has at least: a wafer boat, wherein the first end to the second end of the wafer boat The inter-system can be configured to configure a plurality of wafers with the surfaces of the wafers being parallel to each other; and y^ a gas inlet, wherein the gas inlet is provided by the first end toward the first portion One gas / ', in order to react the fluorine with the wafers; 11741twf.ptd 20th 1270161 VI. Patent application scope The wafer processing process at least includes: arranging the day skin in the boat by #^ a # ^ ^ & - Day back, where the spacing of the wafers is set by the first end of the day, 翱A 荣 — - u _ 六 、, _ # # Ζ gradually toward the first 舳Adding; and processing the wafers with the batch processing device. 10. If you apply the first end of the crystal boat as described in item 9 of the scope of the special case to the first 嫂 之 „ : : : : : : : : : : : : : : : : : Further, a plurality of wafer slots are included, and the Μ2曰曰0 series are individually disposed in the wafer slots. Π·The wafers described in claim 10 (3) The wafer slots in the beans The spacing is from the 兮筮 兮筮 / / / /, £ 1 示 田 This day, the first end of the child of the Japanese Dan gradually increases toward the second end. 12·如申請專例範圍第11項所述之晶圓處理製程,其 中該晶舟係由該第一端部朝向該第二端部的方向分為一第 4为、一第二部分以及一第三部分,且位於該第二部分 之每一該些晶圓插槽之間距彼此相等,並且位於該第三部 分之每一該些晶圓插槽之間距彼此相等。 1 3 ·如申請專利範圍第丨丨項所述之晶圓處理製程,其 中該些晶圓插槽之間距彼此相等,並且該些晶圓的間距係 藉由晶圓間所間隔之晶圓插槽的數目加以調整。12. The wafer processing process of claim 11, wherein the wafer boat is divided into a fourth portion, a second portion, and a first end portion toward the second end portion. And a third part, wherein each of the plurality of wafer slots in the second portion are equal to each other, and each of the wafer slots located in the third portion are equal to each other. 1 3 The wafer processing process of claim 2, wherein the wafer slots are equidistant from each other, and the wafers are spaced apart by wafer inter-wafer spacing The number of slots is adjusted. 1 4·如申請專例範圍第丨3項所述之晶圓處理製程,其 中配置於該第一部分之每一該些晶圓之間距彼此相等,且 配置於該第二部分之每一該些晶圓之間距彼此相等,並且 配置於該第三部分之每一該些晶圓之間距彼此相等。 1 5 ·如申請專例範圍第9項所述之晶圓處理製程’其中 該批式處理裝置包括一垂直式熱爐管。1 4. The wafer processing process of claim 3, wherein each of the wafers disposed in the first portion is equidistant from each other and disposed in each of the second portions The wafers are equidistant from each other, and each of the wafers disposed in the third portion is equidistant from each other. 1 5 - The wafer processing process as described in claim 9 wherein the batch processing apparatus comprises a vertical hot tube. 11741twf.ptd 第21頁 1270161 六、申請專利範圍 1 6.如申請專例範圍第1 5項所述之晶圓處理製程,其 中以該批式處理裝置對該些晶圓進行處理的步驟包括使用 該垂直式熱爐管對該些晶圓進行化學氣相沈積製程。 1 7.如申請專例範圍第1 5項所述之晶圓處理製程,其 中以該批式處理裝置對該些晶圓進行處理的步驟包括使用 該垂直式熱爐管對該些晶圓進行摻雜製程。11741twf.ptd Page 21 1270161 VI. Patent Application Range 1 6. The wafer processing process described in claim 15 of the application scope, wherein the step of processing the wafers by the batch processing apparatus includes using The vertical hot tube performs a chemical vapor deposition process on the wafers. 1 7. The wafer processing process of claim 15, wherein the step of processing the wafers by the batch processing device comprises using the vertical hot tube to perform the wafers Doping process. 11741twf.ptd 第22頁11741twf.ptd Page 22
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