l27〇l52 九、發明說明： 【發明所屬之技術領域】 粒封裝結構，尤其係 圓之封裝製造方法 '二 本發明係為一種晶圓級封裝方法及晶 才曰種使用於含有主動區(active area)之晶 【先前技術】L27〇l52 IX. Description of the invention: [Technical field of invention] Granular package structure, especially the package manufacturing method of the circle] The invention is a wafer level packaging method and a crystal seed for use in an active region (active) Area) [prior art]
由於光電相關技術的蓬勃發展，如光電元件、光電顯八 器、光輸出入、光儲存及雷射等等，使得相關產品日益H不 如影像掃描1、雷料表機、傳賴、數位相機和數位攝影機 等。而這些產品往往會用到光電元件，如發光元件、受光:件 和袓合元件(發光二極體、CCD及光麵合器）。 為了光電元件的封裝，因而發展出各種封裝製程，如美 國專利第6，G4G，235號專利，提出—種「生產積體電路元件之 方法及裝置（Methods And Apparatus For Producing IntegratedDue to the vigorous development of optoelectronic related technologies, such as optoelectronic components, optoelectronic display devices, optical output, optical storage and laser, etc., the related products are increasingly less than image scanning 1, radar watch, pass-through, digital camera and Digital cameras, etc. These products often use optoelectronic components such as light-emitting components, light-receiving components, and composite components (light-emitting diodes, CCDs, and optical combiners). For the packaging of photovoltaic elements, various packaging processes have been developed, such as U.S. Patent No. 6, G4G, No. 235, which teaches "Methods and Apparatus for Producing Integrated Circuit Components" (Methods And Apparatus For Producing Integrated
Circuit Devices)，在一含有複數個晶粒之晶圓上，形成_絕緣 層(passivation layer)，接著塗佈(coating)一第一層環氧化合物 (epoxy)，並將一第一玻璃結合於該晶圓之一面，在晶圓之另 一面進行研磨(grinding)及蝕刻(etch)，接著在晶圓進行研磨 (grinding)及蝕刻（etch)之面塗佈（coating) 一層環氧化合物 (epoxy)，並結合一第二玻璃。 在第二玻璃上塗佈一撓性層(compliantlayer)，接著形成 一凹槽(notch)，並在該凹槽之斜面上，從晶圓上之銲墊延伸一 導電層至外部之銲墊，最後再形成一銲罩層（solder mask layer)、長錫球(solderbump)及進行切割。 5 1270152 上w之封衣構造需採用二層玻璃，且有錫球強度不 足之疑慮。 【發明内容】 本發明之轉目的是提供—種晶圓級域方法及晶粒封 I結構’係採用模轉方法(m〇lding meth。雜一挽性物質 (C〇mpliant material)在晶圓背面形成一介電撓性層 (dielectric and c〇mpliant layer)，該撓性層具有複數個 凸出結構，以增強晶圓背面凸塊之二階可靠度。 本發明之目的是提供一種含有主動區(active area)之光學 元件(optieal deviee)之封裝料紐，對辟树提供良好之 保護。 為了達成上述目的，本發明之晶圓級封裝方法包括有·· 提供-晶®，其財-主動面與—相對之背面，該主動面上具 有複數個銲墊及複數個切财，在該晶圓之絲面上形成一延 伸層，該延伸層從該些銲墊延伸至該些切割道，接著在晶圓之 該主動面上接合一基板，在該晶圓之該背面形成一撓性層 (compliant layer)，且該撓性層具有複數個凸出結構，再來進行 一重分佈層製程，在該撓性層上面形成一重分佈層及塗佈一銲 罩層於該重分佈層上，並暴露出該撓性層之該凸出結構上之重 分佈層，接著接合複數個銲球於該暴露之重分佈層以及進行切 割，在該切割道處進行切割，以形成單一封裝體。 為使能更進一步瞭解本發明之特徵及技術内 谷’睛參閱以下有關本發明之詳細說明與附圖，然而 1270152 所附圖式僅提供參考與說明用，並非用來對本發明加 以限制。 【實施方式】 - —月 > 第Α〜—κ圖所示，為本發明之晶圓級封裝方法 之不思圖，首先，提供一晶圓10，其具有一主動面與一相 對之月面13 ’該主動面12上具有複數個銲墊16及複數個切 贿18，該主動面12可為光學元件之主動層(active h㈣， _ 該』鋅墊16可為輸出/入銲墊(I/O pad)，接著，在該晶圓1〇之 該主動面12上形成一延伸層14，該延伸層14從該些銲墊％ 延伸至該些切割道18，如第—A @，該延伸層14位於晶圓 10含有複數個主動面12上。 在该晶圓10之該主動面12上接合一基板12,該基板义&) 為玻每基板，該接合方式可為晶圓接合(wafer b〇n(jing)，亦 可在忒晶圓10接合該基板Ϊ2之前，在該晶圓1〇之該主動面 _ 12塗佈(coating)—黏著層2〇，該黏著層2〇可為光電膠，如第 一 B、一 C圖。可視實際之需求，將晶圓川作薄化處理 ， (thinning)，如第一 D 圖。 在日日圓10之背面11形成一撓性層(compliant layer)24，且 該撓性層24具有複數個凸出結構241，該撓性層24係用模禱 方法(molding method)形成於該晶圓1〇之背面11，如第一 e圖。 接著進行一重分佈層(redistribution layer-RDL)製程，在撓 性層24上面形成一重分佈層30，將接點移至適當位置，該重 分佈層製程包括形成複數個貫孔(via)26貫穿該撓性層24及該 1270152 晶圓10，如第一 F圖，形成一絕緣層28於該些貫孔26之表 面以及形成一金屬層於該絕緣層28與該撓性層24上，再進行 一微影(photolithography)製程，以形成該重分佈層3〇，如 第一 G、一 Η圖。 再塗佈一銲罩層(soldermasklayer)32於重分佈層30上， 並暴露出該撓性層24之該凸出結構241上之重分佈層30，如 苐I圖，以及接合袓數個銲球七沾）Μ於該暴露之重 为佈層30，如第一 J圖。最後進行切割，在切割道18處進行 切割，以形成複數個單一封裝體。 如第一 K圖所示，本發明之晶粒封裝結構包括有一晶粒 ，其具有一主動面12與一相對之背面13，該主動面12上 具有複數個銲墊16及複數個_道1δ ;—延伸層14，係位於 該晶粒10之該主動面12上，該延伸層14從該些銲墊丨6延伸 至該些切财18 ;-基板22，餘於該晶粒1G之該主動面 12上；-撓性層24 ,其具有複數個凸出結構24卜係位於該 晶粒10之該背面I3 ; 一重分佈層Μ，係位於該撓性層Μ上 面；-銲罩層32，係位於該重分佈層3〇上，並暴露出該繞性 層24之該凸出結構241上之重分佈層3〇 ;以及複數個鲜球 34，係位於該暴露之重分佈層如。 本發明具有下列特點·· 一、容易在晶圓背面採用模鎢方法形成一介電挽性声， =使晶圓正面的接點導接至背面而以晶圓之背面對外電^連 8 1270152 士二、撓性層上具有彈性凸出結構，凸塊形成於繞性声上 時可產生緩衝，增強銲接結構之強度。 曰 三、可以在光學元件上形成一良好之保護作用， 准以上所述僅為本發明之較每 限本發明之專利範圍，因此任何熟悉此項二^，非因此即拘 域内，所實施之變化或修飾，比ζ 、技身者在本發明之領 【圖式簡單說明】’ I、屬本發明之專利範圍。 «本發明之圖式 第-Α- 圖為本發明 之 【主要元件符號說明】 「本發明^ 晶圓級封裝方法之示意 圖 1〇晶圓 12主動面 13 背面Circuit Devices), forming a _ insulating layer on a wafer containing a plurality of dies, then coating a first epoxy layer, and bonding a first glass to One side of the wafer is grinded and etched on the other side of the wafer, and then a layer of epoxy compound is applied on the wafer for grinding and etching. ), and combined with a second glass. Coating a compliant layer on the second glass, and then forming a notch, and extending a conductive layer from the pad on the wafer to the outer pad on the slope of the groove. Finally, a solder mask layer, a solder ball and a cutting are formed. 5 1270152 The sealing structure of the upper w is required to use two-layer glass, and there is doubt that the strength of the solder ball is insufficient. SUMMARY OF THE INVENTION The object of the present invention is to provide a wafer level domain method and a grain seal I structure 'to use a mold transfer method (m〇lding meth. a heterogeneous material (C〇mpliant material) on a wafer A dielectric and c〇mpliant layer is formed on the back surface, and the flexible layer has a plurality of protruding structures to enhance the second-order reliability of the bumps on the back surface of the wafer. The object of the present invention is to provide an active region. The optical element (optieal deviee) of the (active area) provides good protection for the tree. In order to achieve the above object, the wafer level packaging method of the present invention includes the provision of - crystal®, which is financially active. a face and an opposite back surface, the active surface having a plurality of pads and a plurality of cuts, forming an extension layer on the surface of the wafer, the extension layer extending from the pads to the cutting channels Then bonding a substrate on the active surface of the wafer, forming a compliant layer on the back surface of the wafer, and the flexible layer has a plurality of protruding structures, and then performing a redistribution layer process. Shaped on the flexible layer a redistribution layer and a solder mask layer on the redistribution layer, and exposing the redistribution layer on the protruding structure of the flexible layer, and then bonding a plurality of solder balls to the exposed redistribution layer and performing Cutting, cutting at the scribe line to form a single package. To enable a better understanding of the features and techniques of the present invention, reference is made to the following detailed description of the invention and the accompanying drawings, however, the drawings of 1270152 The present invention is not limited by the following description. [Embodiment] - Month > Α~-κ Figure shows the wafer level packaging method of the present invention. First, provide a wafer 10 having an active surface and an opposite moon surface 13'. The active surface 12 has a plurality of pads 16 and a plurality of cut-offs 18, which may be active layers of optical components (active h (4) , the _ zinc pad 16 can be an I/O pad, and then an extension layer 14 is formed on the active surface 12 of the wafer 1 , the extension layer 14 from the pads % extends to the cutting lanes 18, such as the first -A @, the extension The layer 14 is located on the wafer 10 and includes a plurality of active surfaces 12. A substrate 12 is bonded to the active surface 12 of the wafer 10, and the substrate is bonded to each substrate, and the bonding manner can be wafer bonding ( Wafer b〇n (jing), before the wafer 10 is bonded to the substrate 2, the active surface -12 of the wafer 1 coating-adhesive layer 2, the adhesive layer 2 For the photoelectric glue, such as the first B, a C picture. According to the actual needs, the wafer is thinned, such as the first D picture. A compliant layer 24 is formed on the back surface 11 of the Japanese yen 10, and the flexible layer 24 has a plurality of convex structures 241 formed on the crystal by a molding method. The back side 11 of the circle 1 is as shown in the first e diagram. A redistribution layer (RDL) process is then performed to form a redistribution layer 30 over the flexible layer 24 to move the contacts to the appropriate locations. The redistribution layer process includes forming a plurality of vias 26 through the The flexible layer 24 and the 1270152 wafer 10, as shown in FIG. F, form an insulating layer 28 on the surface of the through holes 26 and form a metal layer on the insulating layer 28 and the flexible layer 24, and then perform A photolithography process is performed to form the redistribution layer 3, such as the first G, a map. A solder mask layer 32 is further coated on the redistribution layer 30, and the redistribution layer 30 on the protruding structure 241 of the flexible layer 24 is exposed, such as a 苐I pattern, and a plurality of joints are welded. The ball is immersed in the layer 30, as shown in the first J diagram. Finally, the cutting is performed and the cutting is performed at the dicing street 18 to form a plurality of single packages. As shown in FIG. K, the die package structure of the present invention includes a die having an active surface 12 and an opposite back surface 13. The active surface 12 has a plurality of pads 16 and a plurality of MOSFETs 1 δ. The extension layer 14 is located on the active surface 12 of the die 10, and the extension layer 14 extends from the pad pads 6 to the chips 18; the substrate 22, which is left in the die 1G. On the active surface 12; a flexible layer 24 having a plurality of protruding structures 24 on the back surface I3 of the die 10; a redistribution layer Μ on the flexible layer ;; - a solder mask layer 32 Is located on the redistribution layer 3, and exposes the redistribution layer 3 on the protruding structure 241 of the winding layer 24; and a plurality of fresh balls 34 are located in the exposed redistribution layer. The invention has the following features: First, it is easy to form a dielectric pull sound on the back side of the wafer by using a tungsten mold method, and the contact on the front side of the wafer is connected to the back side and the back side of the wafer is externally connected to the current 8 1270152 Second, the flexible layer has an elastic convex structure, and the bump is formed on the surrounding sound to generate a cushion to enhance the strength of the welded structure. Thirdly, a good protection effect can be formed on the optical component, and the above is only the scope of the invention of the present invention. Therefore, any familiarity with the present invention is not implemented in the scope of the invention. Variations or modifications, comparisons, and techniques are in the scope of the present invention [a brief description of the drawings] 'I. «The drawing of the present invention - Α - Figure is the main component symbol description" "The present invention ^ schematic of the wafer level packaging method Figure 1 〇 wafer 12 active surface 13 back
14延伸層 16銲塾 19切割道 2〇黏著層 22基板 24撓性層 241凸出結構 26貫孔 28絕緣層 30重分佈層 9 1270152 32銲罩層 34鲜球14 extension layer 16 welding 塾 19 cutting path 2 〇 adhesive layer 22 substrate 24 flexible layer 241 protruding structure 26 through hole 28 insulating layer 30 redistribution layer 9 1270152 32 welding cover layer 34 fresh ball