1266349 (案號第093123560號專利案之說明書修正） · 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體構裝製程中之晶片保護方 法，特別是應用於半導體構裝製程中，防止於:塊^金屬 層化中之銲墊氧化，同時可保護晶片不受損之方法。 【先前技術】 自IBM公司在I960年早期揭露出晶片封裝技術以來， 封裝元件即主要設置在價格昂貴之陶瓷電路板上，於此結 構中，矽晶片與陶瓷電路板間的熱膨脹關係則由於差異^ 因此在使用上並不致於造成明顯的可靠度問題。 有鑑於此，業界封裝技術已使用高溫銲錫於陶瓷電路板 上有40年之久，即所謂控制崩解晶片連接技術 (c〇ntr〇l-c〇llapse chip connecti〇n，C4 )。然而近年來，在現 代電子產品漸小化之高密度、高速度及低成本的趨勢下， 將封裝元件鑲嵌於低成本之有機電路板上，並利用環氧樹 脂底膠（epoxy underfill )填充於晶片下方以減輕由矽晶片 與有機電路板結構間的熱應力所產生之不協調，已呈現出 爆炸性的成長。而業界矚目的低溫銲接與有機電路板之利 用’更可使業界得以達到低成本封裝之目的。 在一般低成本之封裝技術中，半導體晶片的最上層表面 係有若干接觸銲墊（Pad)之設計，而有機電路板亦有若干 相對一致性的銲墊設計；在晶片與電路基板間係有低溫銲 錫凸塊或其他導電性黏著材設置，且晶片具銲墊面係朝下 1266349 (案號第093123560號專利案之說明書修正） 並鑲嵌於電路板上，其中銲錫凸塊或導電性黏著材提供晶 片與電路板間的電性輸出/輸入及機械性連線。對銲錫凸塊 而言，在晶片與電路板間的間隙可填入之有機底膠 (underfill) ’藉此可壓制熱膨脹之不協調及降低銲錫接之 應力。 如圖一所示，係為一般業界習知以凸塊下金屬層化技術 之應用於晶片封裝之部分放大結構示意圖。一晶片u形成 有若干接觸銲墊12，並覆有一被動層16露出接觸銲墊12 以供導通銜接用。接續進行所謂的凸塊下金屬層化技術 (Under Bump Metalization，UBM)，形成一凸塊下金屬層 I3 (UBM layer)。該凸塊下金屬層13搭接在晶片u之銲 墊12上，一般而言，該凸塊下金屬層13係包括三層金屬 層.第一金屬層131，通常為鋁層(Ai);第二金屬層132， 通常為錄㈣（Ni_V);以及第三金屬層133,通常為銅層 (ju)。實際上’凸塊下金屬層13充當著銲錫凸塊丨5的基底。 2具有極佳與晶片n和銲錫凸塊15材料的粘接性能，充當 著銲錫凸塊15与晶片1丨之鍵合金屬之間的鋅錫擴散層。 接著在一迴焊溫度（refl〇w)使熔融暨重塑銲錫以形成 銲錫凸塊15。在佈設《(圖中未示）於晶片㈣電路板 14之間隙後’所述之封裝元件1〇於焉完成，如圖_所示。 然而，在此業界常用之技術中，在將晶片丨丨於凸塊下 金屬層化製程結束至鑲入高密度之電路板14中，會因 ^過長’而使得晶片U上之銲墊12表面金屬氧化，而使 于後續產品品率降低。而且，在晶片U鑲入電路板14使用 1266349 (案號第093123560號專利案之說明書修正） 機械設備作傳輸工具’易使晶片11及晶片11上之鋅塾16， 進而破壞晶片11結構而產生產品問題。 有鑑於此，本發明係提供一種半導體構裝製程中之晶 片保護方法’特別是應用於半導體構裝製程中，防止凸塊 下金屬層化中之銲墊氧化，同時可保護晶片不受損之方法。 【發明内容】 本發明之主要目的在於提供一種半導體構裝製程中之 晶>1保護方法，其係塗佈一保護層於晶圓表面上，使晶圓 在切割和後續製程中有良好之應力緩衝，以利製程進行。 本發明之再一目的在於提供一種於半導體構裝製程 中，防止凸塊下金屬層化中之銲墊氧化，使單位晶片與電 路板有更好之結合層。 為達上述之目的，本發明係提供一種半導體構裝製程中 之晶片保護方法，可使單位晶片，鑲入電路板時以機械設 備作為傳輸工具，可保護其單位晶片而不受損。 為達上述目的，本發明係提供一種一種丰導體構裝製3 :之晶片保護方法。首先提供一半導體晶圓，該晶圓係I 形成有右干電路佈局，並包含至少一接觸銲墊對該晶圓_ 上了=鬼下金屬層化，覆上一凸塊下金屬層於該接觸銲1 上’塗佈一保護層於該晶圓表面上，該保護層並包覆住言 $觸輝塾。接續進行晶圓切割，分割成若干單位晶片；# 二，取製程，設置於如IC封裝基板之電路板内， 續半導體構裝製程使用。^ ^ ^ 1266349 (案號第093123560號專利案之說明書修正） . 為了使貝審查委員對本發明之目的、特徵及功效，有 更進一步的瞭解與認同，茲配合圖式詳加說明如後： 【實施方式】 為了使貴審查委員對本發明之目的、特徵及功效，有 更進一步的瞭解與認同，茲配合圖式詳加說明如後。當然， 本發明可以多種不同方式實施，並不只限於本說明書中所 述内谷。且本發明之圖式僅為簡單說明，並非依實際尺度 描繪，亦即未反映出晶片載體結構中，各層次之實際尺寸 與特色，合先敘明。 請參閱圖二A至二E所示，係本發明實施例之防止於凸塊 金屬層中之銲墊氧化之方法。首先提供一已形成有若干電 路佈局之半導體晶圓21，該晶圓21係已包括有若干未分割 的單位晶片設計於其中，並包含已開出之若干接觸銲墊 22。接續對該晶圓21上進行凸塊金屬層化（UBM)步驟，於接 觸銲墊22上形成一第一金屬層231及一第二金屬層232，其 中接觸銲墊22係如一般常用之鋁墊，第一金屬層231係可選 自一般常用之化學金層、化學鎳層、化學鈦層或化學錯層 所組成之群組之一，而第二金屬層232係可選自一般業界常 用之化學銅層、化學鎳層或化學金層所組成之群組之一， 如圖二B所示，因而形成一包括第一金屬層231、第二金屬 層之232之凸塊金屬層下結構（under Bump Metalization layer，UBM layer)。當然，這裡所舉係為本發明之較佳實施 例’ 一般業界使用技術包括鋁層、金層、鎳層、鈦層、锆 1266349 (案號第093123560號專利案之說明書修正） · 層及銅層等等亦可實施應用之。而形成方式也可包括物理 氣相沈積或化學物理氣相沈積，及有機金屬化學相沉積 (Metallorganic CVD)等，因非本發明之重點，在此不再 贅述。 接下所㈣為本發明重點，塗佈—保護層24於該晶圓 21表面上’該保護層21並完全包覆住接觸銲墊r、第一 金屬層23卜第二金屬層之232之凸塊金屬層結構。該保護 層21可為一樹脂，高分子薄膜或有機絕保護層等所組成之 群組之一，凡具有可防止氧化而保護銲墊22之功能皆可應 用實施之。而其高度並不設限，僅需高於該凸塊金屬層ς ?即可。如圖二C所示。如此’可保護凸塊金屬層，尤其 疋最外層之第二金屬層232，可防止其氧化。 接著，進饤晶圓21切割25 ( Saw )，分割成若干單位晶 片26’各該單位晶片26係為一具有完整功能設計之晶片， 將個別與對應之電路板進行接合。係如磨姓金剛石刀片以 6〇,〇〇Orpm的轉速進行切片，並要使用去離子水以提高切割 的質量。由於該金屬凸塊層附有保護層24保護之，因此在 切割過程中’凸塊金屬層不受溶劑或切割之碎屬污染，或 使碎屑不沾附於凸塊金屬層與凸塊金屬層間，且保護層％ 可緩衝切割晶圓26時所產生之應力，防止晶圓26碎裂之。 在刀。i疋後，再經挾取製程（pick and place)，設置於如^匸 封裝基板之電路板内，保護層以即便於凸塊金屬層及單位 晶片26拿取與移動中易於動作且不致受損，並防止氧化現 1266349 (案號第093123560號專利案之說明書修正） 综上所述，本發明揭示了一種半導體構裝製程中之晶片 保護方法，係具有下列優點： (1) 本發明在凸塊下金屬層化製程後，再增一保護層，使 晶圓在切割和後續製程中有良好之應力緩衝，以利製 程進行。 (2) 本發明在凸塊下金屬層化製程後，再增一保護層，使 單位晶片與封裝基板有更好之結合層。 (3) 本發明之保護層可使單位晶片，鑲入電路板時所需之 機械設備作為傳輸工具，可保護其單位晶片而不受 損，減少傷害。 综上所述，本發明提供高製程良率，有效改善習知之製 程困難及良率損失等缺失，且本發明之整體製程容易、成 本亦非常低廉，量產性高，充分顯示出本發明之目的及功 效上均深富實施之進步性，極具產業之利用價值，且為目 前市面上所未見之新發明。因此，本發明誠已符合專利法 中所規定之發明專利要件，爰依法提出申請，謹請貴審查 委員惠予審視，並賜准專利為禱。 當然，以上所述僅為本發明之較佳實施例，並非用以限 制本發明之實施範圍，任何熟習該項技藝者在不違背本發 明之精神所做之修改，均應屬於本發明之範圍，因此本發 明之保護範圍當以下列所述之申請專利範圍做為依據。 【圖式簡單說明】 圖一係為習知以凸塊下金屬層化技術之應用於晶片封裝之 1266349 (案號第093123560號專利案之說明書修正） 部分結構放大示意圖。 圖二A至二E係本發明實施例之一種半導體構裝製程中之 晶片保護方法。 圖號說明： 10-封裝元件 12, 22，-銲墊 13, 23-凸塊下金屬層 131、 231-第一金屬層 132、 232-第二金屬曾 133-第三金屬層 14,27-電路板 15- 銲錫凸塊 16- 被動層 21-晶圓 24- 保護層 25- 切割 26- 單位晶片1266349 (Amendment of the specification of the patent No. 093123560) · IX. Description of the Invention: [Technical Field] The present invention relates to a wafer protection method in a semiconductor package process, particularly for use in a semiconductor package process , to prevent the oxidation of the pad in the metal layering, and to protect the wafer from damage. [Prior Art] Since IBM revealed the chip packaging technology in the early 1960, the package components were mainly placed on expensive ceramic circuit boards. In this structure, the thermal expansion relationship between the germanium wafer and the ceramic circuit board is different. ^ Therefore, there is no obvious reliability problem in use. In view of this, the industry packaging technology has used high-temperature soldering on ceramic circuit boards for 40 years, the so-called controlled disintegration chip connection technology (c〇ntr〇l-c〇llapse chip connecti〇n, C4). However, in recent years, in the trend of high density, high speed and low cost of modern electronic products, package components are embedded on low-cost organic circuit boards and filled with epoxy underfill. The underside of the wafer has been shown to mitigate the inconsistencies caused by thermal stresses between the germanium wafer and the organic circuit board structure, and has shown explosive growth. The industry's attention to low-temperature soldering and the use of organic boards has enabled the industry to achieve low-cost packaging. In the general low-cost packaging technology, the uppermost surface of the semiconductor wafer is designed with a number of contact pads (Pad), and the organic circuit board also has a number of relatively uniform pad designs; between the wafer and the circuit substrate Low-temperature solder bumps or other conductive adhesive materials, and the wafer pads are facing downwards 1266349 (corrected in the specification of the patent No. 093123560) and embedded on the circuit board, wherein the solder bumps or conductive adhesives Provides electrical output/input and mechanical connection between the chip and the board. For solder bumps, an underfill can be filled in the gap between the wafer and the board, thereby suppressing the thermal expansion mismatch and reducing the solder joint stress. As shown in FIG. 1, it is a schematic diagram of a partially enlarged structure applied to a chip package by a conventional under-bump metallization technique. A wafer u is formed with a plurality of contact pads 12 and is covered with a passive layer 16 to expose the contact pads 12 for conduction. The so-called Under Bump Metalization (UBM) is continued to form a sub-bump metal layer I3 (UBM layer). The under bump metal layer 13 is overlapped on the pad 12 of the wafer u. Generally, the under bump metal layer 13 comprises three metal layers. The first metal layer 131 is usually an aluminum layer (Ai); The second metal layer 132, typically recorded as (four) (Ni_V); and the third metal layer 133, typically a copper layer (ju). Actually, the under bump metal layer 13 serves as a base for the solder bumps 5. 2 has excellent adhesion to the material of the wafer n and the solder bump 15, and serves as a zinc-tin diffusion layer between the solder bump 15 and the bonding metal of the wafer. The solder is then melted and reshaped at a reflow temperature (refl〇w) to form solder bumps 15. After the placement of "(not shown) in the gap of the wafer (four) circuit board 14, the package component 1 is completed, as shown in FIG. However, in the technique commonly used in the industry, the pad 12 on the wafer U may be caused by the end of the under-metal delamination process until the high-density circuit board 14 is mounted. The surface metal is oxidized, which lowers the yield of subsequent products. Moreover, the wafer U is embedded in the circuit board 14 using 1266349 (corrected in the specification of the patent No. 093123560). The mechanical device is used as a transfer tool to easily cause the zinc germanium 16 on the wafer 11 and the wafer 11, thereby destroying the structure of the wafer 11. product problem. In view of the above, the present invention provides a wafer protection method in a semiconductor package process, particularly in a semiconductor package process, which prevents oxidation of a pad in a metallization under bumps, and at the same time protects the wafer from damage. method. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for protecting a crystal in a semiconductor package process by coating a protective layer on a wafer surface to make the wafer good in cutting and subsequent processes. Stress buffering for the process. It is still another object of the present invention to provide a method for preventing oxidation of a pad in a metallization under bumps in a semiconductor package process to provide a better bonding layer between the unit wafer and the circuit board. In order to achieve the above object, the present invention provides a wafer protection method in a semiconductor package process which allows a unit wafer to be mounted as a transfer tool when mounted on a circuit board to protect its unit wafer without damage. In order to achieve the above object, the present invention provides a wafer protection method for a conductor assembly 3:. First, a semiconductor wafer is provided, the wafer system I is formed with a right-handed circuit layout, and includes at least one contact pad for stratifying the wafer, and coating a metal layer under the bump. The contact solder 1 is coated with a protective layer on the surface of the wafer, and the protective layer covers the surface. The wafer is cut and divided into a plurality of unit wafers; #2, the process is set, and is disposed in a circuit board such as an IC package substrate, and is used in a semiconductor package process. ^ ^ ^ 1266349 (Amendment of the specification of the patent No. 093123560). In order to make the Beck Review Committee have a better understanding and approval of the purpose, features and effects of the present invention, it is explained in detail with the following: Embodiments In order to enable the reviewing committee to have a better understanding and approval of the purpose, features and effects of the present invention, the detailed description of the drawings is as follows. Of course, the invention can be implemented in a number of different ways, and is not limited to the inner valleys described in this specification. Moreover, the drawings of the present invention are only for the sake of simplicity, and are not depicted on the actual scale, that is, the actual dimensions and characteristics of each layer in the structure of the wafer carrier are not reflected. Referring to Figures 2A through 2E, a method of preventing oxidation of a pad in a bump metal layer in accordance with an embodiment of the present invention. First, a semiconductor wafer 21 having a plurality of circuit layouts is formed. The wafer 21 includes a plurality of undivided unit wafers designed therein and includes a plurality of contact pads 22 that have been opened. A bump metallization (UBM) step is performed on the wafer 21, and a first metal layer 231 and a second metal layer 232 are formed on the contact pad 22, wherein the contact pads 22 are commonly used aluminum. The pad, the first metal layer 231 can be selected from one of the group consisting of a commonly used chemical gold layer, a chemical nickel layer, a chemical titanium layer or a chemically dislocated layer, and the second metal layer 232 can be selected from the general industry. One of the group consisting of a chemical copper layer, a chemical nickel layer or a chemical gold layer, as shown in FIG. 2B, thus forming a bump metal underlayer structure including the first metal layer 231 and the second metal layer 232 (under Bump Metalization layer, UBM layer). Of course, the preferred embodiment of the present invention is a general industrial use technology including an aluminum layer, a gold layer, a nickel layer, a titanium layer, and a zirconium 1266349 (corrected in the specification of the patent No. 093123560). Layers and the like can also be applied. The formation method may also include physical vapor deposition or chemical physical vapor deposition, and metallurgical CVD, etc., which are not the focus of the present invention and will not be described herein. (4) is the focus of the present invention, the coating-protective layer 24 on the surface of the wafer 21 'the protective layer 21 and completely covers the contact pad r, the first metal layer 23 and the second metal layer 232 Bump metal layer structure. The protective layer 21 can be one of a group consisting of a resin, a polymer film or an organic protective layer, and any function that can prevent oxidation and protect the pad 22 can be applied. The height is not limited, only need to be higher than the bump metal layer. As shown in Figure 2C. Thus, the bump metal layer, particularly the outermost second metal layer 232, can be protected from oxidation. Next, the wafer 21 is cut 25 (Saw) and divided into a plurality of unit wafers 26'. Each of the unit wafers 26 is a wafer having a complete functional design, and is individually bonded to the corresponding circuit board. For example, the diamond blade of the grinding name is sliced at 6 rpm, 〇〇Orpm, and deionized water is used to improve the quality of the cutting. Since the metal bump layer is protected by the protective layer 24, the bump metal layer is not contaminated by solvent or cutting during the cutting process, or the debris is not adhered to the bump metal layer and the bump metal. Between the layers, and the protective layer % can buffer the stress generated when the wafer 26 is diced, preventing the wafer 26 from being broken. In the knife. After being rubbed, the pick and place are disposed in a circuit board such as a package substrate, and the protective layer is easy to move and is not affected even when the bump metal layer and the unit wafer 26 are taken and moved. The present invention discloses a wafer protection method in a semiconductor package process, which has the following advantages: (1) The present invention is in the prior art, which discloses a wafer protection method in a semiconductor package process. After the metal stratification process under the bumps, a protective layer is added to make the wafer have good stress buffer during the cutting and subsequent processes for the process. (2) After the under-bump metal stratification process, the present invention further adds a protective layer to provide a better bonding layer between the unit wafer and the package substrate. (3) The protective layer of the present invention can use a mechanical device required for inserting a unit wafer into a circuit board as a transfer tool, thereby protecting the unit wafer from damage and reducing damage. In summary, the present invention provides a high process yield, effectively improves the conventional process difficulties and yield loss, and the overall process of the present invention is easy, the cost is also very low, and the mass production is high, which fully demonstrates the present invention. Both the purpose and the efficacy are profoundly advanced, and the value of the industry is extremely valuable, and it is a new invention that has not been seen on the market. Therefore, the invention has already complied with the invention patent requirements stipulated in the Patent Law, and has applied for it according to law. I would like to ask your review committee to give a review and grant the patent as a prayer. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modifications made by those skilled in the art without departing from the spirit of the present invention should fall within the scope of the present invention. Therefore, the scope of protection of the present invention is based on the scope of the patent application described below. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an enlarged schematic view showing a partial structure of a conventionally used under-bump metallization technique for chip packaging 1266349 (correction of the specification of the patent No. 093123560). 2A to 2E are wafer protection methods in a semiconductor package process according to an embodiment of the present invention. Description of the drawings: 10-package component 12, 22, - pad 13, 23 - under bump metal layer 131, 231 - first metal layer 132, 232 - second metal 133 - third metal layer 14, 27- Circuit Board 15 - Solder Bump 16 - Passive Layer 21 - Wafer 24 - Protective Layer 25 - Cut 26 - Unit Wafer