TWI265573B - Isolation trench thermal annealing method for non-bulk silicon semiconductor substrate - Google Patents

Isolation trench thermal annealing method for non-bulk silicon semiconductor substrate

Info

Publication number
TWI265573B
TWI265573B TW094117029A TW94117029A TWI265573B TW I265573 B TWI265573 B TW I265573B TW 094117029 A TW094117029 A TW 094117029A TW 94117029 A TW94117029 A TW 94117029A TW I265573 B TWI265573 B TW I265573B
Authority
TW
Taiwan
Prior art keywords
semiconductor substrate
isolation trench
bulk silicon
silicon semiconductor
thermal annealing
Prior art date
Application number
TW094117029A
Other languages
English (en)
Other versions
TW200616089A (en
Inventor
Jhon-Jhy Liaw
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW200616089A publication Critical patent/TW200616089A/zh
Application granted granted Critical
Publication of TWI265573B publication Critical patent/TWI265573B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
TW094117029A 2004-11-04 2005-05-25 Isolation trench thermal annealing method for non-bulk silicon semiconductor substrate TWI265573B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/982,456 US20060094171A1 (en) 2004-11-04 2004-11-04 Isolation trench thermal annealing method for non-bulk silicon semiconductor substrate

Publications (2)

Publication Number Publication Date
TW200616089A TW200616089A (en) 2006-05-16
TWI265573B true TWI265573B (en) 2006-11-01

Family

ID=36262548

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094117029A TWI265573B (en) 2004-11-04 2005-05-25 Isolation trench thermal annealing method for non-bulk silicon semiconductor substrate

Country Status (3)

Country Link
US (1) US20060094171A1 (zh)
CN (1) CN1770406A (zh)
TW (1) TWI265573B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4427489B2 (ja) * 2005-06-13 2010-03-10 株式会社東芝 半導体装置の製造方法
CN101459066B (zh) * 2007-12-13 2010-08-11 中芯国际集成电路制造(上海)有限公司 栅极、浅沟槽隔离区形成方法及硅基材刻蚀表面的平坦化方法
CN109346562A (zh) * 2018-08-30 2019-02-15 华灿光电（浙江）有限公司 一种发光二极管外延片的制备方法及发光二极管外延片
CN109585273B (zh) * 2018-11-30 2020-04-28 中国电子科技集团公司第十三研究所 一种氧化镓器件隔离区的制备方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5985735A (en) * 1995-09-29 1999-11-16 Intel Corporation Trench isolation process using nitrogen preconditioning to reduce crystal defects
US6833280B1 (en) * 1998-03-13 2004-12-21 Micron Technology, Inc. Process for fabricating films of uniform properties on semiconductor devices
JP2001230315A (ja) * 2000-02-17 2001-08-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6657276B1 (en) * 2001-12-10 2003-12-02 Advanced Micro Devices, Inc. Shallow trench isolation (STI) region with high-K liner and method of formation
WO2003060992A1 (fr) * 2002-01-09 2003-07-24 Matsushita Electric Industrial Co., Ltd. Appareil a semi-conducteurs et procede de fabrication
JP2004260073A (ja) * 2003-02-27 2004-09-16 Seiko Epson Corp 半導体装置およびその製造方法
US6887798B2 (en) * 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
JP2005150403A (ja) * 2003-11-14 2005-06-09 Fujitsu Ltd 半導体装置の製造方法
US7462549B2 (en) * 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption

Also Published As

Publication number Publication date
US20060094171A1 (en) 2006-05-04
TW200616089A (en) 2006-05-16
CN1770406A (zh) 2006-05-10

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