TWI263316B - Leadframe for enhanced downbond registration during automatic wire bond process - Google Patents
Leadframe for enhanced downbond registration during automatic wire bond processInfo
- Publication number
- TWI263316B TWI263316B TW092119143A TW92119143A TWI263316B TW I263316 B TWI263316 B TW I263316B TW 092119143 A TW092119143 A TW 092119143A TW 92119143 A TW92119143 A TW 92119143A TW I263316 B TWI263316 B TW I263316B
- Authority
- TW
- Taiwan
- Prior art keywords
- leadframe
- downbond
- enhanced
- wire bond
- during automatic
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Abstract
A process for enhancing visual detectability of a leadframe having a die attach pad and a plurality of contacts, during automated wirebonding in the production of an integrated circuit package. At least one of a ring, a line and array of dots are plated on the die attach pad of the leadframe and around a periphery of the die attach pad. The leadframe is surface treated to cause a color change on a surface of the leadframe for improved visual detectability of the at least one of the ring, the line and the dots.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TH083796 | 2003-07-11 | ||
SG200304072-2A SG140446A1 (en) | 2003-07-11 | 2003-07-11 | Leadframe for enhanced downbond registration during automatic wire bond process |
MYPI20032625 MY129449A (en) | 2003-07-14 | 2003-07-14 | Leadframe for enhanced downbond registration during automatic wire bond process |
CN031495796A CN1571130B (en) | 2003-07-15 | 2003-07-15 | Lead frame for reinforcing lower joint alignment in automatic lead bonding process |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200503196A TW200503196A (en) | 2005-01-16 |
TWI263316B true TWI263316B (en) | 2006-10-01 |
Family
ID=37966332
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092119143A TWI263316B (en) | 2003-07-11 | 2003-07-14 | Leadframe for enhanced downbond registration during automatic wire bond process |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI263316B (en) |
-
2003
- 2003-07-14 TW TW092119143A patent/TWI263316B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW200503196A (en) | 2005-01-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SG125168A1 (en) | Multi-leadframe semiconductor package and method of manufacture | |
SG117542A1 (en) | Integrated circuit leadframe and fabrication meth od therefor | |
MY126696A (en) | Structure and method of direct chip attach | |
TW200742033A (en) | Stackable semiconductor package | |
TW200601472A (en) | Leadframe for leadless flip-chip package and method for manufacturing the same | |
HK1073721A1 (en) | Method for forming an encapsulated device and structure | |
EP1237187A3 (en) | Resin-encapsulated semiconductor device and method for manufacturing the same | |
TW344123B (en) | Semiconductor device and process for producing the same | |
WO2003105223A3 (en) | Quad flat non-leaded package comprising a semiconductor device | |
TW200607034A (en) | Power semiconductor package | |
TW200741924A (en) | Method for making QFN package with power and ground rings | |
TW200503221A (en) | Semiconductor device having a bond pad and method therefor | |
TW200725861A (en) | Semiconductor package and process for making the same | |
TW200515557A (en) | Semiconductor package, method for manufacturing the same and lead frame for use in the same | |
WO2011049959A3 (en) | Methods and devices for manufacturing cantilever leads in a semiconductor package | |
TWI265617B (en) | Lead-frame-based semiconductor package with lead frame and lead frame thereof | |
US8164203B2 (en) | Leadframe, semiconductor device, and method of manufacturing the same | |
TWI263316B (en) | Leadframe for enhanced downbond registration during automatic wire bond process | |
TWI263286B (en) | Wire bonding method and semiconductor package using the method | |
SG140446A1 (en) | Leadframe for enhanced downbond registration during automatic wire bond process | |
MY129449A (en) | Leadframe for enhanced downbond registration during automatic wire bond process | |
CN102543931A (en) | Center-wiring double-circle-arrangement single-IC (integrated circuit) chip packaging piece and preparation method thereof | |
SG131789A1 (en) | Semiconductor package with position member and method of manufacturing the same | |
SG103824A1 (en) | Leadframe and semiconductor package with improved solder joint strength | |
HK1068511A1 (en) | Leadframe for enhanced downbond registration during automatic wire bond process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |