TWI262574B - Sidewall spacer structure for self-aligned contact and method for forming the same - Google Patents

Sidewall spacer structure for self-aligned contact and method for forming the same Download PDF

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TWI262574B
TWI262574B TW092113946A TW92113946A TWI262574B TW I262574 B TWI262574 B TW I262574B TW 092113946 A TW092113946 A TW 092113946A TW 92113946 A TW92113946 A TW 92113946A TW I262574 B TWI262574 B TW I262574B
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Taiwan
Prior art keywords
layer
spacer
forming
inner insulating
conductive patterns
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TW092113946A
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Chinese (zh)
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TW200419711A (en
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Dong-Jun Lee
Tae-Young Chung
Jae-Goo Lee
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Samsung Electronics Co Ltd
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    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04F—FINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
    • E04F13/00—Coverings or linings, e.g. for walls or ceilings
    • E04F13/07—Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor
    • E04F13/08—Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor composed of a plurality of similar covering or lining elements
    • E04F13/0871—Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor composed of a plurality of similar covering or lining elements having an ornamental or specially shaped visible surface
    • E04F13/0873—Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor composed of a plurality of similar covering or lining elements having an ornamental or specially shaped visible surface the visible surface imitating natural stone, brick work, tiled surface or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04F—FINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
    • E04F13/00—Coverings or linings, e.g. for walls or ceilings
    • E04F13/002—Coverings or linings, e.g. for walls or ceilings made of webs, e.g. of fabrics, or wallpaper, used as coverings or linings
    • E04F13/005—Stretched foil- or web-like elements attached with edge gripping devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04F—FINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
    • E04F2201/00—Joining sheets or plates or panels
    • E04F2201/07—Joining sheets or plates or panels with connections using a special adhesive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

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  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Civil Engineering (AREA)
  • Structural Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

In one embodiment, adjacent conductive patterns are formed overlying a semiconductor substrate. The conductive patterns each have a conductive line and a capping layer. A first spacer formation layer is formed between the adjacent conductive patterns. The first spacer formation layer is formed between the top surface of the capping layer and the bottom surface of the conductive line. A conformal second spacer formation layer is formed on the conductive patterns. A first interlayer insulating layer is formed on the conformal second spacer formation layer. Next, an opening is formed to extend to a portion of the first spacer formation layer, in the first interlayer insulating layer. The portion of the first spacer formation layer is etched, using the second spacer formation layer as an etch mask, to form a single-layer spacer on sidewalls of the conductive patterns, concurrently with a contract hole.

Description

1262574 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種半導體元件，且特別是有關於一 種自我對準接觸窗(Self_Aligned CGn s 壁結構及其製造方法。 、【先前技術】 當半導體元件變得更密集，在製作過程中要確定對不 準的適當範圍就會變的更蝴難，這是因為部分受到 刻技術的限制。舉例來說，當在電容器的節點接 、相鄰的位元線之間的空間減少時，要在位元線之 ，形成接觸窗開口而不造成像是電性短路制題會變的更 為困難。 業上進行了各種嘗試，像是顧自動對準接觸窗 (S=呈’來解決這些問題。第1A圖印E圖係為利 白4 SAC製程來形成儲存節點接觸窗之流程剖面 ^芬照第1A圖’第—内層絕緣層120形成於-半導體 土 (未顯不），其具有—儲存節點接缝130,-層第二 =層絶緣層140會形成在第—内層絕緣層⑽上，接著， 已括位兀線150與盍層16〇的位元 $ 二内層絕緣層140上。 〜风在弟 = = :，—層氮切層18〇會形成在位元線堆 "層絕緣層14G上，此氮切層180接著合 被回蝕刻，如第1Γ岡邮— ^普曰 ^ 以形成—單層側壁間隙壁 月 > '、'、 圖，在形成單層間隙壁180,以後，在 1262574 單層間隙壁⑽，之位元線堆叠〗55以及第_ 圖:二用:=?一第三内層絕—1262574 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor element, and more particularly to a self-aligned contact window (Self_Aligned CGn s wall structure and a method of fabricating the same). [Prior Art] As semiconductor components become more dense, it is more difficult to determine the appropriate range of misalignment during the manufacturing process because it is partially limited by the engraving technique. For example, when the capacitor is connected, the phase When the space between the adjacent bit lines is reduced, it is more difficult to form a contact window opening in the bit line without causing the problem of being electrically short-circuited. Various attempts have been made in the industry, such as Automatically align the contact window (S=present' to solve these problems. The 1A image is shown in the process of the Lie 4 SAC process to form the storage node contact window process section ^Fen photo 1A' first inner insulating layer 120 Formed on-semiconductor soil (not shown) having a storage node seam 130, a layer second layer insulation layer 140 is formed on the first inner insulating layer (10), and then the alignment lines 150 and 已 are included. Layer 16 〇 bit $ Two inner insulating layers 140. ~ wind in the brother = = :, - layer nitride layer 18 〇 will be formed on the bit line stack " layer insulating layer 14G, the nitrogen layer 180 is then etched back, as in 1Γ冈邮—^ Pu'er ^ To form a single-layer sidewall spacer month> ', ', Fig., in the formation of a single-layer spacer 180, after that, in the 1262574 single-layer spacer (10), the bit line is stacked. And the first _ Figure: two with: =? a third inner layer absolutely -

接=回綱的早層間隙壁18〇’作為 E 義弟二内層絕緣層19〇，以 、層义 存節點接觸窗開口 2〇〇。 白°的自動對準儲 其中二圖广E圖所示的習知SAC製程， f缺舉例來說，在形成單層間隙壁ι80，的π 钱刻的過程中’側壁間隙壁⑽ 的回 蝕（蠻的*&gt; 曰被钱刻械态過度侵 侵蝕合導致戶== 虫刻期間也會形成接觸窗開口；過度 3導致“過度餘刻以及/或肩部缺陷，也就是合導致 線150與儲存節點接觸墊130產生電性短：，在 ====^_開口 暴露出來的側 处合^^&amp;取/ ^刀科’因為單層間隙壁⑽’可 月匕《 胃®開σ 200的形成期間被過度餘刻，單声間隙 度可能會變的很薄，這會增加^ 合因此妨礙了記憶體元件積集度的增加。 此外，當傾向較高積集密度時，接觸窗開口的口徑會 二小^度會增加’因此會使高寬比（高對寬的比例）增 口 ’ *此要填滿深又窄的接觸窗開口會很困難， ^之=内層介電層中就會有空隙存在，在清潔㈣程(比 ==刻過程)中空隙可能會被揭開，而造成位元線之間 以及/或相鄰接觸塾130之間的橋接，而形成短路電路。 需要一種改良的半導體製造方法，可以增加飾 刻格度或肩部寬度’並減少位元線的負載電容，以進一步 1262574 降低肩部的耗損。 【發明内容】 有二ΜίΓ的目的就是在提供一種半導體元件，且 有更可㈣自朗準儲存節點朗窗収其 二 不會出現上述的問題。 /而 、在-實施例中，相鄰的導電圖案可以形成在— =上，這些導電圖案每—個都具有—導線與—蓋層^ ^ -間隙郷絲會形絲帅 =壁形成，形成在蓋層的頂端表面與=二 圄宏μ :層第—間隙壁形成層會共形的形成在這些導電 回/.、，—層第—内層絕緣層會形成在第二間隙壁形成層 形成在第:内層絕緣層中，延伸往第、 ^ ^ 區域，把第二間隙壁形成層作為蝕刻罩 1¾、辟2第—間隙壁形成層的此區域，以形成—個單層間 ’、土 ； V電圖案的側壁上，同時形成一個接觸窗開口。 ，讓本發明之上述和其他目的、特徵、和優點能更明 ”、、_董，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 ^ ，然本發明已以一較佳實施例揭露如下，然其並非用 t限Ϊ本發明，任何熟習此技藝者，在不脫離本發明之精 才和範圍内’當可作些許之更動與潤飾，因此本發明之保 護範，當視後附之申請專利範圍所界定者為準。 第2A圖至第2F圖緣示係根據本發明一較佳實施例， 8 1262574 的-種自我對準儲存節點接觸窗之製作流程剖面圖。首先 明 &gt; 第2A圖，利用習知的技術（比如低壓化學氣相沈積 法(LP-CVD)或是高密度電漿化學氣相沈積法(HDp_c 在半導體基底10上沈積—層第—内層絕緣層2()，The early interlayer spacer 18〇' of the connection = the second layer is the inner insulating layer 19〇 of the E-Yi, and the contact opening of the node is 2〇〇. The automatic alignment of white ° stores the conventional SAC process shown in the figure E, f. For example, in the process of forming a single-layer spacer ι80, the etchback of the sidewall spacer (10) (Rare*&gt; 曰 曰 曰 曰 曰 曰 曰 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The contact pad 130 with the storage node is electrically short: at the side exposed by the ====^_ opening, ^^& is taken / ^刀科' because the single-layer spacer (10)' can be used for the month of the stomach When the formation of σ 200 is excessively left, the monophonic gap may become thin, which may increase the integration and thus hinder the increase in the memory element accumulation. Further, when the tendency is higher, the contact density is increased. The diameter of the opening will increase by two small degrees - thus increasing the aspect ratio (high to wide ratio). * It is difficult to fill the deep and narrow contact window opening. ^The inner dielectric layer There will be gaps in the middle, and the gap may be uncovered in the cleaning (four) process (than == inscription process), causing the bit A bridge between the lines and/or adjacent contacts 130 forms a short circuit. There is a need for an improved semiconductor fabrication method that can increase the trim or shoulder width and reduce the load capacitance of the bit lines to Further 1262574 reduces the wear of the shoulder. [Summary] The purpose of the two is to provide a semiconductor component, and there is a better way to (4) the first problem is that the above problem does not occur. In an embodiment, adjacent conductive patterns may be formed on -=, and each of the conductive patterns has a wire and a cap layer ^ ^ - a gap wire is formed in the shape of a wire = formed in the cap layer The top surface and the =2 圄 macro μ: layer-stitch formation layer will be conformally formed on these conductive back/., - layer first inner insulating layer will be formed in the second spacer forming layer formed on the inner layer In the insulating layer, extending to the first, ^^ region, the second spacer forming layer is used as the etching mask 126, the second spacer layer forming layer, to form a single layer ', soil; V electric pattern On the side wall The above and other objects, features and advantages of the present invention will become more apparent from the accompanying claims. [Embodiment] The present invention has been disclosed in a preferred embodiment as follows, but it is not intended to limit the invention, and anyone skilled in the art can do it without departing from the spirit and scope of the invention. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A cross-sectional view of the fabrication process of a self-aligned storage node contact window. First of all, Figure 2A, using conventional techniques (such as low pressure chemical vapor deposition (LP-CVD) or high density plasma chemical vapor deposition). Method (HDp_c is deposited on the semiconductor substrate 10 - layer first - inner insulating layer 2 (),

較適當為1000-3000埃。 X 、、一些適當的介電材料，像是硼磷矽酸玻璃(BpsG)、旋 塗式玻璃(SOG)、電漿誘導的四乙基如㈣鹽(pE_TE〇s)、 未摻雜的矽酸鹽玻璃(USG)等都可以用來形成第一内層絕 緣層2〇 ’接著會在第—㈣絕緣層Μ⑽成儲存節點接 觸墊30卩a性連接以習知製程形成與儲存節點接觸 一起的主動區。 、按者在儲存郎點接觸墊30與第一内層絕緣層2〇上 成一層弟一内層、纟巴緣層40，第二内層絕緣層4〇的厚声 適當的範圍為1〇〇〇至3〇〇〇埃，較適當的是利用平坦化 技術，像是化學機械研磨法(CMp)對此第二内層絕緣層, 進2平坦化，以改善微影製程的餘裕，在平坦製程以j灸 此第二内層絕緣層40的厚度較適當是約為2000埃。More appropriate is 1000-3000 angstroms. X, some suitable dielectric materials, such as borophosphoric acid glass (BpsG), spin-on glass (SOG), plasma-induced tetraethyl (tetra) salt (pE_TE〇s), undoped ruthenium The acid salt glass (USG) and the like can be used to form the first inner insulating layer 2', and then the first (four) insulating layer Μ(10) is formed into the storage node contact pad 30a. The conventional connection is formed in contact with the storage node by a conventional process. Active area. The thickness of the second inner insulating layer 4 is suitably set to 1 〇〇〇 to the first inner insulating layer 2 3 〇〇〇, it is more appropriate to use flattening technology, such as chemical mechanical polishing (CMp) for this second inner insulating layer, 2 flattening to improve the margin of the lithography process, in the flat process to j The thickness of the second inner insulating layer 40 is suitably about 2000 angstroms.

具有侧壁52的導電圖案55會形成在半導體基底 上，這，導電圖案55每一個包括像是位元線的二&amp;線 以及一盍層60(比如一層圖案化的位元線罩幕層），此位 線5〇較適當是由-種像是厚度為4〇請〇埃的鶴之導· 料形成，而蓋層60較佳是由厚度為1〇〇〇_3〇〇〇埃的I 形成，，是此蓋層60還是可以由其他適當的材料組^ 。 接著，請參照第2B圖，第一間隙壁形成層％較佳 9 1262574 形成在導電S1案55之間的第二内層絕緣層4〇上，此第一A conductive pattern 55 having sidewalls 52 may be formed on the semiconductor substrate, wherein the conductive patterns 55 each comprise a second &amp; line such as a bit line and a germanium layer 60 (such as a patterned bit line mask layer) ), the bit line 5 〇 is suitably formed by a kind of guide material having a thickness of 4 〇 〇 , ,, and the cover layer 60 is preferably 1 〇〇〇 3 〇〇〇 厚度The formation of I, is that the cover layer 60 can still be composed of other suitable materials. Next, referring to FIG. 2B, the first spacer formation layer % is preferably 9 1262574 formed on the second inner insulating layer 4 之间 between the conductive S1 cases 55, this first

間隙壁形成層70可以是比如LP-CVD、BPSG、HDP或CVD 氧化物等具有相對較低係數或介電常數的材質，第一間隙 壁形成層70的高度可以透過濕蝕刻製程來加以定義。舉個 例子來說，最好將一層材料層形成在導電圖案55與第二内 層絕緣層40上，以形成第一間隙壁形成層70，接著在形 成的結構上進行蝕刻（比如濕蝕刻）以調整第一間隙壁形成 ， 層7 0的南度。 因此’第一間隙壁形成層7〇的頂端表面會形成在蓋層 馨 60的頂端表面61以及位元線5〇的底部表面51之間，第 -間隙壁形成層7G的頂端表面71最適當是大致在蓋層6〇 的頂端表面61之下，或是在位元線50的底部表面51上方 約100_2000埃。或者是，第一間隙壁形成層7〇的頂端表 面 了以被放置在蓋層60的頂端表面61以及位元線5〇 的底部表面51之間的中間位置處。 恭明參照弟2C圖，用習知的方法像是Lp_CVD製程在 圖案Μ上形成一層共形的第二間隙壁形成層80，此 f 第-間隙壁形成層8〇較適當是用與形成第—間隙壁形$ V 層之材料（比如一氧化石夕)具有姓刻選擇比的一種材料構 j曰相幸乂於第二間隙壁形成層8〇，第一間隙壁形成層最適 當是具有較低的介電常數(低係數），第二間隙壁形成層80 可以=比如氮化矽構成，其厚度較佳為⑻埃。熟習 二者句知在不脫难本發明的範圍與精神之内，可以採 用具有適當的蝕刻率與介電常數的材料。 10 1262574 接著請參照第2D圖，用習知的方法像是lPCVD或是 HDP CVD，在共形的，二間隙壁形成層8〇上形成一層第 二内層、纟巴緣層90，此弟二内層絕緣層較佳是與第二間 隙壁形成層80具有#刻選擇比，第三内層絕緣層9〇最好 疋用與第一間隙壁形成層70相同的材料構成，然後用習知 的平坦化技術將第三内層絕緣層90平坦化。接著，利用第 二間隙壁形成層80(如第3C圖）作為蝕刻阻擋層，在第三 内層絕緣層90内形成一個開口 92，暴露出第二間隙壁形 成層80的一區域，此開口 92會形成在相鄰導電圖案％ 之間並利用第二間隙壁形成層8〇自動對準。 、請參照第2E圖，根據本發明的較佳實施例，第二間 隙壁形成層8 G暴露出來的區域最好可以被㈣或移除，以 ，露出第-間隙壁形成層7G的—部分(開口 92會被 第一間隙壁形成層70的一區域）。 〃接著請參照第2FSI，可以在第—間隙壁形成層7〇與 第二内層絕緣層4G中形成-個儲存節點接觸窗開口 1〇〇: 此儲存節點接觸窗開口〗〇 〇的形成係透過利用第二 形成層80(具有未被蝕刻的平整上表面)作為蝕刻罩^ 刻第二間隙壁形成層70與第二内層絕緣層4()，儲存節= 妾觸窗開口 100會延伸穿過第二内層絕緣層4〇以暴t ’’、、 觸墊30的一部分。 *路出接 在此製作過程中，因為用第二間隙壁形成層80 刻罩幕進行蝕刻時，第一間隙壁形成層70暴露出來:蝕 也會被蝕刻到，所以會形成單層間隙壁85，，，單層，，表^份 1262574 導電圖案55的側壁上形成的側壁 疊自其上。儲存節點接觸^ 口 ^會透^ 因Γη二動對準形成於相鄰的導電圖案55之間， 】早層間隙壁85會與儲存節點接觸窗開口 10。同時形 程巾’SAC糾製較細_間隙壁 在；=才匕始’如第1D圖至第1E圖；換句話說， 開：形成成ί T,緣層190以前以及進行SAC接觸窗 :飩二&gt; t刖’氮化矽層180會被回蝕刻以形成沒有 ί中隙壁180’，因此在SAC㈣過 二綠^ 足夠的肩部寬度或是_裕度，習知的 短路現^ ::壁則’因此會消耗更多的間隙壁，導致意外的 短路現象，比如在位元線150與接觸塾130之間。 SAC飾+像自知技術’根據本發明之較佳實施例， 圖至Jin 柿成單和_ 85之前進行，如第2C ΙΐΓΛ’換句話說’ SAC_製程開始會在第二間 在頂二Λ下未被㈣的區域(比如頂端部分），因此 有比較平整的區域·^邊緣區域會比f知的厚，在 出第二=點接觸窗開口1GG的步驟進行顧會首次暴露 —間隙壁形成層80，而SAC蝕刻备在呈右车、 =頂端平整區域處進行，因為這個原因 4二 ===降低，間_因此 =無 接又的耗彳貝或疋磨蝕產生，在導電圖案55鱼 之間的意外短路也因此可以藉由增純祕度或肩部來加 12 1262574 以避免。 在另 1¼例中（如在一個線型接觸窗的例子中），在 第®圖麻的步财形朗⑽的頂部即使 被餘刻的Μ ’在邊緣部份還是纽習知厚。像之前的實 施例，SAC_還是在形成_壁之前以及形成第三内層 絕緣層90 t蓋於第二間隙壁形成層8〇之後進行。在此例 ^，。單層間隙壁85也可以與儲存節點接觸窗⑽的形成 存節方法，接著將接觸插塞(未顯示)形成在儲 = 口⑽内，並與接觸墊扣作連接，舉 i末况像疋鎢的金屬可以被沈積在儲 _内，在沈積步驟之後，會進行一道平拍;:囱= 包括CMP。 一化步驟，可月匕 平面η圖種自我對準儲存節點接觸窗1〇〇之 千面圖’弟3Β圖為沿著第3Α圖的α_α 對準儲存$點接觸窗之剖帛 ”、、717、The spacer formation layer 70 may be a material having a relatively low coefficient or dielectric constant such as LP-CVD, BPSG, HDP or CVD oxide, and the height of the first spacer formation layer 70 may be defined by a wet etching process. For example, a layer of material is preferably formed on the conductive pattern 55 and the second inner insulating layer 40 to form the first spacer forming layer 70, followed by etching (such as wet etching) on the formed structure. The first spacer wall is adjusted to form a south degree of the layer 70. Therefore, the tip end surface of the first spacer formation layer 7〇 is formed between the top end surface 61 of the cap layer 60 and the bottom surface 51 of the bit line 5〇, and the tip end surface 71 of the first spacer formation layer 7G is most appropriate. It is substantially below the top surface 61 of the cap layer 6 or about 100-2000 angstroms above the bottom surface 51 of the bit line 50. Alternatively, the top end surface of the first spacer forming layer 7 is placed at an intermediate position between the top end surface 61 of the cap layer 60 and the bottom surface 51 of the bit line 5A. With reference to the 2C diagram, a conventional second spacer formation layer 80 is formed on the pattern by a conventional method such as the Lp_CVD process, and the f-gap formation layer 8 is suitably used and formed. - the material of the gap wall $ V layer (such as a oxidized stone eve) having a material composition ratio of the surname selection ratio is favored by the second spacer formation layer 8 〇, the first spacer formation layer is most suitably The lower dielectric constant (lower coefficient), the second spacer formation layer 80 may be composed of, for example, tantalum nitride, and its thickness is preferably (8) angstroms. Those skilled in the art will be able to use materials having suitable etch rates and dielectric constants within the scope and spirit of the present invention. 10 1262574 Next, referring to FIG. 2D, a conventional inner layer such as lPCVD or HDP CVD is used to form a second inner layer and a bain edge layer 90 on the conformal two-gap formation layer 8〇. Preferably, the inner insulating layer has a #selective ratio to the second spacer forming layer 80, and the third inner insulating layer 9 is preferably made of the same material as the first spacer forming layer 70, and then is flattened by conventional means. The third inner insulating layer 90 is planarized by a chemical technique. Next, a second spacer formation layer 80 (as shown in FIG. 3C) is used as an etch barrier, and an opening 92 is formed in the third inner insulating layer 90 to expose a region of the second spacer formation layer 80. It will be formed between adjacent conductive patterns % and automatically aligned by the second spacer forming layer 8 . Referring to FIG. 2E, in accordance with a preferred embodiment of the present invention, the exposed region of the second spacer formation layer 8 G may preferably be removed (4) or removed to expose portions of the first spacer formation layer 7G. (The opening 92 will form a region of the layer 70 by the first spacer). Next, referring to the 2nd FSI, a storage node contact opening 1〇〇 may be formed in the first spacer layer 7〇 and the second inner insulating layer 4G: the formation of the storage node contact opening is transmitted through Using the second formation layer 80 (having a flat upper surface that is not etched) as an etch mask to etch the second spacer formation layer 70 and the second inner isolation layer 4 (), the storage section = the 妾 window opening 100 extends through The second inner insulating layer 4 is a part of the contact pad 30. *The way out is in the manufacturing process, because the second spacer forming layer 80 is used to etch the mask, the first spacer forming layer 70 is exposed: the etching is also etched, so a single layer spacer is formed. 85,,, single layer, and surface portion 1262574 The side walls formed on the side walls of the conductive pattern 55 are stacked thereon. The storage node contacts ^ is transparently formed between the adjacent conductive patterns 55 because of the second alignment, and the early interlayer spacers 85 contact the window opening 10 with the storage node. At the same time, the shape of the towel 'SAC is finer than the _ gap is in; = only to start ' as in 1D to 1E; in other words, open: formed into ί T, edge layer 190 before and carry out SAC contact window:饨二&gt; t刖' the tantalum nitride layer 180 will be etched back to form no gaps 180', so in the SAC (four) over two green ^ sufficient shoulder width or _ margin, the known short circuit is now ^ The :: wall then 'will consume more spacers, resulting in an unexpected short circuit, such as between the bit line 150 and the contact 塾 130. SAC decoration + like self-knowledge technology 'according to the preferred embodiment of the present invention, the picture is taken before Jin and the _ 85, as the 2C ΙΐΓΛ 'in other words, the SAC_ process will start in the second in the top two The area that is not under (4) (such as the top part), so there is a relatively flat area. The edge area is thicker than that of f. In the second step of the contact window opening 1GG, the first exposure is observed. The layer 80 is formed, and the SAC etching is performed at the right car, = top flat area, for this reason, 4 ====lower, and then _ therefore = no connection and no consumption of mussels or 疋 abrasion, in the conductive pattern 55 Accidental short circuits between fish can therefore be avoided by adding 12 1262574 to the purity or shoulder. In the other 11⁄4 cases (as in the case of a linear contact window), even at the top of the ® 财 财 10 10 10 10 10 10 10 10 10 10 10 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在As in the previous embodiment, SAC_ is also performed before the formation of the wall and after the formation of the third inner insulating layer 90 t covering the second spacer formation layer 8 . In this case ^,. The single-layer spacer 85 may also be formed with the storage node contact window (10), and then a contact plug (not shown) is formed in the storage port (10) and connected to the contact pad. The tungsten metal can be deposited in the reservoir, and after the deposition step, a flat shot is taken; the chimney = including CMP. In one step, the 匕 匕 η 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我 自我717,

的B-B方向顯_自我對準儲存節點接 ^弟ΰ 請參照第犯圖，以上述方法形成的單面圖。 以包括-上部份87與—下部份89，上部份二隙壁85可 種與下部份89不同之材質 3 取好具有一 比如包括二氧切的第―間隙Γ形成層下^:最好是由 87最好是由比如包括氮化石夕 0構成’而上部份 因此，相對於單獨用古 ^隙土形成層80構成。 將較低係數的介電材料^ ㈤氮切來形成間隙壁， 切（比如二氧切)與較高係數的介 13 1262574 電材料層（比如氮化矽）結合可以大幅降低導線（負載）寄生 電容（比如位元線寄生電容）。因此，每個位元線可以加Λ 更多的記憶胞來改善記憶胞陣列的效率，藉以增加產率與 降低製作成本。 因此，如第3Β圖所示，上述製程的結果會在儲存節 點接觸窗100形成的區域内形成單層間隙壁85，相對的如 第3C圖所示，在線段β-Β’延伸穿過的區域内，只有未被 蝕刻的結構層（無單層間隙壁形成），這是因為單層間隙壁 85會在儲存節點接觸窗1〇〇形成的區域内以及形成的ς 形成。 、^ 假如此製程是在半導體元仙.進行，—個非記憶胞區 (未個別介紹）因此不包括單層間隙壁，如第3C圖所示的姓 構，而記憶胞的區域則包括單層間隙壁85，如上所述 3Β圖）’其中，，非記憶胞區，，就是指半導體元件内沒有記 胞的區域’比如週邊電路區、核心電路區或兩者。°心 壁，：兄明是在位元線的側壁上形成間隙 =件像=極電極。本發明也可以應用到各種:茲 2件，像是DRAM、SRAM與嵌人拉憶體的半導體^ * ㈠’本發明的制也可以應用到各種型能的^觸 :上，比如線型的接觸窗，這樣的線型接觸窗可：=觸 如形成-個具有線型凹槽垂直樺跨位元以透過比 案於内声介帝展μ m 且仏5位70線接觸窗的罩幕圖 形成“，口^方法就可以在内層介電層中 接^開口，此線型接觸窗開口的延伸方向係垂 1262574B-B direction display _ self-aligned storage node connection ΰ ΰ Please refer to the first map, the single-sided diagram formed by the above method. Including the upper portion 87 and the lower portion 89, the upper portion of the two-gap wall 85 can be made of a material different from the lower portion 89. 3 has a first-gap Γ formation layer including, for example, a dioxotomy. Preferably, the upper portion of 87 is preferably composed of, for example, including nitride rock eve 0. Therefore, it is formed with respect to the layer 80 formed alone. A lower coefficient dielectric material is cut to form a spacer. The combination of a cut (such as dioxotomy) and a higher coefficient of dielectric layer (such as tantalum nitride) can significantly reduce the parasitic (load) parasitics. Capacitance (such as bit line parasitic capacitance). Therefore, each bit line can add more memory cells to improve the efficiency of the memory cell array, thereby increasing the yield and reducing the manufacturing cost. Therefore, as shown in FIG. 3, the result of the above process will form a single-layer spacer 85 in the region where the storage node contact window 100 is formed, as shown in FIG. 3C, the line segment β-Β' extends through. Within the region, there are only structural layers that are not etched (no single-layer spacers are formed) because the single-layer spacers 85 are formed in the regions where the storage node contact openings 1 are formed and the formed defects. , ^ If the process is carried out in the semiconductor element, a non-memory cell (not individually introduced) therefore does not include a single-layer spacer, as shown in Figure 3C, and the memory cell includes a single The layer spacer 85, as described above, "wherein, the non-memory cell region" refers to a region in the semiconductor element where no cell is recorded, such as a peripheral circuit region, a core circuit region, or both. ° Heart wall,: Brother is to form a gap on the side wall of the bit line = piece image = pole electrode. The invention can also be applied to various types: two pieces, such as DRAM, SRAM, and embedded semiconductors. (1) The system of the present invention can also be applied to various types of touches, such as linear contact. Window, such a linear contact window can be: = touch-formed - a vertical birch straddle with a linear groove to form a mask image that is more than a 70-degree contact window with a 5 m line and a 位 5 position. , the mouth ^ method can be connected to the inner dielectric layer opening, the extension of the line type contact window opening is 1262574

直於位元線。接著，在線型接觸窗開口内形成導電材料， 然後平坦化形成的結構就會形成個別的儲存節點接觸墊 大體來說，在此揭露的實施例可以形成高可靠度的 SAC結構，舉例來說，利用本發明的實施例，可以減=戶 部的耗損（比如間隙壁的耗損或是蓋層的耗損），藉以二二 對、不準或製程的裕度，也可崎低位元線的貞載;容。曰J 此，因為第-間隙壁形成層7〇是在形成第三内層絕緣声 90之前就形成在導電圖案55之間與第二内層絕緣層仙^ 上，會改進間隙充填裕度，且高寬比也可以 : 變成2.5:1)，在接觸墊之間不樂見的短路^因此^ 率可it文善’另外產 丰了以改進而製作成本可以降低。 以二 =:二=揭露如上:然其並非用 請專利範圍所界定者為準。…、 儲存；侧她^ 的—ΐΓ我示係根據本發明—較佳實施例， 第3A圖觸窗之製作流程剖面圖； 圖4及 日不為―種自我對準儲存節點接觸窗之平面 1262574 第3B圖至第3C圖為沿著第3A圖的A-A’、B-B’方向 顯示的自我對準儲存節點接觸窗之剖面圖。 【主要元件符號說明】 120, 20 第一内層絕緣層 130, 30 儲存節點接觸墊 14Ό，40 第二内層絕緣層 150, 50 位元線 160, 60 蓋層 155 位元線雄疊 180 氮化矽層 180’，85 單層間隙壁 190, 90 第三内層絕緣層 200, 100 儲存節點接觸窗開口 10 半導體基底 55 導電圖案 52 導電圖案的侧壁 70 第一間隙壁形成層 61 蓋層60的頂端表面 51 位元線50的底部表面 71第一間隙壁形成層的頂端表面 80 第二間隙壁形成層 92 開口 87 單層間隙壁85的上部份 89 單層間隙壁85的下部份Straight to the bit line. Next, a conductive material is formed in the in-line contact window opening, and then the planarized structure forms an individual storage node contact pad. Generally, the disclosed embodiments can form a highly reliable SAC structure, for example, With the embodiment of the present invention, it is possible to reduce the consumption of the household (such as the wear of the gap or the wear of the cover), by the margin of the two pairs, the inaccuracy or the process, or the load of the low bit line. ; Rong. That is, since the first-gap formation layer 7 is formed between the conductive patterns 55 and the second inner insulating layer before the formation of the third inner insulating sound 90, the gap filling margin is improved and is high. The width ratio can also be: 2.5:1), a short circuit that is unpleasant between the contact pads. Therefore, the rate can be used to improve the production cost. Take two =: two = expose the above: but it is not the use of the scope of the patent as defined. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 1262574 Figures 3B through 3C are cross-sectional views of the self-aligned storage node contact window shown along the A-A', BB' direction of Figure 3A. [Main component symbol description] 120, 20 First inner insulating layer 130, 30 storage node contact pad 14A, 40 second inner insulating layer 150, 50 bit line 160, 60 cap layer 155 bit line male stack 180 tantalum nitride Layer 180', 85 single layer spacer 190, 90 third inner insulating layer 200, 100 storage node contact opening 10 semiconductor substrate 55 conductive pattern 52 conductive pattern sidewall 70 first spacer forming layer 61 top layer of cap layer 60 The bottom surface 71 of the surface 51-bit line 50, the top surface 80 of the first spacer formation layer, the second spacer formation layer 92, the opening 87, the upper portion 89 of the single-layer spacer 85, and the lower portion of the single-layer spacer 85

Claims (1)

1262574 十、申請專利範圍： 1:一種半導料件的製造方法，該方法包括： 每數個導電圖案覆蓋於-半導體基底上， 母忒些導電圖案具有一導線與―蓋層； T成一第一間隙壁形成層於相鄰曰的該 成層形成於— 共形的形成-第二間隙壁形成層於該些導電圖案上. 形成二第一内層絕緣層於該第二間隙壁形成層^;， 在该第-内層絕緣層中形成一開口延伸往該第 壁形成層之一部份；以及 永 ,、利用该第二間隙壁形成層作為一罩幕，蝕刻該第一 隙壁形成層之該部分，則彡成_單相隙 案之側壁上。 弘圖 2·如申請專利範圍第1項所述之方法，其中該第一 隙壁形成層大致上位於該蓋層之頂端表面卞方。 曰 3·如申請專利範圍第丨項所述之方法，其中該第一 隙壁形成層之頂端表面大約介於該蓋層之頂端表面以 導線之底部表面之間。 Λ 4.如申請專利範圍第丨項所述之方法，其中形成芎_ 一間隙壁形成層的步驟包括沈積〆介電層覆蓋於該牲/導^ 圖案上以及調整該介電層之高度。 μ二、兒 5·如申請專利範圍第4頊所述之方法，其中調整該八 電層之高度的步驟包括濕蝕刻該介電層。 正 18 1262574 6. 如申請專利範圍第1項所述之方法，其中共形的形 成該第二間隙壁形成層之步驟包括形成該第二間隙壁形成 層於該第一間隙壁形成層上。 7. 如申請專利範圍第1項所述之方法，其中形成一開 口的步驟包括： 、暴露該第二間隙壁形成層之一部份；以及 移除該第二間隙壁形成層暴露之該部份以暴露該第一 間隙壁形成層之一部份。 8. 如申請·專利範圍第1項所述之方法，進一步包括在 形成該開口之前平坦化該第一内層絕緣層。 9. 如申請專利範圍第1項所述之方法，其中該第二間 隙壁形成層與該第一間隙壁形成層具有一蝕刻選擇比。 10. 如申請專利範圍第8項所述之方法，其中平坦化的 該内層介電層與該第二間隙壁形成層具有一蝕刻選擇比。 11. 如申請專利範圍第1項所述之方法，其中蝕刻該第 一間隙壁形成層的暴露部分會同時形成一接觸窗開口，係 用在相鄰的該些導電圖案之間的該單層間隙壁自動對準。 12. 如申請專利範圍第11項所述之方法，進一步包括 在形成該些導電圖案之前接續形成第二與第三内層絕緣層 於該半導體基底上，該第二内層絕緣層具有一接觸墊形成 於其中。 13. 如申請專利範圍第12項所述之方法，其中該接觸 窗開口也延伸經過該第三内層絕緣層以暴露出該接觸墊之 一部份。 19 1262574 形成申請專利範㈣12柄述之方法，進—步包括 觸插塞於該接觸窗開口内以電性連接該接觸墊。 用於線二㈣1項所述之方法，其中該開口係 隙壁專鄕㈣1項所述之方法，其中該單層間 分不與—下部分，該上部分包括-與該下部 分全16項所述之方法’其中該上部 4 S垂直的堆疊在該下部分之上。 隙壁二申:有專:t 成期間平坦。 '心’且接者在該單層間隙壁形 19·-種半導體記憶體元件的製造方法 形成-第-内層絕緣層於—半導體基底上方法匕括. 形成一接觸墊於該第一内層絕緣層内·， 形成Γ第二内層絕緣層於該第—内層絶緣層上； —形风複數個相連位元線堆疊於該第二内 母一該些位元線堆疊包括一位元線與—蓋層「、、θ ， 形成-第一間隙壁形成層於位於θ 之間的該第二内層絕緣層上，該第 Μ :線隹- 表面會在該些位元線堆叠的頂端表面之下土層之頂端 形成層於該第-_形成 形成-第三内層絕緣層於該共形的第二間隙壁形成層 20 1262574 上； 形成一開口於該第三内層絕緣層内以暴露出該第二間 隙壁形成層之一部份； 移除該第二間隙壁形成層暴露之部分以暴露出該第一 間隙壁形成層之一部份； 、同時形成一單層間隙壁於該些位元線堆疊之側壁上以 及形成一接觸窗開口以該單層間隙壁自動對準在該些相鄰 位元線堆疊之間。 20. 如申請專利範圍第19項所述之方法，其中該開口 形成於該些相鄰位元線堆疊之間，該開口會利用該第二間 隙壁形成層自動對準。 21. 如申請專利範圍第19項所述之方法，其中接續形 成一單層間隙壁與一接觸窗開口的步驟包括利用該第二間 隙壁形成層作為一蝕刻罩幕，蝕刻該第一間隙壁形成層以 及該第二内層絕緣層之暴露部分。 22. —種半導體元件，包括一記憶胞區以及一非記憶胞 區，其中 該記憶胞區包括： 複數個相鄰第一導電圖案位於一半導體基底上，每一 該些第一導電圖案具有一導線與一蓋層，該些第一導電圖 案具有一單層間隙壁形成於其側壁上，其中該單層間隙壁 包括一上部份與一下部分，該上部分之材質與該下部分不 同；以及 該非記憶胞區包括： 1262574 複數個相鄰第二導電圖案覆蓋於該半導體基底上，卞 一該些第二導電圖案包括一導線與一蓋層； 母 一第一間隙壁形成層沈積在該些相鄰第二導電圖 間，該第-間随形成層形成於該蓋層之卿表面以及 導線之底部表面之間； ^ 、一第二間隙壁形成層共形的形成於該些第二導電圖案 上， ’、 第内層絕緣層形成於共形的該第二間隙壁形成声 其中在該非記憶胞區内位於相鄰該些第二導電 間的該第-與第二間隙壁形成層是不會被蝕刻的。-23·如申請專利範圍第22項所述之元件，i 分之介電常數比該上部分低。 一 μ下邛 24·如申請專利範圍第22項所述之元件，其中誃 份與該上部分具有餘刻選擇比。 25·如申請專利範圍第22項所述之元件，其中 分係全部垂直堆疊於該下部分上。 μ邛 26. —種半導體元件，係包括： 相鄰的複數個導電圖案，其係形成於一半導俨臭底 上，每:該些導電圖案具有—導線與一蓋層；n 、^第—一間隙壁，其係形成在該些導電圖案之間，且形 成在該^層之頂端表面以及該導線之底部表面之間；y ^間隙壁，其係共形地形成在該些導電圖案上； 一第一内層絕緣層，其係形絲該第二_壁形成層 22 1262574 一開口，其係形成在該第一内層絕緣層内且延伸至該 第一間隙壁形成層之一區域；以及 一單層間隙壁，其係利用該第二間隙壁形成層作為一 罩幕，蝕刻該第一間隙壁形成層的該區域，而形成在該些 導、電圖案之側壁上。 27.如申請專利範圍第26項所述之半導體元件，其中 該開口的形成步驟包括： 暴露該第二間隙壁形成層之一區域；以及 移除該第二間隙壁形成層暴露之該區域，以暴露出該 第一間隙壁形成層之一區域。 23 1262574 七、指定代表圖： (一） 本案指定代表圖為：第（2F )圖。 (二） 本代表圖之元件符號簡單說明： 10 半導體基底 20 第一内層絕緣層 30 儲存節點接觸墊 40 第二内層絕緣層 50 位元線 60 蓋層 85 單層間隙壁 90 第三内層絕緣層 100 儲存節點接觸窗開 V 55 導電圖案 80 第二間隙壁形成層 八、本案若有化學式時，請揭示最能顯示發明特徵的化學 式：1262574 X. Patent Application Range: 1: A method for manufacturing a semi-conductive material, the method comprising: covering each of a plurality of conductive patterns on a semiconductor substrate, the conductive patterns having a wire and a cap layer; a spacer layer forming layer is formed on the adjacent germanium layer - a conformal formation - a second spacer is formed on the conductive patterns. Forming two first inner insulating layers on the second spacer forming layer ^; Forming an opening in the first inner insulating layer to a portion of the first wall forming layer; and, for example, using the second spacer forming layer as a mask to etch the first gap forming layer This part is then formed on the side wall of the _ single phase gap case. The method of claim 1, wherein the first gap forming layer is substantially located on the top surface of the cap layer. The method of claim 3, wherein the top surface of the first gap forming layer is approximately between the top surface of the cap layer and the bottom surface of the wire. 4. The method of claim 2, wherein the step of forming a spacer layer comprises depositing a tantalum dielectric layer over the pattern and adjusting a height of the dielectric layer. The method of claim 4, wherein the step of adjusting the height of the eight electrical layer comprises wet etching the dielectric layer. 6. The method of claim 1, wherein the conformal forming of the second spacer forming layer comprises forming the second spacer forming layer on the first spacer forming layer. 7. The method of claim 1, wherein the forming an opening comprises: exposing a portion of the second spacer forming layer; and removing the exposed portion of the second spacer forming layer Part to expose a portion of the first spacer formation layer. 8. The method of claim 1, further comprising planarizing the first inner insulating layer prior to forming the opening. 9. The method of claim 1, wherein the second spacer formation layer has an etch selectivity ratio to the first spacer formation layer. 10. The method of claim 8, wherein the planarized inner dielectric layer and the second spacer formation layer have an etch selectivity ratio. 11. The method of claim 1, wherein etching the exposed portion of the first spacer formation layer simultaneously forms a contact opening for the single layer between adjacent conductive patterns The spacers are automatically aligned. 12. The method of claim 11, further comprising forming second and third inner insulating layers on the semiconductor substrate prior to forming the conductive patterns, the second inner insulating layer having a contact pad formed In it. 13. The method of claim 12, wherein the contact opening extends also through the third inner insulating layer to expose a portion of the contact pad. 19 1262574 Forms the method of claim 4, wherein the step further comprises inserting a plug into the opening of the contact window to electrically connect the contact pad. The method of claim 2, wherein the open chord wall is the method of (4), wherein the single layer is not related to the lower portion, the upper portion includes - and the lower portion is all 16 items The method 'where the upper portion 4 S is vertically stacked above the lower portion. The second wall of the gap: there is a special: t is flat during the period. The 'heart' is formed by the method of manufacturing the single-layer spacer 19-type semiconductor memory device. The first-inner insulating layer is formed on the semiconductor substrate. A contact pad is formed on the first inner insulating layer. In the layer, a second inner insulating layer is formed on the first inner insulating layer; a plurality of connected bit lines are stacked on the second inner mother, and the bit line stack comprises a bit line and The cap layer ", , θ , forming a first spacer forming layer on the second inner insulating layer between θ, the second 隹: 隹 - surface will be below the top surface of the bit line stack a top layer of the soil layer is formed on the first-formed-third inner insulating layer on the conformal second spacer formation layer 20 1262574; an opening is formed in the third inner insulating layer to expose the first a portion of the second spacer forming layer; removing the exposed portion of the second spacer forming layer to expose a portion of the first spacer forming layer; and simultaneously forming a single spacer in the plurality of spacers a sidewall of the line stack and forming a contact opening The method of claim 19, wherein the opening is formed between the adjacent bit line stacks, wherein the single layer spacer is automatically aligned between the adjacent bit line stacks. The method of claim 19, wherein the step of forming a single layer of spacers and a contact opening comprises using the second The spacer formation layer serves as an etching mask to etch the first spacer formation layer and the exposed portion of the second inner isolation layer. 22. A semiconductor component comprising a memory cell region and a non-memory cell region, wherein the spacer layer The memory cell region includes: a plurality of adjacent first conductive patterns on a semiconductor substrate, each of the first conductive patterns having a wire and a cap layer, wherein the first conductive patterns have a single layer of spacers formed thereon a sidewall, wherein the single-layer spacer comprises an upper portion and a lower portion, the material of the upper portion being different from the lower portion; and the non-memory cell region comprises: 1262574 a plurality of adjacent second portions An electrical pattern is disposed on the semiconductor substrate, wherein the second conductive patterns comprise a wire and a cap layer; and a first spacer formation layer is deposited between the adjacent second conductive patterns, the first-between Forming a layer formed between the surface of the cap layer and the bottom surface of the wire; ^, a second spacer forming layer is conformally formed on the second conductive patterns, and the first inner insulating layer is formed in the conformal shape The second spacers form sounds in which the first and second spacer formation layers located adjacent to the second conductive regions in the non-memory cell region are not etched. -23. In the 22th element, the dielectric constant of the i component is lower than the upper portion. The device of claim 22, wherein the component has a residual selection ratio with the upper portion. 25. The component of claim 22, wherein the components are all vertically stacked on the lower portion. The semiconductor device includes: an adjacent plurality of conductive patterns formed on a half of the conductive bottom, each of: the conductive patterns having a wire and a cap layer; n, ^ first a spacer formed between the conductive patterns and formed between a top end surface of the layer and a bottom surface of the wire; y ^ spacers formed conformally on the conductive patterns a first inner insulating layer, the second wire forming layer 22 1262574 having an opening formed in the first inner insulating layer and extending to a region of the first spacer forming layer; A single-layer spacer is formed by using the second spacer formation layer as a mask to etch the region of the first spacer formation layer to form sidewalls of the conductive and electrical patterns. 27. The semiconductor device of claim 26, wherein the forming of the opening comprises: exposing a region of the second spacer forming layer; and removing the exposed region of the second spacer forming layer, To expose a region of the first spacer formation layer. 23 1262574 VII. Designated representative map: (1) The representative representative of the case is: (2F). (b) The symbol of the representative figure is briefly described as follows: 10 semiconductor substrate 20 first inner insulating layer 30 storage node contact pad 40 second inner insulating layer 50 bit line 60 cap layer 85 single layer spacer 90 third inner insulating layer 100 Storage node contact window open V 55 Conductive pattern 80 Second spacer forming layer 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention:
TW092113946A 2003-03-31 2003-05-23 Sidewall spacer structure for self-aligned contact and method for forming the same TWI262574B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI685085B (en) * 2019-02-26 2020-02-11 華邦電子股份有限公司 Memory device and method of manufacturing the same
US11723191B2 (en) 2020-07-24 2023-08-08 Samsung Electronics Co., Ltd. Semiconductor memory devices having protruding contact portions

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100956597B1 (en) 2003-07-22 2010-05-11 주식회사 하이닉스반도체 method for fabricating semiconductor device
KR100596845B1 (en) * 2003-10-22 2006-07-04 주식회사 하이닉스반도체 Method for Forming Contact of Semiconductor Device
JP4543392B2 (en) 2005-11-01 2010-09-15 エルピーダメモリ株式会社 Manufacturing method of semiconductor device
KR100805009B1 (en) * 2006-03-02 2008-02-20 주식회사 하이닉스반도체 Method for manufacturing a semiconductor device
KR102321373B1 (en) 2015-08-19 2021-11-02 삼성전자주식회사 Method for fabricating semiconductor device
KR102572514B1 (en) * 2018-04-17 2023-08-31 삼성전자주식회사 Semiconductor device and method for manufacturing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4086926B2 (en) * 1997-01-29 2008-05-14 富士通株式会社 Semiconductor device and manufacturing method thereof
KR100334393B1 (en) * 1999-06-30 2002-05-03 박종섭 Fabricating method for semiconductor device
US6194302B1 (en) * 1999-09-30 2001-02-27 Taiwan Semiconductor Manufacturing Company Integrated process flow to improve the electrical isolation within self aligned contact structure
KR100314134B1 (en) * 1999-12-06 2001-11-15 윤종용 Semiconductor device having a self-aligned contact and fabricating method therefor
US6372525B1 (en) * 1999-12-20 2002-04-16 Taiwan Semiconductor Manufacturing Company Wafer-level antenna effect detection pattern for VLSI
KR100352909B1 (en) * 2000-03-17 2002-09-16 삼성전자 주식회사 Method of forming self-aligned contact structure in semiconductor device and self-aligned contact structure fabricated thereby
JP3410063B2 (en) * 2000-05-15 2003-05-26 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
US6380042B1 (en) * 2001-02-15 2002-04-30 Winbond Electronics Corp. Self-aligned contact process using stacked spacers

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI685085B (en) * 2019-02-26 2020-02-11 華邦電子股份有限公司 Memory device and method of manufacturing the same
US11257833B2 (en) 2019-02-26 2022-02-22 Winbond Electronics Corp. Memory device and manufacturing method thereof
US11723191B2 (en) 2020-07-24 2023-08-08 Samsung Electronics Co., Ltd. Semiconductor memory devices having protruding contact portions
TWI819288B (en) * 2020-07-24 2023-10-21 南韓商三星電子股份有限公司 Semiconductor memory devices

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