GB2400237B - Sidewall spacer structure for self-aligned contact and method for forming the same - Google Patents
Sidewall spacer structure for self-aligned contact and method for forming the sameInfo
- Publication number
- GB2400237B GB2400237B GB0327715A GB0327715A GB2400237B GB 2400237 B GB2400237 B GB 2400237B GB 0327715 A GB0327715 A GB 0327715A GB 0327715 A GB0327715 A GB 0327715A GB 2400237 B GB2400237 B GB 2400237B
- Authority
- GB
- United Kingdom
- Prior art keywords
- self
- forming
- same
- sidewall spacer
- spacer structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 125000006850 spacer group Chemical group 0.000 title 1
Classifications
-
- E—FIXED CONSTRUCTIONS
- E04—BUILDING
- E04F—FINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
- E04F13/00—Coverings or linings, e.g. for walls or ceilings
- E04F13/07—Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor
- E04F13/08—Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor composed of a plurality of similar covering or lining elements
- E04F13/0871—Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor composed of a plurality of similar covering or lining elements having an ornamental or specially shaped visible surface
- E04F13/0873—Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor composed of a plurality of similar covering or lining elements having an ornamental or specially shaped visible surface the visible surface imitating natural stone, brick work, tiled surface or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- E—FIXED CONSTRUCTIONS
- E04—BUILDING
- E04F—FINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
- E04F13/00—Coverings or linings, e.g. for walls or ceilings
- E04F13/002—Coverings or linings, e.g. for walls or ceilings made of webs, e.g. of fabrics, or wallpaper, used as coverings or linings
- E04F13/005—Stretched foil- or web-like elements attached with edge gripping devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- E—FIXED CONSTRUCTIONS
- E04—BUILDING
- E04F—FINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
- E04F2201/00—Joining sheets or plates or panels
- E04F2201/07—Joining sheets or plates or panels with connections using a special adhesive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
Landscapes
- Engineering & Computer Science (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Civil Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0019873A KR100499161B1 (en) | 2003-03-31 | 2003-03-31 | Sidewall spacer structure for self-aligned contact and method for forming the same |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0327715D0 GB0327715D0 (en) | 2003-12-31 |
GB2400237A GB2400237A (en) | 2004-10-06 |
GB2400237B true GB2400237B (en) | 2005-09-21 |
Family
ID=29997550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0327715A Expired - Lifetime GB2400237B (en) | 2003-03-31 | 2003-11-28 | Sidewall spacer structure for self-aligned contact and method for forming the same |
Country Status (6)
Country | Link |
---|---|
JP (1) | JP5107499B2 (en) |
KR (1) | KR100499161B1 (en) |
CN (1) | CN100358089C (en) |
DE (1) | DE10347458B4 (en) |
GB (1) | GB2400237B (en) |
TW (1) | TWI262574B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11723191B2 (en) | 2020-07-24 | 2023-08-08 | Samsung Electronics Co., Ltd. | Semiconductor memory devices having protruding contact portions |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100956597B1 (en) | 2003-07-22 | 2010-05-11 | 주식회사 하이닉스반도체 | method for fabricating semiconductor device |
KR100596845B1 (en) * | 2003-10-22 | 2006-07-04 | 주식회사 하이닉스반도체 | Method for Forming Contact of Semiconductor Device |
JP4543392B2 (en) | 2005-11-01 | 2010-09-15 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
KR100805009B1 (en) * | 2006-03-02 | 2008-02-20 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
KR102321373B1 (en) | 2015-08-19 | 2021-11-02 | 삼성전자주식회사 | Method for fabricating semiconductor device |
KR102572514B1 (en) * | 2018-04-17 | 2023-08-31 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
TWI685085B (en) * | 2019-02-26 | 2020-02-11 | 華邦電子股份有限公司 | Memory device and method of manufacturing the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6194302B1 (en) * | 1999-09-30 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Integrated process flow to improve the electrical isolation within self aligned contact structure |
GB2366076A (en) * | 2000-03-17 | 2002-02-27 | Samsung Electronics Co Ltd | Methods for forming integrated circuit devices through selective etching of an insulation layer to increase self-aligned contact area |
US6372575B1 (en) * | 1999-06-30 | 2002-04-16 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating capacitor of dram using self-aligned contact etching technology |
US6380042B1 (en) * | 2001-02-15 | 2002-04-30 | Winbond Electronics Corp. | Self-aligned contact process using stacked spacers |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4086926B2 (en) * | 1997-01-29 | 2008-05-14 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
KR100314134B1 (en) * | 1999-12-06 | 2001-11-15 | 윤종용 | Semiconductor device having a self-aligned contact and fabricating method therefor |
US6372525B1 (en) * | 1999-12-20 | 2002-04-16 | Taiwan Semiconductor Manufacturing Company | Wafer-level antenna effect detection pattern for VLSI |
JP3410063B2 (en) * | 2000-05-15 | 2003-05-26 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
-
2003
- 2003-03-31 KR KR10-2003-0019873A patent/KR100499161B1/en active IP Right Grant
- 2003-05-23 TW TW092113946A patent/TWI262574B/en not_active IP Right Cessation
- 2003-07-03 JP JP2003270765A patent/JP5107499B2/en not_active Expired - Fee Related
- 2003-07-21 CN CNB031328059A patent/CN100358089C/en not_active Expired - Lifetime
- 2003-10-13 DE DE10347458A patent/DE10347458B4/en not_active Expired - Lifetime
- 2003-11-28 GB GB0327715A patent/GB2400237B/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6372575B1 (en) * | 1999-06-30 | 2002-04-16 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating capacitor of dram using self-aligned contact etching technology |
US6194302B1 (en) * | 1999-09-30 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Integrated process flow to improve the electrical isolation within self aligned contact structure |
GB2366076A (en) * | 2000-03-17 | 2002-02-27 | Samsung Electronics Co Ltd | Methods for forming integrated circuit devices through selective etching of an insulation layer to increase self-aligned contact area |
US6380042B1 (en) * | 2001-02-15 | 2002-04-30 | Winbond Electronics Corp. | Self-aligned contact process using stacked spacers |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11723191B2 (en) | 2020-07-24 | 2023-08-08 | Samsung Electronics Co., Ltd. | Semiconductor memory devices having protruding contact portions |
Also Published As
Publication number | Publication date |
---|---|
KR100499161B1 (en) | 2005-07-01 |
KR20040085241A (en) | 2004-10-08 |
JP5107499B2 (en) | 2012-12-26 |
GB0327715D0 (en) | 2003-12-31 |
JP2004304141A (en) | 2004-10-28 |
CN1534724A (en) | 2004-10-06 |
CN100358089C (en) | 2007-12-26 |
DE10347458B4 (en) | 2007-02-08 |
GB2400237A (en) | 2004-10-06 |
TWI262574B (en) | 2006-09-21 |
TW200419711A (en) | 2004-10-01 |
DE10347458A1 (en) | 2004-10-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PE20 | Patent expired after termination of 20 years |
Expiry date: 20231127 |