GB2400237B - Sidewall spacer structure for self-aligned contact and method for forming the same - Google Patents

Sidewall spacer structure for self-aligned contact and method for forming the same

Info

Publication number
GB2400237B
GB2400237B GB0327715A GB0327715A GB2400237B GB 2400237 B GB2400237 B GB 2400237B GB 0327715 A GB0327715 A GB 0327715A GB 0327715 A GB0327715 A GB 0327715A GB 2400237 B GB2400237 B GB 2400237B
Authority
GB
United Kingdom
Prior art keywords
self
forming
same
sidewall spacer
spacer structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB0327715A
Other versions
GB0327715D0 (en
GB2400237A (en
Inventor
Dong-Jun Lee
Tae-Young Chung
Jae-Goo Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB0327715D0 publication Critical patent/GB0327715D0/en
Publication of GB2400237A publication Critical patent/GB2400237A/en
Application granted granted Critical
Publication of GB2400237B publication Critical patent/GB2400237B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04FFINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
    • E04F13/00Coverings or linings, e.g. for walls or ceilings
    • E04F13/07Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor
    • E04F13/08Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor composed of a plurality of similar covering or lining elements
    • E04F13/0871Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor composed of a plurality of similar covering or lining elements having an ornamental or specially shaped visible surface
    • E04F13/0873Coverings or linings, e.g. for walls or ceilings composed of covering or lining elements; Sub-structures therefor; Fastening means therefor composed of a plurality of similar covering or lining elements having an ornamental or specially shaped visible surface the visible surface imitating natural stone, brick work, tiled surface or the like
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04FFINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
    • E04F13/00Coverings or linings, e.g. for walls or ceilings
    • E04F13/002Coverings or linings, e.g. for walls or ceilings made of webs, e.g. of fabrics, or wallpaper, used as coverings or linings
    • E04F13/005Stretched foil- or web-like elements attached with edge gripping devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335Making a connection between the transistor and the capacitor, e.g. plug
    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04FFINISHING WORK ON BUILDINGS, e.g. STAIRS, FLOORS
    • E04F2201/00Joining sheets or plates or panels
    • E04F2201/07Joining sheets or plates or panels with connections using a special adhesive material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • H10B12/482Bit lines
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00Climate change mitigation technologies for sector-wide applications
    • Y02P80/30Reducing waste in manufacturing processes; Calculations of released waste quantities

Landscapes

  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Civil Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
GB0327715A 2003-03-31 2003-11-28 Sidewall spacer structure for self-aligned contact and method for forming the same Expired - Lifetime GB2400237B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2003-0019873A KR100499161B1 (en) 2003-03-31 2003-03-31 Sidewall spacer structure for self-aligned contact and method for forming the same

Publications (3)

Publication Number Publication Date
GB0327715D0 GB0327715D0 (en) 2003-12-31
GB2400237A GB2400237A (en) 2004-10-06
GB2400237B true GB2400237B (en) 2005-09-21

Family

ID=29997550

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0327715A Expired - Lifetime GB2400237B (en) 2003-03-31 2003-11-28 Sidewall spacer structure for self-aligned contact and method for forming the same

Country Status (6)

Country Link
JP (1) JP5107499B2 (en)
KR (1) KR100499161B1 (en)
CN (1) CN100358089C (en)
DE (1) DE10347458B4 (en)
GB (1) GB2400237B (en)
TW (1) TWI262574B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11723191B2 (en) 2020-07-24 2023-08-08 Samsung Electronics Co., Ltd. Semiconductor memory devices having protruding contact portions

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100956597B1 (en) 2003-07-22 2010-05-11 주식회사 하이닉스반도체 method for fabricating semiconductor device
KR100596845B1 (en) * 2003-10-22 2006-07-04 주식회사 하이닉스반도체 Method for Forming Contact of Semiconductor Device
JP4543392B2 (en) 2005-11-01 2010-09-15 エルピーダメモリ株式会社 Manufacturing method of semiconductor device
KR100805009B1 (en) * 2006-03-02 2008-02-20 주식회사 하이닉스반도체 Method for manufacturing a semiconductor device
KR102321373B1 (en) 2015-08-19 2021-11-02 삼성전자주식회사 Method for fabricating semiconductor device
KR102572514B1 (en) * 2018-04-17 2023-08-31 삼성전자주식회사 Semiconductor device and method for manufacturing the same
TWI685085B (en) * 2019-02-26 2020-02-11 華邦電子股份有限公司 Memory device and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194302B1 (en) * 1999-09-30 2001-02-27 Taiwan Semiconductor Manufacturing Company Integrated process flow to improve the electrical isolation within self aligned contact structure
GB2366076A (en) * 2000-03-17 2002-02-27 Samsung Electronics Co Ltd Methods for forming integrated circuit devices through selective etching of an insulation layer to increase self-aligned contact area
US6372575B1 (en) * 1999-06-30 2002-04-16 Hyundai Electronics Industries Co., Ltd. Method for fabricating capacitor of dram using self-aligned contact etching technology
US6380042B1 (en) * 2001-02-15 2002-04-30 Winbond Electronics Corp. Self-aligned contact process using stacked spacers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4086926B2 (en) * 1997-01-29 2008-05-14 富士通株式会社 Semiconductor device and manufacturing method thereof
KR100314134B1 (en) * 1999-12-06 2001-11-15 윤종용 Semiconductor device having a self-aligned contact and fabricating method therefor
US6372525B1 (en) * 1999-12-20 2002-04-16 Taiwan Semiconductor Manufacturing Company Wafer-level antenna effect detection pattern for VLSI
JP3410063B2 (en) * 2000-05-15 2003-05-26 沖電気工業株式会社 Semiconductor device and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6372575B1 (en) * 1999-06-30 2002-04-16 Hyundai Electronics Industries Co., Ltd. Method for fabricating capacitor of dram using self-aligned contact etching technology
US6194302B1 (en) * 1999-09-30 2001-02-27 Taiwan Semiconductor Manufacturing Company Integrated process flow to improve the electrical isolation within self aligned contact structure
GB2366076A (en) * 2000-03-17 2002-02-27 Samsung Electronics Co Ltd Methods for forming integrated circuit devices through selective etching of an insulation layer to increase self-aligned contact area
US6380042B1 (en) * 2001-02-15 2002-04-30 Winbond Electronics Corp. Self-aligned contact process using stacked spacers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11723191B2 (en) 2020-07-24 2023-08-08 Samsung Electronics Co., Ltd. Semiconductor memory devices having protruding contact portions

Also Published As

Publication number Publication date
KR100499161B1 (en) 2005-07-01
KR20040085241A (en) 2004-10-08
JP5107499B2 (en) 2012-12-26
GB0327715D0 (en) 2003-12-31
JP2004304141A (en) 2004-10-28
CN1534724A (en) 2004-10-06
CN100358089C (en) 2007-12-26
DE10347458B4 (en) 2007-02-08
GB2400237A (en) 2004-10-06
TWI262574B (en) 2006-09-21
TW200419711A (en) 2004-10-01
DE10347458A1 (en) 2004-10-21

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Expiry date: 20231127