TW200419711A - Sidewall spacer structure for self-aligned contact and method for forming the same - Google Patents

Abstract

In one embodiment, adjacent conductive patterns are formed overlying a semiconductor substrate. The conductive patterns each have a conductive line and a capping layer. A first spacer formation layer is formed between the adjacent conductive patterns. The first spacer formation layer is formed between the top surface of the capping layer and the bottom surface of the conductive line. A conformal second spacer formation layer is formed on the conductive patterns. A first interlayer insulating layer is formed on the conformal second spacer formation layer. Next, an opening is formed to extend to a portion of the first spacer formation layer, in the first interlayer insulating layer. The portion of the first spacer formation layer is etched, using the second spacer formation layer as an etch mask, to form a single-layer spacer on sidewalls of the conductive patterns, concurrently with a contract hole.

Description

200419711

200419711 V. Description of the invention (2) 140 A single layer gap 璧 180 / is formed on a third inner layer Shaoluo㈣. ; As shown in Figure 1 and then use the back opening 200. A kind of known automatic alignment storage node contact window + right # ^ ϋ π from the conventional SAC process shown in Figure 1A to Figure 1E, which μ μ, μ π +, τ Η #; The layer gap 璧 180, during the etch-back process, the side gap 璧] s η, rm ^ j.. _ ', Yu 8 0 can be excessively eroded by the etching machine (too bound), in this worm Age 丨 | Love ^. ^ D / month will also form a contact window opening; excessive surplus will lead to excessive money engraved on the shoulder / ten e one move ~ and / or shoulder defects, that is, it will cause along the position ^ The line 150 and the storage node contact pad 13 are electrically short-circuited. The word "shoulder 2:" refers to the thinnest part of the side exposed by the contact window opening 200 than the gap 璧 180. In addition, ra ^ 1 knife In addition, because the early layer gap 璧 180, it may be over-etched during the formation of the contact window opening 200, and the single-layer gap 璧 180-80 'may become very thin, which will increase the bit The load load valley of the line thus hinders the increase of the accumulation degree of the memory element. Therefore, when the higher accumulation density is inclined, the diameter of the opening of the contact window The reduction in height will increase the height-to-width ratio (height-to-width ratio), so it will be difficult to fill the deep and narrow contact window openings. As a result, there will be an inner dielectric layer between the lines. There are gaps. During the cleaning process (such as the wet etching process), the gaps may be exposed, causing bridging between bits and / or adjacent contact pads 13 and forming short circuits / circuits. Therefore There is a need for an improved semiconductor manufacturing method that can increase the engraving margin or gas width and reduce the load capacitance of the bit line in order to further

V. Description of the invention (3) The purpose of reducing the wear of the shoulder is to provide a semiconductor device with a clearer purpose: the above-mentioned: storage node contact window and manufacturing method thereof: on the substrate, These conductive patterns ::,: The electrical pattern can be formed in the-semiconductor layer-the gap 璧 formation layer: both have-a wire and a capping layer;-a gap 璧 formation layer prepared two / Ϊ between adjacent conductive patterns 'Between this surface;-layer: gap 璧; end surface and bottom of the wire: on the case;-layer-inner layer must =: = shape; on these conductive, an opening will form 9 formed in the brother The two gaps form a layer of the gap. The layer of insulating layer in the region extends to the first curtain, and the first gap is etched. The gap 1 is formed as an etching mask gap in the conductive pattern. In order to form a single layer, μ ^ of the present invention also forms a contact window opening. It is easy to understand, and the following specific purposes, features, and advantages can be explained in more detail as follows: The preferred embodiments and the accompanying drawings are used to make detailed implementations: Although the present invention is to limit the present invention, two The best embodiment is disclosed as follows, but it is not within the scope of God. When this artisan can not deviate from the scope of the present invention, see the attached application and retouching. Therefore, the second warranty of the present invention The eight figures are subject to the definition of the patent scope. The first figure shows 11453pif.ptd according to a preferred embodiment of the present invention. Page 10 200419711 V. Description of the invention (4) 昭昭 笛 9 ^ pair A cross-sectional view of the manufacturing process of the quasi-storage node contact window. First, please use Figure A to apply conventional techniques (such as low-pressure chemical vapor deposition and high-density plasma chemical vapor deposition (HDP — CVD)). Half-bottom: Upper: 'Layered first-inner insulation layer 2 °' Its thickness is more suitable to apply some appropriate dielectric materials, such as borophosphosilicate glass (), spin glass (SOG), plasma induced Tetraethylphosphosilicate (PE-TE0S),: Acid f glass (USG), etc. can be used The first-inner layer insulation pad 3 is 0, with electricity: ί The first inner-layer insulation layer 20 forms a storage node contact M Φ 2 connection to form a contact window with the storage node in a conventional process in a conventional process. A thick The contact pad 3 of the storage node is formed on the first inner insulating layer 20 with a first inner insulating layer 40, and the target circumference of the second inner insulating layer 40 is 100 to 300 angstroms. It is more appropriate to use a mechanical polishing method (CMP) for this second inner layer of insulation = two 'two daggers to improve the margin of the lithography process'. The thickness of the inner layer of the insulating layer 40 in a flat system is more suitably about 2 The first conductive pattern 55 with side ridges 52 will be formed in half of each of these conductive patterns 55. Each of these conductive patterns 55 includes a cover layer such as a bit conductive layer (such as a patterned bit: line 50: and -Appropriately-the type is like a thickness of 40 "0〇4;) compared to the following: Nitrogen cut kernels with a thickness of 10 ° " 〇〇 ° angstrom. This layer 60 can be selected from other suitable materials Next, please refer to FIG. 2B, the first gap 璧, 7 ,, and.-The jade forming layer 70 is preferably shaped

11453pif.ptd Page 11 200419711 V. Description of the invention (5) It is formed on the second inner layer insulating layer 40 between the conductive patterns 55. The first gap-forming layer 70 may be, for example, LP-CVD, BPSG, OP Materials such as CVD oxides or CVD oxides have relatively low coefficients or dielectric constants. The height of the first gap 璧 forming layer 70 can be defined by a wet-relief process. For example, it is better to form a layer of material on the conductive pattern 55 and the second inner insulating layer 40 to form a first gap 璧 forming layer 70, and then perform etching on the formed structure (such as wet etching) ) To adjust the height of the first gap 璧 forming layer 70. The surface 61 of the first gap 璧 forming layer 70 and the top surface 71 of the bottom layer 70 of the bit line 50 are most suitable below the surface 61, or the bottom of the bit line 50 is between 100 and 200 angstroms. Alternatively, the first gap can be formed at the top gap of 60, which can be placed between the surfaces. Please refer to the pattern gap forming material on the pattern 55 (for example, the second lower medium such as nitride is known in the Improper surnames are engraved in the middle of the top surface 61 of the cover layer 60. According to Figure 2C, it is more appropriate to form a conformal second interstitial layer 80 using conventional methods to form a second silicon oxide) A material having an etching-selective specific-gap formation layer 80, a first gap electric constant (low coefficient), and a second interlayer, and its thickness is preferably 2000-out of the scope of the present invention and the mental rate and dielectric constant. The surface will be formed between the cover layer surface 51, and the first space is about the top surface of the cover layer 60 above the top surface 60 of the cover layer 60? !! And the bottom surface of the bit line 50 looks like a material composed of a material that forms a layer 80 in the conductive rhenium during the LP-CVD process, and a second space that forms the layer 70 in the gap. The erbium-forming layer 80 may be used at a ratio of 600 angstroms. Those skilled in the art can use

200419711 V. Description of the invention (6) Next, please refer to FIG. 2D, and use the conventional CVD ^,,, AVs〇 // L; C; D ίΤ insulating layer 90, the third inner layer insulating layer 90 is 1 / The second and second inner layer layers 80 have an etching selection ratio, and the third inner sound f a gap jade formation gap 璧 formation layer 70 of the same material structure, it is best to use the third inner insulation layer 90 as the first technique. flattened. Then, using a conventional planarization technique to form a layer 80 (as shown in FIG. 3C) as a money engraver II, an opening 92 is formed in the second gap 璧, and is exposed =: in the third inner layer insulation layer 90 domain, The opening 92 is formed in a region of the formation layer 80, and the formation layer 80 is automatically aligned. ° The second space between the wood 55 and the second space is referred to FIG. 2E. According to the present invention, the area exposed by each of the formation layers 80 is preferably two, and the second gap exposes the first gap formation layer 70. _unit? Engraved or removed to form a region of the layer 70). 92 will be extended to the second eye. Referring to FIG. 2F, a storage force can be formed in the second inner insulation layer 40—a gap 璧 formation layer 70, and the contact opening 100 of the storage node and the point contact window opening 100. ， 成 成 ㈣ (has not been == through the use of the second gap 璧 shaped the first gap 璧 forming layer 70 and the second inner layer, = engraved mask, the money engraved window opening 100 will extend through the second inner layer 3 I, say 0, the storage node is in contact with a part of 30. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, etc. 5. Description of the Invention (7) The side wall of the conductive pattern 55 has additional layers stacked on the side. The gap 璧 is a single layer, and it will not be a single layer 璧 85 ^ move its ^ storage node contact window The opening 100 will be formed between the adjacent conductive patterns 55 through this single-layer gap 璧 85 and 22, because the contact opening 1100 of the contact window opening 100 is simultaneously formed in a conventional system. 1 80 ′ Only after completion is completed. The SAC rhyme engraving process is formed above the etch-back gap 璧 structure: 'as shown in Figure 1D to Figure 1 E; in other words, before the formation step, the lamella marginal layer 1 90 and the siliconized silicon layer 1 80 before the SAC contact window opening is flattened will be etched back to form no unetched and not easy to obtain = Line gap 璧 18〇, so during the SAC etching process, the line gap 璧 1 8 〇, so 2 f part visibility or etching margin, a known bit phenomenon, such as the consumption of more gaps璧, causing an accidental short-circuit Opposite: between the line 150 and the contact pad 130. SAC etching step% | / Like the conventional technology, according to the preferred embodiment of the present invention, Ϊ =… SAC remaining process will start at the first The end of the second gap = Ι ㈣ the area (such as the top part), so in the top area and the edge area will be better than the conventional 4, during the step of forming the storage = two-point contact window opening 100 will be exposed for the first time = Gap formation layer 80 ', and SAC will be performed at the top and non-engraved areas where the last name is not engraved. For this reason, the wear (such as reduction, shoulder) of gap 璧 can be greatly reduced, and the single-layer gap 璧 85 Therefore, there will be no wear or abrasion that cannot be received. The accidental short circuit between the conductive pattern 55 and the contact pads 30 can also be avoided by increasing the etch margin or shoulders.

200419711

200419711 V. Description of the invention (9) " '' Capacitance (such as bit line parasitic capacitance). Therefore, more memory cells can be added to each bit line to improve the efficiency of the memory cell array, thereby increasing productivity and reducing manufacturing costs. Therefore, as shown in FIG. 3B, the result of the above process will form a single-layer gap 璧 85 in the area formed by the storage node contact window 100, as opposed to FIG. 3C, which extends through the line segment B — β. In the passing region, there is only an unetched structural layer (no single-layer gap 璧 is formed). This is because the single-layer gap 璧 85 is formed in the area where the storage node contact window 100 is formed and when it is formed. If the process is performed in a semiconductor device, a non-memory cell region (not individually introduced) therefore does not include a single-layer gap 璧, the structure shown in Figure 3C 'and the area of the memory cell includes a single-layer gap 璧 85, As described above (Fig. 3B), the "non-memory cell region" refers to a region without a memory cell in the semiconductor element, such as a peripheral circuit region, a core circuit region, or both. ~ Although the above description of the present invention is to form a gap 璧 'on the side wall of the bit line, the principles of the present invention can also be applied to other side gaps 璧 and structures, such as gate electrodes. The present invention can also be applied to various semiconductor devices, such as semiconductor elements j, of DRAM, SRAM, and embedded memory. In addition, the principles of the present invention can also be applied to various types of contact windows, such as linear contact windows. Such a linear contact window can be formed like a contact window with a linear groove vertically across the bit line, such as an inner dielectric layer. In the above method, a linear contact window opening can be formed in the inner / J-screen pattern by the above method, and the extension line of the linear contact window opening is formed in a line. -Next, conductive ^ is formed in the opening of the linear contact window, vertical

Page 16 200419711 V. General description of the invention (10) In general, the SAC structure, such as the loss of the pE alignment or the process, is generally formed after the SAC structure is flattened, because the first room was formed before the guide. Gap filling 4: 1 becomes 2 · 5 ·· 1) Free. Therefore, the semiconductivity can be improved and manufactured. Although the present invention is limited to the present invention, within the scope of God and the protection range, when the attached structure is viewed, the individual storage node contacts will form. The embodiment disclosed here can form a highly reliable production. According to the embodiment of the present invention, the "loss of small households or the loss of cover layer" can be reduced, thereby increasing the margin and reducing the position. Load capacity of the element line: The gap forming layer 70 is formed between the third inner insulating layer 90 electrical pattern 55 and the second inner insulating layer 40, the margin, and the aspect ratio can also be greatly reduced (such as Therefore, the unpleasant short circuit between the contact pads can thus significantly improve the reliability of the avoidance element, and in addition, the production cost can be reduced. It has been disclosed above with the preferred embodiment, but it is not used with any heat Those skilled in the art can make some modifications and retouching without departing from the essence of the present invention, so the definition of the scope of the patent application of the present invention shall prevail. Μ zuuHiy / l1 Schematic illustration Schematic illustration Figure E is a flow sectional view of a node contact window. "The conventional SAC process is used to form and store Figures 2A to 2F. Figure 2A is a self-aligning storage node contact. Figure 3A is shown as a chimney A cross-sectional view of the clothing process; Figures; and Self-alignment to the plane of the contact window of the storage node to Figure 3C are A ~ A, BR, Ancient self-aligned storage nodes Λ, along Figure 3A The β-β direction shows the pattern standard ~ the cross-sectional view of the contact window. You do not explain: 120, 20 Chu ^ 130, 30 140, 40 150, 50 160, 60 The first contact pad of the inner insulation storage node Two inner layer insulation layer bit line cover layer 155 bit line stack 18 0 nitride nitride layer 180,? 85 single layer gap 璧 19 0? 9 0 ^ $ two inner layer insulation layer 20 0, 1 〇〇 Germany six ... 10 Semiconductor substrate 55 conductive pattern 52 conductive pattern 70 first gap 璧 storage point contact window opening 1 U lane «, 11453pif.ptd page 18 200419711 schematic illustration 61 top surface of the cover 60 51 bit line 5 0 Bottom surface 71 Top surface of first gap 璧 forming layer 80 Second gap 璧 forming layer 92 Opening 87 Upper part of single-layer gap 璧 85 89 Lower part of single-layer gap 璧 85

11453pif.ptd Page 19

Claims (1)

200419711 6. Application Patent Scope 1. A method for manufacturing a semiconductor device, the method includes: forming a plurality of adjacent conductive patterns to cover a semiconductor substrate, each of the conductive patterns having a conductive line and a cover layer; forming a A first gap-forming layer is formed between the adjacent conductive patterns, and the first gap-forming layer is formed between a top surface of the cover layer and a bottom surface of the wire; a second gap is formed conformally Forming a layer on the conductive patterns; forming a first inner layer insulating layer on the second gap forming layer; forming an opening in the first inner layer insulating layer extending to a portion of the first gap forming layer And using the second spacer formation layer as a mask to etch the portion of the first spacer formation layer to form a single-layer spacer on the sidewalls of the conductive patterns. 2. The method according to item 1 of the scope of patent application, wherein the first gap wall forming layer is located substantially below the top surface of the capping layer. 3. The method according to item 1 of the scope of patent application, wherein the top surface of the first gap-forming layer is approximately between the top surface of the cover layer and the bottom surface of the wire. 4. The method according to item 1 of the scope of patent application, wherein the step of forming the first spacer formation layer includes depositing a dielectric layer over the conductive patterns and adjusting the height of the dielectric layer. 5. The method according to item 4 of the scope of patent application, wherein the step of adjusting the height of the dielectric layer includes wet etching the dielectric layer. 6. The method as described in item 1 of the scope of patent application, wherein the conformal shape 11453pif.ptd Page 20 The second barrier formation method, in which the steps of forming an opening and six, applying for a patent to form the second barrier wall-shaped layer on the first barrier wall ^ layer are covered and formed 7 · If applying for a patent Fan = ^ 上. The step of mouth includes: · exposing the second gap as described in item 1; removing the second door toe formation layer 4 of the gap wall formation layer 1: the formation of the layer of mist and the wound to expose The method of J.t. of the No.-Small Patent Application, which further includes forming a layer on the gap wall: the method described in item 1 'II \ Second Intermediate II, Patent Paradigm Second = Narrative-method 'wherein the flattened 11 I: formed by the second gap wall with θ f and a wide selection ratio. -Gap? The method described in item 1 of the patent scope, wherein a contact window opening is formed during the etching of the exposed portion of the soil layer, and the single-layer gap wall between the conductive patterns adjacent to the target is automatically aligned. 12. The method according to item 11 of the patent application scope, further comprising forming second and third inner insulating layers on the semiconductor substrate successively before forming the conductive patterns, the second inner insulating layer having a contact pad Formed in it. 1 3. The method as described in item 2 of the patent application scope, wherein the contact window opening also extends through the third inner insulation layer to expose a portion of the contact pad. The method described in item 4 of the scope of the patent application, which further includes No. 21, 200419711 6. The scope of the patent application, a contact plug is formed in the opening of the contact window to electrically connect the contact pad. 1 5. The method according to item 1 of the scope of patent application, wherein the opening is for a contact window of a linear node. 16. The method according to item 1 of the scope of patent application, wherein the single-layer gap wall includes an upper portion and a lower portion, and the upper portion includes a material different from the lower portion. 1 7. The method according to item 16 of the scope of patent application, wherein the upper portion is all stacked vertically on the lower portion. 1 8. The method as described in item 1 of the scope of patent application, wherein the second gap wall forming layer has an unetched portion and is then flat during the formation of the single-layer gap wall. 1 9. A method for manufacturing a semiconductor memory device, the method comprising: forming a first inner layer insulating layer on a semiconductor substrate; forming a contact pad in the first inner layer insulating layer; forming a second inner layer insulating layer on A plurality of connected bit lines are stacked on the second inner layer insulation layer, and each of the bit line stacks includes a bit line and a cap layer; a first gap is formed; Layer on the second inner layer insulation layer between the adjacent bit line stacks, the top surface of the first spacer forming layer will be below the top surface of the bit line stacks; conformal formation A second gap-forming layer is formed on the first gap-forming layer and the bit line stacks; a third inner-layer insulating layer is formed on the conformal second gap-forming layer 11453pif.ptd Page 22 6. In the scope of the patent application; the formation of the gap; ::: the second and third inner layers of the insulating layer to expose the second containing layer-one of the gap forming layer, 3 = the exposed layer is exposed 4 points to expose the first and shape i a contact window 5 3 gap wall on the side wall of the TV line stack with bit line stacks with the single layer gap &gt; automatic alignment on the adjacent Formed in the method described in item 4b of the phase 4b of the moon next to the position-where the opening gap wall formation layer is between the stacks of the line, the opening will use the second gap 璧 formation layer as the second surplus = The step of opening includes using the second interlayer and the second inner layer insulating layer to etch the first gap 璧 to form a layer of 0 9 <Tchrome. 22 · —Semiconductor Openings> Cell area, wherein the memory cell area and a non-memory cell area include: a plurality of adjacent first conductive lines—the first conductive patterns are fortunate ^ ^, cattle On the body substrate, the mother is slaughtered and has a single glottic gap: there is a V Λ person and a cover layer, and these first conductive patterns have early layer gaps formed on their sides including-upper part and-lower,-middle The early layer gap J is the same; and the material of σ 卩 on the blade 3 and the non-memory cell area of the lower part include: 200419711 6. Scope of patent application: A plurality of adjacent second conductive patterns are covered on the semiconductor substrate. Each of the second conductive patterns includes a wire and a cap layer; a first gap-forming layer is deposited on the adjacent substrates. Between the second conductive patterns, the first gap-forming layer is formed between the top surface of the capping layer and the bottom surface of the wire; a second gap-forming layer is conformally formed on the second conductive patterns. A first inner layer insulating layer is formed on the second gap-forming layer that is conformal, wherein the first and second gap-forming layers are located between the adjacent second conductive patterns in the non-memory cell area; It will not be etched. 2 3. The component according to item 22 of the scope of patent application, wherein the dielectric constant of the lower portion is lower than that of the upper portion. 2 4. The component according to item 22 of the scope of patent application, wherein the lower portion and the upper portion have an etching selection ratio. 25. The component according to item 22 of the scope of patent application, wherein the upper part is all stacked vertically on the lower part. 2 6. A semiconductor substrate is formed through the following steps: forming a plurality of adjacent conductive patterns on a semiconductor substrate, each of the conductive patterns having a wire and a capping layer; forming a first gap-forming layer Between the adjacent conductive patterns, the first gap-forming layer is formed between the top surface of the capping layer and the bottom surface of the wire; a second gap-forming layer is conformally formed between the conductive patterns. On a conductive pattern; 11453pif.ptd Page 24 200419711 Sixth, the scope of the patent application forms a first inner layer insulation layer on the second gap formation layer; an opening is formed in the first inner layer insulation layer and extends to the first gap formation layer. A region; and using the second gap-forming layer as a mask to etch the region of the first gap-forming layer, thereby forming a single-layer gap on the sidewalls of the conductive patterns. 2 7. The component according to item 26 of the scope of patent application, wherein the step of forming the opening comprises: exposing an area of the second gap-forming layer; and removing the area exposed by the second gap-forming layer To expose a region of the first gap-forming layer. 11453pif.ptd Page 25