TW200419711A - Sidewall spacer structure for self-aligned contact and method for forming the same - Google Patents
Sidewall spacer structure for self-aligned contact and method for forming the same Download PDFInfo
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- TW200419711A TW200419711A TW092113946A TW92113946A TW200419711A TW 200419711 A TW200419711 A TW 200419711A TW 092113946 A TW092113946 A TW 092113946A TW 92113946 A TW92113946 A TW 92113946A TW 200419711 A TW200419711 A TW 200419711A
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- 125000006850 spacer group Chemical group 0.000 title claims abstract 14
- 238000000034 method Methods 0.000 title claims description 45
- 239000010410 layer Substances 0.000 claims abstract description 182
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 34
- 239000002356 single layer Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 4
- 238000009413 insulation Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims 3
- 241000283690 Bos taurus Species 0.000 claims 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 239000003595 mist Substances 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- 238000003860 storage Methods 0.000 description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010977 jade Substances 0.000 description 2
- 241000446313 Lamella Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000003340 mental effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 nitride nitride Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000005328 spin glass Effects 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
200419711200419711
200419711 五、發明說明(2) 140上形成一第三内層绍絡 ㈣的單層間隙璧180 /為=。;照第1£圖,接著用回 開口 2〇〇。 種白知的自動對準儲存節點接觸窗 +右# ^ ϋ π由ί 1 A圖至第1 E圖所示的習知SAC製程,其 μ μ、μ π + , τ Η# ; 在形成早層間隙璧180,的回蝕 刻的過程中,側璧間隙辟]s η , r m ^ j. . _ '、玉8 0可此會被蝕刻機器過度侵蝕 (受的太缚),在這名虫岁丨|爱 ^ . ^ d /月間也會形成接觸窗開口;過度侵 餘會導致肩部過度钱刻以乃/十e 一 挪〜以及/或肩部缺陷,也就是會導致 沿著位^線150與儲存節點接觸墊13〇產生電性短路,在此 用到的詞”肩二:指的是被接觸窗開口 2〇〇暴露出來的側比 間隙璧1 8 0最薄的部分。另外 ra ^ 1刀 另外,因為早層間隙璧1 8 0,可能 會在接觸窗開口 200的形成期間被過度蝕刻,單層間隙璧 1一80’的厚度可能會變的很薄,這會增加位元線的負載電 谷’因此妨礙了 §己憶體元件積集度的增加。 此^卜,當傾向較高積集密度時,接觸窗開口的口徑會 縮小而高度會增加,因此會使高寬比(高對寬的比例)增 加,因此要填滿深又窄的接觸窗開口會很困難,結果^ 線之間的内層介電層中就會有空隙存在,在清潔的過程 (比如說濕蝕刻過程)中空隙可能會被揭開,而造成位元 之間以及/或相鄰接觸墊13〇之間的橋接,而形成短路電/ 路。 因此,需要一種改良的半導體製造方法,可以增加 刻裕度或气部寬度,並減少位元線的負載電容,以進—步200419711 V. Description of the invention (2) 140 A single layer gap 璧 180 / is formed on a third inner layer Shaoluo㈣. ; As shown in Figure 1 and then use the back opening 200. A kind of known automatic alignment storage node contact window + right # ^ ϋ π from the conventional SAC process shown in Figure 1A to Figure 1E, which μ μ, μ π +, τ Η #; The layer gap 璧 180, during the etch-back process, the side gap 璧] s η, rm ^ j.. _ ', Yu 8 0 can be excessively eroded by the etching machine (too bound), in this worm Age 丨 | Love ^. ^ D / month will also form a contact window opening; excessive surplus will lead to excessive money engraved on the shoulder / ten e one move ~ and / or shoulder defects, that is, it will cause along the position ^ The line 150 and the storage node contact pad 13 are electrically short-circuited. The word "shoulder 2:" refers to the thinnest part of the side exposed by the contact window opening 200 than the gap 璧 180. In addition, ra ^ 1 knife In addition, because the early layer gap 璧 180, it may be over-etched during the formation of the contact window opening 200, and the single-layer gap 璧 180-80 'may become very thin, which will increase the bit The load load valley of the line thus hinders the increase of the accumulation degree of the memory element. Therefore, when the higher accumulation density is inclined, the diameter of the opening of the contact window The reduction in height will increase the height-to-width ratio (height-to-width ratio), so it will be difficult to fill the deep and narrow contact window openings. As a result, there will be an inner dielectric layer between the lines. There are gaps. During the cleaning process (such as the wet etching process), the gaps may be exposed, causing bridging between bits and / or adjacent contact pads 13 and forming short circuits / circuits. Therefore There is a need for an improved semiconductor manufacturing method that can increase the engraving margin or gas width and reduce the load capacitance of the bit line in order to further
五、發明說明(3) 降低肩部的耗損 發明内容 、 有更的明的目的就是在提供一種半導體元件,目 不會:現上述的::儲存節點接觸窗以及其製作方法,: 基底上,這些導電圖::,:電圖案可以形成在-半導體 層第-間隙璧形成層: 都具有-導線與一蓋層;— 一間隙璧形成層备形二/Ϊ在相鄰的導電圖案之間’此第 面之間;-層第:間隙璧;端表面與導線的底部表 :案上;-層第-内層絕=:=形;在這些導電 上,一個開口會形成 曰9形成在弟二間隙璧形成層 隙璧形成層的一區内層絕緣層中,延伸往第一間 幕,蝕刻第一間1 ε —間隙璧形成層作為蝕刻罩 隙璧於導電圖以::ί層r區域,以形成一個單層間 為讓本發明之μ ^ 同恰形成一個接觸窗開口。 顯易懂,下文特舉一他目的、特徵、和優點能更明 細說明如下: 較佳貫施例,並配合所附圖式,作詳 實施方式: 雖然本發明ρ 以限定本發明,:二;佳實施例揭露如下,然其並非用 神和範圍内,當可4 ”此技藝者,在不脫離本發明之精 護範圍當視後附之申動與潤飾’因此本發明之保 第2八圖$ j爻申睛專利範圍所界定者為準。 一圖繪示係根據本發明一較佳實施例,的 11453pif.ptd 第10頁 200419711 五、發明說明(4) 矢昭笛9^對準儲存節點接觸窗之製作流程剖面圖。首先請 A 圖,利用習知的技術(比如低壓化學氣相沈積法 首辨且或是高密度電漿化學氣相沈積法(HDP — CVD))在半 底:。上:'積一層第-内層絕緣層2° ’其厚度較適當 涂些適當的介電材料,像是硼磷矽酸玻璃()、旋 璃(S〇G)、電漿誘導的四乙基磷矽酸鹽(PE-TE0S)、 的:酸f玻璃(USG)等都可以用來形成第-内層絕 墊3曰〇,以電:;ί第一内層絕緣層2〇内形成儲存節點接觸 Μ Φ 2連接以習知製程形成與儲存節點接觸窗在一 超的主動區。 一厚ί著Ϊ ΐ存節點接觸墊3 〇與第一内層絕緣層2 0上形成 ^第一内層絕緣層4〇,第二内層絕緣層4〇的 的靶圍為1 00 0至30〇〇埃,較適當的是利 ς ^田 機械研磨法(CMP)對此第二内層絕緣層=二’ 二匕,以改善微影製程的餘裕’在平坦製 内層絕緣層40的厚度較適當是約為2〇〇〇埃。 匕第一 具有側璧52的導電圖案55會形成在半 這些導電圖案55每一個包括像是位 一導Π 蓋層6〇(比如一層圖案化的位 :線5〇:及- 適當是由-種像是厚度為40"0〇4;)之導此較 i: 厚度為10°"〇〇°埃的氮切形 仁疋此i層60選疋可以由其他適當的材 接著,請參照第2B圖,第一間隙璧, 7、、成。 - 玉形成層70較佳是形V. Description of the invention (3) The purpose of reducing the wear of the shoulder is to provide a semiconductor device with a clearer purpose: the above-mentioned: storage node contact window and manufacturing method thereof: on the substrate, These conductive patterns ::,: The electrical pattern can be formed in the-semiconductor layer-the gap 璧 formation layer: both have-a wire and a capping layer;-a gap 璧 formation layer prepared two / Ϊ between adjacent conductive patterns 'Between this surface;-layer: gap 璧; end surface and bottom of the wire: on the case;-layer-inner layer must =: = shape; on these conductive, an opening will form 9 formed in the brother The two gaps form a layer of the gap. The layer of insulating layer in the region extends to the first curtain, and the first gap is etched. The gap 1 is formed as an etching mask gap in the conductive pattern. In order to form a single layer, μ ^ of the present invention also forms a contact window opening. It is easy to understand, and the following specific purposes, features, and advantages can be explained in more detail as follows: The preferred embodiments and the accompanying drawings are used to make detailed implementations: Although the present invention is to limit the present invention, two The best embodiment is disclosed as follows, but it is not within the scope of God. When this artisan can not deviate from the scope of the present invention, see the attached application and retouching. Therefore, the second warranty of the present invention The eight figures are subject to the definition of the patent scope. The first figure shows 11453pif.ptd according to a preferred embodiment of the present invention. Page 10 200419711 V. Description of the invention (4) 昭昭 笛 9 ^ pair A cross-sectional view of the manufacturing process of the quasi-storage node contact window. First, please use Figure A to apply conventional techniques (such as low-pressure chemical vapor deposition and high-density plasma chemical vapor deposition (HDP — CVD)). Half-bottom: Upper: 'Layered first-inner insulation layer 2 °' Its thickness is more suitable to apply some appropriate dielectric materials, such as borophosphosilicate glass (), spin glass (SOG), plasma induced Tetraethylphosphosilicate (PE-TE0S),: Acid f glass (USG), etc. can be used The first-inner layer insulation pad 3 is 0, with electricity: ί The first inner-layer insulation layer 20 forms a storage node contact M Φ 2 connection to form a contact window with the storage node in a conventional process in a conventional process. A thick The contact pad 3 of the storage node is formed on the first inner insulating layer 20 with a first inner insulating layer 40, and the target circumference of the second inner insulating layer 40 is 100 to 300 angstroms. It is more appropriate to use a mechanical polishing method (CMP) for this second inner layer of insulation = two 'two daggers to improve the margin of the lithography process'. The thickness of the inner layer of the insulating layer 40 in a flat system is more suitably about 2 The first conductive pattern 55 with side ridges 52 will be formed in half of each of these conductive patterns 55. Each of these conductive patterns 55 includes a cover layer such as a bit conductive layer (such as a patterned bit: line 50: and -Appropriately-the type is like a thickness of 40 "0〇4;) compared to the following: Nitrogen cut kernels with a thickness of 10 ° " 〇〇 ° angstrom. This layer 60 can be selected from other suitable materials Next, please refer to FIG. 2B, the first gap 璧, 7 ,, and.-The jade forming layer 70 is preferably shaped
11453pif.ptd 第11頁 200419711 五、發明說明(5) 成在導電圖案55之間的第二内層絕緣層4〇上,此第一間隙 璧形成層70可以是比如LP-CVD、BPSG、〇Ρ或CVD氧化物等 具有相對較低係數或介電常數的材質,第一間隙璧形成層 7 〇的高度可以透過濕餘刻製程來加以定義。舉個例子來 說,最好將一層材料層形成在導電圖案55與第二内層絕緣 層4 0上’以形成第一間隙璧形成層7 0,接著在形成的結構 上進行蝕刻(比如濕蝕刻)以調整第一間隙璧形成層7〇的高 度。 ,第一間隙璧形成層7 0的 表面61以及位元線50的底 層70的頂端表面71最適當 表面61之下,或是在位元線50的底 1 0 0 - 2 0 0 0埃。或者是,第一間隙璧 因此 6 0的頂端 隙璧形成 可以被放 面5 1之間 請參 圖案55上 隙璧形成 料(比如二 於第二間 較低的介 如氮化石夕 均知在不 當的姓刻 置在蓋層60的頂端表面61 的中間位置處。 照弟2 C圖,用習知的方法 形成一層共形的第二間隙 層80較適當是用與形成第 二氧化矽)具有蝕刻選擇比 隙璧形成層8 0,第一間隙 電常數(低係數),第二間 構成,其厚度較佳為2〇〇 -脫離本發明的範圍與精神 率與介電常數的材料。 表面會形成在蓋層 部表面5 1之間,第一間 是大致在蓋層6 0的頂端 部表面5 1上方約 形成層70的頂端表面?! 以及位元線50的底部表 像是LP-CVD製程在導電 璧形成層8 0,此第二間 一間隙璧形成層7〇之材 的一種材料構成,相較 璧形成層最適當是具有 隙璧形成層80可以用比 6 0 〇埃。熟習此技藝者 之内,可以採用具有適11453pif.ptd Page 11 200419711 V. Description of the invention (5) It is formed on the second inner layer insulating layer 40 between the conductive patterns 55. The first gap-forming layer 70 may be, for example, LP-CVD, BPSG, OP Materials such as CVD oxides or CVD oxides have relatively low coefficients or dielectric constants. The height of the first gap 璧 forming layer 70 can be defined by a wet-relief process. For example, it is better to form a layer of material on the conductive pattern 55 and the second inner insulating layer 40 to form a first gap 璧 forming layer 70, and then perform etching on the formed structure (such as wet etching) ) To adjust the height of the first gap 璧 forming layer 70. The surface 61 of the first gap 璧 forming layer 70 and the top surface 71 of the bottom layer 70 of the bit line 50 are most suitable below the surface 61, or the bottom of the bit line 50 is between 100 and 200 angstroms. Alternatively, the first gap can be formed at the top gap of 60, which can be placed between the surfaces. Please refer to the pattern gap forming material on the pattern 55 (for example, the second lower medium such as nitride is known in the Improper surnames are engraved in the middle of the top surface 61 of the cover layer 60. According to Figure 2C, it is more appropriate to form a conformal second interstitial layer 80 using conventional methods to form a second silicon oxide) A material having an etching-selective specific-gap formation layer 80, a first gap electric constant (low coefficient), and a second interlayer, and its thickness is preferably 2000-out of the scope of the present invention and the mental rate and dielectric constant. The surface will be formed between the cover layer surface 51, and the first space is about the top surface of the cover layer 60 above the top surface 60 of the cover layer 60? !! And the bottom surface of the bit line 50 looks like a material composed of a material that forms a layer 80 in the conductive rhenium during the LP-CVD process, and a second space that forms the layer 70 in the gap. The erbium-forming layer 80 may be used at a ratio of 600 angstroms. Those skilled in the art can use
200419711 五、發明說明(6) 接著請參照第2D圖,用習知 CVD ^ , , , AVs〇?//L;C;D ίΤ 絕緣層90,此第三内層絕緣層9〇較盘成一/第、二内層 層80具有蝕刻選擇比,第三内声 f 一間隙玉形成 間隙璧形成層70相同的材料構^、巴妙广〇最好是用與第一 術將第三内層絕緣層90平坦化。接j後用習知的平坦化技 成層80(如第3C圖)作為钱刻 者二利用第二間隙璧形 内形成-個開口92,暴露出=:在第三内層絕緣層9〇 域,此開口 92會形成在=形成層80的一區 隙璧形成層80自動對準。 °木55之間亚利用第二間 凊參照第2Ε圖,根據本發明的較佳每 璧形成層80暴露出來的區域最好 二也例,第二間隙 露出第一間隙璧形成層7〇的_部?刻或移除,以暴 一間隙璧形成層70的一區域)。92會被延伸往第 接著睛參照第2 F圖,可以a楚 二内層絕緣層40中形成一個儲力—一間隙璧形成層7〇與第 儲存節點接觸窗開口100 子即點接觸窗開口100,此 成㈣(具有未被㈣的== 過利用第二間隙璧形 第一間隙璧形成層70與第二内層、=餘刻罩幕,钱刻 窗開口100會延伸穿過第二内層3絕I、曰0、,儲存節點接觸 3 0的一部分。 、、、、、,曰4 〇以暴露出接觸墊 刻罩幕進行中第璧形成層8。作為# 也會糊到,所以會形成單以 五、發明說明(7) 導電圖案55的側壁 有額外的層堆疊於复 > 成的側璧間隙璧是一單層,而不會 單層間隙璧85 ^動其^儲存節點接觸窗開口1〇〇會透過 此單層間隙璧8 5备2準形成於相鄰的導電圖案5 5之間,因 在習知的製^ f健存節點接觸窗開口 1 00同時形成。 1 80 ’完成以後才開 ’ SAC韻刻製程是在回蝕刻間隙璧 結構上方形成第:’如第1 D圖至第1 E圖;換句話說,在 形成步驟之前,纟巴緣層1 90以前以及進行SAC接觸窗開口 刻平坦區域的位虱化矽層1 80會被回蝕刻以形成沒有未蝕 並不容易得到=線間隙璧18〇,,因此在SAC蝕刻過程中 線間隙璧1 8 〇,因此2 f部見度或是蝕刻裕度,習知的位元 現象,比如在朽-^消耗更多的間隙璧,導致意外的短路 相對的::線150與接觸墊130之間。 SAC蝕刻步% | /象習知技術,根據本發明之較佳實施例, Ϊ = …SAC餘刻製程開始會在第二間隙璧 端=Ιί被㈣的區域(比如頂端部分),因此在頂 ΪΪ 域且邊緣區域會比習知的4,在形成 儲=二點接觸窗開口100的步驟進行期間會首次暴露出第 =隙璧形成層80 ’而SAC餘刻會在具有未被姓刻的頂端 、’正區域處進行,因為這個原因間隙璧的耗損(比如減少 ,肩部)可以大幅降低,單層間隙璧85因此不會有無法接 文的耗損或是磨蝕產生,在導電圖案55與接觸墊3〇之間的 意外短路也因此可以藉由增加蝕刻裕度或肩部來加以避 免0200419711 V. Description of the invention (6) Next, please refer to FIG. 2D, and use the conventional CVD ^,,, AVs〇 // L; C; D ίΤ insulating layer 90, the third inner layer insulating layer 90 is 1 / The second and second inner layer layers 80 have an etching selection ratio, and the third inner sound f a gap jade formation gap 璧 formation layer 70 of the same material structure, it is best to use the third inner insulation layer 90 as the first technique. flattened. Then, using a conventional planarization technique to form a layer 80 (as shown in FIG. 3C) as a money engraver II, an opening 92 is formed in the second gap 璧, and is exposed =: in the third inner layer insulation layer 90 domain, The opening 92 is formed in a region of the formation layer 80, and the formation layer 80 is automatically aligned. ° The second space between the wood 55 and the second space is referred to FIG. 2E. According to the present invention, the area exposed by each of the formation layers 80 is preferably two, and the second gap exposes the first gap formation layer 70. _unit? Engraved or removed to form a region of the layer 70). 92 will be extended to the second eye. Referring to FIG. 2F, a storage force can be formed in the second inner insulation layer 40—a gap 璧 formation layer 70, and the contact opening 100 of the storage node and the point contact window opening 100. , 成 成 ㈣ (has not been == through the use of the second gap 璧 shaped the first gap 璧 forming layer 70 and the second inner layer, = engraved mask, the money engraved window opening 100 will extend through the second inner layer 3 I, say 0, the storage node is in contact with a part of 30. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, etc. 5. Description of the Invention (7) The side wall of the conductive pattern 55 has additional layers stacked on the side. The gap 璧 is a single layer, and it will not be a single layer 璧 85 ^ move its ^ storage node contact window The opening 100 will be formed between the adjacent conductive patterns 55 through this single-layer gap 璧 85 and 22, because the contact opening 1100 of the contact window opening 100 is simultaneously formed in a conventional system. 1 80 ′ Only after completion is completed. The SAC rhyme engraving process is formed above the etch-back gap 璧 structure: 'as shown in Figure 1D to Figure 1 E; in other words, before the formation step, the lamella marginal layer 1 90 and the siliconized silicon layer 1 80 before the SAC contact window opening is flattened will be etched back to form no unetched and not easy to obtain = Line gap 璧 18〇, so during the SAC etching process, the line gap 璧 1 8 〇, so 2 f part visibility or etching margin, a known bit phenomenon, such as the consumption of more gaps璧, causing an accidental short-circuit Opposite: between the line 150 and the contact pad 130. SAC etching step% | / Like the conventional technology, according to the preferred embodiment of the present invention, Ϊ =… SAC remaining process will start at the first The end of the second gap = Ι ㈣ the area (such as the top part), so in the top area and the edge area will be better than the conventional 4, during the step of forming the storage = two-point contact window opening 100 will be exposed for the first time = Gap formation layer 80 ', and SAC will be performed at the top and non-engraved areas where the last name is not engraved. For this reason, the wear (such as reduction, shoulder) of gap 璧 can be greatly reduced, and the single-layer gap 璧 85 Therefore, there will be no wear or abrasion that cannot be received. The accidental short circuit between the conductive pattern 55 and the contact pads 30 can also be avoided by increasing the etch margin or shoulders.
200419711200419711
200419711 五、發明說明(9) " ' ' ' 電容(比如位元線寄生電容)。因此,每個位元線可以加入 更多的記憶胞來改善記憶胞陣列的效率,藉以增加產率與 降低製作成本。 、 因此’如第3B圖所示,上述製程的結果會在儲存節點 接觸窗1 00形成的區域内形成單層間隙璧85,相對的如第 3C圖所不’在線段Β — β,延伸穿過的區域内,只有未被蝕刻 的結構層(無單層間隙璧形成),這是因為單層間隙璧85會 在儲存節點接觸窗1 0 0形成的區域内以及形成的時候形 成。 假如此製程是在半導體元件内進行,一個非記憶胞區 (未個別介紹)因此不包括單層間隙璧,如第3C圖所示的結 構’而記憶胞的區域則包括單層間隙璧85,如上所述(第 3B圖),其中”非記憶胞區”就是指半導體元件内沒有記憶 胞的區域’比如週邊電路區、核心電路區或兩者。 〜 雖然本發明上面的說明是在位元線的側壁上形成間隙 璧’但是本發明的原則也可以應用到其他的側璧間隙璧、社 構上,像是閘極電極。本發明也可以應用到各種衽邙: 體元件,像是DRAM、SRAM與嵌入式記憶體的半導體元j、 上。此外,本發明的原則也可以應用到各種 = 上’比如線型的接觸窗,這樣的線型接觸窗可:类接觸窗 形成一個具有線型凹槽垂直橫跨位元線接 =比如 於内層介電層上,用上述的方法就可以在内/ J幕圖案 成線型接觸窗開口,此線型接觸窗開口的延^^層中形 於位兀線。-接著,在線型接觸窗開口内形成導電^,垂直 十午200419711 V. Description of the invention (9) " '' Capacitance (such as bit line parasitic capacitance). Therefore, more memory cells can be added to each bit line to improve the efficiency of the memory cell array, thereby increasing productivity and reducing manufacturing costs. Therefore, as shown in FIG. 3B, the result of the above process will form a single-layer gap 璧 85 in the area formed by the storage node contact window 100, as opposed to FIG. 3C, which extends through the line segment B — β. In the passing region, there is only an unetched structural layer (no single-layer gap 璧 is formed). This is because the single-layer gap 璧 85 is formed in the area where the storage node contact window 100 is formed and when it is formed. If the process is performed in a semiconductor device, a non-memory cell region (not individually introduced) therefore does not include a single-layer gap 璧, the structure shown in Figure 3C 'and the area of the memory cell includes a single-layer gap 璧 85, As described above (Fig. 3B), the "non-memory cell region" refers to a region without a memory cell in the semiconductor element, such as a peripheral circuit region, a core circuit region, or both. ~ Although the above description of the present invention is to form a gap 璧 'on the side wall of the bit line, the principles of the present invention can also be applied to other side gaps 璧 and structures, such as gate electrodes. The present invention can also be applied to various semiconductor devices, such as semiconductor elements j, of DRAM, SRAM, and embedded memory. In addition, the principles of the present invention can also be applied to various types of contact windows, such as linear contact windows. Such a linear contact window can be formed like a contact window with a linear groove vertically across the bit line, such as an inner dielectric layer. In the above method, a linear contact window opening can be formed in the inner / J-screen pattern by the above method, and the extension line of the linear contact window opening is formed in a line. -Next, conductive ^ is formed in the opening of the linear contact window, vertical
第16頁 200419711 五、發明說明(10) 後平坦化形成的 大體來說, SAC結構,舉例与 部的耗損(比如pE 對不準或製程的 此,因為第一間 之前就形成在導 會改進間隙充填 4 : 1 變成 2 · 5 ·· 1 ) 免。 因此,半導 率可以改進而製 雖然本發明 以限定本發明, 神和範圍内,當 護範圍當視後附 結構就會形成個別的儲存節點接觸塾。 在此揭露的實施例可以形成高可靠产的 1說,利用本發明的實施例,可以減"少戶 巧隙璧的耗損或是蓋層的耗損),藉以增加 裕度,也可以降低位元線的負載電容: 隙璧形成層70是在形成第三内層絕緣層9〇 電圖案55之間與第二内層絕緣層4〇之上, 裕度,且高寬比也可以大幅縮小(比如由 ,在接觸墊之間不樂見的短路可以因此避 體兀件的可靠度可以明顯的改善,另外產 作成本可以降低。 已以=較佳實施例揭露如上,然其並非用 任何热習此技藝者,在不脫離本發明之精 可作些許之更動與潤飾,因此本發明之= 之申請專利範圍所界定者為準。 μ zuuHiy/l1 圖式簡單說明 圖式簡單說明 第1A圖至第〗E圖係 節點接觸窗之流程剖面圖·’用習知的SAC製程來形成儲存 第2A圖至第2F圖繪系 一種自我對準儲存節點接觸f據^發明一較佳實施例,的 第3A圖繪示為一 、囪之衣作流程剖面圖; 圖;,及 我對準儲存節點接觸窗之平面 的自我對ΐ至第3C圖為沿著第3A圖的A〜A,、B R,古 的自我對準儲存節 Λ 、β — β方向顯示 圖式標干〜 接觸窗之剖面圖。 w八你不說明: 120, 20 楚 ^ „ 130, 30 140,40 150, 50 160, 60 弟一内層絕緣層 儲存節點接觸墊 第二内層絕緣層 位元線 蓋層 155 位元線堆疊 18 0 氮化石夕層 18〇,? 85單層間隙璧 19 0? 9 0 ^ $二内層絕緣層 20 0, 1 〇〇 德六… 10 半導體基底 55 導電圖案 52 導電圖案的 70 第一間隙璧 儲存郎點接觸窗開口 1 U 车道 «、 11453pif.ptd 第18頁 200419711 圖式簡單說明 61 蓋層60的頂端表面 51 位元線5 0的底部表面 71 第一間隙璧形成層的頂端表面 80 第二間隙璧形成層 92 開口 87 單層間隙璧85的上部份 89 單層間隙璧85的下部份Page 16 200419711 V. General description of the invention (10) In general, the SAC structure, such as the loss of the pE alignment or the process, is generally formed after the SAC structure is flattened, because the first room was formed before the guide. Gap filling 4: 1 becomes 2 · 5 ·· 1) Free. Therefore, the semiconductivity can be improved and manufactured. Although the present invention is limited to the present invention, within the scope of God and the protection range, when the attached structure is viewed, the individual storage node contacts will form. The embodiment disclosed here can form a highly reliable production. According to the embodiment of the present invention, the "loss of small households or the loss of cover layer" can be reduced, thereby increasing the margin and reducing the position. Load capacity of the element line: The gap forming layer 70 is formed between the third inner insulating layer 90 electrical pattern 55 and the second inner insulating layer 40, the margin, and the aspect ratio can also be greatly reduced (such as Therefore, the unpleasant short circuit between the contact pads can thus significantly improve the reliability of the avoidance element, and in addition, the production cost can be reduced. It has been disclosed above with the preferred embodiment, but it is not used with any heat Those skilled in the art can make some modifications and retouching without departing from the essence of the present invention, so the definition of the scope of the patent application of the present invention shall prevail. Μ zuuHiy / l1 Schematic illustration Schematic illustration Figure E is a flow sectional view of a node contact window. "The conventional SAC process is used to form and store Figures 2A to 2F. Figure 2A is a self-aligning storage node contact. Figure 3A is shown as a chimney A cross-sectional view of the clothing process; Figures; and Self-alignment to the plane of the contact window of the storage node to Figure 3C are A ~ A, BR, Ancient self-aligned storage nodes Λ, along Figure 3A The β-β direction shows the pattern standard ~ the cross-sectional view of the contact window. You do not explain: 120, 20 Chu ^ 130, 30 140, 40 150, 50 160, 60 The first contact pad of the inner insulation storage node Two inner layer insulation layer bit line cover layer 155 bit line stack 18 0 nitride nitride layer 180,? 85 single layer gap 璧 19 0? 9 0 ^ $ two inner layer insulation layer 20 0, 1 〇〇 Germany six ... 10 Semiconductor substrate 55 conductive pattern 52 conductive pattern 70 first gap 璧 storage point contact window opening 1 U lane «, 11453pif.ptd page 18 200419711 schematic illustration 61 top surface of the cover 60 51 bit line 5 0 Bottom surface 71 Top surface of first gap 璧 forming layer 80 Second gap 璧 forming layer 92 Opening 87 Upper part of single-layer gap 璧 85 89 Lower part of single-layer gap 璧 85
11453pif.ptd 第19頁11453pif.ptd Page 19
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KR100596845B1 (en) * | 2003-10-22 | 2006-07-04 | 주식회사 하이닉스반도체 | Method for Forming Contact of Semiconductor Device |
JP4543392B2 (en) | 2005-11-01 | 2010-09-15 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
KR100805009B1 (en) * | 2006-03-02 | 2008-02-20 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
KR102321373B1 (en) | 2015-08-19 | 2021-11-02 | 삼성전자주식회사 | Method for fabricating semiconductor device |
KR102572514B1 (en) * | 2018-04-17 | 2023-08-31 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
TWI685085B (en) | 2019-02-26 | 2020-02-11 | 華邦電子股份有限公司 | Memory device and method of manufacturing the same |
KR20220014387A (en) * | 2020-07-24 | 2022-02-07 | 삼성전자주식회사 | Semiconductor memory device and method for manufacturing the same |
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US6194302B1 (en) * | 1999-09-30 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Integrated process flow to improve the electrical isolation within self aligned contact structure |
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