DE10347458B4 - A method of manufacturing a semiconductor device and a semiconductor device manufactured by the method - Google Patents

Abstract

A method of manufacturing a semiconductor device, which method comprises the following steps in the following order:
a) forming adjacent conductive patterns (55) overlying a semiconductor substrate (10), the conductive patterns (55) each comprising a conductive line (50) and a capping layer (60);
and where
b) forming a first spacer formation layer (70) between the adjacent conductive patterns (55), the first spacer formation layer (70) being sandwiched between the upper surface (61) of the cap layer (60) and the bottom surface (51) of the conductive layer Line (50) is formed;
c) forming a second spacer formation layer (80) conforming to the conductive patterns (55);
d) then forming on the second spacer formation layer (80) an interlayer insulating layer (90) without etching the second spacer formation layer (80);
e) in the interlayer insulating layer (90) an opening (100) is made which extends to a portion of the first spacer formation layer (70), which portion is located between the conductive patterns (55) ...

Description

BACKGROUND THE INVENTION

Territory of invention

The The present invention relates to a process for the preparation of a A semiconductor device according to claim 1 and a manufactured according to this method Semiconductor device according to Claim 21.

Out US 2001/0045666 A1 is a semiconductor device with a self-aligned contact (SAC) and also a method of manufacture the same known. The semiconductor device includes a Variety of conductive patterns formed side by side are formed by a first conductive layer and a masking layer a special underlying layer stacked and in a Patterns are brought. A first insulating layer fills one Gap between adjacent conductive layer patterns in such Way that an upper section of each conductive layer pattern is exposed. A second insulating layer having a spacer shape is then formed on the sides of each of the conductive layer patterns the above the first insulating layer are exposed. A second senior Layer fills then a contact hole, which in relation to the second insulation layers is aligned between the adjacent conductive layer patterns themselves and passes through the first insulation layer.

From the US 6495889 B1 For example, a semiconductor device having an SAC structure comprising sidewall spacers and staggered nitride films is known. Specifically, in this known semiconductor device, the sidewall spacers are formed of lower sidewall spacers composed of silicon oxide films and in contact with the lower side of gate electrode sidewalls. Also, upper sidewall spacers are provided, which are composed of silicon nitride films and which are in contact with the upper side of the gate electrode sidewalls. As a result, a distance between the substrate and the intermediate layer between the silicon nitride film and the silicon oxide film is realized. This avoids poor contact and also suppresses a hot-carrier appearance.

From the DE 10107125 A1 For example, a method of forming integrated circuit devices by selectively etching an insulating layer to increase the self-aligning area adjacent to a semiconductor region is known.

There Semiconductor devices are becoming increasingly integrated It is becoming increasingly difficult to achieve adequate misalignment limits or margins during one Ensure the manufacturing process. This is partly true due to limitations in the photolithographic technique and etching technique. If, for example the distance between a node contact of a capacitor and its adjacent bitlines decreases, it becomes more difficult form a contact hole between the bit lines without doing so Problems, such as electrical short circuits, too cause.

Various attempts have been made in the industry, such as the use of a self-aligning contact (SAC) process, to deal with these problems. The 1A to 1E FIG. 15 are cross-sectional views illustrating a process of forming a storage node contact using a conventional SAC process. FIG. According to 1A becomes a first interlayer insulating layer 120 with a storage node contact pad 13 formed over a semiconductor substrate (not shown). A second interlayer insulating layer 140 is then on the first interlayer insulating layer 120 educated. Next will be bit line stacks 155 each of which is a bitline 150 and a cover layer 160 on the second interlayer insulating layer 140 produced.

According to 1B becomes a silicon nitride layer 180 on the bit line stacks 155 and on the second interlayer insulating layer 140 educated. The silicon nitride layer 180 is subsequently etched back, as shown in 1C is shown a single-ply sidewall spacer 180 ' to build. According to 1D is after the formation of the single-layer spacer 180 ' a third interlayer insulating layer 190 on the bit line stacks 188 formed, which the re-etched single-layer spacers 180 ' included, and on the second interlayer insulating layer 140 educated. According to 1E then becomes the third interlayer insulating layer 190 using the back etched single ply spacer 180 ' patterned as an etch stopper around a conventional self-alignment memory node contact hole 200 set.

Unfortunately, in the conventional SAC process, there are many disadvantages, such as those in the 1A to 1E are presented. For example, the sidewall spacer 180 ' over-eroded (thinned) by the etching chemicals during the etch-back process in which the single-layer spacer 180 ' is formed and also during the etching process in which the contact hole 200 is trained. Over-erosion results in shoulder over-etch and / or shoulder weakening, which in turn leads to electrical shorts along the bitline 150 and the storage node contact pad 160 leads. The term "shoulder" here refers to the thinnest portions of the sidewall spacer 180 ' passing through the contact hole 200 is exposed. As the single-layer spacer 180 ' during the formation of the contact hole 200 can be over etched, in addition, the thickness of the single-layer spacer 180 ' be very thin. This then increases the bitline load capacity, thereby preventing further integration of memory devices.

Further, as part of the trend towards higher integration densities, a height of the contact holes increases while, however, an opening of the contact holes is reduced, resulting in an increased aspect ratio (height-width ratio). It is therefore difficult to completely fill the deep and narrow contact hole, which then results in a void in the interlayer dielectric layer between the conductive lines (eg, the bit lines). This vacancy can be extended during a cleaning process (eg during wet cleaning processes), which then leads to bridging between the bitlines 150 and / or adjacent contact pads 130 leads, which can cause short circuits.

It There is thus a need for an improved semiconductor manufacturing process, in which an etching edge region or shoulder width increased can be and the Bitleitungsbelastungskapazität can be reduced, however the shoulder losses can be further minimized.

SUMMARY

The The problem underlying the invention is a method for producing a semiconductor device and a method produced by the method To provide a semiconductor device, in a reliable manner Self-alignment memory node contacts can be made and which methods are carried out particularly economically can.

In Compound with the method according to the invention This object is achieved by the features listed in claim 1 solved.

Especially advantageous developments and refinements of the method according to the invention emerge from the dependent claims.

A according to the inventive method produced semiconductor device is apparent from the claim 21, wherein advantageous embodiments of the semiconductor device from the claims 22 to 24 come out.

in an embodiment adjacent conductive patterns are superimposed overlying a semiconductor substrate are. The conductive patterns each have a conductive line and a cover layer. A first spacer formation layer is formed between the adjacent conductive patterns. The first Spacer formation layer is sandwiched between the upper surface of the Cover layer and the bottom surface of the conductive line formed. A second spacer formation layer will conform to formed conductive patterns. It becomes a first interlayer insulating layer formed on the second spacer formation layer. Further becomes an opening formed in the first interlayer insulating layer, which is too a portion of the first spacer formation layer extends. The portion of the first spacer formation layer is etched using the second spacer formation layer as an etching mask, around a single-layer spacer on the side walls of the form conductive pattern concurrently with a contact hole.

SHORT DESCRIPTION THE DRAWINGS

The explained preceding and other objects, features and advantages of the invention will become apparent from the following detailed description of a preferred embodiment having regard to the attached Drawings.

1A to 1E 10 are cross-sectional views illustrating the process steps for forming a self-aligning memory-dot contact according to the prior art;

2A to 2F 12 are cross-sectional views illustrating the steps of a method of manufacturing a self-aligned memory node contact according to an embodiment of the present invention;

3A Fig. 10 is a plan view illustrating a self-aligning storage node contact; and

3B to 3C FIG. 15 are cross-sectional views showing a self-aligning storage node contact along directions A-A ', BB' of FIG 3A show, according to an embodiment of the present invention.

DETAILED DESCRIPTION

It Now different embodiments of the present invention in detail in the following Description explained, a more complete one understanding to impart the present invention. It should be noted, however, that for professionals it can be seen that the Invention are practiced in various alternative forms can. It should also be noted that various well-known Structures and techniques not shown here and in detail are described to obscure the principles of the present Invention in unnecessary Way to avoid.

The 2A to 2F show a self-alignment storage node contact process according to an embodiment of the invention. To first on 2A to enter, so is a first interlayer insulating layer 20 preferably in a thickness of about 100-300 nm on a semiconductor substrate 10 using conventional techniques (eg, using a low pressure chemical vapor deposition process (LP-CVD) or a high density plasma chemical vapor deposition (HDP-CVD) process).

Other suitable dielectric materials, such as borophosphosilicate glass (BPSG), spin-on-glass (SOG), plasma-fired tetraethyl orthosilicate oxide (PE-TEOS), and undoped silicate glass (USG), may also be used to form the first interlayer insulating layer 20 manufacture. It then becomes a storage node contact pad 30 in the first interlayer insulating layer 20 configured to electrically connect active zones to the storage node contact formed using the processes known in the art.

It then becomes a second interlayer insulating layer below 40 on the storage groove point contact pad 30 and on the first liner insulating layer 20 educated. The thickness of the second interlayer insulating layer 40 is preferably in a range between about 100 to 300 nm. The second interlayer insulating layer 40 is preferably planarized using planarization techniques, such as a chemical mechanical polishing (CMP) process, to thereby improve, for example, the photolithographic process edges or edge areas. After the planarization process, the second interlayer insulating layer is 40 preferably about 200 nm thick.

It will become conductive patterns 55 with side walls 52 over the semiconductor substrate 10 educated. The conductive pattern 55 each comprise a conductive line, such as a bit line 50 , and a cover layer 60 (eg, a patterned bitline mask layer). The bit line 50 is preferably formed of a conductive material such as tungsten to a thickness of about 40 to 80 nm. The cover layer 60 is preferably formed of silicon nitride to a thickness of about 100 to 300 nm. The cover layer 60 however, it can also be made from other suitable insulating materials.

To get up now 2 B to enter, so will a first spacer formation layer 70 preferably on the second interlayer insulating layer 40 between the conductive patterns 55 educated. The first spacer formation layer 70 For example, it may be formed from LP-CVD, BPSG, HDP or a CVD oxide having a relatively low permeability or dielectric constant. Other suitable low dielectric constant materials may also be used. The height of the first spacer formation layer 70 can be determined for example by means of a wet etch process. By way of example, a layer of material preferably becomes on the conductive patterns 55 and on the second interlayer insulating layer 40 formed around the first spacer formation layer 70 to build. An etch process (eg, wet etch) in conjunction with the resulting structure is then performed to increase the height of the first spacer formation layer 70 adjust.

As a result, the upper surface of the first spacer formation layer becomes 70 between the upper surface 61 the cover layer 60 and the floor area 51 the bit line 50 educated. The upper surface 71 the first spacer formation layer 70 is preferably substantially below the upper surface 61 the cover layer 60 arranged or will be 10 to 200 nm above the ground surface 51 the bit line 50 arranged. Alternatively, the upper surface 71 the first spacer formation layer 70 also approximated in the middle between the upper surface 61 the cover layer 60 and the floor area 51 the bit line 50 to be ordered.

According to 2C may be a conformal second spacer formation layer 80 on the conductive patterns 55 be formed using a conventional technique such as an LP-CVD process. The second Spacer-forming layer 80 is preferably prepared from a material having an etch selectivity with respect to the material (eg, silicon dioxide) comprising the first spacer formation layer 70 forms. The first spacer formation layer 70 preferably has a lower dielectric constant (lower absolute dielectric constant) than the second spacer formation layer 80 , The second spacer formation layer 80 For example, it may be formed of silicon nitride to a thickness of about 20 to 60 nm. Those skilled in the art will recognize that other suitable materials having suitable etch rates and dielectric constants can be used and still fall within the scope of the present invention.

According to 2D may be a third interlayer insulating layer 90 on the conformal second spacer formation layer 80 be formed using a conventional technique, such as an LP-CVD or HDP-CVD process. The third interlayer insulating layer 90 preferably has an etch selectivity with respect to the second spacer formation layer 80 , The third interlayer insulating layer 90 is preferably made of a material similar to that of the first spacer forming layer 70 , The third interlayer insulating layer 90 can be leveled using conventional planing techniques. Below is an opening 92 in the third interlayer insulating layer 90 using the second spacer formation layer 80 (please refer 3C ) is formed as an etch stop layer, wherein a portion of the second spacer formation layer 80 is exposed. The opening 92 is between adjacent conductive patterns 55 formed and is self-aligning with respect to the second spacer formation layer 80 ,

To get up now 2E a portion of the exposed second spacer formation layer 80 preferably etched to a portion of the first spacer formation layer 70 to remove or expose (the opening 92 extends to a portion of the first spacer formation layer 70 ), according to an embodiment of the present invention.

According to 2F may also be a storage node contact hole 100 in the first spacer formation layer 70 and the second interlayer insulating film 40 be formed. The storage node contact hole 100 can by etching the first spacer formation layer 70 and the second interlayer insulating film 40 are formed using the second spacer formation layer 80 (with unetched upper flat sections) as an etch mask. The storage node contact hole extends through the second interlayer insulating film 40 to a portion of the contact pad 30 expose.

During this process becomes a single-layer spacer 85 formed, namely, the exposed portion of the first spacer formation layer 70 also etched. using the second spacer formation layer 80 as an etching mask. The term "single layer" refers to the fact that the layer forming a sidewall spacer is on the sidewall of the conductive patterns 55 consists of a single layer that has no additional layers stacked thereon. The storage node contact hole 100 is preferably self-aligned with the single-layer spacer 85 and is between adjacent conductive patterns 55 arranged. As a result, the single-layer spacer becomes 85 concurrently with the storage node contact hole 100 educated.

In the prior art described earlier, the SAC etch process begins with the already etched back spacer 180 ' , See the 1D to 1E , In other words, the silicon nitride layer becomes 180 etched back to a bit line spacer 180 ' form, which has no unetched flat portions, before the third insulating layer 190 is formed and before the SAC contact hole formation process is performed. It was therefore not easy to obtain sufficient shoulder width or shoulder width or etch margins during the SAC etch process. The bitline spacer 180 ' Therefore, the prior art tends to result in a larger spacer loss, which can lead to accidental short circuits, for example, between the bit lines 150 and the contact pad 130 ,

In contrast and in contrast to the prior art and according to the previously explained embodiments of the present invention, the SAC etching process begins before the formation of the single-layer spacer 85 , See the 2C to 2D , In other words, the SAC etching process starts with portions (eg, an upper portion) of the second spacer formation layer 80 which have remained unetched and therefore have flatter areas at the top portions and also have thicker edge portions than in the prior art. The second spacer formation layer 80 is first during the process of forming the storage node contact hole 100 uncovered and it becomes the SAC etching performed on the structure with an unetched upper flat section. For this reason, a loss of the spacer (eg falling or decreasing shoulder) can be significantly reduced. The single-layer spacer 85 therefore does not suffer from unacceptable loss or erosion thereof. Random shorts between conductive patterns 55 and the contact pad 30 can thus be prevented by namely the etching or Ätzschulter is increased.

In another embodiment (as in the case of a line type contact), during the process, that of 2D corresponds to the upper part of the second spacer formation layer 80 more etched, but still has thicker edge or edge portions than in the prior art. As with the previously discussed embodiment, the SAC etch continues to commence prior to spacer formation and after formation of the third interlayer insulating layer 90 that of the second spacer formation layer 80 over lies. In this case, the single-layer spacer becomes 85 also concurrently with the formation of the storage node contact hole 100 educated.

Subsequently, a contact plug (not shown) within the storage node contact hole will become 100 formed and becomes electrically connected to the contact pad 30 using methods known in the art. For example, a metal such as tungsten may be on the storage node contact hole 100 be knocked down. Following the deposition, a planarization step may be performed which may include CMP.

3A FIG. 10 is a plan view of a self-aligning storage node contact hole. FIG 100 , 3B shows a cross-sectional view of the self-alignment storage node contact hole 100 , along the line AA 'in 3A , 3C is a cross-sectional view of the area corresponding to the section line BB 'in 3A ,

According to 3B can be the single-layer spacer 85 prepared according to the above-described process, an upper portion 87 and a lower section 89 contain. The upper section 87 contains in a preferred manner under a different material from the lower portion 89 , This is the case because the lower section 89 preferably from the first spacer formation layer 70 is formed, which contains, for example, silicon dioxide; and the top section 87 becomes preferably the second spacer formation layer 80 formed, which contains, for example, silicon nitride.

As a result, may be the parasitic Capacity of the conductive line (load) (e.g., the bit line parasitic capacitance) can be reduced (e.g., by more than 25%) by combining Layers of a dielectric material with relatively lower absolute dielectric constant (e.g. Silicon dioxide) and a dielectric material (e.g., silicon nitride) with a relatively high absolute dielectric constant, which in contrast to form the spacer of only silicon nitride with a high dielectric constant. It can consequently more cells for every bit line added in order to improve the cell array efficiency, whereby the Output is increased and the manufacturing costs are lowered.

Thus, as in 3B As a result of the process described above, the single-layer spacer is shown 85 formed in a region where the storage node contact hole 100 is formed. In contrast, there is, as in 3C however, in the region through which line BB 'extends, only unetched layers are shown (no single-layer spacer is formed). This is the case because of the single-layer spacer 85 is formed when and where the storage node contact hole 100 is trained.

Thus, when this process is performed on semiconductor devices, a non-cell region (not illustrated separately) does not contain a single-layer spacer as in the structure disclosed in US Pat 3C however, one cell area shows a single-layer spacer 85 contains as explained above ( 3B ). The term "non-cell area" refers to a portion of the semiconductor device that does not consist of a memory cell, eg, a peripheral circuit area, a core circuit area, or both.

Although the invention has been described primarily with reference to the formation of a spacer on sidewalls of bitlines, the principles of the present invention may also be applied to other sidewall spacer structures, such as gate electrodes. The principles of the present invention may also be applied to various types of semiconductor devices, including memory devices such as DRAMs, SRAMs, and embedded memory. Furthermore, the principles of the present invention may also be applied to a variety of types of contacts, such as line type contacts. Such conductive type contacts can be made, for example, by forming a mask pattern with a groove of line type crossing the bit line at right angles to an interlayer dielectric layer. A conduction type contact hole is formed in the interlayer dielectric layer using the methods described above. The conduction type contact hole extends in a direction perpendicular to the bit line. Then, a conductive material is introduced in the contact hole of the conductivity type. The resulting structure is subsequently planarized to then form individual storage node contact pads.

In summary, the disclosed embodiments enable the formation of a highly reliable SAC structure. For example, embodiments of the present invention make it possible to reduce shoulder erosion (eg, spacer loss or cap layer loss), thereby extending misalignment or process margins. It is also possible to reduce the bit line load capacity. Further, because the first spacer formation layer 70 between the conductive patterns 55 and on the second interlayer insulating layer 40 is formed, prior to the formation of the third interlayer insulating layer 90 , the gap fill margin is improved and the aspect ratio can be significantly reduced (eg to 4: 1 to 2.5: 1). Undesirable short circuits between contact pads can also be avoided.

As a result, becomes the reliability of the semiconductor device is significantly improved. Corresponding the output is improved and the manufacturing costs are reduced.

After this the principles of the invention have been described and illustrated, namely, with reference to preferred embodiments, it should be noted that the Invention can be modified in the arrangement and in detail can, without departing from the principles of the invention. It will therefore claims all the modifications and variations that in the The scope of the following claims fall.

Claims (24)

A method of manufacturing a semiconductor device, the method comprising the following steps in the following order: a) forming adjacent conductive patterns ( 55 ) over a semiconductor substrate ( 10 ), the conductive patterns ( 55 ) one conductive line ( 50 ) and a cover layer ( 60 ); and wherein b) a first spacer formation layer ( 70 ) between the adjacent conductive patterns ( 55 ), the first spacer formation layer ( 70 ) between the upper surface ( 61 ) of the cover layer ( 60 ) and the floor surface ( 51 ) of the senior management ( 50 ) is formed; c) on the conductive patterns ( 55 ) a second spacer formation layer ( 80 ) is formed conforming; d) then on the second spacer formation layer ( 80 ) an interlayer insulating layer ( 90 ) without etching the second spacer formation layer (FIG. 80 ) is formed; e) in the interlayer insulating layer ( 90 ) an opening ( 100 ) which forms a portion of the first spacer formation layer ( 70 ), which section between the conductive patterns ( 55 ) is located; and f) the portion of the first spacer formation layer ( 70 ) using the second spacer formation layer ( 80 ) is etched as an etching mask, whereby a spacer ( 85 ) on the sidewalls of the conductive patterns ( 55 ) is formed. The method of claim 1, wherein the first spacer formation layer (10) 70 ) below the upper surface ( 61 ) of the cover layer ( 60 ) lies. Method according to claim 1, wherein the upper surface ( 61 ) of the first spacer formation layer ( 70 ) in the middle between the upper surface ( 61 ) of the cover layer ( 60 ) and the floor surface ( 51 ) of the senior management ( 50 ) is arranged. The method of claim 1, wherein forming the first spacer formation layer (10) 70 ) comprises depositing a dielectric layer overlying the conductive patterns ( 55 ), and adjusting the height of the dielectric layer. The method of claim 4, wherein adjusting the height the dielectric layer, a wet etching of the dielectric layer includes. The method of claim 1, wherein conforming the second spacer formation layer (10) comprises: 80 ) forming the second spacer formation layer (FIG. 80 ) on the first spacer formation layer ( 70 ). Method according to claim 1, wherein the formation of an opening ( 100 ) exposing a portion of the second spacer formation layer ( 80 ); and removing the exposed portion of the second spacer formation layer (FIG. 80 ), where one Section of the first spacer formation layer ( 70 ) is exposed. The method of claim 1, further comprising the interlayer insulating layer (10). 90 ) before the opening ( 100 ) is leveled. The method of claim 1, wherein the second spacer formation layer (14) 80 ) an etch selectivity with respect to the first spacer formation layer (FIG. 70 ) having. The method of claim 8, wherein the planarized interlayer insulating layer ( 90 ) an etching selectivity with respect to the second spacer formation layer (FIG. 80 ) Has. The method of claim 1, further comprising etching the exposed portion of the first spacer formation layer (14). 70 ) at the same time a contact hole ( 100 ) formed with the spacer ( 85 ) between the adjacent contact patterns ( 55 ) is self-aligned. Method according to claim 11, in which two further interlayer insulation layers (2) are sequentially 20 . 40 ) on the semiconductor substrate ( 10 ), prior to the formation of the conductive pattern ( 55 ), one ( 40 ) of the two interlayer insulating layers ( 20 . 40 ) a contact pad ( 30 ) is formed therein. Method according to Claim 12, in which the contact hole ( 100 ) also by the interlayer insulating layer ( 90 ), and a portion of the contact pad ( 30 ). The method of claim 12, further comprising a contact plug within the contact hole (16). 100 ) is formed and this electrically connected to the contact pad ( 30 ) is connected. Method according to Claim 1, in which the opening ( 100 ) is formed to form a node contact of the conductivity type. Method according to Claim 1, in which the spacer ( 85 ) consists of a single layer and an upper section ( 87 ) and a lower section ( 89 ), wherein the upper section ( 87 ) one from the lower section ( 89 ) has different or different material. Method according to Claim 16, in which the upper section ( 87 ) vertically above the lower section ( 89 ) is piled up. The method of claim 1, wherein the second spacer formation layer (14) 80 ) is formed with an unetched portion which during the formation of the spacer ( 85) is flat. Method according to Claim 1, in which the conductive line ( 50 ) is formed as a bit line, or in the form of adjacent bit line stacks. Method according to claim 19, wherein the opening ( 100 ) is formed between the adjacent bit line stacks and wherein the opening ( 100 ) with the second spacer formation layer ( 80 ) is formed self-aligning. A semiconductor device fabricated according to the method of any one of the preceding claims, comprising a cell region and a non-cell region, the cell region comprising: first adjacent conductive patterns ( 55 ) on a semiconductor substrate ( 10 ), each first conductive pattern ( 55 ) a conductive line ( 50 ) and a cover layer ( 60 ), the first conductive patterns ( 55 ) a spacer ( 85 ), which is formed on the side walls thereof, wherein the spacer ( 85 ) an upper section ( 87 ) and a lower section ( 89 ), the upper section ( 87 ) of a different material than the lower section ( 89 ) consists; and the non-cell region comprises: adjacent second conductive patterns ( 55 ), which over the semiconductor substrate ( 10 ), the second conductive patterns ( 55 ) one conductive line ( 50 ) and a cover layer ( 60 ) exhibit; a first spacer formation layer ( 70 ) between the adjacent second conductive patterns ( 55 ), the first spacer formation layer ( 70 ) between the upper surface of the cover layer ( 60 ) and the floor surface ( 51 ) of the senior management ( 50 ) is trained; a second spacer formation layer ( 80 ) conforming to the second conductive patterns ( 55 ) is trained; an interlayer insulating layer ( 90 ) formed on the compliant second spacer forming layer ( 80 ), the first and second spacer formation layers ( 70 . 80 ) between the adjacent second conductive patterns ( 55 ) are unetched in the non-cell region. A semiconductor device according to claim 21, wherein said lower portion ( 89 ) has a dielectric constant which is substantially lower than that of the upper portion ( 87 ). A semiconductor device according to claim 21, wherein said lower portion ( 89 ) an etching selectivity in with reference to the upper section ( 87 ) having. Semiconductor device according to Claim 21, in which the upper section ( 87 ) vertically on the lower section ( 89 ) is piled up.