126075^ wfl .doc/006 95-4-20 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路之封裝結構，且特別是 有關於一種具有散熱片之晶片封裝結構。 【先前技術】 在高度情報化社會的今日’可攜式電子裝置(p〇rtabie electric device)的市場不斷地急速擴張。而晶片封裝結構亦 配合電子裝置的數位化、網路化、區域連線化以及人性化 • 荨趨勢’而不斷地朝向南速處理化、多功能化、積集 (Integration)化、微型化及低價化等方面發展。然而晶片封 裝結構在朝向微型化與高密度化等方面發展的同時，卻相 應地產生了晶片散熱的問題。 針對此一問題，習知技術提出一種晶片封裝結構，其 具有政熱片，以使晶片的操作溫度在操作過程中維持在 適，的溫度範圍内，其中此晶片封裝結構之示意圖如圖j 戶^示。凊芩照圖1，晶片封裝結構100包括晶片（die) 110、 曰片座120 (die pad)、散熱片130、多個引腳14〇、多條 導線150以及封膠（m〇ldingc〇mp_d) 16〇。晶片ιι〇係 配置於晶片座120之一表面上。散熱片130具有相對應之 上表面132與下表面134，而晶片座120則配置於散埶片 上表面132上。封膠160係包覆住晶片丨1〇、晶5座 120與散熱片130,並且封膠160暴露出散熱片13〇之 面 134 。 ^ 邊又而言，晶片座120與散熱片13〇均以銅製成。由 於銅的熱傳導係數（thermal c〇nductiv办）高達 I26075S twfl.doc/006 95 - 4-20 393W/m°K’因此晶片11〇在運作的過程中所產生的熱量q 能夠快速且有效地經由晶片座120而傳遞至散熱片ι3〇 上’並且經由熱對流（heat convection)或熱輻射（heat radiation)等熱傳遞機制將熱量q自下表面134排除至外 界環境。另外散熱片13〇能夠具有較晶片110更大之散面 積，是以晶片封裝結構100具有良好的散熱能力，並且晶 片Π0不容易因為熱量的累積而造成晶片11〇之操作溫度 超出其容許的溫度範圍。126075^wfl .doc/006 95-4-20 IX. Description of the Invention: [Technical Field] The present invention relates to a package structure of an integrated circuit, and more particularly to a chip package structure having a heat sink . [Prior Art] The market of today's portable electronic devices (p〇rtabie electric devices) has been rapidly expanding in a highly information society. The chip package structure is also continually moving toward the south speed processing, multi-functionalization, integration, miniaturization, and the digitalization, networking, regional connection, and humanization of the electronic device. Development in terms of low prices. However, while the wafer package structure has been developed toward miniaturization and high density, the problem of heat dissipation of the wafer has been correspondingly produced. In response to this problem, the prior art proposes a chip package structure having a thermal sheet so that the operating temperature of the wafer is maintained within an appropriate temperature range during operation, wherein the schematic diagram of the chip package structure is shown in FIG. ^ Show. Referring to FIG. 1, the chip package structure 100 includes a die 110, a die pad 120, a heat sink 130, a plurality of leads 14A, a plurality of wires 150, and a sealant (m〇ldingc〇mp_d). ) 16〇. The wafer is disposed on one surface of the wafer holder 120. The heat sink 130 has a corresponding upper surface 132 and a lower surface 134, and the wafer holder 120 is disposed on the upper surface 132 of the heat sink. The sealant 160 covers the wafer 丨1, the crystal 5 seat 120 and the heat sink 130, and the sealant 160 exposes the face 134 of the heat sink 13〇. ^ In other words, both the wafer holder 120 and the heat sink 13 are made of copper. Since the thermal conductivity of copper (thermal c〇nductiv) is as high as I26075S twfl.doc/006 95 - 4-20 393W/m°K', the heat q generated by the wafer 11〇 during operation can be quickly and efficiently The wafer holder 120 is transferred to the heat sink ι3' and the heat q is removed from the lower surface 134 to the outside environment via a heat transfer mechanism such as heat convection or heat radiation. In addition, the heat sink 13 can have a larger area than the wafer 110, so that the wafer package structure 100 has good heat dissipation capability, and the wafer 不0 is not easily caused by the accumulation of heat, and the operating temperature of the wafer 11 exceeds its allowable temperature. range.
^ 白知技術為防止晶片封裝結構100之引腳14〇 又到外界因素的影響而發生鏽# ( c〇rr〇ded )，其通常會 士弓>丨=卩140之表面上形成一錫層，其示意圖如圖2所示。 圖:錫層⑽的形成方式是先經由接地引線170 生連接於晶片座120，以產生晶片電訊接地 應。之後再經由電鍍（_ng)將錫層l8G形成於引^ Baizhi Technology generates rust# (c〇rr〇ded) to prevent the pin 14 of the chip package structure 100 from being affected by external factors, and it usually forms a tin on the surface of the 会 & & 卩 卩 卩 140 The layer, its schematic diagram is shown in Figure 2. The tin layer (10) is formed by first connecting to the wafer holder 120 via a ground lead 170 to generate a wafer telecommunications ground. Then, the tin layer l8G is formed by electroplating (_ng).
熱片•引腳14。、導線15〇、晶片== 片座12〇係處在同—i回政e 1〇A 川以及日日 :⑽上’更會形成於散熱 ί的:的散熱片130便會造成晶片封裝結構刚ut 之表面m具:片130’其中銘製散熱片⑽ 方法為陽極處理（二、::、·氧:匕層，而形成此絕緣氧化層的 將錫層⑽形成上id:g)。當習知技術以電鑛的方式 ;引腳140上時，此絕緣氧化層由於其具 Ι2607Ά fl.doc/006 95-4-20 有不導電的待性，因 用具有絕緣氣化層的鋁製A:埶卜法形成於其上。是以使 構100之製程上的困擾二=130能夠解決晶片封裝結 為銅的二分之_，因此當習知，叙的熱傳導係數大约僅 ΐ發明:容7降。 、成Β日片封襄結構之散熱 本發明的目的就是在提供 銅製散熱月之高散熱性以及紹晶月封裝結構，兼且有 錫層於電鍍時形成於散熱片上熱片之絕緣性，以避免 本發明提出-種晶片封 個引腳、多數個導線、—第_：全屬冓，其包括〜晶月、多數 —封膠。晶片具有一主動表面以第二金屬片以及 配置於主動表面上。這些弓I 月面’而多數個薛墊 線係電性連接於這些銲‘2:向外延伸。 表 表面接_—金w上表面 二二V、，泉、第一金屬片以及第 ，包覆晶片、 封膠之外，且第二金屬 面這些Μ延伸於 露於封膠之外。 下表面具有-絕緣鍍層，其暴 在本發明之一實施例中，a 黏著層1 連接於第-金屬片包括- 銅 ’ 二=:，為 在本發明之一實施例中，絕緣鏡層例如是以陽極處理 12607紹 丨 twfl .doc/006 95-4-20 的方式而形成氧化層。 在本發明之一實施例中，晶片封裝結構例如更包括一 晶片座，其配置於晶片之背面與第一金屬片之間，並且晶 片座之材質例如與這些引腳的材質相同，而晶片座與這也 引腳的材質包括銅。 經由適當地選取第一金屬片的材質（例如為銅）與第 二金屬片的材質（例如為鋁）’第—與第二金屬片之整體 的熱傳導係數能夠南於銘製散熱片並且接近銅製散熱片。 修此外，本發明更可以經由形成於弟-金屬片上的絕緣鍍層 來避免錫層於電鍍時形成於第二金屬片上，是以能夠避免 晶片封裝結構在製程上的困擾。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖3纟會示為本發明一實施例之晶片封裝結構的示意 # 圖。請參照圖3，晶片封裝結構200主要包括晶片210、多 個引腳220、多個導線230、第一金屬片240、第二金屬片 250以及封膠270。晶片210具有一主動表面212以及一背 面214’而且主動表面212上更配置有多個銲墊216。這些 引腳220係由晶片210之周圍向外延伸，其中這些引腳220 的材質例如為銅或其他的導電材質。而這些導線230係電 性連接於這些銲墊216與這些引腳220之間，其中這些導 線230之材質例如為金或是其它的導電材質。 1260观 :wfl .doc/006 第-金屬片240係配置於晶片21〇之背面2i4， 晶片210例如是經由黏著膠體3〇〇黏著於第一” 孟/鸯片24Π 上。更詳細的説:黏著層的材質例如為銀膠（姐， paste)或是其它導熱性良好的黏著膠體。 弟一金屬片250係具有上表面252以及下表面254 且上表面252係與第一金屬片240接觸。第二金屬片5=5〇 之下表面254例如具有一層絕緣鍍層256 ,其中絕緣铲： 256不具有導電性。絕緣鍍層256之形成方式包括對 金屬片250進行陽極處理，以形成一氧化層於表面254 1， 其中此氧化層即為絕緣鍍層256。更詳細地說，陽極處理 係將第二金屬片250與一直流電源（DCp〇wersupply)之 陽極（anode)電性連接，並且將直流電源之陰極（cath〇d〇 與低化學活性之導體（例如石墨、鎳、不鏽鋼等等）電性 連接接者將笫一金屬片250與低化學活性之導體置入去 離子水槽中，並且開啟此直流電源，以使得第二金屬片25〇 之表面與去離子水反應以產生氧化層於表面254上，同時 與陰極電性連接之低化學活性之導體處亦會產生氫氣。 — 在第一金屬片240與第二金屬片25〇的接合方法中， 第—金屬片240例如可以經由焊接的方式與第二金屬片 25〇結合。而在另一個較佳的接合方法中，第一金屬片240 ，可以經由黏著層31〇來與第二金屬片250結合，其中黏 著層的材質如為銀膠（silver paste)或是其它導熱性良好 的黏著膠體。 封膠270係包覆晶片210、導線230、第一金屬片240 10 12607誠 twfl .doc/006 95-4-20 以及第二金屬片25G。此外，這些 270之外，且第二金屬片25〇之下表面=申於封膠 暴露於封膠270之外。 1、、巴緣鍍層256 請共同參照圖2與圖3，由習知 片130雖然具有極佳的熱傳導係數，但^ °鋼製的散熱 鑛錫層180的過程中，錫層引腳140電 表面上。若以鋁製的散埶片 ;开;;成於放熱片130的 時，雖然可以經由陽極處理在紹製的散30 成絕緣氧化層，以避免錫層180形成於散表面形 上，但是這種改變散熱片130之材質的方的表面 片別的熱傳導係數下降。反觀本發明方=衫成散熱 ㈣與第二金屬片250之結合視為一散右金屬片 適當地選擇第—金屬片24G與第二金屬、片⑽亚且經由 散熱片260不但能夠呈右,木 * 的材料時， 免錫層於電_嫩散=26^_同時更能夠避 舉例而言，本實施例可以採用銅作為第 之材料，並且採魏作為第二金屬片25料蜀片_ 來，本實施例便可以經由調整第一 枓如此― μ 9c0 ^ „ 如门正弟孟屬片240與第二金屬 知之銘= 使传T片之熱傳導係數高於習 請，亚且接近於銅製散熱片13〇。此外白 由；弟一至屬片250之材質為鋁，因此當 極處理使得M -八麗Η从主 田本貝知例輕由陽 時，气埶t! 一垚 、义面254具有絕緣電鍍層256 片25月〇Ϊ 便可以避免錫層於電鍍時形成於第二金屬 1260说 wfl .doc/006 95-4-20 此外’本發明之晶片封裝結構除了上述圖3所示的結 構外’更可以將晶片配置於一晶片座上，其示意圖如圖4 所示。請參照圖4,其繪示為本發明另一實施例之晶片封 裝結構的不思圖。在晶片封裝結構200’中，晶片21 〇例如 配置於晶片座280上’而晶片座280例如經由黏著層3〇〇 而與第一金屬片240結合，其中黏著層300的材質例如為 銀膠或是其它導熱性良好的黏著膠體。晶片座280之材質 例如與引腳220之材質相同’其材質例如為銅。由於晶片 封裝結構200’之各個元件與各元件之間的相對位置與晶片 封装結構200十分相似，於此便不再多作贅述。 基於上述，本發明係經由適當地選取第一金屬片的材 質（例如為銅）與第二金屬片的材質（例如為鋁），使得 散熱片之熱傳導係數能高於鋁並且接近銅，進而使得本發 明所提出之晶片封裝結構的散熱能力高於具有鋁製散熱片 之晶片封裝結構，並且接近具有銅製散熱片之晶片封裴結 構。此外，本發明更可以經由形成於第二金屬片上的絕^ • 鍍層來避免錫層於電鍍時形成於第二金屬片上，是以^夠 避免晶片封裝結構在製程上的困擾。 ° 雖然本發明已以較佳實施例揭露如上，然其並非用以 限疋本散明，任何熟習此技藝者，在不脫離本發明之粹神 和範圍内，當可作些許之更動與潤飾，因此本發明之 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1繪示為習知晶片封裝結構之示意圖。 12 12607涊 twfl .doc/006 95-4-20 圖2繪示為對圖1之引腳電鍍錫層後的習知晶片封裝 結構意圖。 圖3繪示為本發明一實施例之晶片封裝結構的示意 圖。 圖4繪示為本發明另一實施例之具有晶片座之晶片封 裝結構的示意圖。 【主要元件符號說明】 100、200 :晶片封裝結構 110、210 :晶片 120、280 :晶片座 130、260 :散熱片 132、134 :表面 140、220 :引腳 150、230 :導線 160、270 :封膠 170 :接地引線 180 :錫層 212 ··主動表面 214 :背面 216 :銲墊 240 ·•第一金屬片 250 :第二金屬片 252 :上表面 254 :下表面 13 12607iS^^twfl .doc/006 95-4-20 256 :絕緣鍍層 300、310 :黏著層Hot film • Pin 14. , the wire 15 〇, the wafer == the pedestal 12 〇 is in the same - i Huizhen e 1 〇 A Chuan and the day: (10) on the 'more will be formed in the heat sink: the heat sink 130 will cause the chip package structure The surface of the just ut has: sheet 130' in which the heat sink (10) is anodized (2, ::, · oxygen: tantalum layer, and the tin layer (10) forming the insulating oxide layer is formed with id: g). When the conventional technique is in the form of electric ore; when it is on the lead 140, the insulating oxide layer has a non-conducting property due to its Ά2607Ά fl.doc/006 95-4-20 due to the use of an aluminum having an insulating vaporization layer. System A: The method is formed on it. Therefore, the trouble of the process of the structure 100 = 130 can solve the two-part of the copper encapsulation of the wafer package, so when it is conventionally known, the heat transfer coefficient is only about the invention: the capacitance is reduced. The heat dissipation of the Β Β 片 襄 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热It is avoided that the present invention proposes a chip to seal a pin, a plurality of wires, and a _: all 冓, which includes ~ crystal moon, majority - sealant. The wafer has an active surface with a second metal sheet and is disposed on the active surface. These bows are the same as the majority of the Xue mats and are electrically connected to these solders '2: extending outward. The surface of the surface is connected to the upper surface of the gold, the spring, the first metal piece and the first, the outer surface of the coated metal and the sealing material, and the second metal surface extends beyond the sealing material. The lower surface has an insulating coating, which is an embodiment of the invention, a bonding layer 1 is attached to the first metal sheet comprising - copper '2 =:, in an embodiment of the invention, the insulating mirror layer is for example The oxide layer is formed by anodizing 12607 丨 twfl.doc/006 95-4-20. In an embodiment of the present invention, the chip package structure further includes a wafer holder disposed between the back surface of the wafer and the first metal piece, and the material of the wafer holder is the same as the material of the pins, and the wafer holder The material with this pin also includes copper. By appropriately selecting the material of the first metal piece (for example, copper) and the material of the second metal piece (for example, aluminum), the heat transfer coefficient of the first and second metal pieces can be made up of the heat sink and close to copper. heat sink. In addition, the present invention can prevent the tin layer from being formed on the second metal sheet during electroplating through the insulating plating formed on the metal-metal sheet, so as to avoid the trouble of the wafer package structure in the process. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] FIG. 3A is a schematic view showing a wafer package structure according to an embodiment of the present invention. Referring to FIG. 3, the chip package structure 200 mainly includes a wafer 210, a plurality of pins 220, a plurality of wires 230, a first metal piece 240, a second metal piece 250, and a sealant 270. The wafer 210 has an active surface 212 and a back surface 214' and the active surface 212 is further provided with a plurality of pads 216. These pins 220 extend outward from the periphery of the wafer 210, and the materials of the pins 220 are, for example, copper or other conductive materials. The wires 230 are electrically connected between the pads 216 and the pins 220. The wires 230 are made of gold or other conductive materials. 1260: wfl.doc/006 The first metal piece 240 is disposed on the back surface 2i4 of the wafer 21, and the wafer 210 is adhered to the first "Meng/鸯 piece 24" via the adhesive 3, for example. More specifically: The material of the adhesive layer is, for example, silver glue or other adhesive body having good thermal conductivity. The metal piece 250 has an upper surface 252 and a lower surface 254 and the upper surface 252 is in contact with the first metal piece 240. The second metal sheet 5=5〇 lower surface 254 has, for example, an insulating coating 256, wherein the insulating shovel: 256 has no conductivity. The insulating coating 256 is formed by anodizing the metal sheet 250 to form an oxide layer. Surface 254 1, wherein the oxide layer is an insulating coating 256. In more detail, the anode treatment electrically connects the second metal piece 250 to the anode of the DC power supply, and the DC power supply a cathode (cath〇d〇 and a low-chemically active conductor (such as graphite, nickel, stainless steel, etc.) electrically connected to the metal sheet 250 and the low-chemically active conductor into the deionized water tank, and open this straight The power source is such that the surface of the second metal piece 25 is reacted with deionized water to produce an oxide layer on the surface 254, while hydrogen is also generated at the low chemically active conductor electrically connected to the cathode. In the bonding method of the second metal piece 25, the first metal piece 240 may be bonded to the second metal piece 25A by soldering, for example, in another preferred bonding method, the first metal piece 240, The adhesive layer can be bonded to the second metal sheet 250, wherein the adhesive layer is made of silver paste or other adhesive with good thermal conductivity. The sealant 270 is coated with the wafer 210, the wire 230, The first metal piece 240 10 12607 is twfl.doc/006 95-4-20 and the second metal piece 25G. In addition, these 270 are outside, and the surface of the second metal piece 25〇 is exposed to the sealant. In addition to the glue 270. 1. Bar edge plating 256 Please refer to FIG. 2 and FIG. 3 together. Although the conventional film 130 has an excellent heat transfer coefficient, the process of heat-distributing the tin layer 180 of the steel is tin. Layer pin 140 on the electrical surface. If it is made of aluminum When the heat release sheet 130 is formed, although the insulating oxide layer can be formed by the anode treatment to prevent the tin layer 180 from being formed on the surface shape, the material of the heat sink 130 is changed. The heat transfer coefficient of the surface of the square is decreased. In contrast, the combination of the heat sink (four) and the second metal piece 250 is regarded as a loose right metal piece, and the first metal piece 24G and the second metal piece (10) are appropriately selected. And the heat sink 260 can not only be used as the material of the right, wood*, but also the tin-free layer can be used as the first material, and the copper can be used as the first material. As the second metal piece 25 material _ _, this embodiment can be adjusted by the first 枓 so - μ 9c0 ^ „ 如门正弟孟属片240 and the second metal know Zhiming = heat transfer The coefficient is higher than that of the household, and is close to the copper heat sink 13〇. In addition, the white one; the brother one to the piece 250 is made of aluminum, so when the extreme treatment makes the M-Bali from the main Tianbenbei, the light is 阳, the 埶 t, the 面 254 has an insulating plating 256 pieces of 25 〇Ϊ can avoid the formation of the tin layer on the second metal 1260 during plating. Www.doc/006 95-4-20 Furthermore, the chip package structure of the present invention is in addition to the structure shown in FIG. 3 above. The wafer can be placed on a wafer holder, the schematic of which is shown in FIG. Please refer to FIG. 4, which illustrates a wafer package structure according to another embodiment of the present invention. In the chip package structure 200 ′, the wafer 21 〇 is disposed, for example, on the wafer holder 280 ′ and the wafer holder 280 is bonded to the first metal piece 240 via the adhesive layer 3 , for example, the material of the adhesive layer 300 is, for example, silver paste or It is another adhesive with good thermal conductivity. The material of the wafer holder 280 is, for example, the same as that of the lead 220. The material thereof is, for example, copper. Since the relative positions of the various components of the wafer package structure 200' and the components are very similar to those of the wafer package structure 200, no further details are provided herein. Based on the above, the present invention appropriately selects the material of the first metal piece (for example, copper) and the material of the second metal piece (for example, aluminum), so that the heat transfer coefficient of the heat sink can be higher than that of aluminum and close to copper, thereby making The chip package structure proposed by the present invention has a higher heat dissipation capability than a chip package structure having an aluminum heat sink, and is close to a wafer package structure having a copper heat sink. In addition, the present invention can prevent the tin layer from being formed on the second metal sheet during electroplating via the solder plating layer formed on the second metal sheet, so as to avoid the trouble of the wafer package structure in the process. While the invention has been described above by way of a preferred embodiment, it is not intended to limit the scope of the invention, and may be modified and retouched without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional chip package structure. 12 12607涊 twfl .doc/006 95-4-20 FIG. 2 is a schematic view of a conventional wafer package structure after plating a tin layer on the pin of FIG. 3 is a schematic view of a wafer package structure in accordance with an embodiment of the present invention. 4 is a schematic view showing a wafer package structure having a wafer holder according to another embodiment of the present invention. [Main component symbol description] 100, 200: chip package structure 110, 210: wafer 120, 280: wafer holder 130, 260: heat sink 132, 134: surface 140, 220: pins 150, 230: wires 160, 270: Sealant 170: Ground lead 180: Tin layer 212 · Active surface 214: Back surface 216: Solder pad 240 • First metal sheet 250: Second metal sheet 252: Upper surface 254: Lower surface 13 12607iS^^twfl .doc /006 95-4-20 256 : Insulation Plating 300, 310: Adhesive layer
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