1259396 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種系統單晶片積體電路與其他包 括嵌入式可配置邏輯陣列作為特定用途或客戶晶片邏輯 的處理器裝置及方法。 【先前技術】 包括例如已知的可程式化邏輯裝置（PLD)及場可程式 化閘極陣列（FPGA)的可配置邏輯陣列，以及更廣為熟知的 可程式化邏輯陣列（PLA)，具有愈來愈高密度的設計，配 置此類高密度裝置的技術通常需要特定的邏輯在晶片上 或在與可配置邏輯陣列經系統匯流排溝通的主機處理器 上執行。可配置邏輯陣列核心的配置資料管理需要複雜的 邏輯，參見頒給Lawman的美國專利第6, 049, 222號，配 置裝置用的特定技術限制該技術可應用的環境。 可配置邏輯陣列可經由使用者載入一配置資料以設 定在裝置上的可程式化元件的指定配置，並將配置資料交 付於其中的可程式化配置點以完成使用者指定的功能，例 如場可程式化閘極陣列包括一邏輯元件的陣列及大量可 使用配置資料加以程式化的連線。在晶片中配置資料儲存 於以記憶元件所構成的配置點中，通常以靜態隨機存取記 憶體（SRAM)之類的記憶胞實現，其他可配置邏輯陣列包括 非揮發性配置記憶體，使用唯讀記憶體（ROM)、快閃記憶 體（f lash)或可抹除可程式化唯讀記憶體（EPROM)之類的 1259396 記憶胞實現。 可電荷程式化、非揮發性記憶元件已經被用來作為可 程式化的開關及可配置邏輯陣列中的其他配置點。參見美 國專利第 5, 247, 478 號、第 5, 764, 096 號及第 6, 122, 209 號。 有關可配置邏輯陣列的一個問題係將配置資料載入 安裝在印刷電路板上的晶片或以其他方式結合到功能系 統中。參見美國專利第4, 879, 688號「系統中可程式化的 邏輯叙置」、弟5, 995, 744號「可程式化電路的網路裝置」、 第6, 028, 445號「場可程式化閘極陣列結構的解碼器構造 與方法」、第6, 049, 222號「使用嵌入式記憶體配置場可 程式化閘極陣列」以及第6，102,963號「具有在系統中程 式化及確認功能之電氣式可抹除及可程式化的非揮發性 整合儲存裝置以支援可程式化邏輯裝置在系統中的在配 置」。 系統單晶片（system-on-a-chip ; SOC)裝置增加了系 統的複雜度’因此S0C系統不易設計且改變費用昂貴。藉 由在處理益核心增加一可配置邏輯陣列與該處理器核心 連接可使得改變及設計較為容易，因此，可配置邏輯陣列 中的邏輯可利用工業上的工具結合可程式化邏輯的使用 而進行配置，同時處理器核心可使用習知的軟體程式技術 而程式化，但是可配置邏輯陣列模組的配置資料管理的問 通依舊存在。糸統早晶片技術在複雜系統上遇到的典型問 題即係不易設計且改變費用昂貴，將可配置邏輯陣列與處 1259396 理斋核心結合在一起，邏輯的組合可隨著處理器核心的改 良而改變，亦即經由可程式化邏輯陣列的配置工具可達成 邏輯的配置。 使系統單晶片在設計上更具彈性以及改良可配置邏 輯中管理配置的技術有所需求。 本發明提供使用嵌入式可配置邏輯的系統單晶片的 设計更大的彈性以及提供可配置邏輯的配置載入。 【發明内容】 本發明提供一種系統單晶片積體電路，包括一可配置 邏輯陣列、-處理器核心以及—記憶體用以儲存系統單晶 片的任務魏指令與用於經由積體電路上的輸人璋從外 部，載入配置資料到積體電路中的配置載入功能指令，處 理器核心從記憶體中呼叫並執行指令。 在-些實施例中，記憶體亦儲存了配置功能指令以載 入配置資料到可配置邏輯陣列中的電氣式可程式化配置 點、’在另一些實施例中，使用與可配置邏輯陣列結合的專 用建輯執仃配置功能’ 一介面介於處理器核心與晶片中可 配置邏輯陣列或配置邏輯之間以支援配置功能。 —記憶體包括-記憶陣列以儲存配置載入功能指令，在 1施例中該記憶體為非揮發性記憶體，如唯讀記憶體、 =動閘極記憶體及氮化金屬氧化半導體（nitHde娜）記 ^等’同樣地，配置功能指令亦可儲存於該記憶陣列 ，較佳者’配置載人功能指令儲存在可程式化記憶體 1259396 :，使得在電路中可以改變配置載人功能以適應不同配置 貝枓的遠端源以及與遠端源建立溝通管道的協定。 、，經由在晶片上提供配置功能及/或配置載入功能指令 亚由處理器核心執行’本發明的系統單晶片積體電路可以 t易地應用於廣泛的各種希冀可配置邏輯陣列的配置載 入的環境中。 —任務功能包括達成系統使用任務的特定使用者及/或 特疋用途指令。在使用非揮發性記憶體的實施例中，如高 速靜態隨機存取記憶體（high —speed SRM)或㈣隨機存 取π己k、體（DRAM)，該記憶體包括一記憶陣列以儲存任務功 能指令。在其他的實施例中，儲存任務功能指令的記憶體 包括非揮發性記憶體，如唯讀記憶體、浮動閘極記憶體、 氮化至屬氧化半導體記憶體或類似的記憶體。在一些實施 例中，儲存任務功能指令的記憶體可能包括揮發性與非揮 發性記憶體的組合。 在另外的實施例中，系統中配置載入及任務功能的配 置载入的指令均儲存於晶片中的非揮發性記憶體 ，如此， 可配置邏輯陣列的配置資料與任務功能指令二者的載入 可以被寫入位於電路板或其他系統中的系統單晶片裡。 在一些實施例中’配置載入功能及/或配置功能包括 使用看門狗計時器的程序，且積體電路中包括與處理器核 心結合在一起的看門狗計時器電路。 可配置邏輯陣列具有一由儲存於可配置邏輯陣列内 的電氣式可程式化配置點中的配置資料所定義的可程式 1259396 化配置，例如電氣式可程式化配置點包括浮動閘極記憶胞 或其他可電荷程式化、非揮發性記憶胞，在可配置邏輯陣 歹J的配置私序中配置資料會轉移到配置點中。 ^在一些實施例中，可程式化配置記憶體被包含在積體 上用以儲存配置資料，根據這些實施例，配置功能包 括從配置§己憶體中轉移配置資料到可配置邏輯陣列中的 If式化配置點’同樣地’配置載人功能包括經由在系統 早晶片積體電路中的輸人埠從資料的遠端源載入配置資 =配置記憶體中。在—些實_中，可程式化配置記憶 t用非揮發性、可程式化記憶胞，例如浮動閘極記憶體 或其他可電荷程式化非揮發性記憶體。在一些實施例中， 遺if取記憶體作為可程式化配置記憶體 支杈了配置璉輯陣列的快速配置改變。同樣地，一些實 ，例。，非揮發性§己憶體與高速揮發性記憶體二者，以 援配置資料在晶片上的儲存與處理。 在其他的實施例中，處理器核心回應一初始化事件， =如重置以執行配置載入及配置功能。根據本發明的系統 早晶片積體電路的-個實施例包括—看門狗計時器，依據 該看門狗計時器的時間間隔引發—初始化事件，該配置載 入功能包括設定看門狗計時器的時間間隔使其適用於從 遠端源接，配置資料的程序，以及若到達時叫隔時則執 行包括重試配置載入功能的初始化功能。 在另外的實施例中，記憶體儲存配置載人功能 功能及配置魏的指令。在諸如此類的實施例中力 置載入功能儲存於免於受配置載人功能而覆寫或修改的 1259396 記憶體中’第-配置載人功能提供—通道以供配置 貝=從一預設位置嵌入受保護的記憶體中。第二配置载入 功能儲存於未受保護的記憶體中，用來和配置資料遠 溝通’該配置資料可以^在預設位置。假如初始化事件^ 生於配置載人操作到改變第二配置載人功能的執行期 間，則第-配置載入功能可以絲回復配置載入操作。， 【實施方式】 本發明實施例的詳細說明參考圖1-8。一基本的系統 單晶片積體電路10如圖i所示，包括處理器核心⑴、例 如已知標準的觀或先進精簡指令集運算器（纖)模組， 或者，處理器核心11 Φ可由其他資料處理器核心例如數 位訊號處理器核心、高效率精簡指令集運算 (high-performance RISC)處理器核心或其他微處理器或 數位訊號處理器模組所取代或補充，受保護記憶體13及 可程式化記憶體14包括在積體電路1〇中，典型的受保護 記憶體13儲存啟動功能及其類似功能的指令避免被覆寫 或修改’典型的可程式化記憶體14儲存積體電路的任 務功能指令，輸出/輸人埠12亦包括在積體電路1〇中， 以支援輸人與輸出積體電路1Q #串聯資料通道及並聯資 料通道其中一個或二者。 在積體電路10中包括可配置邏輯陣列15以支援處理 器核心1卜可配置邏輯陣列15使用場可程式化閘極陣列 或其他形式的㈣置邏難組實現，可配置邏輯陣列15 1259396 包=弄多配置點用以儲存可配置邏輯陣列15的配置資料 並定義其功能，典型地，可配置邏輯陣列15包含在二系 統單晶片積體電路中以支援任務功能及執行特定的邏 輯。根據本發明，受保護記憶體13與可程式化記憶體14 其中之一所儲存的指令經由處理器核心U執行，該指令 包括邏輯以完成轉移配置資料到可配置邏輯陣列15中^ 置的配置功旎，該指令亦包含邏輯以完成配置載入以 萑定經由輸入/輸出埠12從遠端源載入配置資料到積體+ 路中的溝通管道。 、私 圖2係系統單晶片積體電路1〇替代實施例之簡化方 塊圖，根據圖2的實施例，在晶片上的處理器核心經由可 配置邏輯陣列15的程式段15A實現，程式段…的配置 資料儲存在程式段15A中非揮發性配置點或積體電路中受 保護記憶體13内，在本實施例中，根據積體電路的初始 化’配置資料從受保護記憶體13轉移到程式段i5A中， 處理器核心經由可配置邏輯陣列的程式段⑽實現，其執 仃指令類似於習知微處理器核心或其他處理器核心。 圖3係根據本發明的系統單晶片積體電路1〇另一替 代實施例之簡化方塊圖，在圖3的實施例中，一配置記‘ 體16被包括在晶片中，配置記憶體16儲存可配置邏輯陣 列15的配置資料且該配置資料根據初始化或在處理哭核 心。11的控制下或其他在晶片上的配置邏輯轉移到可配置 邏輯陣列中’配置記憶體16可使用唯讀記憶體實現，以 確定可配置邏輯陣列在製造過程中具有最小集合的配置 11 1259396 資料。在另一系統中，配 控制指令經由處理器核心二 從遠端源載入。在另一系 肖配置載入功此 讀記憶體與可程式化記憶體。m憶體16可結合唯 圖4係根據本發明的系統單晶片積體 :功能圖，根據本發明的較佳實施例，所有在單—積體電 路中實施的構成要素如圖 =早積體電 心inn制田⑯ 口 4所不5亥曰日片包括一處理器核 輯陳❹I特定目的的電路或如圖2中所述的可配置邏 旦to 2 =式段所實現’處理器核心100包括啟動向 里 5日守态102以支援看門狗計時器103，處理哭核 輸入/輸出物、至少-中斷請及其μ 輸入兵輸出106，在積體電路上的記憶體用以儲存指令 亚經由處理器核心100執行’該記憶體包括記憶陣列⑽ 用以儲存配置操作裝置的指令，其包括配置載入功能及配 置功能以支援在積體電路上的可配置邏輯陣列11〇。在一 些實施例中，配置操作裝置包括一初始化功能的執行以回 應-初始化事件’像是經由—中斷訊號或看門狗計時器 103重置所引發的重置。該記憶體尚包括記憶陣列⑽用 以儲存系統單晶片積體電路的任務功能指令，以及記憶陣 列109用以儲存受保護的功能，包括啟動功能、内電路程 式化功能及可配置邏輯陣列配置載入備份功能。記憶陣列 109被保護免於經由一内電路程式化（icp)功能而覆寫或 修改，並在例如重置事件及内電路程式化程序或配置載入 程序失敗時的初始化功能期間回復系統。 12 1259396 該記憶體可使用變化多樣的記憶胞技術，包括遮罩式 唯讀記憶體（mask ROM)、快閃記憶體、靜態隨機存取記憶 體以及類似的適合特定實施裝置來實現，典型的受保護記 k陣列10 9經由非揮發性記憶體例如遮罩式唯讀記憶體或 快閃記憶體來實現，當經由快閃記憶體或其他電氣式可程 式化纪憶體所實現時，邏輯結構可保護記憶陣列1 〇9免於 因配置載入的操作或意外而被覆寫或修改。 在積體電路中可配置邏輯陣列11〇如圖4的實施例， 經由一以快閃記憶體為基礎的可配置邏輯陣列來實現，在 以〖夬閃0己憶體為基礎的可配置邏輯陣列中，配置點係為非 揮卷，使付配置資料在重置或斷電時仍會保留下來。 在積體電路中有一介面介於處理器核心1〇〇與可配置 璉輯陣列110之間，該介面包括其他在此技術中已知的結 構:資料記錄m、配置記錄112以及計時記錄113，且 f資料、配置資料以及計時訊號經由該介面在模組間進行 父換狀恶圮錄115經由協議的配置功能破認使用配置資 料的可配置邏輯陣列的配置成功。 處理器核心100可經由如多工器114所示的指令路徑 從包括記憶_ 1G7、⑽、1G9的記憶體中檢索指令，: 他2括如靜態隨機存取記憶體或記錄陣列的記憶體結構 包含在積體電路中，以支援經由處理器核w 10G或可配置 邏輯陣列110的執行功能。 在® 4的實施财，配置操作裝置的配置載人功能儲 子㈠己憶陣列107中，以嫁定介於系統單晶片積體電路與 13 !259396 配置遠端源之_溝衫道，該料管道藉由輸入 士則出皐1G4接收配置資料，該配置資料經由在配置操 ^置中的配置功能通過配置記錄112到達在可配置邏輯陣 列110中以快閃記憶體為基礎的配置點。 在配置載入演算的過程中發生重置的事件或其他初 始化事件，則配置載入功能將會重新執行。 内電路程式化（ICP)程式亦可儲存於記憶體中，例 如儲存於受保護的記憶陣列1〇9中或其他位置，用於覆寫 或修改配置操作裝置，使得配置載入功能可適用於從使用鲁 者選定的遠端源接收配置資料，根據本發明的這些實施 例可配置邏輯陣列的配置載入備份功能儲存於受保護的 以思陣列109中’當儲存於記憶陣列107中的配置操作裝 置發生錯誤時，系統可湘儲存於受保護的記憶_⑽· 中的功能回復原狀，根據美國專利第6, 401，221號、第、 6,493,788號以及第5,901，33〇號中所揭露的内電: 化功能是適合使用的。 ' 圖5係根據本發明的系統單晶片積體電路的替代結馨 構’相似的構成要素給予目4中使用的相同編號。根據如 圖5所示的替代結構，可配置邏輯陣列15〇不需使用以快 閃=憶體或其他非揮發性配置點為基礎的可配置邏輯陣 列實現，例如，可配置邏輯陣列15〇可使用具有以靜態隨 機存取記憶體（SRAM)為基礎的配置點的標準型場可程式 化閘極陣列（FPGA)來實現。 、 可配置邏輯陣列150的配置資料儲存在非揮發性配置 14 Ϊ259396 貧料記憶陣列151中，並由處理器核心loo取得積體電路 的部份記憶體而實現，在本實施例中使用控制電路丨作 為配置資料記憶陣列151與處理器核心1〇〇之間的介面， 在記憶陣列107中配置操作裝置的配置載入功能用以確定 遠端源與配置資料記憶陣列151間的通道，在配置演算過 程中記憶陣列107中配置操作裝置的配置功能從配置資料 圮憶陣列151經過處理器核心1〇〇轉移配置資料到可配置 邏輯陣列150。 圖6係根據本發明的系統單晶片積體電路的替代結 構，相似的構成要素給予圖5中使用的相同編號。根據如 圖6所不的替代結構，可配置邏輯陣列16〇可使用可程式 化邏輯裝置（PLD)模組來實現，可配置邏輯陣列16〇的配 置資料儲存在非揮發性配置資料記憶陣列161中，並由處 理器核心100取得積體電路的部份記憶體而實現，控制電 路162作為配置資料記憶陣列161與可配置邏輯陣列16〇 之間的介面，使得記憶陣列1〇7的配置功能直接經由配置 功能專用的資料路徑170、171從配置資料記憶陣列161 轉移配置資料到可配置邏輯陣列16〇中，資料路徑17〇、 171 了使用覓頻並聯資料路徑或其他適用於配置功能之高 速、特別配置的資料路徑來實現，在本實施例中，記憶陣 列107中的配置功能可以簡化或忽略，且其更多的功能由 控制電路162來達成。 記憶陣列107中配置操作裝置的配置載入功能用以 確疋运％源與配置資料記憶陣列1 6 1間的通道。 15 1259396 圖7係根據本發明的系統單晶片積體電路的替代釺 構，相似的構成要素給予目6中使用的相同編號。根據如 囷7所示的替代結構，記憶體增加一記憶陣列1 π用以儲 存加密/解密功能及壓縮/解壓縮功能指令其中至少之 -，根據如® 7所示的實施例，配置載人功能確遠端 源與配置貧料記憶陣列161間的通道，配置資料以加密形 式、壓縮形式或加密及壓縮形式從遠端源接收，當载入配 置資料到配置資料記憶陣列161肖，配置載人功能從記憶 陣列172中進行解密及/或解壓縮功能，或者，當轉移配 置貧料到可配置邏輯陣列中的配置點時，酉己置載入功能從 讀陣列172巾進行解密及/或解壓縮功能，增加的記憶 陣列172儲存加密/解密功能及壓縮/解壓縮功能其中至少 之一，以用於不同的系統單晶片積體電路的實施例，包括 如圖4及圖5所示之實施例。 、圖8係一些與本發明觀點相同的内電路程式化及配置 載入的容錯系統之主要功能構成要素的方塊圖， 一系統單 晶片積體電路包括一處理器核心（cpu)212及一可配置邏 輯陣列251。内電路程式化程序及配置載入系統包括非揮 發記憶體200、隨機存取記憶體（RAM)2〇8、cpu 212及周 邊裝置214。該内電路程式化程序及配置載入系統亦包括 容錯系統的構成要素，包括跳躍啟動向量216、多工器 (MUX)210、内電路程式化/配置載入（Icp/CL)狀態218、遠 知主機地址§己錄220及JXP/CL看門狗222。 更明確地，CPU 212係任何形式的處理系統，包括微 16 1259396 控制态、微處理器或數位訊號處理器。cpu 212與r趙2⑽ 釔&在起且隨機存取記憶體所包含的編碼及資料經由 CPU 212執仃，此外，CPU 212亦經過由MUX 21〇所表示 的資料路徑與非揮發性記憶體2〇〇結合在一起。 非揮發性記憶體200係當系統斷電時仍可保存資料的 任何形式的記憶體，包括快閃記憶體、可㈣式化唯 讀記憶體(EP_)、電氣式可抹除可程式化唯讀記憶體 (EEPROM)及唯讀記憶體，非揮發性記憶體包括啟動程 式202 a用％式204、内電路程式化（ICp)操作裝置2〇6、 配置操作裝置250以及微啟動碼2〇7。啟動程式2〇2包括 在系統減化的程序中執行程式的收集以將系統的硬體 及权體貝源初始化，啟動程< 2Q2儲存於可程式化記憶體 中並可在配置載人的過程中被修正。非揮發性記憶體糊 亦包括公用程式2Q4，該公用程式m在系統的演算過程 中。包括許多程式經由CPU 212執行以完成任務功能，公用 弋204亦可被包含於經由内電路程式化載入程序中可被 壯弋化的屺f思體中。非揮發性記憶體亦包括配置操作 衣置250以進仃系統的配置載入功能且其可被包含於經由 -置載入私序中可被程式化的記憶體中，非揮發性記憶體 2⑽中所包括的配置操作裝置聊可被包含於經由内電路 淨式化私序中可被程式化的記憶體中。配置操作裝置 所執行的功能如之前圖4-7所述。 μ非揮發性Α憶體2〇〇同時包括位於受保護記憶體内的 動馬207 ’彳政啟動碼207在相同内電路正常啟動程式 17 1259396 程序與配置操作壯 替代系統初始化二八呈式中不會被修改’微啟動碼207可 能，然而，當有以Γ成許多如啟動程式202的相同功 於内電路程式化=1此由啟動程式2G2引起的錯誤發生 裝置250失敗β 即iCP彳呆作裝置206或配置操作 行為，因此時，微啟動竭207只是-個跳脫的 的^ 過程巾不會被修改的記憶體巾。在本發明 及丨CP操作裝請儲存在可程一^^^ 守’微啟動碼207儲存在遮罩式唯讀記憶體中。 —在ICP程序中，CPU 212同時結合硬體構成要素以幫 助容錯，CPU 212結合臓210作為非揮發性記憶體2〇〇 及跳躍啟動向量216的輸入且控制從Icp/CL狀態218的 輸入，MUX 210視ICP/CL狀態218的狀況選擇性切換cpu 212於跳躍啟動向量216及非揮發性記憶體2〇〇之間，若 ICP/CL狀態218是髒的，表示之前的ICP演算或演算修正 配置載入運算沒有完成，則CPU 212在系統初始化的程序 中輸入一個跳躍指令給啟動向量216以指向微啟動碼 207，另一方面，若κρ/CL狀態218是乾淨的，表示沒有 配置載入運算在進行，則CPU 212在系統初始化的程序中 輸入非揮發性記憶體200的初始載入，CPU 212同時結合 遠端主機地址記錄220並包含備份遠端主機地址，避免在 内電路程式化程序中發生系統重置，CPU 212亦透過讀/ 寫路徑230及重置線232與ICP/CL看門狗222結合， 18 1259396 ICP/CL看門狗222包括到期週期（timeout period)記錄 226及計時器224與匹配邏輯228，計時器224及到期週 期記錄226二者可透過讀/寫路徑230經由CPU 212而被 初始化，當計時器224的值與到期週期記錄226相同時， 匹配邏輯228引發一個重置訊號經由重置線232傳送到 CPU 212。在一實施例中，上述提到的硬體構成要素提供 的容錯包括保護可程式化記憶元件免受内電路程式化程 序的影響。 此外，CPU 212結合周邊裝置214，包括連接系統使 用者的輸入及輸出裝置，如圖中周邊裝置214左邊的雙箭 號所示，周邊裝置214亦包括一介面通過周邊裝置214與 網際網路234、或其他溝通管道或網路結合。網際網路234 本身結合了遠端主機236、238及240，遠端主機238結合 了包含新版本的啟動及公用程式的磁碟片242，包括例如 新的内電路程式化功能或新的配置載入功能並經由網際 網路234下載到系統中。 配置載入程序通常運作如下，首先CPU 212透過周邊 裝置214與使用者244連接，使用者244引發CPU 212開 始執行配置操作裝置250進行配置載入程序，配置操作裝 置250引發通過周邊裝置214到網際網路234及通過網際 網路234到遠端主機238之間的連接，接著遠端主機238 開始從磁碟片242通過網際網路234下載資料到非揮發性 記憶體200中，同時資料開始轉移、在ICP/CL看門狗222 中的到期週期記錄226設定一估計值及計時器224開始計 19 1259396 若配置載入程序進行順利，則本發明的容錯特徵為非 活性化的，另一方面，若在配置載入程序中發生過度延 遲’則計時器224最終將與到期週期記錄226相同而引發 一重置訊號經由重置線232到達CPU 212，並引發CPU 212 開始進行一連串的啟動。若系統在配置載入程序中重新啟 動’則ICP/CL狀態218設定為髒的值，因而引發圆X 210 直接跳躍啟動向量216到CPU 212中，使得微啟動碼207 代替啟動程式202引發CPU 212啟動。若ICP/CL狀態218 設定為乾淨的值，表示配置載入程序已全部完成且Μυχ 210 從啟動程式202引發CPU 212啟動。 微啟動碼207引發CPU 212重新開始配置載入程序， 係經由從遠端主機地址記錄220的第一個讀取值決定遠端 主機的連接以重新開始配置載入程序，然後配置載入程序 即重新開始。在另一實施例中’微啟動碼2〇7包括一配置 載入程式化的設計，用域魏位置存取配置資料的設 t 性記憶體或經由連接—預定的主 機與系統單晶片積體電路結合。 、 icp程序通常運作如下，首先Gpu 212透過周邊裝置 用⑽連接，一些非典型系統單晶片積體電路 係^由輸人/輸出埠而與使用者連接，使用者⑽引發㈣ 212開始執行1CP操作裝置2〇6進行ICP程序，icp操 裝置2G6引發通過周邊裝置214到網際網路234及通過網 際網路234到遠端主機238之間的連接，接著遠端主編 20 1259396 開始從磁碟片242通過網際網路234下載資料到非揮發性 記憶體200中，同時資料開始轉移、在Icp/CL看門狗222 中的到期週期記錄226設定一估計值及計時器224開始計 時。 若ICP程序進行順利，則本發明的容錯特徵為非活性 化的，另一方面，若在ICP程序中發生過度延遲，則計時 224最終將與到期週期記錄226相同而引發一重置訊號 經由重置線232到達CPU 212，並引發CPU 212開始進行 一連串的啟動。若系統在ICP程序中重新啟動，則ICP/CL 狀態218設定為髒的值，因而引發Μυχ 21〇直接跳躍啟動 向量216到CPU 212中，使得微啟動碼207代替啟動程式 202引發CPU 212啟動。若ICP/CL狀態218設定為乾淨的 值，表示ICP程序已全部完成，且MUX 210從啟動程式202 引發CPU 212啟動。 微啟動碼207引發CPU 212重新開始ICP程序，係經 由從遠端主機地址記錄220的第一個讀取值決定遠端主機 的連接以重新開始ICP程序，然後icp程序即重新開始。 在一些實施例中，ICP程序可以覆寫或修改配置操作 裝置250，在這些實施例中，ICP程序首先備份配置操作 裝置250到非揮發性記憶體中以碟定在系統單晶片上配置 載入的二份備份，其中一份備份是修改過的，若修改完全 成功則另一份備份會被刪除，不過，若修改沒有完全成功 則配置操作裝置的安全備份可用來回復系統操作。 以上對於本發明之較佳實施例所作的敘述係為闡明 21 1259396 之目的無意限定本發_確地為所揭露的形式，基於 以^的教導或從本發明的實施例學習而作修改或變化是 可月b的，貫施例係為解說本發明的原理以及讓熟習該項技 術者以各種實施例湘本發明在實際制上*選擇及敘 ，，本發明的技術思想企圖由以下的申請專利範圍及其均 【圖式簡單說明】 對於熟習本技藝之人士而言，從以下所作的詳細敛述 配合伴隨的圖式’本發明將能夠更清楚地被瞭解，其上述 及其他目的及優點將會變得更明顯，其中·· 圖1係根據本發明的系統單晶片積體電 例之簡化方塊圖； 圖2係根據本發明的系統單晶片積體電路的另一實施 例之簡化方塊圖； 、 圖3係根據本發明的系統單晶片積體電 例之簡化方塊圖； s % 圖4係根據本發明的系統單晶片積體電路之較詳細的 功能示意圖； „圖5係根據本發明在晶片上包括配置資料記憶體的系 統早晶片積體電路的一個實施例之功能示意圖； 圖6係根據本發明在晶片上包括配置資料記憶體的系 統單晶片積體電路的另—實施例之功能示意圖； 圖7係根據本备明在晶片上包括配置資料記憶體並支 22 1259396 援加密/解密及/級縮/解I縮的系統單晶片 —個實施例之功能示意圖；以及 电路的 圖8係根據本發明所提供系統單晶片1259396 IX. Description of the Invention: [Technical Field] The present invention relates to a system single-chip integrated circuit and other processor devices and methods including embedded configurable logic arrays as special purpose or client wafer logic. [Prior Art] Configurable logic arrays including, for example, known programmable logic devices (PLDs) and field programmable gate arrays (FPGAs), and more widely known programmable logic arrays (PLAs) having Increasingly dense designs, the technology to configure such high-density devices typically requires specific logic to be executed on the wafer or on a host processor that communicates with the configurable logic array via the system bus. The configuration data management of the configurable logic array core requires complex logic, see U.S. Patent No. 6,049,222 issued to Lawman, the specifics of which are incorporated herein by reference. The configurable logic array can load a configuration profile by the user to set a specified configuration of the programmable elements on the device and deliver the configuration data to the programmable configuration points therein to perform user-specified functions, such as The programmable gate array includes an array of logic elements and a number of connections that can be programmed using configuration data. The configuration data in the wafer is stored in a configuration point formed by the memory element, usually implemented by a memory cell such as a static random access memory (SRAM), and other configurable logic arrays include non-volatile configuration memory, using only Read memory (ROM), flash (flash) or erasable programmable read-only memory (EPROM) such as 1259396 memory cell implementation. Charge-stabilized, non-volatile memory components have been used as programmable switches and other configuration points in configurable logic arrays. See U.S. Patent Nos. 5,247,478, 5,764,096 and 6,122,209. One problem with configurable logic arrays is loading the configuration data into a wafer mounted on a printed circuit board or otherwise incorporated into a functional system. See U.S. Patent No. 4,879,688, "Programmable Logic Arrangement in Systems", Brother 5, 995, 744, "Network Devices for Programmable Circuits", No. 6, 028, 445 "Decoder structure and method for stylized gate array structure", No. 6, 049, 222 "Using embedded memory to configure field programmable gate array" and No. 6,102,963 "has been programmed in the system and Confirmation of functional electrical erasable and programmable non-volatile integrated storage devices to support the configuration of programmable logic devices in the system". System-on-a-chip (SOC) devices increase the complexity of the system. Therefore, the SOC system is not easy to design and expensive to change. By adding a configurable logic array to the processor core at the processing core to make changes and design easier, the logic in the configurable logic array can be leveraged using industrial tools in conjunction with the use of programmable logic. Configuration, while the processor core can be programmed using conventional software programming techniques, but the configuration data management of the configurable logic array module still exists. The typical problems encountered by SiS early wafer technology on complex systems are that they are not easy to design and costly to change. The configurable logic array is combined with the 1259396 core, and the combination of logic can be improved with the processor core. The change, that is, the configuration tool through the programmable logic array, can achieve a logical configuration. Techniques are needed to make system single-chips more flexible in design and to improve management configurations in configurable logic. The present invention provides greater flexibility in the design of system single-chips using embedded configurable logic and configuration loading that provides configurable logic. SUMMARY OF THE INVENTION The present invention provides a system single-chip integrated circuit including a configurable logic array, a processor core, and a memory for storing a system single-chip task and a command for transmission via an integrated circuit. From the outside, the configuration load data is loaded into the configuration load function instruction in the integrated circuit, and the processor core calls and executes the instruction from the memory. In some embodiments, the memory also stores configuration function instructions to load configuration data into an electrically programmable configuration point in the configurable logic array, 'in other embodiments, the use is combined with a configurable logic array The dedicated configuration configuration feature 'an interface between the processor core and the configurable logic array or configuration logic in the chip to support configuration functions. The memory includes a memory array for storing configuration load function commands. In one embodiment, the memory is a non-volatile memory such as a read-only memory, a dynamic gate memory, and a metal nitride oxide semiconductor (nitHde).娜)记^等' Similarly, the configuration function instructions can also be stored in the memory array. Preferably, the 'configure manned function command is stored in the programmable memory 1259396: so that the configuration manned function can be changed in the circuit. Adapt to the remote source of different configurations of Bellow and the agreement to establish communication channels with the remote source. The system single-chip integrated circuit of the present invention can be easily applied to a wide variety of configurations of various configurable logic arrays by providing configuration functions on the wafer and/or configuring load function instructions. Into the environment. - Task functions include specific user and/or special purpose instructions for achieving system usage tasks. In embodiments using non-volatile memory, such as high-speed SRAM or (four) random access π, k, DRAM, the memory includes a memory array to store tasks Function instructions. In other embodiments, the memory storing the task function instructions includes non-volatile memory such as read only memory, floating gate memory, nitrided to oxidized semiconductor memory, or the like. In some embodiments, the memory storing the task function instructions may include a combination of volatile and non-volatile memory. In another embodiment, the configuration load instructions of the load and task functions in the system are stored in non-volatile memory in the chip, and thus, the configuration data of the configurable logic array and the task function instructions are loaded. Incoming can be written to a single system chip on a circuit board or other system. In some embodiments, the configuration load function and/or configuration function includes a program that uses a watchdog timer, and the integrated circuit includes a watchdog timer circuit that is coupled to the processor core. The configurable logic array has a programmable 1259396 configuration defined by configuration data stored in an electrically programmable configuration point within the configurable logic array, such as an electrically programmable configuration point including a floating gate memory cell or Other chargeable, non-volatile memory cells, in the configuration logic of the configurable logic array J, will be transferred to the configuration point. In some embodiments, the programmable configuration memory is included on the integrated body for storing configuration data. According to these embodiments, the configuration function includes transferring configuration data from the configuration § memory to the configurable logic array. The If-style configuration point 'samely' configures the manned function including loading the configuration resource = configuration memory from the remote source of the data via the input in the system early chip integrated circuit. In some real _, stylized configuration memory t uses non-volatile, programmable memory cells, such as floating gate memory or other chargeable stylized non-volatile memory. In some embodiments, the legacy of the memory as a programmable configuration memory supports a quick configuration change of the configuration array. Similarly, some real, examples. , non-volatile § memory and high-speed volatile memory, in order to aid in the storage and processing of configuration data on the wafer. In other embodiments, the processor core responds to an initialization event, such as resetting to perform configuration loading and configuration functions. An embodiment of the system early wafer integrated circuit according to the present invention includes a watchdog timer that initiates an initialization event according to a time interval of the watchdog timer, the configuration load function including setting a watchdog timer The time interval makes it suitable for programs that are connected from a remote source, configures the data, and performs an initialization function that includes a retry configuration load function if called when it arrives. In a further embodiment, the memory stores instructions for maneuvering functional functions and configuring Wei. In an embodiment such as this, the force loading function is stored in the 1259396 memory that is overwritten or modified from the configuration manned function. The 'first-management function provides a channel for the configuration of the bay = from a preset position Embed in protected memory. The second configuration load function is stored in unprotected memory and is used to communicate with the configuration data. The configuration data can be placed at a preset location. If the initialization event is generated during the execution of the manned operation to change the execution of the second configuration manned function, the first configuration load function can revert to the configuration load operation. [Embodiment] A detailed description of an embodiment of the present invention refers to FIGS. 1-8. A basic system single-chip integrated circuit 10, as shown in FIG. 1, includes a processor core (1), such as a known standard view or advanced reduced instruction set operator (fiber) module, or the processor core 11 Φ can be other Data processor cores such as digital signal processor cores, high-performance RISC processor cores or other microprocessor or digital signal processor modules are replaced or supplemented, protected memory 13 and The stylized memory 14 is included in the integrated circuit 1A. The typical protected memory 13 stores instructions for the boot function and the like to avoid overwriting or modifying the task of the typical programmable memory 14 storing the integrated circuit. The function command, output/input 埠12 is also included in the integrated circuit 1 , to support one or both of the input and output integrated circuits 1Q # series data channel and parallel data channel. Included in the integrated circuit 10 is a configurable logic array 15 to support the processor core 1 configurable logic array 15 using a field programmable gate array or other form of (four) set of logic difficulties, configurable logic array 15 1259396 package The configuration point is used to store the configuration data of the configurable logic array 15 and define its functionality. Typically, the configurable logic array 15 is included in the two-system single-chip integrated circuit to support task functions and execute specific logic. In accordance with the present invention, instructions stored by one of the protected memory 13 and the programmable memory 14 are executed via the processor core U, the instructions including logic to complete the configuration of transferring the configuration data to the configurable logic array 15. In effect, the instruction also includes logic to complete the configuration load to determine the communication pipeline from the remote source to the integrated data via the input/output port 12. The private graph 2 system single-chip integrated circuit 1 〇 simplified block diagram of an alternative embodiment, according to the embodiment of FIG. 2, the processor core on the wafer is implemented via the program segment 15A of the configurable logic array 15 ... The configuration data is stored in the protected memory 13 in the non-volatile configuration point or the integrated circuit in the block 15A. In this embodiment, the configuration data is transferred from the protected memory 13 to the program according to the initialization of the integrated circuit. In segment i5A, the processor core is implemented via a configurable logic array block (10), the execution instructions of which are similar to conventional microprocessor cores or other processor cores. 3 is a simplified block diagram of another alternative embodiment of a system monolithic integrated circuit 1 in accordance with the present invention. In the embodiment of FIG. 3, a configuration of the body 16 is included in the wafer, and the memory 16 is stored. The configuration data of the logic array 15 can be configured and the configuration data is based on initialization or processing the crying core. The configuration logic under 11 or other on-wafer transfers to the configurable logic array 'configuration memory 16 can be implemented using read-only memory to determine the configuration of the configurable logic array with the smallest set of manufacturing 11 1259396 . In another system, the control instructions are loaded from the remote source via processor core two. In another system, the read memory and the programmable memory are loaded. The m memory 16 can be combined with only the system 4 single-chip integrated body according to the present invention: a functional diagram. According to a preferred embodiment of the present invention, all the constituent elements implemented in the single-integrated circuit are as shown in the figure: early integrated body The core of the inn 16 mouth 4 not 5 曰 曰 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 100 includes starting the inward 5th state of the gate 102 to support the watchdog timer 103, processing the crying core input/output, at least the interrupt and its μ input soldier output 106, and storing the memory on the integrated circuit for storage. The instructions are executed via the processor core 100. The memory includes a memory array (10) for storing instructions to configure the operating device, including configuration load functions and configuration functions to support the configurable logic array 11 on the integrated circuit. In some embodiments, the configuration operating device includes an initialization function to respond to the initialization event as if the reset was initiated via an interrupt signal or a reset of the watchdog timer 103. The memory further includes a memory array (10) for storing task function instructions of the system single-chip integrated circuit, and a memory array 109 for storing protected functions, including a boot function, an internal circuit stylization function, and a configurable logic array configuration. Enter the backup function. The memory array 109 is protected from being overwritten or modified via an internal circuit stylization (icp) function and replies to the system during initialization functions such as reset events and internal circuit stylization programs or configuration loader failures. 12 1259396 This memory can be implemented using a variety of memory cell technologies, including masked ROM, flash memory, SRAM, and similar suitable implementation devices, typically Protected k array 10 9 is implemented via non-volatile memory such as masked read-only memory or flash memory, when implemented via flash memory or other electrically programmable memory. The structure protects the memory array 1 〇 9 from being overwritten or modified due to configuration loading operations or accidents. The logic array 11 can be configured in an integrated circuit, as in the embodiment of FIG. 4, via a configurable logic array based on a flash memory, in a configurable logic based on a flash memory In the array, the configuration point is non-revolution, so that the configuration data will remain when reset or power off. There is an interface between the processor core 1 and the configurable array 110 in the integrated circuit, the interface including other structures known in the art: a data record m, a configuration record 112, and a timing record 113, And the f data, the configuration data, and the timing signal are successfully configured by the configuration function of the protocol through the configuration function of the parent to change the configuration of the configurable logic array using the configuration data. The processor core 100 can retrieve instructions from the memory including the memory _1G7, (10), 1G9 via an instruction path as shown by the multiplexer 114: the memory structure of the static random access memory or the recording array Included in the integrated circuit to support execution functions via the processor core w 10G or the configurable logic array 110. In the implementation of the ® 4, the configuration of the operating device configuration manned function storage (1) memory array 107, to marry the system single-chip integrated circuit and 13 !259396 configuration of the remote source of the ditch shirt, the The material pipeline receives the configuration data by inputting 1G4, and the configuration data reaches the flash memory-based configuration point in the configurable logic array 110 through the configuration record 112 via the configuration function in the configuration operation. The configuration load function will be re-executed if a reset event or other initialization event occurs during the configuration of the load calculus. The internal circuit programming (ICP) program can also be stored in the memory, for example, in the protected memory array 1 or 9 or other locations for overwriting or modifying the configuration operating device, so that the configuration loading function can be applied to The configuration data is received from the remote source selected by the user, and the configuration load backup function of the configurable logic array is stored in the protected array 109 in the configuration of the storage array 107 in accordance with the embodiments of the present invention. In the event of an error in the operating device, the system can be restored to its original state in the protected memory _(10)·, as disclosed in U.S. Patent Nos. 6,401,221, 6,493,788 and 5,901,33. Internal power: The function is suitable for use. Figure 5 is a diagram showing the same components used in the fourth embodiment of the system single-chip integrated circuit according to the present invention. According to an alternative configuration as shown in FIG. 5, the configurable logic array 15 does not need to be implemented with a configurable logic array based on flash = memories or other non-volatile configuration points, for example, a configurable logic array 15 This is accomplished using a standard field programmable gate array (FPGA) with static random access memory (SRAM) based configuration points. The configuration data of the configurable logic array 150 is stored in the non-volatile configuration 14 Ϊ 259396 poor memory array 151, and is implemented by the processor core loo to obtain a partial memory of the integrated circuit. In this embodiment, the control circuit is used. As a interface between the configuration data memory array 151 and the processor core 1A, the configuration loading function of the operating device is configured in the memory array 107 to determine the channel between the remote source and the configuration data memory array 151. The configuration function of the configuration operating device in the memory array 107 during the calculation process transfers the configuration data from the configuration data memory array 151 to the configurable logic array 150 via the processor core 1 . Fig. 6 is an alternative construction of a system single wafer integrated circuit in accordance with the present invention, and similar constituent elements are given the same reference numerals as used in Fig. 5. According to an alternative configuration as shown in FIG. 6, the configurable logic array 16 can be implemented using a programmable logic device (PLD) module, and the configuration data of the configurable logic array 16A is stored in the non-volatile configuration data memory array 161. The memory core 100 is implemented by the processor core 100 to obtain a partial memory of the integrated circuit. The control circuit 162 serves as an interface between the configuration data memory array 161 and the configurable logic array 16A, so that the memory array 1-7 is configured. The configuration data is transferred from the configuration data storage array 161 directly to the configurable logic array 16A via the configuration function-specific data paths 170, 171. The data paths 17〇, 171 use the parallel frequency data path or other high speed suitable for the configuration function. The specially configured data path is implemented. In this embodiment, the configuration function in the memory array 107 can be simplified or ignored, and more functions thereof are achieved by the control circuit 162. The configuration loading function of the operating device is arranged in the memory array 107 to ensure the channel between the % source and the configuration data memory array 161. 15 1259396 Figure 7 is an alternative construction of a system monolithic integrated circuit in accordance with the present invention, with similar components being given the same numbering as used in Figure 6. According to an alternative structure as shown in FIG. 7, the memory adds a memory array 1 π for storing at least one of an encryption/decryption function and a compression/decompression function command, and according to the embodiment shown in FIG. 7, the configuration manned The function is the channel between the remote source and the configured poor memory memory array 161. The configuration data is received from the remote source in encrypted form, compressed form or encrypted and compressed form. When the configuration data is loaded into the configuration data memory array 161, the configuration is carried. The human function performs a decryption and/or decompression function from the memory array 172, or when the transfer configuration is poor to a configuration point in the configurable logic array, the load function is decrypted from the read array 172 and/or Decompression function, the added memory array 172 stores at least one of an encryption/decryption function and a compression/decompression function for different system single-chip integrated circuit embodiments, including as shown in FIG. 4 and FIG. Example. FIG. 8 is a block diagram showing the main functional components of the internal circuit stylized and configured loaded fault-tolerant system, which is the same as the present invention. The system single-chip integrated circuit includes a processor core (cpu) 212 and a The logic array 251 is configured. The internal circuit programming program and configuration loading system includes non-volatile memory 200, random access memory (RAM) 2〇8, cpu 212, and peripheral device 214. The internal circuit programming program and configuration loading system also includes components of the fault tolerant system, including a jump start vector 216, a multiplexer (MUX) 210, an internal circuit stylization/configuration load (Icp/CL) state 218, and a far Know the host address § has recorded 220 and JXP / CL watchdog 222. More specifically, CPU 212 is any form of processing system, including micro 16 1259396 control state, microprocessor or digital signal processor. Cpu 212 and r Zhao 2(10) 钇& The code and data contained in the random access memory are executed by the CPU 212, and the CPU 212 also passes through the data path and non-volatile memory represented by the MUX 21〇. 2〇〇 combined. Non-volatile memory 200 is any form of memory that can save data when the system is powered off, including flash memory, (4-) read-only memory (EP_), electrical erasable programmable only Read memory (EEPROM) and read-only memory. Non-volatile memory includes boot program 202a using %204, internal circuit stylized (ICp) operating device 2〇6, configuration operating device 250, and micro-boot code 2〇 7. The startup program 2〇2 includes the collection of the execution program in the system reduction program to initialize the hardware and the source of the system, and the startup process < 2Q2 is stored in the programmable memory and can be configured in the manned Corrected in the process. The non-volatile memory paste also includes the utility 2Q4, which is in the process of calculating the system. A number of programs are executed via the CPU 212 to perform the task function, and the public device 204 can also be included in the body that can be enhanced by the internal circuit stylized loading program. The non-volatile memory also includes a configuration loading device 250 configured to perform the configuration loading function of the system and can be included in the memory that can be programmed in the private sequence via the -, non-volatile memory 2 (10) The configuration of the operating device included in the memory can be included in the memory that can be programmed in the private program via the internal circuit. Configuring the operating device The functions performed are as described in Figure 4-7 above. μ non-volatile memory 2〇〇 also includes the moving horse 207 in the protected memory. The 启动 启动 startup code 207 is in the same internal circuit normal startup program 17 1259396 program and configuration operation strong replacement system initialization two eight presentation It will not be modified 'micro-start code 207 may, however, when there is a lot of the same function as the start-up program 202, the error-generating device 250 is caused by the start-up program 2G2 = β is iCP Actuating device 206 or configuring the operational behavior, therefore, micro-starting 207 is just a tripping of the process towel that will not be modified by the memory towel. In the present invention and the CP operating device, it is stored in a maskable read-only memory stored in the mask-type read-only memory. - In the ICP procedure, CPU 212 incorporates hardware components to aid fault tolerance, CPU 212 combines 臓210 as input to non-volatile memory 2 and jump start vector 216 and controls input from Icp/CL state 218, The MUX 210 selectively switches the cpu 212 between the jump start vector 216 and the non-volatile memory 2〇〇 depending on the state of the ICP/CL state 218. If the ICP/CL state 218 is dirty, it indicates the previous ICP calculation or calculation correction. If the configuration load operation is not completed, the CPU 212 inputs a jump instruction to the start vector 216 to point to the micro start code 207 in the system initialization program. On the other hand, if the κρ/CL state 218 is clean, it indicates that no load is configured. When the operation is in progress, the CPU 212 inputs the initial loading of the non-volatile memory 200 in the system initialization program, and the CPU 212 combines the remote host address record 220 and includes the backup remote host address to avoid the internal circuit stylization program. In the event of a system reset, the CPU 212 also interfaces with the ICP/CL watchdog 222 via the read/write path 230 and the reset line 232. 18 1259396 The ICP/CL watchdog 222 includes an expiration period (timeout pe) The riod) record 226 and the timer 224 and the matching logic 228, both the timer 224 and the expiration cycle record 226 are initialized via the CPU 212 via the read/write path 230, when the value of the timer 224 and the expiration cycle are recorded 226 When identical, matching logic 228 causes a reset signal to be transmitted to CPU 212 via reset line 232. In one embodiment, the fault tolerance provided by the hardware components mentioned above includes protecting the programmable memory component from internal circuit stylization. In addition, the CPU 212 incorporates peripheral devices 214, including input and output devices for connecting system users. As shown by the double arrows on the left side of the peripheral device 214, the peripheral device 214 also includes an interface through the peripheral device 214 and the Internet 234. , or other communication channels or networks. The Internet 234 itself incorporates remote hosts 236, 238, and 240 that incorporate a disk 242 containing a new version of the boot and utility, including, for example, new internal circuit staging functions or new configuration loads. The function is entered and downloaded to the system via the Internet 234. The configuration loader generally operates as follows. First, the CPU 212 is connected to the user 244 through the peripheral device 214. The user 244 causes the CPU 212 to start executing the configuration operation device 250 to perform a configuration load program, and the configuration operation device 250 causes the peripheral device 214 to pass through the peripheral device 214 to the Internet. The network 234 and the connection between the Internet 234 and the remote host 238, and then the remote host 238 begins to download data from the disk 242 through the Internet 234 to the non-volatile memory 200, and the data begins to be transferred. The expiration cycle record 226 in the ICP/CL watchdog 222 sets an estimate and the timer 224 starts counting 19 1259396. If the configuration load procedure is successful, the fault tolerance feature of the present invention is inactive, and the other In the aspect, if an excessive delay occurs in the configuration loader, the timer 224 will eventually be the same as the expiration cycle record 226, causing a reset signal to reach the CPU 212 via the reset line 232, and causing the CPU 212 to initiate a series of starts. . If the system is restarted in the configuration loader' then the ICP/CL state 218 is set to a dirty value, thus causing the circle X 210 to directly jump the start vector 216 into the CPU 212, causing the micro-start code 207 to cause the CPU 212 instead of the initiator 202. start up. If the ICP/CL state 218 is set to a clean value, it indicates that the configuration loader has all been completed and Μυχ 210 causes the CPU 212 to boot from the boot program 202. The micro-boot code 207 causes the CPU 212 to restart the configuration loader, and determines the connection of the remote host via the first read value from the remote host address record 220 to restart the configuration loader, and then configures the loader. Restart. In another embodiment, the 'micro-boot code 2〇7 includes a configuration load stylized design, accessing the configuration data of the configuration data using the domain location or via the connection-predetermined host and system single-chip integration. Circuit combination. The icp program usually operates as follows. First, the Gpu 212 is connected through the peripheral device (10). Some atypical system single-chip integrated circuit systems are connected to the user by the input/output port, and the user (10) initiates (4) 212 to perform the 1CP operation. The device 2〇6 performs an ICP program, and the icp device 2G6 initiates a connection between the peripheral device 214 to the Internet 234 and through the Internet 234 to the remote host 238, and then the remote editor 20 1259396 starts from the disk 242. The data is downloaded over the Internet 234 to the non-volatile memory 200, while the data begins to be transferred, the expiration cycle record 226 in the Icp/CL watchdog 222 sets an estimate and the timer 224 begins timing. If the ICP procedure is successful, the fault tolerance feature of the present invention is inactive. On the other hand, if excessive delay occurs in the ICP procedure, the timing 224 will eventually be the same as the expiration cycle record 226, causing a reset signal via the reset signal. The reset line 232 reaches the CPU 212 and causes the CPU 212 to begin a series of starts. If the system is restarted in the ICP program, the ICP/CL state 218 is set to a dirty value, thus causing the hop 21 to jump directly into the CPU 212, causing the micro-start code 207 to cause the CPU 212 to start in place of the initiator 202. If the ICP/CL state 218 is set to a clean value, it indicates that the ICP program has all been completed, and the MUX 210 initiates the CPU 212 to boot from the boot program 202. The micro-boot code 207 causes the CPU 212 to restart the ICP program, by determining the connection of the remote host from the first read value of the remote host address record 220 to restart the ICP program, and then the icp program is restarted. In some embodiments, the ICP program can overwrite or modify the configuration operating device 250. In these embodiments, the ICP program first backs up the configuration operating device 250 to non-volatile memory for placement on the system single wafer. Two backups, one of which is modified, will be deleted if the modification is completely successful, but a secure backup of the operating device can be used to respond to system operations if the modification is not completely successful. The above description of the preferred embodiments of the present invention is intended to clarify the purpose of the present invention, which is not intended to limit the scope of the present invention, and is modified or changed based on the teachings of the present invention or from the embodiments of the present invention. The present invention is intended to illustrate the principles of the present invention and to enable those skilled in the art to select and describe the actual invention in various embodiments. The technical idea of the present invention is intended to be applied to the following application. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; It will become more apparent that FIG. 1 is a simplified block diagram of a system single-chip integrated circuit in accordance with the present invention; FIG. 2 is a simplified block of another embodiment of a system single-wafer integrated circuit in accordance with the present invention. Figure 3 is a simplified block diagram of a system single-chip integrated circuit in accordance with the present invention; s % Figure 4 is a more detailed functional diagram of the system single-chip integrated circuit in accordance with the present invention; Figure 5 is a functional schematic diagram of one embodiment of a system pre-wafer integrated circuit including a profile memory on a wafer in accordance with the present invention; Figure 6 is a system single-wafer body including a profile memory on a wafer in accordance with the present invention; A functional schematic diagram of another embodiment of the circuit; FIG. 7 is a system single chip including a configuration data memory on the wafer and supporting the encryption/decryption and/or down-scaling/de-sizing on the wafer. Functional schematic; and Figure 8 of the circuit is a system single chip provided in accordance with the present invention
署的理論圖，1中配詈眘袓山、土 、包路衣i兄口P 體…= 通端源提供且系統單晶片積 體电路允許配置載人功能的配置載人 早曰曰片孝貝 溝通管道。 建立與遠端源的 【主要元件符號說明】 10糸統單晶片積體電路 11 處理器核心 12 輸入/輸出琿 13 受保護記憶體 14可程式化記憶體 15 可配置邏輯陣列 15 A可配置邏輯陣列的程式段 16 配置記憶體 100處理器核心 101啟動向量 102計時器 10 3看門狗計時器 104輸入/輸出埠 105中斷線 106其他訊號輸入與輸出 107記憶陣列 23 1259396 108記憶陣列 109記憶陣列 110可配置邏輯陣列 111資料記錄 112配置記錄 113計時記錄 114多工器 115狀態記錄 150可配置邏輯陣列 151配置資料記憶陣列 152控制電路 160可配置邏輯陣列 161配置資料記憶陣列 162控制電路 170資料路徑 171資料路徑 172記憶陣列 200非揮發性記憶體 202啟動程式 204公用程式 206内電路程式化操作裝置 208隨機存取記憶體 210多工器 212處理器核心（CPU) 24 1259396 214周邊裝置 216跳躍啟動向量 218内電路程式化/配置載入狀態 220遠端主機地址記錄 222内電路程式化/配置載入看門狗 224計時器 226到期週期記錄 228匹配邏輯 230讀/寫路徑 232重置線 234網際網路 236遠端主機 238遠端主機 240遠端主機 242磁碟片 244使用者 250配置操作裝置 251可配置邏輯陣列 25The theoretical map of the Department, 1 in the 詈 袓 袓 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Bay communication pipeline. Established and remote source [main component symbol description] 10 system single chip integrated circuit 11 processor core 12 input / output 珲 13 protected memory 14 programmable memory 15 configurable logic array 15 A configurable logic Array of blocks 16 Configurable memory 100 Processor core 101 Start vector 102 Timer 10 3 Watchdog timer 104 Input/output 埠 105 Interrupt line 106 Other signal input and output 107 Memory array 23 1259396 108 Memory array 109 Memory Array 110 configurable logic array 111 data record 112 configuration record 113 timing record 114 multiplexer 115 status record 150 configurable logic array 151 configuration data memory array 152 control circuit 160 configurable logic array 161 configuration data memory array 162 control circuit 170 data Path 171 data path 172 memory array 200 non-volatile memory 202 boot program 204 utility 206 circuit programming operation device 208 random access memory 210 multiplexer 212 processor core (CPU) 24 1259396 214 peripheral device 216 jump Startup vector 218 internal circuit programming / configuration loading state 220 remote host address Recording 222 Circuit Stylization/Configuration Loading Watchdog 224 Timer 226 Expiration Period Record 228 Matching Logic 230 Read/Write Path 232 Reset Line 234 Internet 236 Remote Host 238 Remote Host 240 Remote Host 242 Disk 244 user 250 configuration operating device 251 configurable logic array 25