1257571 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種系統單晶片積體電路與其他包 括嵌入式可配置邏輯陣列作為特定用途或客戶晶片邏輯 的處理器裝置。 【先前技術】 包括例如已知的可程式化邏輯裝置（PLD)及場可程式 化閘極陣列（FPGA)的可配置邏輯陣列，以及更廣為熟知 的可程式化邏輯陣列（PLA)，具有愈來愈高密度的設計’ 配置此類高密度裝置的技術通常需要特定的邏輯在晶片 上或在與可配置邏輯陣列經系統匯流排溝通的主機處理 器上執行。可配置邏輯陣列核心的配置資料管理需要複雜 的邏輯，參見頒給Lawman的美國專利第6, 049, 222號’ 配置裝置用的特定技術限制該技術可應用的環境。 可配置邏輯陣列可經由使用者載入一配置資料以設 定在裝置上的可程式化元件的指定配置，並將配置資料交 付於其中的可程式化配置點以完成使用者指定的功能，例 如場可程式化閘極陣列包括一邏輯元件的陣列及大量4 使用配置資料加以程式化的連線。在晶片中配置資料儲存 於以δ己憶元件所構成的配置點中，通常以靜態隨機存取δ己 憶體（SRAM)之類的記憶胞實現，其他可配置邏輯陣列包括 非揮發性配置記憶體，使用唯讀記憶體（ROM)、快閃記憶 體（flash)或可抹除可程式化唯讀記憶體（EPROM)之類的 1257571 記憶胞實現。 可電荷程式化、非揮發性記憶元件已經被用來作為可 程式化的開關及可配置邏輯陣列中的其他配置點。參見美 國專利第 5,247,478 號、第 5,764,096 號及第6，122,2〇9 號。 有關可配置邏輯陣列的一個問題係將配置資料載入 文装在印刷電路板上的晶片或以其他方式結合到功能争 統中。參見美國專利第4, 879, 688號「系統中可程式化的 邏輯裝置」、第5, 995, 744號「可程式化電路的網路裝置」、 第6, 028, 445號「場可程式化閘極陣列結構的解碼器構造 與方法」、第6,049,222號「使用嵌入式記憶體配置場可 程式化閘極陣列」以及第6, 102, 963號「具有在系統中程 式化及確認功能之電氣式可抹除及可程式化的非揮夢性 整合儲存裝置以支援可程式化邏輯裝置在系統中的在配 置」。 系統單晶片（system-on-a-chip ; SOC)裝置増加了系 統的複雜度，因此S0C系統不易設計且改變費用昂貴。藉 由在處理器核心增加一可配置邏輯陣列與該處理器核: 連接可使得改變及設計較為容易，因此，可配置邏輯陣列 中的邏輯可利用工業上的工具結合可程式化邏輯的使用 而進行配置，同時處理器核心可使用習知的軟體程式技術 而私式化，但是可配董邏輯陣列換組的配置資料管理的門 題依舊存在。系統單晶片技術在複雜系統上遇到的典型問 題即係不易設計且改變費用昂貴，將可配置邏輯陣列與處 1257571 理器核心結合在一起，邏輯的組合可隨著處理器的改良而 改變，亦即經由可程式化邏輯陣列的配置工具可達成邏輯 的配置。 使系統單晶片在設計上更具彈性以及改良可配置邏 輯中管理配置的技術有所需求。 本發明提供使用嵌入式可配置邏輯的系統單晶片的 設計更大的彈性以及提供可配置邏輯的配置載入。 【發明内容】 本發明提供一種系統單晶片積體電路，包括一可配置 邏輯陣列、一處理器核心以及一記憶體用以儲存系統單晶 片的任務功能指令與用於經由積體電路上的輸入埠從外 部源載入配置資料到積體電路中的配置載入功能指令，處 理器從記憶體中呼叫並執行指令。 在一些實施例中，記憶體亦儲存了配置功能指令以載 入配置資料到可配置邏輯陣列中的電氣式可程式化配置 點，在另一些實施例中，使用與可配置邏輯陣列結合的專 用邏輯執行配置功能，一介面介於處理器與晶片中可配置 邏輯陣列或配置邏輯之間以支援配置功能。 記憶體包括第一記憶陣列以儲存配置載入功能指 令，在一實施例中該記憶體為非揮發性記憶體，如唯讀記 憶體、浮動閘極記憶體及氮化金屬氧化半導體（nitride MOS)記憶體等，同樣地，配置功能指令亦可儲存於第一記 憶陣列中，較佳者，配置載入功能指令儲存在可程式化記 1257571 憶體中，使得在電路中可以改變配置載入功能以適應不同 配置資料的遠端源以及與遠端源建立溝通管道的協定。 經由在晶片上提供配置功能及/或配置載入功能指令 並由處理器核心執行，本發明的系統單晶片積體電路可以 輕易地應用於廣泛的各種希冀可配置邏輯陣列的配置載 入的環境中。 任務功能包括達成系統使用任務的特定使用者及/或 特定用途指令。在使用非揮發性記憶體的實施例中，如高 速靜態隨機存取記憶體（high-speed SRAM)或動態隨機存 取記憶體（DRAM)，該記憶體包括一記憶陣列以儲存任務功 能指令。在其他的實施例中，儲存任務功能指令的記憶體 包括非揮發性記憶體，如唯讀記憶體、浮動閘極記憶體、 氮化金屬氧化半導體記憶體或類似的記憶體。在一些實施 例中，儲存任務功能指令的記憶體可能包括揮發性與非揮 發性記憶體的組合。 在另外的實施例中，系統中配置載入及任務功能的配 置載入的指令均儲存於晶片中的非揮發性記憶體，如此， 可配置邏輯陣列的配置資料與任務功能指令二者的載入 可以被寫入位於電路板或其他系統中的系統單晶片裡。 在一些實施例中，配置載入功能及/或配置功能包括 使用看門狗計時器的程序，且積體電路中包括與處理器結 合在一起的看門狗計時器電路。 可配置邏輯陣列具有一由儲存於可配置邏輯陣列内 的電氣式可程式化配置點中的配置資料所定義的可程式 1257571 化配置，例如電氣式可程式化配置點包括浮動閘極記憶胞 或其他可電荷程式化、非揮發性記憶胞，在可配置邏輯陣 列的配置程序中配置資料會轉移到配置點中。 在一些實施例中，可程式化配置記憶體被包含在積體 電路上用以儲存配置資料，根據這些實施例，配置功能包 括從配置記憶體中轉移配置資料到可配置邏輯陣列中的 可程式化配置點，同樣地，配置載入功能包括經由在系統 早晶片積體電路中的輸入璋從資料的遠端源載入配置資 料到配置記憶體中。在一些實施例中，可程式化配置記憶 體使用非揮發性、可程式化記憶胞，例如浮動閘極記憶體 或其他可電荷程式化非揮發性記憶體。在一些實施例中， 使用高速靜態隨機存取記憶體作為可程式化配置記憶體 以支援可配置邏輯陣列的快速配置改變。同樣地，一些實 施例包括非揮發性記憶體與高速揮發性記憶體二者，以支 援配置資料在晶片上的儲存與處理。 在其他的實施例中，處理器核心回應一初始化事件， 例如重置以執行配置載入及配置功能。根據本發明的系統 單晶片積體電路的一個實施例包括一看門狗計時器，依據 該看門狗計時器的時間間隔引發一初始化事件，該配置載 入功能包括設定看門狗計時器的時間間隔使其適用於從 遠端源接收配置資料的程序，以及若到達時間間隔時則執 行包括重試配置載入功能的初始化功能。 在另外的實施例中，記憶體儲存配置載入功能、任務 功能及配置功能的指令。在諸如此類的實施例中，第一配 置載入功能儲存於免於受配置載入功能而覆寫或修改的 1257571 受保護記憶體中，第一配置載入功能提供一通道以供配置 資料從一預設位置嵌入受保護的記憶體中。第二配置載入 功此儲存於未受保護的記憶體中，用來和配置資料遠端源 溝通，該配置資料可以不在預設位置。假如初始化事件發 生於配置载入操作到改變第二配置載入功能的執行期 間’則第一配置載入功能可以用來回復配置載入操作。 【實施方式】 本發明實施例的詳細說明參考圖1-8。一基本的系統 早曰日片積體電路1 〇如圖1所不’包括微控制器核心模組 11，例如已知標準的8051或先進精簡指令集運算器（arm) 模組，或者，微控制核心模組11亦可由其他資料處理器 核心例如數位訊號處理器核心、高效率精簡指令集運算 (high-performance RISC)處理器核心或其他微處理器或 數位訊號處理器模組所取代或補充，受保護記愫體13及 可程式化記憶體14包括在積體電路1〇中，典型的受保護 記憶體13儲存啟動功能及其類似功能的指令 或修改，典型的可程式化記憶體14儲存積體電路1〇的任 務功能指令’輸出/輸入結構12亦包括在積體電路1〇中， 以支援輸人與輸出積體電路1G的串聯資料通道及並聯資 料通道其中一個或二者。 ' 在積體電路10中包括可配置邏輯陣列15以支援處理 器核心1卜可配置邏輯陣列15使用場可程式化閘極陣列 或其他形式的可配置邏輯模組實現，可配置邏輯陣列15 1257571 包括許多配置點用以儲存可配置邏輯陣列15的配置資料 並定義其功能，典型地，可配置邏輯陣列15包含在_系 統單晶片積體電路中以支援任務功能及執行特定的邏 輯。根據本發明，受保護記憶體13與可程式化記憶體14 其中之一所儲存的指令經由處理器核心丨丨執行，該指令 包括邏輯以完成轉移配置資料到可配置邏輯陣列15中的 配置點的配置功能，該指令亦包含邏輯以完成配置載入以 確定經由輸入/輸出蟑12從遠端源載入配置資料到積體 路中的溝通管道。 、 圖2係系統單晶片積體電路1 〇替代實施例之簡化方 塊圖，根據圖2的實施例，在晶片上的處理器經由可配置 邏輯陣列15的程式段15A實現，程式段⑽的配置資料 儲存在程式段15A中非揮發性配置點或積體電路中受保護 記憶體13内，在本實施例中，根據積體電路的初始化， ，置資料從受保護記憶體13轉移到程式段15A中，處理 器經由可配置邏輯陣列的程式段15A實現，其執行指令類 似於習知微處理器核心u或其他處理器核心。 、圖3係根據本發明的系統單晶片積體電路1〇另一替 代實施例之簡化方塊圖，在圖3的實施例中，—配置記憶 體16被包括在晶片中，配置記憶體儲存可配置邏輯陣列 15的配置資料且該配置f料根據初始化或在微控制器核 11的控制下或其他在晶片上的配置邏輯轉移到可配置 邏^陣列中’配置記憶體16可使用唯讀記憶體實現，以 確疋可配置邏輯陣列在製造過程中具有最小集合的配置 11 1257571 資料。在另一系統中，配置記憶體16是可。 控制指令經由微控制器核心11執行下可 °匕的且在 不用配置藝人工六 能從遠端源載入。在另一系統中，配置 ^ 77 ^上士 &體16可结人 唯碩記憶體與可程式化記憶體。 σ 圖4係根據本發明的系統單晶片積體電者> 細功能圖，根據本發明的較佳實施例，所有在例之詳 路中實施的構成要素如圖4所示，該晶片勺早年貝體電 核心100利用一特定目的的電路或如圖=微控制器 邏輯陣列中的—程式段所實現，微控制斤述的可配置 動向量101及計時器電路102以支援看門狗1 士 L祜啟 微控制器核心100支援輸入/輸出埠1〇4、、十，态1〇3， 105及其他訊號的輸入與輸出1〇6，在積體、中斷線 體用以儲存指令並經由微控制器核心執料:路上的記憶 尬 丁’該記憶體句； 第一記憶陣列107用以儲存配置操作裝置 " i的指令，盆包括 配置载入功能及配置功能以支援在積體 八 ^ A 瓶尾路上的可配置 邏輯陣列110。在一些實施例中，配置操作裝置包括一寺 始化功能的執行以回應一初始化事件，像是經由t中斷= 號或一看門狗計時器重置所引發的重置。該記憶體尚包括 第二記憶陣列108用以儲存系統單晶片積體電路的任務功 能指令，以及第三記憶陣列109用以儲存受保護的功能， 包括啟動功能、内電路程式化功能及可配置邏輯陣列配置 載入備份功能。第三記憶陣列109被保護免於經由一内電 路程式化（ICP )功能而覆寫或修改，並在例如重置事件及 内電路程式化程序或配置載入程序失敗時的初始化功能 12 1257571 期間回復系統。 /玄心體可使用變化多樣的記憶胞技術，包括遮罩式 食靖。己1^體（mask職）、快閃記憶體、靜態隨機存取記憶 體以及類似的適合特定實施裝置來實現，典型的受保護記 憶陣列109經由非揮發性記憶體例如遮罩式唯讀記憶體或 決閃.己體來實現，當經由快閃記憶體或其他電氣式可程 式化記憶體所實現時，邏輯結構可保護記憶陣列⑽免於 因配置載人的操作或意外而被覆寫或修改。 在積體電路中可配置邏輯陣列1 1 0如圖4的實施例， 經由-以快閃記龍為基礎的可配置邏輯陣列來實現，在 以快閃記紐為基礎的可g[置邏輯陣列巾，配置點係為非 揮發性’使得配置資料在重置或斷電時仍會保留下來。 在積體電路中有—介面介於微控制器核心丨⑼與可配 置邏輯陣列11Q之間，該介面包括其他在此技術中已知的 結構、資料記錄m、配置記錄112以及計時記錄113， 且該資料、配置資料以及計時訊號經由該介面在模組間進 =父換，狀態記錄115經由協議的配置功能確認使用配置 資料的可配置邏輯陣列的配置成功。 少微控制器核心100可經由如多工器114所示的指令路 徑從包括記憶陣列107、1〇8、1〇9的記憶體中檢索指令， 其他包括如靜態隨機存取記憶體或記錄陣列的記憶體結 構包含在積體電路中，以支援經由微控制器核心或可 配置邏輯陣列110的執行功能。 在圖4的實施例中，配置操作裝置的配置載入功能儲 13 ^於第—記憶陣列107中，以確定介於 路與配置資料的遠端源之間的溝㈣糸、，先早曰曰片積體電 輪，出埠丨〇4接收配置 置中的配置功能通過配置：置 料陣列川中以快閃記憶體為基礎的配置=在了配置邏 始4Γ=的過程中發生重置的事件或其他勒 〜件，則配置載入功能將會重新執行。 初 、二程=)9?亦可儲存於記憶體中，例 改配置::：：r中或其他位置，用於覆寫J 定的遠端源接收配置=置使用者選 入備份功能儲存二：二 錯誤時^ ㈣7巾軸置齡裝置發生 回'系統可利用儲存於受保護記憶陣列109中的功能 ，、狀，根據美國專利第6 4〇1221號、第6 493, 788 儿以及第5, 901，330號中所揭露的内電路程式化功能是適 合使用的。 圖5係根據本發明的系統單晶片積體電路的替代結 構’相似的構成要素給予圖4中使用的相同編號。根據如 圖5所示的替代結構，可配置邏輯陣列15〇不需使用以快 閃記憶體或其他非揮發性配置點為基礎的可配置邏輯陣 列實現，例如，可配置邏輯陣列15〇可使用具有以靜態隨 機存取記憶體（SRAM)為基礎的配置點的標準型場可程式 化閘極陣列（FPGA)來實現。 1257571 可配置邏輯陣列150的配置資料儲存在非揮發性配置 資料記憶陣列151中，並由微控制器核心100取得積體電 路的部份記憶體而實現，在本實施例中使用控制電路152 作為配置資料記憶體151與微控制器核心100之間的介 面，在陣列107中配置操作裝置的配置載入功能用以確定 遠端源與配置資料記憶體151間的通道，在配置演算過程 中陣列107中配置操作裝置的配置功能從配置資料記憶體 151經過微控制器核心100轉移配置資料到可配置邏輯陣 列 150 〇 圖6係根據本發明的系統單晶片積體電路的替代結 構，相似的構成要素給予圖5中使用的相同編號。根據如 圖6所示的替代結構，可配置邏輯陣列160可使用可程式 化邏輯裝置（PLD)模組來實現，可配置邏輯陣列160的配 置資料儲存在非揮發性配置資料記憶陣列161中，並由微 控制器核心100取得積體電路的部份記憶體而實現，控制 電路162作為配置資料記憶體161與可配置邏輯陣列160 之間的介面，使得配置操作裝置107的配置功能直接經由 配置功能專用的資料路徑170、171從配置資料記憶體161 轉移配置資料到可配置邏輯陣列160中，資料路徑170、 171可使用寬頻並聯資料路徑或其他適用於配置功能之高 速、特別配置的資料路徑來實現，在本實施例中，配置操 作裝置107中的配置功能可以簡化或忽略，且其更多的功 能由控制電路162來達成。 在陣列107中配置操作裝置的配置載入功能用以確定 15 1257571 遠端源與配置資料記憶體161間的通道。 圖7係根據本發明的系統單晶片積體電路的替代結 構，相似的構成要素給予圖6中使用的相同編號。根據如 固7所示的替代結構，記憶體增加一記憶陣列172用以儲 存加岔/解密功能及壓縮/解壓縮功能指令其中至少之 一，根據如圖7所示的實施例，配置載入功能確定一遠端 源與配置資料記憶體161間的通道，配置資料以加密形 式、壓縮形式或加密及壓縮形式從遠端源接收，當載入配 置為料到配置資料記憶體161時，配置載入功能從陣列 中進行解密及/或解壓縮功能，或者，當轉移配置資料到 可配置邏輯陣列中的配置點時，配置載入功能從陣列 中進行解密及/或解壓縮功能，增加的記憶陣列172儲存 加岔/解密功能及壓縮/解壓縮功能其中至少之一，以用於 不同的系統單晶片積體電路的實施例，包括如圖4及圖5 所示之實施例。 圖8係一些與本發明觀點相同的内電路程式化及配置 載入的容錯系統之主要功能構成要素的方塊圖，一系統單 晶片積體電路包括一處理器核心（CPU212)及一可配置邏 輯陣列251。内電路程式化程序及配置載入系統包括非揮 發記憶體200、隨機存取記憶體（RAM)208、CPU212及周邊 裝置214。該内電路程式化程序及配置載入系統亦包括容 錯系統的構成要素，包括跳躍啟動向量216、多工器 (MUX)210、内電路程式化/配置載入（ICp/CL)狀態記錄 218、遠端主機地址記錄220及ICP/CL看門狗222。 1257571 更明確地’CPU212係任何形式的處理系統，包括微护 制器、微處理器或數位訊號處理器。cpU212與Ram2〇8 ^ 合在一起且隨機存取記憶體所包含的編碼及資料妙： CPU212執行，此外，CPU212亦經過由MUX21〇所表示=次 料路徑與非揮發性記憶體200結合在一起。 、、貝 非揮發性記憶體200係當系統斷電時仍可保存資料的 任何形式的記憶體’包括快閃記憶體、可抹除可程式化唯 讀記憶體（EPROM)、電氣式可抹除可程式化唯讀記憶體 (EEPR0M)及唯讀記憶體，非揮發性記憶體2〇〇 式2〇 2、梅讀、㈣路織lep 配置操作裝置250以及微啟動碼207。啟動程式202包括 在系統初始化的程序中執行程式的收集以將系統的硬體 及軟體資源初始化，啟動程式202儲存於可程式化記憶體 中並可在配置載入的過程中被修正。非揮發性記憶體2〇〇 亦包括公用程式204 ,該公用程式204在系統的演算過程 中包括許多程式經由CPU212執行以完成任務功能，公用 程式204亦可被包含於經由内電路程式化載入程序中可被 程式化的記憶體中。非揮發性記憶體2〇〇亦包括配置操作 裝置250以進行系統的配置載入功能且其可被包含於經由 配置載入程序中可被程式化的記憶體中，非揮發性記憶體 200中所包括的配置操作裝置25〇可被包含於經由内電路 程式化程序中可被程式化的記憶體中。配置操作裝置25〇 所執行的功能如之前圖4—7所述。 非揮發性記憶體2〇〇同時包括位於受保護記憶體内的 17 !25757l 微啟動碼207，微啟動碼2〇7在相 ::與配置操作裝置程式中不會被修改，微 :代糸統初始化指令以完成許多如啟動程式2〇2的相同功 d而田有個可能由啟動程式2⑽引起的錯誤發生 j内電路程式化程序巾，㈣電路程式化程序或配置 喿作裝置功能250失敗及不穩定時，微啟動碼挪只是一 個跳脫的行為’因此，微啟動碼m必須儲存在相同内電 路正常啟動程式的程式化過程巾*會被修改的記憶體 中。在本發明的一個實施例中，當啟動程式2〇2、公用程 式204、配置操作裝置25〇及lcp操作裝置2〇6儲存在可 程式化快閃記憶體時，微啟動碼2〇7儲存在遮罩式唯讀記 憶體中。 11 在ICP程序中，CPU212同時結合硬體構成要素以幫助 容錯，CPU212結合MUX210作為非揮發性記憶體2〇〇及跳 躍啟動向量216的輸入且控制從ICP/CL狀態記錄218的 輸入，MUX210視ICP/CL狀態218的狀況選擇性切換cpu212 於跳躍啟動向；!： 216及非揮發性記憶體200之間，若 ICP/CL狀態218是鱗的，表示之前的ICP演算或演算修正 配置載入運算沒有完成，則CPU212在系統初始化的程序 中輸入一個跳躍指令給啟動向量216以指向微啟動碼 207，另一方面，若iCp/CL狀態218是乾淨的，表示沒有 配置載入運舁在進行，則CPU212在糸統初始化的程序中 輸入非揮發性記憶體2〇〇的初始載入，CPU212同時結合遠 端主機地址記錄220並包含備份遠端主機地址，避免在内 • 18 1257571 電化程序中發生系統重置，圆2亦透過讀/寫路 徑及重置線232與ICP/CL看門狗222結合，ICP/CL 看門狗222包括到期週期（timeout period)記錄226及計 時為224，匹配邏輯228，計時器224及到期週期226二 ^可透過讀/寫路徑23()經由⑽12而被初始化，當計時 為224的值與到期週期226相同時，匹配邏輯2 個重置訊號經由重置線232傳送到cpU212。在—實^例 中^述提_硬體構成要素提供的容錯包括保護可程式 化記憶元件免受内電路程式化程序的影響。 此外’CPU212結合周邊裝置214，包括連接系統使用 者的輸入及輸出裝置，如圖中周邊裝置214左邊的雙箭號 所不，周邊裝置214亦包括一介面通過周邊裝置214與網 際網路234、或其他溝通管道或網路結合。網際網路234 本身結合了遠端主機236、238及240，遠端主機238結合 了包含新版本的啟動及公用程式的磁碟片242，包括例如 新的内電路程式化功能或新的配置載入功能並經由網際 網路234下載到系統中。 配置載入程序通常運作如下，首先CPU212透過周邊 裝置214與使用者244連接，使用者244引發cpu212開 始執行配置操作裝置2 0 6進行配置載入程序，配置操作裝 置250引發通過周邊裝置214到網際網路234及通過網際 網路234到遠端主機238之間的連接，接著遠端主機238 開始從磁碟片242通過網際網路234下載資料到非揮發性 記憶體200中，同時資料開始轉移、在ICP/CL看門狗222 1257571 中的到期週期226設定一估計值及計時器224開始計時。 若配置載入程序進行順利，則本發明的容錯特徵為非 活性化的，另一方面，若在配置载入程序中發生過度延 遲，則計時器224最終將與到期週期226相同而引發一重 置訊號經由重置線232到達CPU212，並引發cpU2j開始 進仃一連串的啟動。若系統在配置載入程序中重新啟動， 則ICP/CL狀態記錄218設定為髒的值，因而引發21〇 直接跳躍啟動向量216到CPU212中，使得微啟動碼 啟動程式202引發CPU212啟動。若Icp/CL狀態218 »又疋為乾淨的值，表示配置載入程序已全部完成且Μ⑽2仙 從啟動程式202引發CPU212啟動。 微啟動碼207引發CPU212重新開始配置載入程序， 係、’么由從运％主機地址§己錄220的第一個讀取值決定遠端 主機的連接以重新開始配置載入程序，然後配置載入程序 即重新開始。在另一實施例中’微啟動碼2G7包括一配置 載入程式化的設計，用以從預設位置存取配置資料的設 定，例如晶片中的非揮發性記憶體或經由連接一預定的主 機與系統單晶片積體電路結合。 ICP程序通常運作如下，首先CPU212透過周邊裝置 214與使用者244連接，-些非典型系統單晶片積體電路 係經由輸入/輪出埠而與使用者連接，使用者244引發 CPU212開始執行lcp裝置進行⑽程序，⑽裝置2〇6 引發通過周邊裝置214到網際網路234及通過網際網路 234到遠^主機238之間的連接，接著遠端主機238開始 1257571 攸磁碟片242通過網際網路234下載資料到非揮發性記憶 體200中，同時資料開始轉移、在icp/a看門狗222中 的到期週期226設定一估計值及計時器224開始計時。 若iCP程序進行順利，則本發明的容錯特徵為非活性 化的另一方面，若在ICP程序中發生過度延遲，則計時 裔224最終將與到期週期226相同而引發一重置訊號經由 重置線232到達CPU212，並引發CPU212開始進行一連串 的啟動。若系統在icp程序中重新啟動，則ICP/CL狀態 記錄218設定為髒的值，因而引發Μυχ 21〇直接跳躍啟動 向1 216到CPU212中，使得微啟動碼2〇7代替啟動程式 202引發CPU212啟動。若ICP/CL狀態218設定為乾淨的 值，表示icp程序已全部完成，且MUX21{)從啟動程式202 引發CPU212啟動。 微啟動碼207引發CPU212重新開始icp程序，係經 由從返端主機地址記錄220的第一個讀取值決定遠端主機 的連接以重新開始ICP程序，然後ICP程序即重新開始。❿ 在一些實施例中’ ICP程序可以覆寫或修改配置操作 裝置，在這些實施例中，ICP程序首先備份配置操作裝置 250到非揮發性記憶體中以確定在系統單晶片上配置載入 的二份備份，其中一份備份是修改過的，若修改完全成功 則另一份備份會被刪除，不過，若修改沒有完全成功則配 置操作裝置的安全備份可用來回復系統操作。 以上對於本發明之較佳實施例所作的敘述係為 闡明之目的，而無意限定本發明精確地為所揭露的形式， 21 1257571 基於以上的教導或從本發明的實施例學習而作修改或變 化是可能的，實施例係為解說本發明的原理以及讓熟習該 項技術者以各種實施例利用本發明在實際應用上而選擇 及敘述，本發明的技術思想企圖由以下的申請專利範圍及 其均等來決定。 【圖式簡單說明】1257571 IX. Description of the Invention: Field of the Invention The present invention relates to a system single-chip integrated circuit and other processor devices including an embedded configurable logic array as a special purpose or client wafer logic. [Prior Art] Configurable logic arrays including, for example, known programmable logic devices (PLDs) and field programmable gate arrays (FPGAs), and more widely known programmable logic arrays (PLAs) having Increasingly high density designs' Techniques for configuring such high density devices typically require specific logic to be executed on the wafer or on a host processor that communicates with the configurable logic array via the system bus. The configuration data management of the configurable logic array core requires complex logic, see U.S. Patent No. 6,049,222 to Lawman's specification for the specific technology used to limit the application of the technology. The configurable logic array can load a configuration profile by the user to set a specified configuration of the programmable elements on the device and deliver the configuration data to the programmable configuration points therein to perform user-specified functions, such as The programmable gate array includes an array of logic elements and a large number of connections that are stylized using configuration data. The configuration data in the wafer is stored in a configuration point formed by the δ-resonance element, usually implemented by a memory cell such as static random access δ memory (SRAM), and other configurable logic arrays include non-volatile configuration memory. Body, using a read-only memory (ROM), flash memory (flash) or erasable programmable read-only memory (EPROM) 1257571 memory cell implementation. Charge-stabilized, non-volatile memory components have been used as programmable switches and other configuration points in configurable logic arrays. See U.S. Patent Nos. 5,247,478, 5,764,096 and 6,122,2,9. One problem with configurable logic arrays is loading the configuration data into a wafer mounted on a printed circuit board or otherwise incorporated into a functional continuation. See U.S. Patent No. 4,879,688, "Programmable Logic Devices in Systems," No. 5, 995, 744, "Network Devices for Programmable Circuits," No. 6, 028, 445, "Field Programs" "Decoder structure and method for gate array structure", No. 6,049,222 "Using embedded memory to configure field programmable gate array" and No. 6, 102, 963 "with stylized and confirmed functions in the system" An electrically erasable and programmable non-swinging integrated storage device to support the configuration of programmable logic devices in the system. System-on-a-chip (SOC) devices add to the complexity of the system, so the SOC system is not easy to design and expensive to change. By adding a configurable logic array to the processor core at the processor core: the connections make changes and designs easier, so the logic in the configurable logic array can take advantage of industrial tools combined with the use of programmable logic. Configuration, while the processor core can be privateized using conventional software programming techniques, but the configuration of the configuration data management that can be configured with the Dong logic array still exists. The typical problems encountered by system-on-a-chip technology on complex systems are that they are not easy to design and costly to change. The configurable logic array is combined with the 1257571 processor core, and the combination of logic can change as the processor improves. That is, a logical configuration can be achieved via a configuration tool of the programmable logic array. Techniques are needed to make system single-chips more flexible in design and to improve management configurations in configurable logic. The present invention provides greater flexibility in the design of system single-chips using embedded configurable logic and configuration loading that provides configurable logic. SUMMARY OF THE INVENTION The present invention provides a system single-chip integrated circuit including a configurable logic array, a processor core, and a memory for storing system function instructions of the system single chip and for input via the integrated circuit载入 Loading configuration data from an external source to the configuration load function instruction in the integrated circuit, the processor calls and executes the instruction from the memory. In some embodiments, the memory also stores configuration function instructions to load configuration data into an electrically programmable configuration point in the configurable logic array, and in other embodiments, a dedicated combination with a configurable logic array. The logic performs configuration functions, with an interface between the processor and the configurable logic array or configuration logic in the chip to support configuration functions. The memory includes a first memory array to store configuration load function instructions. In one embodiment, the memory is a non-volatile memory such as a read-only memory, a floating gate memory, and a metal nitride oxide semiconductor (nitride MOS). Memory, etc. Similarly, the configuration function instructions can also be stored in the first memory array. Preferably, the configuration load function instructions are stored in the programmable record 1257571 memory, so that the configuration loading can be changed in the circuit. The function is to adapt to the remote source of different configuration data and the agreement to establish communication channels with the remote source. The system single-chip integrated circuit of the present invention can be easily applied to a wide range of configuration loading environments of various configurable logic arrays by providing configuration functions and/or configuration load function instructions on the wafer and being executed by the processor core. in. Task functions include specific user and/or specific use instructions that achieve the system's use of tasks. In embodiments that use non-volatile memory, such as high-speed SRAM or DRAM, the memory includes a memory array to store task function instructions. In other embodiments, the memory storing the task function instructions includes non-volatile memory such as read only memory, floating gate memory, metal nitride oxide semiconductor memory or the like. In some embodiments, the memory storing the task function instructions may include a combination of volatile and non-volatile memory. In another embodiment, the configuration load instructions of the load and task functions in the system are stored in non-volatile memory in the chip, and thus, the configuration data of the configurable logic array and the task function instructions are loaded. Incoming can be written to a single system chip on a circuit board or other system. In some embodiments, the configuration load function and/or configuration function includes a program that uses a watchdog timer, and the integrated circuit includes a watchdog timer circuit that is combined with the processor. The configurable logic array has a programmable 1257571 configuration defined by configuration data stored in an electrically programmable configuration point within the configurable logic array, such as an electrically programmable configuration point including a floating gate memory cell or Other chargeable, non-volatile memory cells are transferred to the configuration point in the configuration program of the configurable logic array. In some embodiments, the programmable configuration memory is included on an integrated circuit for storing configuration data. According to these embodiments, the configuration function includes transferring configuration data from the configuration memory to the programmable in the configurable logic array. The configuration point, as such, configures the load function to load configuration data from the remote source of the data into the configuration memory via input in the system's early wafer integrated circuit. In some embodiments, the programmable memory is a non-volatile, programmable memory cell, such as a floating gate memory or other chargeable, non-volatile memory. In some embodiments, high speed SRAM is used as a programmable configuration memory to support fast configuration changes of the configurable logic array. Similarly, some embodiments include both non-volatile memory and high speed volatile memory to support the storage and processing of configuration data on the wafer. In other embodiments, the processor core responds to an initialization event, such as a reset to perform configuration loading and configuration functions. An embodiment of a system single-chip integrated circuit in accordance with the present invention includes a watchdog timer that initiates an initialization event in accordance with a time interval of the watchdog timer, the configuration loading function including setting a watchdog timer The time interval makes it suitable for programs that receive configuration data from a remote source, and if the time interval is reached, performs an initialization function that includes a retry configuration load function. In other embodiments, the memory stores instructions for loading functions, task functions, and configuration functions. In an embodiment such as this, the first configuration load function is stored in 1257571 protected memory that is overwritten or modified from the configuration load function, and the first configuration load function provides a channel for configuration data from one The preset position is embedded in the protected memory. The second configuration load is stored in the unprotected memory and used to communicate with the remote source of the configuration data, which may not be in the preset location. The first configuration load function can be used to reply to the configuration load operation if the initialization event occurs during the configuration load operation to change the execution of the second configuration load function. [Embodiment] A detailed description of an embodiment of the present invention refers to FIGS. 1-8. A basic system is as follows: Figure 1 does not include a microcontroller core module 11, such as the known standard 8051 or advanced reduced instruction set (arm) module, or micro Control core module 11 may also be replaced or supplemented by other data processor cores such as digital signal processor cores, high-performance RISC processor cores or other microprocessor or digital signal processor modules. The protected memory 13 and the programmable memory 14 are included in the integrated circuit 1A, and the typical protected memory 13 stores instructions or modifications of the startup function and the like, and the typical programmable memory 14 The task function command 'output/input structure 12' for storing the integrated circuit 1' is also included in the integrated circuit 1A to support one or both of the serial data channel and the parallel data channel of the input and output integrated circuit 1G. Included in the integrated circuit 10 includes a configurable logic array 15 to support the processor core 1 configurable logic array 15 implemented using a field programmable gate array or other form of configurable logic module, configurable logic array 15 1257571 A number of configuration points are included to store the configuration data of the configurable logic array 15 and define its functionality. Typically, the configurable logic array 15 is included in the _system single-chip integrated circuit to support task functions and execute specific logic. In accordance with the present invention, instructions stored by one of the protected memory 13 and the programmable memory 14 are executed via a processor core, the instructions including logic to complete the transfer of configuration data to a configuration point in the configurable logic array 15. The configuration function also includes logic to complete the configuration load to determine the communication pipeline loaded from the remote source via the input/output port 12 to the integrated circuit. 2 is a simplified block diagram of an alternative embodiment of the system, and according to the embodiment of FIG. 2, the processor on the wafer is implemented via the program segment 15A of the configurable logic array 15, the configuration of the program segment (10). The data is stored in the non-volatile configuration point in the block 15A or in the protected memory 13 in the integrated circuit. In this embodiment, according to the initialization of the integrated circuit, the data is transferred from the protected memory 13 to the program segment. In 15A, the processor is implemented via a program segment 15A of a configurable logic array, the execution instructions of which are similar to conventional microprocessor cores u or other processor cores. 3 is a simplified block diagram of another alternative embodiment of the system single-chip integrated circuit 1 according to the present invention. In the embodiment of FIG. 3, the configuration memory 16 is included in the wafer, and the memory is configured to be stored. The configuration data of the logic array 15 is configured and transferred to the configurable logic array according to initialization or under the control of the microcontroller core 11 or other configuration logic on the wafer. The configuration memory 16 can use read-only memory. The implementation is to confirm that the configurable logic array has the smallest set of configuration 11 1257571 data during the manufacturing process. In another system, configuration memory 16 is possible. The control commands are executed via the microcontroller core 11 and can be loaded from the remote source without configuration. In another system, the configuration ^ 77 ^Sergeant & Body 16 can be used to connect people with memory and programmable memory. σ FIG. 4 is a schematic diagram of a system single-chip integrated body according to the present invention. According to a preferred embodiment of the present invention, all of the constituent elements implemented in the detailed description of the example are shown in FIG. In the early years, the shell power core 100 is implemented by a specific purpose circuit or as shown in the figure = the logic array in the microcontroller logic array, and the configurable motion vector 101 and the timer circuit 102 are micro-controlled to support the watchdog 1 The L-switched microcontroller core 100 supports input/output 埠1〇4, tens, state 1, 〇3, 105 and other signals input and output 1〇6, in the integrated body, interrupt line body for storing instructions And through the microcontroller core material: the memory of the road on the road 'the memory sentence; the first memory array 107 is used to store the configuration of the operation device " i instructions, the basin includes configuration loading function and configuration function to support in-product The configurable logic array 110 on the tail of the bottle. In some embodiments, the configuration operating device includes an execution of a temple initialization function in response to an initialization event, such as a reset caused by a t interrupt = number or a watchdog timer reset. The memory further includes a second memory array 108 for storing task function instructions of the system single chip integrated circuit, and a third memory array 109 for storing protected functions, including a boot function, an internal circuit stylization function, and a configurable function. The logical array configuration loads the backup function. The third memory array 109 is protected from being overwritten or modified via an internal circuit staging (ICP) function and during initialization functions 12 1257571, such as reset events and internal circuit stylization programs or configuration loader failures Reply to the system. / Xuan Xin body can use a variety of memory cell technology, including masked food. The implementation of a masked memory, flash memory, static random access memory, and the like is suitable for a particular implementation device. A typical protected memory array 109 is via a non-volatile memory such as a masked read-only memory. A physical or simplistic implementation, when implemented via flash memory or other electrically programmable memory, the logical structure protects the memory array (10) from being overwritten by configuration manned operations or accidents or modify. The logic array 110 can be configured in an integrated circuit as shown in the embodiment of FIG. 4, via a configurable logic array based on a flash memory, and a flash array based on a flash memory The configuration point is non-volatile' so that the configuration data will remain when reset or power off. In the integrated circuit, there is an interface between the microcontroller core (9) and the configurable logic array 11Q, the interface including other structures known in the art, data records m, configuration records 112, and timing records 113, The data, the configuration data, and the timing signal are exchanged between the modules via the interface. The status record 115 confirms the configuration of the configurable logic array using the configuration data via the configuration function of the protocol. The less microcontroller core 100 can retrieve instructions from memory including the memory arrays 107, 1〇8, 1〇9 via an instruction path as shown by the multiplexer 114, including, for example, static random access memory or a recording array. The memory structure is included in the integrated circuit to support execution functions via the microcontroller core or configurable logic array 110. In the embodiment of FIG. 4, the configuration loading function of the configuration operating device is stored in the first memory array 107 to determine the ditch (four) between the path and the remote source of the configuration data.曰 积 电 电 电 , 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收For events or other items, the configuration load function will be re-executed. The first and second passes =) 9? can also be stored in the memory, and the configuration is modified in ::::r or other location, which is used to overwrite the remote source receiving configuration of the setting = the user selects the backup function to store Two: two errors ^ (four) 7 towel shaft ageing device occurs back 'system can be used to store the function in the protected memory array 109, shape, according to US Patent No. 6 4〇1221, 6 493, 788 and The internal circuit stylization function disclosed in 5, 901, 330 is suitable for use. Figure 5 is an alternative construction of a system single-wafer integrated circuit in accordance with the present invention. Similar constituent elements are given the same reference numerals as used in Figure 4. According to an alternative configuration as shown in FIG. 5, the configurable logic array 15 does not need to be implemented with a configurable logic array based on flash memory or other non-volatile configuration points, for example, a configurable logic array 15 can be used A standard field programmable gate array (FPGA) with static random access memory (SRAM) based configuration points is implemented. The configuration data of the 1257571 configurable logic array 150 is stored in the non-volatile configuration data memory array 151, and is realized by the microcontroller core 100 acquiring a partial memory of the integrated circuit. In the embodiment, the control circuit 152 is used as the The interface between the data memory 151 and the microcontroller core 100 is configured, and the configuration loading function of the operating device is configured in the array 107 to determine the channel between the remote source and the configuration data memory 151, and the array is configured during the calculation process. The configuration function of the configuration operating device in 107 transfers the configuration data from the configuration data memory 151 through the microcontroller core 100 to the configurable logic array 150. FIG. 6 is an alternative structure of the system single-chip integrated circuit according to the present invention, similar composition. The elements are given the same numbers as used in Figure 5. According to an alternative configuration as shown in FIG. 6, the configurable logic array 160 can be implemented using a programmable logic device (PLD) module, and the configuration data of the configurable logic array 160 is stored in the non-volatile configuration data memory array 161. And the microcontroller core 100 obtains a part of the memory of the integrated circuit. The control circuit 162 serves as an interface between the configuration data memory 161 and the configurable logic array 160, so that the configuration function of the configuration operation device 107 is directly configured. The function-specific data paths 170, 171 transfer configuration data from the configuration data memory 161 to the configurable logic array 160. The data paths 170, 171 can use wideband parallel data paths or other high speed, specially configured data paths suitable for configuration functions. To achieve this, in the present embodiment, the configuration function in the configuration operating device 107 can be simplified or ignored, and more of its functions are achieved by the control circuit 162. The configuration loading function of the operating device is configured in array 107 to determine the channel between the 15 1257571 remote source and the configuration data memory 161. Figure 7 is an alternative construction of a system single-chip integrated circuit in accordance with the present invention, with similar components being given the same reference numerals as used in Figure 6. According to an alternative structure as shown in FIG. 7, the memory adds a memory array 172 for storing at least one of a twist/decrypt function and a compression/decompression function command. According to the embodiment shown in FIG. 7, the configuration is loaded. The function determines a channel between the remote source and the configuration data memory 161, and the configuration data is received from the remote source in an encrypted form, a compressed form, or an encrypted and compressed form. When the load configuration is configured to the configuration data memory 161, the configuration is configured. The load function decrypts and/or decompresses from the array, or the configuration load function decrypts and/or decompresses from the array when transferring configuration data to a configuration point in the configurable logic array. The memory array 172 stores at least one of a twist/decrypt function and a compression/decompression function for embodiments of different system single-chip integrated circuits, including the embodiments shown in FIGS. 4 and 5. 8 is a block diagram of the main functional components of a fault-tolerant system with internal circuit stylization and configuration loading as in the present invention. A system single-chip integrated circuit includes a processor core (CPU 212) and a configurable logic. Array 251. The internal circuit programming program and configuration loading system includes non-volatile memory 200, random access memory (RAM) 208, CPU 212, and peripheral device 214. The internal circuit programming program and configuration loading system also includes components of the fault tolerant system, including a jump start vector 216, a multiplexer (MUX) 210, an internal circuit programming/configuration load (ICp/CL) state record 218, Remote host address record 220 and ICP/CL watchdog 222. 1257571 More specifically, the 'CPU 212 is any form of processing system, including micro-guards, microprocessors or digital signal processors. cpU212 and Ram2〇8^ together with the code and data contained in the random access memory: CPU212 performs, in addition, CPU212 is also represented by MUX21〇=the secondary path is combined with the non-volatile memory 200. . , non-volatile memory 200 is any form of memory that can save data when the system is powered off, including flash memory, erasable programmable read only memory (EPROM), electrical wipeable In addition to the programmable read-only memory (EEPR0M) and the read-only memory, the non-volatile memory 2 〇 2 梅 2, the mei read, the (4) woven lep configuration operating device 250 and the micro-start code 207. The launcher 202 includes executing program collection in a system initialized program to initialize the system's hardware and software resources. The launcher 202 is stored in the programmable memory and can be modified during configuration loading. The non-volatile memory 2 includes a utility 204. The utility 204 includes a plurality of programs executed by the CPU 212 to perform task functions during the calculation of the system, and the utility 204 can also be included for programmatic loading via the internal circuit. Programs can be programmed in memory. The non-volatile memory 2〇〇 also includes a configuration operating device 250 for performing a configuration loading function of the system and which can be included in a memory that can be programmed in the configuration loading program, in the non-volatile memory 200. The included configuration operating device 25A can be included in a memory that can be programmed via an internal circuit stylized program. The functions performed by the configuration operating device 25 are as described in the previous Figures 4-7. The non-volatile memory 2〇〇 also includes the 17 !25757l micro-start code 207 located in the protected memory. The micro-start code 2〇7 is not modified in the phase:: and the configuration operating device program. The initialization command is completed to complete many of the same functions as the startup program 2〇2, and there is an error that may be caused by the startup program 2 (10). The circuit program program is not generated. (4) The circuit program program or the configuration device function 250 fails. When it is unstable, the micro-start code is only a tripping behavior. Therefore, the micro-start code m must be stored in the memory of the stylized process towel* of the same internal circuit normal startup program. In one embodiment of the present invention, when the boot program 2〇2, the utility 204, the configuration operating device 25〇, and the lcp operating device 2〇6 are stored in the programmable flash memory, the micro boot code 2〇7 is stored. In masked read-only memory. 11 In the ICP program, CPU 212 combines hardware components to aid fault tolerance. CPU 212 combines MUX 210 as input to non-volatile memory 2 and jump start vector 216 and controls input from ICP/CL status record 218. MUX210 views The ICP/CL state 218 conditionally switches cpu212 between the jump start direction and the ::: 216 and the non-volatile memory 200. If the ICP/CL state 218 is scaled, it indicates that the previous ICP calculation or calculation correction configuration is loaded. If the operation is not completed, the CPU 212 inputs a jump instruction to the start vector 216 to point to the micro start code 207 in the system initialization program. On the other hand, if the iCp/CL state 218 is clean, it indicates that no load operation is being performed. The CPU 212 inputs the initial loading of the non-volatile memory 2〇〇 in the initialization program of the system, and the CPU 212 combines the remote host address record 220 and includes the backup remote host address, which is avoided in the 18 1257571 electrification program. A system reset occurs, circle 2 is also coupled to ICP/CL watchdog 222 via read/write path and reset line 232, and ICP/CL watchdog 222 includes a timeout period. Recording 226 and timing 224, matching logic 228, timer 224 and expiration period 226 can be initialized via (10) 12 through read/write path 23(), when the value of timing 224 is the same as expiration period 226, The matching logic 2 reset signals are transmitted to the cpU 212 via the reset line 232. The fault tolerance provided by the hardware component in the context of the implementation includes protecting the programmable memory component from internal circuit programming. In addition, the CPU 212 is combined with the peripheral device 214, including the input and output devices of the user connected to the system. As shown by the double arrows on the left side of the peripheral device 214, the peripheral device 214 also includes an interface through the peripheral device 214 and the Internet 234. Or other communication channels or networks. The Internet 234 itself incorporates remote hosts 236, 238, and 240 that incorporate a disk 242 containing a new version of the boot and utility, including, for example, new internal circuit staging functions or new configuration loads. The function is entered and downloaded to the system via the Internet 234. The configuration loader generally operates as follows. First, the CPU 212 is connected to the user 244 through the peripheral device 214. The user 244 causes the CPU 212 to start executing the configuration operation device 206 to perform the configuration load program, and the configuration operation device 250 causes the peripheral device 214 to pass through the peripheral device 214 to the Internet. The network 234 and the connection between the Internet 234 and the remote host 238, and then the remote host 238 begins to download data from the disk 242 through the Internet 234 to the non-volatile memory 200, and the data begins to be transferred. The expiration period 226 in the ICP/CL watchdog 222 1257571 sets an estimate and the timer 224 begins timing. If the configuration loader goes smoothly, the fault tolerance feature of the present invention is inactive. On the other hand, if excessive delay occurs in the configuration loader, the timer 224 will eventually be the same as the expiration cycle 226. The reset signal reaches the CPU 212 via the reset line 232 and causes cpU2j to start a series of starts. If the system is restarted in the configuration loader, the ICP/CL status record 218 is set to a dirty value, thus causing 21 〇 direct jump start vector 216 to the CPU 212, causing the micro-start code launch program 202 to cause the CPU 212 to start. If the Icp/CL state 218 » is again a clean value, it indicates that the configuration loader has all been completed and Μ(10)2 sen starts the CPU 212 from the startup program 202. The micro-boot code 207 causes the CPU 212 to restart the configuration of the loader, which is determined by the first read value of the slave % host address § record 220 to restart the configuration of the loader, and then configured. The loader will start over. In another embodiment, the 'micro-start code 2G7 includes a configuration load stylized design for accessing configuration settings from a preset location, such as non-volatile memory in a wafer or via a predetermined host. Combined with the system single-chip integrated circuit. The ICP program generally operates as follows. First, the CPU 212 is connected to the user 244 through the peripheral device 214. Some of the atypical system single-chip integrated circuits are connected to the user via the input/rounding port, and the user 244 causes the CPU 212 to start executing the lcp device. The (10) procedure is performed, (10) the device 2〇6 initiates a connection between the peripheral device 214 to the Internet 234 and through the Internet 234 to the remote host 238, and then the remote host 238 begins the 1257571 攸 disk 242 through the Internet. The path 234 downloads the data into the non-volatile memory 200, and at the same time the data begins to shift, the expiration period 226 in the icp/a watchdog 222 sets an estimate and the timer 224 begins timing. If the iCP procedure proceeds smoothly, the fault-tolerant feature of the present invention is inactive. On the other hand, if excessive delay occurs in the ICP procedure, the chrono 224 will eventually be the same as the expiration period 226, causing a reset signal to pass through Line 232 reaches CPU 212 and causes CPU 212 to begin a series of starts. If the system is restarted in the icp program, the ICP/CL status record 218 is set to a dirty value, thus causing the 跳跃 21〇 direct jump to start into the 216 to the CPU 212, causing the micro-start code 2〇7 to trigger the CPU 212 instead of the initiator 202. start up. If the ICP/CL state 218 is set to a clean value, it indicates that the icp program has all been completed, and the MUX 21{) causes the CPU 212 to boot from the boot program 202. The micro-boot code 207 causes the CPU 212 to restart the icp program, which determines the connection of the remote host by the first read value from the back-end host address record 220 to restart the ICP program, and then the ICP program restarts. ❿ In some embodiments, the ICP program can overwrite or modify the configuration operating device. In these embodiments, the ICP program first backs up the configuration operating device 250 into non-volatile memory to determine the configuration of the load on the system single wafer. Two backups, one of which is modified. If the modification is completely successful, another backup will be deleted. However, if the modification is not completely successful, the secure backup of the configuration operating device can be used to reply to the system operation. The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the present invention to the disclosed form. 21 1257571 Modifications or variations based on the above teachings or learning from embodiments of the present invention. It is possible to exemplify the principles of the present invention and to enable those skilled in the art to use the present invention in various embodiments to select and describe the present invention. The technical idea of the present invention is intended to be Equal to decide. [Simple description of the map]
對於熟習本技藝之人士而言，從以下所作的詳細敘述 配合伴隨的圖式，本發明將能夠更清楚地被瞭解，其上述 及其他目的及優點將會變得更明顯，其中： 圖1係根據本發明的系統單晶片積體電路的一個實施 例之簡化方塊圖； 圖2係根據本發明的系統單晶片積體電路的另一實施 例之簡化方塊圖；The above and other objects and advantages will become more apparent from the following detailed description of the invention. A simplified block diagram of one embodiment of a system single wafer integrated circuit in accordance with the present invention; FIG. 2 is a simplified block diagram of another embodiment of a system single wafer integrated circuit in accordance with the present invention;
圖3係根據本發明的糸統早晶片積體電路的又^一實施 例之簡化方塊圖； 圖4係根據本發明的系統單晶片積體電路之較詳細的 功能不意圖， 圖5係根據本發明在晶片上包括配置資料記憶體的系 統單晶片積體電路的一個實施例之功能示意圖； 圖6係根據本發明在晶片上包括配置資料記憶體的系 統單晶片積體電路的另一實施例之功能示意圖； 圖7係根據本發明在晶片上包括配置資料記憶體並支 援加密/解密及/或壓縮/解壓縮的系統單晶片積體電路的 22 1257571 一個實施例之功能示意圖；以及 圖8係根據本發明所提供系統單晶片積體電路環境部 署的理論圖，其中配置資料由遠端源提供且系統單晶片積 體電路允許配置載入功能的配置載入，以建立與遠端源的 溝通管道。 【主要元件符號說明】 10 系統單晶片積體電路 11 微控制器核心模組 12 輸入/輸出結構 13 受保護記憶體 14 可程式化記憶體 15 可配置邏輯陣列 15A可配置邏輯陣列的程式段 16 配置記憶體 100微控制器核心 101啟動向量 102計時器 103開門狗計時器 104輸入/輸出埠 105中斷線 106其他訊號輸入與輸出 107第一記憶陣列 108第二記憶陣列 23 1257571 109第三記憶陣列 110可配置邏輯陣列 111資料記錄 112配置記錄 113計時記錄 114多工器 115狀態記錄 150可配置邏輯陣列 151配置資料記憶陣列 152控制電路 160可配置邏輯陣列 161配置資料記憶陣列 162控制電路 170資料路徑 171資料路徑 172記憶陣列 200非揮發性記憶體 202啟動程式 204公用程式 206内電路程式化操作裝置 208隨機存取記憶體 210多工器 212中央處理器（CPU) 214周邊裝置 1257571 216跳躍啟動向量 218内電路程式化/配置載入狀態 220遠端主機地址記錄 222内電路程式化/配置載入看門狗 224計時器 226到期週期記錄 228匹配邏輯 230讀/寫路徑 232重置線 234網際網路 236遠端主機 238遠端主機 240遠端主機 242磁碟片 244使用者 250配置操作裝置 251可配置邏輯陣列 25Figure 3 is a simplified block diagram of another embodiment of a system of integrated wafers in accordance with the present invention; Figure 4 is a more detailed functional notation of a system of single-chip integrated circuits in accordance with the present invention, Figure 5 is based on BRIEF DESCRIPTION OF THE DRAWINGS The present invention includes a functional schematic diagram of one embodiment of a system monolithic integrated circuit in which a data memory is disposed on a wafer. FIG. 6 is another embodiment of a system monolithic integrated circuit including a data memory on a wafer in accordance with the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a functional schematic diagram of an embodiment of a system of a single-chip integrated circuit that includes a data memory configuration and supports encryption/decryption and/or compression/decompression on a wafer in accordance with the present invention; 8 is a theoretical diagram of a system single-chip integrated circuit environment deployment in accordance with the present invention, wherein the configuration data is provided by a remote source and the system single-chip integrated circuit allows configuration loading of the configuration load function to establish a remote source Communication pipeline. [Main component symbol description] 10 System single chip integrated circuit 11 Microcontroller core module 12 Input/output structure 13 Protected memory 14 Programmable memory 15 Configurable logic array 15A Configurable logic array block 16 Configuration Memory 100 Microcontroller Core 101 Startup Vector 102 Timer 103 Open Dog Timer 104 Input/Output 埠 105 Interrupt Line 106 Other Signal Inputs and Outputs 107 First Memory Array 108 Second Memory Array 23 1257571 109 Third Memory Array 110 configurable logic array 111 data record 112 configuration record 113 timing record 114 multiplexer 115 status record 150 configurable logic array 151 configuration data memory array 152 control circuit 160 configurable logic array 161 configuration data memory array 162 control circuit 170 data Path 171 data path 172 memory array 200 non-volatile memory 202 boot program 204 utility 206 circuit programming operation device 208 random access memory 210 multiplexer 212 central processing unit (CPU) 214 peripheral device 1257571 216 jump start Vector 218 internal circuit stylization / configuration loading state 220 remote host Address Recording 222 Circuit Stylization/Configuration Loading Watchdog 224 Timer 226 Expiration Period Record 228 Matching Logic 230 Read/Write Path 232 Reset Line 234 Internet 236 Remote Host 238 Remote Host 240 Remote Host 242 disk 244 user 250 configuration operating device 251 configurable logic array 25