TWI258824B - Semiconductor package structure - Google Patents

Semiconductor package structure Download PDF

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Publication number
TWI258824B
TWI258824B TW094138421A TW94138421A TWI258824B TW I258824 B TWI258824 B TW I258824B TW 094138421 A TW094138421 A TW 094138421A TW 94138421 A TW94138421 A TW 94138421A TW I258824 B TWI258824 B TW I258824B
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TW
Taiwan
Prior art keywords
wafer
crystal
semiconductor package
crystal holder
package structure
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TW094138421A
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Chinese (zh)
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TW200719414A (en
Inventor
Chi-Jang Lo
Original Assignee
Powertech Technology Inc
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Priority to TW094138421A priority Critical patent/TWI258824B/en
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Publication of TWI258824B publication Critical patent/TWI258824B/en
Publication of TW200719414A publication Critical patent/TW200719414A/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

A semiconductor package structure, which includes a die base composed of two die pads which are disposed in the two sides of the chip with each of the die pads containing two extension arms extending toward the peripheral of the chip, and a plurality of pins which are electrically connected onto the chip. The above-mentioned device is then encapsulated by a package molding compound. By means of using the die base containing two extension arms, the delamination problem generated by the residual air bubbles during processing can be improved, yield of package process can be greatly raised, and the service life-span of the chip can be increased.

Description

1258824 九、發明說明: 【發明所屬之技術領域】 本發明係有關-種半導體封裝結構’特別是有關—種在灌模 大幅降低殘留空氣氣泡的半導體封裝結構。 【先前技術】 隨著半導體製程技術的進步與積體電路的密度销增加,鮮元件之 引:愈來《,對速度之要求亦縣錄,使得製作體積小、速度快及高 =度之^兀件已成趨勢,再加上構裝元件的消耗功率愈來愈大的結果, 導致構裝元件的構裝範圍及散熱問題日趨重要。 ^ 習用半導體封裝結構,如第i圖所示,此封 曰^ ^ ^^„^(LeadFrame), 岐加二,a,此曰曰座16為一晶片承載區可供晶片10,黏貼固定於導 未;敝讀,鋪«财絲—封裝賴 性連接至其:i置Β:。及部分引腳14’,並露_分引腳14,方便電 -- 晶片Κ),脫声的規參Λ 時,例如SMT製程,因遇熱膨脹而造成 力曰9、 更甚者,造成封裝結構在熱脹冷縮時無法消除接點麻 , of Thermal Expanse, CTE) 不间,k成熱脹冷縮時應力損垮接 ^ 外那些殘留且未爆破的片朋衣(P〇PC⑽)的情況發生。另 體封裝結構容易產生彳料致此封裝結構傳熱不良’而使半導 膨脹的因素’而使此曰片:另/一些殘留的空氣氣泡在硬化過程時,因熱 良率。一種解決:產生偏移(sweeP)的效應,進而影響封裝製程中 /、、去為將晶座-分為二,形成兩長方形晶座,分別置放 1258824 於a曰二^兩端但疋如果遇到晶片尺寸較大時一— 的支撐力,使整個封裝膠體強度不足, 4曰曰座將無法提供足夠 力時Μ柄歸體斷裂。 【發明内容】 有鑑於此,本發明係針對上述之問題 有效克服封膠時殘留的空氣氣泡,並加強整^裝^。導體雖結構,可 本發明的目的之―,係提供一種半導體封裳 晶墊所形成的晶座取代制晶座,使灌模 ^ 兩延伸臂之 『為氣蝴所造成遇高—問題,使;留=提 本發明之又一目的,係提供一種半 — 晶墊提供⑼較好之支撐,可改善在構’猎由具兩延伸臂之 晶片或封裝問題。θθ、I ’侧支撐力不足而導致 本七月之X目的’係提供一種半導體封裝結構,因減少殘留在此封 裝結構的氣泡,使晶片傳熱效率良好,進而使此晶片使用壽命增加。 曰孰ΐ發I之再—目的’係提供—種半導體封裝結構,藉由具兩延伸臂之 日曰塾亦可有效控制接合晶片與晶座時的接合剌量,進而降低整體封裝成 本0 根據上述,本發明之-實施例提供-辭導體封裝結構,包括有-晶 座,此晶座係由二晶墊構成,且群晶墊係設置於晶片之兩側,其中任一 晶墊係具有兩延伸臂朝晶片之周緣延伸,另外此封裝結構包括複數引腳, 且引腳電性連接至此晶>}上,再由—封裝膠體將上述晶片予以包覆。 底下藉由具體實施細&合所關圖式詳加說明,當更容^瞭解本發明 之目的、技術内容、特點及其所達成之功效。 1258824 【實施方式】 依據本發明之一實施例係提供一種半導體封裝結構,此封裝結構在封 m中可避免空氣氣>包殘留’而使封裝良率大巾冑提高,而此半導體封裝 結構主要係由-晶座、-0日』及複數引腳馳成,以下就減封裝結構各 個部分構裝予以說明。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure in which a residual air bubble is greatly reduced in a mold. [Prior Art] With the advancement of semiconductor process technology and the increase in the density of integrated circuit, the introduction of fresh components: More and more, the requirements for speed are also recorded in the county, making the production volume small, fast and high=degree^ The trend of the components has become a trend, and as a result of the increasing power consumption of the components, the construction range and heat dissipation of the components have become increasingly important. ^ Conventional semiconductor package structure, as shown in Figure i, this package ^ ^ ^ ^ ^ ^ (LeadFrame), 岐 plus two, a, the 16 16 is a wafer carrying area for the wafer 10, adhered to Guided, read, shop «Fin Silk - package connection is connected to it: i set: and some pins 14', and exposed _ minute pin 14, convenient electricity - wafer Κ), de-sound gauge When participating in the sputum, for example, the SMT process is caused by thermal expansion, and even worse, the package structure cannot be removed during thermal expansion and contraction, and the thermal expansion (CTE) is not good. The shrinkage stress is damaged and the residual and unexploded film (P〇PC(10)) occurs. The other package structure is prone to the poor heat transfer of the package structure and the factor of semi-expansion expansion. And this enamel: another / some residual air bubbles in the hardening process, due to the heat yield. One solution: the effect of offset (sweeP), which in turn affects the packaging process /, to go to the crystal holder - For the second, form two rectangular crystal holders, respectively, placing 1258824 on both ends of the two sides, but if the size of the wafer is large, the support is The force is such that the strength of the entire encapsulant is insufficient, and the crucible is not able to provide sufficient force when the crucible is broken. [Invention] In view of the above, the present invention effectively overcomes the air bubbles remaining during the sealing of the above-mentioned problems. And strengthening the structure of the conductor. The structure of the conductor, which can be used for the purpose of the present invention, is to provide a semiconductor holder to form a crystal seat instead of a crystal holder, so that the two extension arms of the mold are A further object of the present invention is to provide a semi-crystalline pad to provide (9) better support for improving wafer or package problems with two extension arms. Insufficient I's side support force leads to the fact that the X-object of this July provides a semiconductor package structure, which reduces the air bubbles remaining in the package structure, so that the heat transfer efficiency of the wafer is good, thereby increasing the service life of the wafer. The re-issue of the I-purpose is to provide a semiconductor package structure, which can effectively control the bonding amount when bonding the wafer and the crystal seat by using the two extension arms, thereby reducing the overall package cost. According to the above, the embodiment of the present invention provides a conductor package structure including a crystal holder, the crystal holder is composed of a two crystal pad, and the group pad is disposed on both sides of the wafer, and any of the crystal pads is provided. The two extension arms extend toward the periphery of the chip, and the package structure includes a plurality of pins, and the pins are electrically connected to the crystals, and the wafer is coated by the encapsulation colloid. The details of the present invention, the technical content, the features, and the effects achieved by the present invention are further described. 1258824 [Embodiment] According to an embodiment of the present invention, a semiconductor package structure is provided. The package structure can avoid the air gas > package residue in the sealing m, and the package yield is increased, and the semiconductor package structure is mainly composed of a - crystal seat, -0 day, and a plurality of pins. The following describes the construction of each part of the package structure.

首先,請先參閱第2A圖及第2B圖,如圖所示,其中第2A圖是本發 明之-實施例之半導體封裝結構俯視示意圖,第2B圖係為第2A圖的从, 剖線之結構剖視示意圖。此封裝結構包括一晶座2〇、— θ片22、複數引腳 %及-封裝膠體38。其中,此晶座20係、由二晶塾%構^,且該等晶塾% 分別設有-弧形開π 28,於-實施例中,該等晶塾%係為金屬材質所構 成。接著,晶片22係設置於晶座20上並輕鱗弧形開口 28,使致該等 晶墊26可提供晶片22足夠的支撐,如第2Β圖所示,此晶片22係利用_ ,合件30,例如絕緣接合件,使用習知適當方式,例如黏貼方式,設置於 曰曰座20上。於一實施例中’接合件3〇可為絕緣膠帶及絕緣膠體之任一。 =上遠’如第2Β圖所示,每一引腳24包括一外引腳32及一内引腳 母-引腳24係設置在此晶座20的周圍側邊,將每一内引㈣電性 線^ 22上,於—實施财,此電性連接的方式可以為_至少-引 ,二式(職b〇ndmg)將每一内引腳34與晶片D電性連接,於-方5;Γ之材質係為金(罐屬、銅質或晴質職^ ^ 片22、^內t封^體% ’例如環氧樹脂(Ερ_),包覆此晶座2〇、晶 «4: 36 5 26 σ ^ J 又。十使仔空氣谷易排出,不會曰 :r::r:rr ·First, please refer to FIG. 2A and FIG. 2B. As shown in the figure, FIG. 2A is a schematic plan view of a semiconductor package structure according to an embodiment of the present invention, and FIG. 2B is a cross-sectional view of FIG. 2A. A schematic cross-sectional view of the structure. The package structure includes a crystal holder 2〇, a θ sheet 22, a plurality of pins % and a package encapsulant 38. Wherein, the crystal holder 20 is composed of two crystals, and the crystals % are respectively provided with an arc-shaped opening π 28 . In the embodiment, the crystals % are made of a metal material. Next, the wafer 22 is disposed on the crystal holder 20 and has a light-scale curved opening 28, so that the crystal pads 26 can provide sufficient support for the wafer 22. As shown in FIG. 2, the wafer 22 is _ 30, such as an insulative joint, is disposed on the sley 20 using conventional means, such as adhesive means. In one embodiment, the joining member 3 can be either an insulating tape or an insulating colloid. =上远' As shown in Figure 2, each pin 24 includes an outer pin 32 and an inner pin female-pin 24 are disposed on the periphery of the crystal holder 20, each of which is internally (four) On the electrical line ^ 22, in the implementation of the financial, the way of electrical connection can be _ at least - lead, two types (service b 〇 ndmg) each internal lead 34 and the wafer D electrically connected, in the - side 5; the material of the enamel is gold (cans, copper or sunny jobs ^ ^ sheet 22, ^ inside t seal ^ body% 'such as epoxy resin (Ερ_), coated with this crystal holder 2 〇, crystal «4 : 36 5 26 σ ^ J Again. Ten makes the air valley easy to discharge, will not lick: r::r:rr ·

施例之ΐ導圖及第3B圖,第3A W及第3B圖為本發明又-實 體私結構之俯視示意圖及其耻剖線之結構剖視示意圖。I 1258824 .· ...... ..................— 封裝結構包括一晶座4〇、一晶片42、複數引腳44及一封裝膠體58。此晶 座40係用來承載一晶片42,其中,此晶座40係由二晶墊46,例如金屬材 質所構成’且該等晶墊46係利用一接合件50,例如絕緣膠帶及絕緣膠體之 任一’以習知適當方式,例如黏貼方式,將晶片42設置於晶墊46上,於 一實施例中,晶墊46可置於晶片42下方兩側,以用以承載晶片42。其中, 任一晶墊46係具有兩延伸臂48,例如门字型,分別沿晶片42之周緣43 延伸,此延伸臂48長度可依照需求做調整,不限制於此圖示中所示之比例。 於一實施例中,任一該晶墊46之該等延伸臂48係朝該晶片42周緣43並 與另一該晶墊46之該等延伸臂48的對向延伸。該等延伸臂48可以增加晶 座40與晶片42的接觸面積以確保支撐力足夠。 接著,繼續參考第3B圖,每一引腳44包括一外引腳52及一内引腳 54,且每一引腳44係設置在此晶座恥的周圍側邊,將每一内引腳%電性 連接至晶片42上,於一實施例中,此電性連接的方式可以為利用至少一引 線允以打線方式(wireb〇nding)將每一内引腳科與晶片42電性連接,於一 實=例中’引線56之材質係為金㈣金屬材質、鋼質或銘質材質所構成。 接者,用賴方式將-封轉體58,例如環氧樹脂(EpQxy),包覆此晶座 40日:片42、δ亥等内引腳54及該等引線56,由於晶墊46延伸臂48的設 汁(如第3Α圖所示),除了提供支撐外,更使得空氣容易排出,不會在晶座 4〇周邊產生氣泡殘留’以確保不會有脫層的現象發生。接下來進行硬化 (_g)製,’將此封裝膠鹩58硬化,而所霧出的外引腳U則可供接合於 二?^路衣置上。再者’因為排除殘留的氣泡影響,可減少封裝結構崩裂 或疋日日片42偏移的情況發生。 ,據上述,本發明的特徵之…利仏弧形晶墊或具延伸臂之晶塾構 成勺曰曰座’提供晶片-支撐,在灌模時不會在晶片 構Γ行硬化製程時不因殘留的空氣氣泡產生崩裂:散熱不良 °㈣餘程中良率大幅提高,並且因減少殘留在 土衣、構的“ ’使晶片傳熱效率良好,進而使此晶片使用壽命增加。 本毛月的特叙,利用二弧形晶塾或具延伸臂之晶塾構成的晶座, 1258824 =加與晶>!的_面積來加強整體封裝結構之強度,可適麟任何大小之 曰曰片。又’本發明的特徵之_,因為不同於習知晶座之形狀,接合晶片盘 晶座時亦可有效控制接合件之用量。 /、 g惟以上所述之實_僅為本Μ之雛實_,藉由實補說明本發 月之特點其目的在使熟習該技術者能暸解本發明之内容並據以實施,並 ^用以侷限本翻實施之制。舉凡制本Μ中請專纖_述之構 造、=狀、特徵及精神所為之均等變化及修飾,皆應包括於本發明申請 利之範圍内。FIG. 3A and FIG. 3B are schematic top views of the private-solid structure of the present invention and a schematic cross-sectional view of the shave line. I 1258824 ............................... The package structure includes a crystal holder 4, a wafer 42, a plurality of pins 44 and an encapsulant 58. The crystal holder 40 is used to carry a wafer 42. The crystal holder 40 is formed of a two-layer pad 46, such as a metal material, and the crystal pad 46 utilizes a bonding member 50 such as an insulating tape and an insulating colloid. The wafer 42 is disposed on the crystal pad 46 in a suitable manner, such as by pasting. In one embodiment, the crystal pad 46 can be placed on both sides of the wafer 42 to carry the wafer 42. Wherein, any of the crystal pads 46 has two extending arms 48, such as a gate shape, extending along the periphery 43 of the wafer 42, respectively. The length of the extending arm 48 can be adjusted according to requirements, and is not limited to the ratio shown in the figure. . In one embodiment, the extension arms 48 of any of the pads 46 extend toward the periphery of the wafer 42 and opposite the extension arms 48 of the other of the pads 46. The extension arms 48 can increase the contact area of the wafer 40 with the wafer 42 to ensure that the support force is sufficient. Next, referring to FIG. 3B, each pin 44 includes an outer pin 52 and an inner pin 54, and each pin 44 is disposed on the periphery of the crystal seat shame, and each inner pin % is electrically connected to the wafer 42. In an embodiment, the electrical connection may be electrically connected to the wafer 42 by using at least one lead wire to be wire-wired. In the case of a real example, the material of the lead 56 is made of gold (four) metal material, steel or alloy material. Then, the flip-flop 58, such as epoxy resin (EpQxy), is coated with the crystal holder for 40 days: the chip 42, the inner lead 54 and the lead 56 are extended by the crystal pad 46. The juice of the arm 48 (as shown in Fig. 3), in addition to providing support, allows air to be easily discharged without causing bubble residue around the wafer holder 4 to ensure that no delamination occurs. Next, a hardening (_g) system is performed, 'the encapsulating capsule 58 is hardened, and the misted outer pin U is attached to the second coating. Furthermore, since the influence of residual bubbles is excluded, it is possible to reduce the occurrence of cracking of the package structure or the offset of the solar sheet 42. According to the above, the feature of the present invention is that the curved crystal pad or the wafer with the extending arm constitutes a wafer holder, which does not cause a wafer-support during the filling process. Residual air bubbles cause cracking: poor heat dissipation. (4) The yield in the remaining range is greatly improved, and the heat transfer efficiency of the wafer is improved by reducing the residual heat in the soil, and the life of the wafer is increased. Syria, using a two-arc crystal or a crystal holder with a stretching arm, 1258824 = plus the crystal area of the _ area to enhance the strength of the overall package structure, can be suitable for any size of the film. The feature of the present invention is that, unlike the shape of the conventional crystal holder, the amount of the joint member can be effectively controlled when the wafer holder is joined. /, g is only the above-mentioned one. The purpose of this month is to clarify the characteristics of the present month, so that those skilled in the art can understand the contents of the present invention and implement it according to the method, and use it to limit the implementation of the system. The structure, the shape, the characteristics and the spirit are equal And modifications are to be included within the scope of interest in the present application.

【圖式簡單說明】 第1圖為習知封裝結構之俯視示意圖。 第2Α圖為本發明之一實施例之半導體封裝結構之俯視示意圖。 第 第 第 2Β圖為本發明之-實施例第2Α圖之从,剖線之結構剖視示意圖。 3Α圖為本發明之又一實施例之半導體縣結構之俯視示意圖。 3Β圖為本發明之又-實施例第3Α圖之Ββ,剖線之結構剖視示意圖 【主要元件符號說明】 Μ 晶片 14, 引腳 16, 晶座 20、40晶座 22、42晶片 24、44弓|腳 26、46晶墊 28 弧形開口 30、50接合件 1258824 32、52外引腳 34、54内引腳 36、56引線 38、58封裝膠體 43 周緣 48 延伸臂BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view of a conventional package structure. 2 is a top plan view showing a semiconductor package structure according to an embodiment of the present invention. Fig. 2 is a cross-sectional view showing the structure of the second embodiment of the present invention. 3 is a top plan view of a semiconductor county structure according to still another embodiment of the present invention. 3 为本 为本 为本 实施 实施 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 结构 结构 结构44 bow|foot 26, 46 crystal pad 28 arcuate opening 30, 50 joint 1258824 32, 52 outer lead 34, 54 inner lead 36, 56 lead 38, 58 encapsulant 43 circumference 48 extension arm

Claims (1)

1258824 ........ ............, 十、申請專利範圍: -—— 1.一種半導體封裝結構,包括·· -晶座,係用以承載-晶片,其中該晶座係 塾係設置於該晶片之兩側,其中任—該晶塾 :成且射阳 緣延伸; f係具有兩延伸臂朝該晶片之周 複數引腳,係電性連接至該晶片上;及 一封裝膠體,係包覆該晶片。 2為η如字申|糊_ 11賴之半_裝結構,其巾,該晶墊之形狀係 |才質如申請專利範圍第丨項所述之半_裝結構,其中,該綱為金屬 4、 如申請專利範圍第!項所述之半導體封 ,^ ^ 接合件裝設在該晶座上。 1'中‘曰片_用_ 5、 如申請專機_ 4 _述之半導體職 緣膠帶或絕轉體。 τ祕α件係為絕 =曰t專纖圍第1賴述之半輸懷轉,其中,該職膠體係包 覆遠晶墊與部分該等引腳。 不示巴 7、 如申請專利範圍第丨項所述之半導體雕結構,其中,任一該 等延伸臂係朝該晶片周緣與另—該晶塾之鱗延伸臂的對向延伸。μ 8、 一種半導體封裝結構,包括: =晶座’其係由二晶塾構成,且該等晶塾分別設置-弧形開口; =晶片,係設置於該晶座上並覆蓋鱗弧形開口; 複數引腳,係電性連接至該晶片上;及 一封裝膠體,係包覆該晶片。 9、 如中請專利翻第8項所述之半導 其 包含-外引腳及-㈣腳。 肖Ί «引_各別 10、 如申請專刺範圍第8項所述之半導 用至少-引線與該翱形成電性連接。 4射㈣Ρ係利 l2s8824 如申請專利範圍第!所述之半甘一 =金屬#_成者。 構’射,該等_系 S氣如樹ΐ專顺園第8項所述之半導㈣裝結構,其中,該封裝膠趙係 柳糾_物心,叫係_ t如申請專利範圍帛13 _述之半導體封裝 為絕緣膠帶或絕緣膠體。 /、中趣合件係1258824 ........ ............, X. Patent application scope: - 1. 1. A semiconductor package structure, including - crystal holder, used to carry - a wafer, wherein the crystal system is disposed on both sides of the wafer, wherein any one of the crystals is formed and the anode edge is extended; and the f system has two extension arms toward the periphery of the wafer, and is electrically connected. To the wafer; and an encapsulant that coats the wafer. 2 is η如字申|糊_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 4, such as the scope of application for patents! The semiconductor package described in the item is mounted on the crystal holder. 1 '中' 曰片_用_ 5, such as applying for special plane _ 4 _ described semiconductor job tape or absolute body. The τ secret α part is absolutely the first half of the 纤 专 专 专 围 第 第 第 第 第 第 第 第 第 , , , , , , , , , , , , , , , , , , , , , 7. The semiconductor engraving structure of claim 3, wherein any one of the extension arms extends in a direction opposite the circumference of the wafer and the other of the scale extension arms of the wafer. μ 8. A semiconductor package structure comprising: = a crystal holder' which is composed of a germanium, and the crystals are respectively provided with an arc-shaped opening; a wafer is disposed on the crystal holder and covers the scale-shaped opening a plurality of pins electrically connected to the wafer; and an encapsulant that encapsulates the wafer. 9. For example, please refer to the semi-conductor described in Item 8 which contains the - outer pin and - (four) leg. Xiao Wei «引_各各10. If you apply for the semi-conductor as described in item 8 of the special thorn range, at least the lead wire is electrically connected to the 翱. 4 shots (four) Ρ系利 l2s8824 If you apply for the scope of patents! The semi-Ganyi = metal #_ into the person. The structure is a semi-conductor (four) installation structure as described in Item 8 of the tree ΐ ΐ ΐ , , , , , , , , _ _ 纠 纠 _ _ _ 如 如 如 如 如 如 如 如 如 如 如 如 如 如The semiconductor package described is an insulating tape or an insulating colloid. /, Chinese fun parts 如申請專利範圍第8項所述之半導體封裝結 利用灌模方式進行包覆。 ,、中,雜裝膠體係 ’其中,該二晶墊係為 ’其中,該封裝膠體係 16 '如申請專利範圍第8項所述之半導體封裝結構 金屬材質。 17、如申請專利範圍第8項所述之半導體封裝結構 包覆該晶座與該等引腳。 18、 一種封裝用之晶座結構,其係用於進行封裝製程時,提供支撐至少一 晶片,該封裝狀晶座結構係由二晶塾組成,且在該等晶好別設有一弧 形開口,將該晶片設置於該晶座上並覆蓋該等弧形開口。The semiconductor package junction as described in claim 8 is coated by a filling method. , the medium, the miscellaneous rubber system, wherein the two-layer pad is 'the package resin system 16', and the semiconductor package structure metal material as described in claim 8 of the patent application. 17. The semiconductor package structure of claim 8 wherein the semiconductor holder and the pins are covered. 18. A crystal holder structure for packaging, which is used for providing at least one wafer for performing a packaging process, the package-like crystal structure being composed of a germanium, and having an arc-shaped opening in the crystal. The wafer is placed on the crystal holder and covers the arcuate openings. 19、 如申請專利範圍第18項所述之封裝用之晶座結構,其中,該等晶墊係 為金屬材質。 20、 如申請專利範圍第19項所述之封裝用之晶座結構,其中,該晶片係利 用 '一接合件裝設在纟玄專日日座上 21 '如申請專利範圍第20項所述之封裝用之晶座結構,其中,該接合件係 為絕緣膠帶或絕緣膠體。 1219. The crystal holder structure for encapsulation according to claim 18, wherein the crystal pads are made of a metal material. 20. The crystal holder structure for encapsulation according to claim 19, wherein the wafer is mounted on the 纟玄日日座 by a 'joint member' as described in claim 20 The crystal holder structure for packaging, wherein the joint member is an insulating tape or an insulating colloid. 12
TW094138421A 2005-11-02 2005-11-02 Semiconductor package structure TWI258824B (en)

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