TWI257765B - Class-D amplifier - Google Patents
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1257765 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種D類放大器。 【先前技術】 D類放大杰藉由脈衝見度調變(pulse_width-m〇dulating ; PWM)輪入枱號執行功率放大,並用於執行聲訊信號之功率 放大。作為傳統D類放大器,一種此類D類放大器係配置為 用於對類比輸入信號積分之積分器、用於比較該積分器之 輸出信號與預定三角波之比較器以及用於放大該比較器之 輸出化5虎以輸出脈衝信號之緩衝器(脈衝放大器)。此傳統D 颌放大裔中,將自緩衝器輸出之脈衝信號回饋至積分器之 輸入侧。接著,由線圈及電容器構造之低通濾波器過濾緩 衝為之輸出信號,以便獲得驅動負載(例如揚聲器)之類比信 號。 作為傳統脈衝寬度調變放大器,一種此類PWM放大器係 配置為用於比較類比輸入信號與三角波之比較器、用於放 大比車乂為之輪出的放大器以及配置於放大器與負載之間的 又【的(例如’麥考日本專利公開案第Sho-56-27001號)。 另外,作為使用數位信號處理電路之傳統數位放大電 路’種此類數位放大電路配備一雜訊整形器、一轉換器、 一邏輯電路、一開關以及一濾波器(例如,參考日本專利揭 不内容第2〇00_5〇〇625號)。雜訊整形器對數位輸入信號之量 化嘁汛進行頻率整形。轉換器將對應於雜訊整形器之輸出 的PCM(脈衝編碼調變)信號轉換為PWM(脈衝寬度調變)信 95456.doc 1257765 號i邏輯電路補償轉換器之輪出信號的線性。開關藉由邏 輯電路之輪出加以控制。藉由開關將濾波器之輸入側連接 至電源供應。 J而,上述傳統D類放大器中,緩衝器由兩個緩衝器構 成γ即加侧緩衝器及減側緩衝器。即使在無輸入信號時, X等兩個緩衝器輸出具有相反極性之信號,其負荷比為 50/〇。因此,傳統D類放大器中,即使在無輸入信號之情形 中,電流可穿過低通濾波器,其導致較大損失。 在曰本專利公開案第Sho_56-27001號中,說明在無輸入 信號時關閉輸出放大元件的技術理念,以便避免無輸入信 2時的功率損失。然而上述專利公開案丨所說明的傳統脈衝 見度调變放大器具有一問題,即需要變壓器來轉換阻抗並 切斷DC電壓,其會加大設備規模並增加其成本。另外,曰 本專利公開案第Sho-56-27001號所說明的傳統脈衝寬度調 變放大器具有另一問題,即由於比較器比較簡單三角波與 輸入信號,輸出信號之失真較大。 另一方面’日本專利揭示内容第2〇〇〇-5〇〇625號所說明之 數位放大電路使用三個值或四個值(切換狀態)的輸出狀 態,並放大數位輸入信號,而邏輯電路等數位電路用於改 進線性。因而,日本專利揭示内容第2〇〇〇_5〇〇625號所說明 之數位放大電路具有一問題,即由於此數位放大電路無法 藉由使用類比電路加以配置,故無法放大類比輸入信號同 時保持較佳線性。換言之,此傳統數位放大電路中,當輸 入較小信號脈衝時,由於對此較小信號脈衝新增補償脈 95456.doc 1257765 輯電路中之輸出切換失真得以補償。然而,用於補 4員輸出切換φ亩 、 、… 匕毛路僅藉由使用邏輯電路等數位電路 構成,因此傳統數位放大電路無法在較佳線性狀況 下放大類比輸入信號。 【發明内容】 χ月日在解決上述問題,因此將提供可在低失真及較 小功率損失下操作的D類放大器。 另二:本發明將提供可在低失真及較小功率損失下操 ,同Λ不器的D類放大器。 ^卜4¾明將提供能夠將其輸出内之此電壓成分減小 只貝上為零伏特的D類放大器。 =決上述問題,本發明之d類放大器具有下列結構。 ⑴-D類放大器,其包含: 積分器,其對類比輸入信號積分; : 車乂 ’其帛於比較該積分器之-輪出與-第 二角波; 味車乂為,其比較該積分器之該輸出盥一第二三 波,該第二三角浊笪— 一 一一 角波寺於猎由將該第-三角波之一相位偏 一角度(180度加_極 波形; ]角度,或一極小負角度)而獲得的 抑一《器,其根據該第—比較器之—輸出及該第二比 為之一輪出輸出—加側輸出信號及-減側輪出信號; 一回饋電路,复趑好丄,t ^ 之一羔田门钟、、°Λ °貝’輸出信號與該減側輸出信號 兴回饋至該積分器之-輸入側。 95456.doc 1257765 (2)依據(1)之D類放大器 一第一緩衝器,其計算該第一 比較裔之該輸出的一邏輯乘積, 號之一計算結果;以及 其中該緩衝器包括·· 比較器之該輸出舆該第二 以輸出作為該減側輪出信 木W,^t鼻該第—比較器之該輸出盘 比較器之該輸出的一邏輯乘積,以輸出作 側輸: 號之一計算結果。 例輪出k ⑺依據⑴之D類放大器’其中該回饋電路包括—差動放 大二其用於放大該加側輸出信號與該減側輸出信號間之一差兴。 (4)一D類放大器,其包含:一積分器,其對構成一類比輸入信號之 與一減側輸入信號間的一差異積分; 一延遲電路,其將一三角波之一相位延遲 度; 加側輸入信號 預定極小角 一合成電路 遲電路之一輸 一比較器, 比較; 出彼此合成,以輸出複數個輸出信號; 其將該合成電路之該等複數個輪出:論丨 綾衝杰,其輸入該比較器之一輸出;以及 -回饋電路,其將該緩衝器之一輸出回饋至 輸入側。 該積分器之 (5)依據(4)之D類放大器,其中: 該三角波由一第一三角波與一第二 二角波構成 該第二 95456.doc 1257765 三角波對應於藉由將該第-三角波之—相位偏移⑽ 一角度而產生的一波形; 又之 該延遲電路包括一第一延遲電路,其用於將該第— 波之該相位延遲該預定極小肖度,以及—第二延遲^角 其用於將該第三三角波之一相位延遲該預定極小角度 ' , 該合成電路合成該積分器之該減側輪出與該第:三 波以產生一弟一合成波;合成該積分哭 該第二三角波,以產生一第二人成波::綱輸出與 、、 厓王弟口成波,合成該積分器之誃 減側輸出與該第二延遲電路之一輸出,以產生一第三合成 波;以及合成該積分器之該加側輸出與該第一延遲電路: 一輸出,以產生一第四合成波; 私 該=較器包括比較器’其用於比較該第_合成波 與該第二合成波;以及一第二比較器,其用於比較該第三 合成波與該第四合成波; 該緩衝器包括—第—緩衝器,其用於計算該第-比較器 之-輸出與該第二比較器之—輸出的—邏輯乘積;以及— 第”衝器,其用於計算該第一比較器之該輸出與該第二 比較器之该輸出的一邏輯乘積;以及 該回讀電路包括一第一回饋電路,其用於將該第一緩衝 器之該輸出回饋至該積分n之該加側輸人;以及—第二回 饋屯路’其用於將该第二緩衝器之該輸出回饋至該積分器 之該減側輸入。 (6) — D類放大器,其包含: 一積分器,其對構成一類比輸入信號之一加側輸入信號 95456.doc -10- 1257765 與一減側輸入信號間的一差異積分; 一合成電路’其合成該積分器之一輸出與一三角波,並 合成該積分器之該輸出及具有與該首次提及三角波相反的 一相位之一三角波,以便輸出複數個信號,其中該相反相 位之三角波對應於一波形,其相位關於該首次提及三角波 之該相位偏移180度; 一比較器,其將該合成電路之輸出信號彼此比較; 一緩衝器,其將該比較器之一輸出輸入其中;以及 一回饋電路 其將該緩衝器之一輸出回饋至該積分器之 一輸入側;1257765 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a class D amplifier. [Prior Art] Class D amplification performs power amplification by pulse-width modulation (PWM), and is used to perform power amplification of the voice signal. As a conventional class D amplifier, one such class D amplifier is configured as an integrator for integrating an analog input signal, a comparator for comparing the output signal of the integrator with a predetermined triangular wave, and for amplifying the output of the comparator 5 tigers to output a pulse signal buffer (pulse amplifier). In this conventional D-maximum, the pulse signal output from the buffer is fed back to the input side of the integrator. Next, a low-pass filter constructed of coils and capacitors filters the output signal for the analog signal to obtain an analog signal such as a speaker. As a conventional pulse width modulation amplifier, one such PWM amplifier is configured to compare a comparator input signal with a triangular wave comparator, to amplify an amplifier that is more than a wheel, and to configure between the amplifier and the load. [(for example, 'Mcco Japanese Patent Publication No. Sho-56-27001). In addition, as a conventional digital amplifying circuit using a digital signal processing circuit, such a digital amplifying circuit is provided with a noise shaping device, a converter, a logic circuit, a switch, and a filter (for example, refer to Japanese Patent Publication No. No. 2 00_5〇〇 625). The noise shaper performs frequency shaping on the quantization of the digital input signal. The converter converts the PCM (Pulse Code Modulation) signal corresponding to the output of the noise shaper into a PWM (Pulse Width Modulation) signal. 95456.doc 1257765 i Logic circuit compensates for the linearity of the round-out signal of the converter. The switch is controlled by the rotation of the logic circuit. Connect the input side of the filter to the power supply with a switch. In the above conventional class D amplifier, the buffer is composed of two buffers, that is, a side buffer and a side buffer. Even when there is no input signal, the two buffer outputs, such as X, have signals of opposite polarity with a duty ratio of 50/〇. Therefore, in a conventional class D amplifier, even in the absence of an input signal, current can pass through the low pass filter, which results in a large loss. In the Japanese Patent Publication No. Sho_56-27001, the technical concept of turning off the output amplifying element when there is no input signal is explained in order to avoid power loss without input signal 2. However, the conventional pulse-sensing amplifier described in the above patent publication has a problem that a transformer is required to convert the impedance and cut off the DC voltage, which increases the scale of the device and increases its cost. In addition, the conventional pulse width modulation amplifier described in the Japanese Patent Publication No. Sho-56-27001 has another problem that the distortion of the output signal is large due to the relatively simple triangular wave and the input signal of the comparator. On the other hand, the digital amplifier circuit described in Japanese Patent Laid-Open Publication No. 2-5-625 uses an output state of three values or four values (switching state), and amplifies the digital input signal, and the logic circuit Equal-digit circuits are used to improve linearity. Therefore, the digital amplifying circuit described in Japanese Patent Laid-Open No. Hei. No. 255-625 has a problem in that the digital amplifying circuit cannot be configured by using an analog circuit, so that the analog input signal cannot be amplified while maintaining More linear. In other words, in this conventional digital amplifying circuit, when a smaller signal pulse is input, the output switching distortion in the circuit is compensated for by adding a compensation pulse to the smaller signal pulse. However, it is used to compensate the φ mu, ..., bristle path by only using a digital circuit such as a logic circuit, so the conventional digital amplifying circuit cannot amplify the analog input signal under a better linear condition. SUMMARY OF THE INVENTION The above problems are solved on the following day, and thus a class D amplifier that can operate with low distortion and low power loss will be provided. Another two: The present invention will provide a class D amplifier that can operate with low distortion and low power loss. ^ 卜 ⁄ 明 将 将 将 将 ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ 将 ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ = In view of the above problems, the class d amplifier of the present invention has the following structure. (1)-D-class amplifier, comprising: an integrator that integrates an analog input signal;: a rut that is compared to the integrator-round and - second angular wave; the taster is, which compares the integral The output of the device is a second three-wave, and the second triangular turbidity-one-one angle wave temple is hunted by the angle of one of the first-triangle waves by an angle (180 degrees plus _ pole waveform; ) angle, or a very small negative angle obtained by the device, which outputs the output according to the output of the first comparator and the second ratio - the side output signal and the minus side wheel output signal; a feedback circuit, The 输出 趑 , t ^ one of the lambda door clock, ° ° ° Bay 'output signal and the minus side output signal are fed back to the input side of the integrator. 95456.doc 1257765 (2) A first buffer of the class D amplifier according to (1), which calculates a logical product of the output of the first comparator, a result of one of the numbers; and wherein the buffer includes The output of the comparator, the second output, is the logical product of the output of the output-disk comparator of the first-comparator, and the output is for the side: One of the calculation results. The example rounds out k (7) according to the class D amplifier of (1) where the feedback circuit includes a differential amplifier which is used to amplify a difference between the added side output signal and the reduced side output signal. (4) A class D amplifier comprising: an integrator that forms a difference integral between an analog input signal and a subtraction side input signal; a delay circuit that delays a phase of one of the triangular waves; The side input signal is predetermined to be a very small angle, one of the synthesis circuit delay circuits is input to a comparator, and the comparison is performed; the synthesis is performed to output a plurality of output signals; and the plurality of output circuits of the synthesis circuit are rotated: It inputs an output of the comparator; and a feedback circuit that feeds one of the buffer outputs back to the input side. The integrator (5) is based on the class D amplifier of (4), wherein: the triangular wave is composed of a first triangular wave and a second binary wave. The second 95456.doc 1257765 triangular wave corresponds to the first triangular wave Phase shift (10) A waveform generated at an angle; further the delay circuit includes a first delay circuit for delaying the phase of the first wave by the predetermined minimum degree, and - a second delay ^ The angle is used to delay the phase of one of the third triangular waves by the predetermined minimum angle ', and the synthesizing circuit synthesizes the minus side wheel of the integrator and the third: wave to generate a synthesized wave; synthesizing the integral to cry a second triangular wave to generate a second person into a wave: a class output and a wave of the king's mouth, synthesizing the output of the integrator and reducing the output of one of the second delay circuits to generate a third Synthesizing the wave; and synthesizing the added side output of the integrator with the first delay circuit: an output to generate a fourth composite wave; privately = the comparator includes a comparator for comparing the first synthesized wave with The second composite wave; and one a comparator for comparing the third composite wave with the fourth composite wave; the buffer includes a first buffer for calculating an output of the first comparator and the second comparator a logical product of the output; and a first buffer for calculating a logical product of the output of the first comparator and the output of the second comparator; and the readback circuit includes a first feedback circuit And the second feedback loop is used to feed the output of the second buffer to the integrator. (6) - Class D amplifier, comprising: an integrator pairing one of an analog input signal with a side input signal 95456.doc -10- 1257765 and a subtraction side input signal a composite circuit that synthesizes one of the integrator outputs and a triangular wave, and synthesizes the output of the integrator and a triangular wave having a phase opposite to the first mentioned triangular wave to output a plurality of signals, wherein The opposite phase The triangular wave corresponds to a waveform whose phase is shifted by 180 degrees with respect to the phase of the first mentioned triangular wave; a comparator which compares the output signals of the combining circuit with each other; a buffer which outputs one of the outputs of the comparator Wherein; and a feedback circuit that outputs one of the buffers back to the input side of the integrator;
器,並配置成根據該等複數電阻器之 器之一輸入電容在對應於該合成電路 個信號間產生一相位差。 之该寺電阻值及該比較 路之該輸出的該等複數 (7)依據(6)之D類放大器,其中:And configured to generate a phase difference between the signals corresponding to the composite circuit based on one of the plurality of resistors. The resistance value of the temple and the complex number of the output of the comparison path (7) according to the class 6 amplifier of (6), wherein:
一減侧輸出與該三角波,以產 其用於合成該積分a minus side output and the triangular wave to produce the integral for synthesizing the integral
成波; 該第-合成部分包括一 一第一電阻器 ’其一端子與該積分 95456.doc 1257765 益之該減側輪出連接,以及一第 _ 波應用於其-個端子;以及將該第-電阻器= :: = = 接至該第-+ M 刀細于運 弟—电阻益之另一端子,以便構成其— 器::二合成部分包括-第三電阻器,其-端子與::分 /加側輸出連接,以及一第四電阻器,其中將該三角 〉應用:其-個端子;以及將該第三電阻器之另—端子連 接至:第四電阻器之另一端以便構成其一輸出端子; 哭乂弟二合成部分包括-第五電阻器’其-端子與該積分 ;之錢側輸出連接,以及—第六電阻器,其中將該相反 目三角波應用於其一個端子;以及將該第五電阻器之 子連接至該第六電阻器之另一端子,以便構成其一 輸出端子; 时該第四合成部分包括—第七電阻器,其_端子與該積分 -之肩加側輸出連接,以及一第八電阻器,其中將該三角 皮應用於其-個端子;以及將該第七電阻器之另一端子連 接至4人電阻器之另—端子’以便構成其—輸出端子; 該比較ϋ包括—第—比較器’其具有與該第—合成部分 ^亥輸出端子連接的—個輸人端子,以及與該第二合成部 分之該輪出端子連接的另—輸人端子;以及—第二比較 \其具有與㈣三合成部分之該輪出端子連接的一個輸 入如子’以及與該第四合成部分之該輸出端子連接的另一 輸入端子; 該緩衝器包括一第一緩衝器,其用於計算該第一比較器 之-輸出與該第二比較器之一輸出的—邏輯乘積;以及一 95456.doc -12 - 1257765 第二緩衝器,其用於計算該第 t卜座六哭夕兮认, 私為之該輸出與該第二 比車乂為之該輸出的一邏輯乘積; 該回饋電路包括-第-回饋電路,其用 器之該輸出回饋至該積分器之該加侧輸入;以二:: 饋電路,其用於將該第二緩衝器 少w"认 u該輸出回饋至該積分器 之違減側輸入;以及 5亥第一電阻器、該第二電阻器 ^省弟二電阻器及該第四 包阻态中任一項之一電 」%落弟五電阻器、該第六 電阻器、該第七電阻器及該第八電阻器中任一項之一電阻 值0 =)依據⑺之D類放大器,纟中該第_電阻器、該第二電 阻器、該第三電阻器及該第四電阻器中每個電阻器的該電 阻值係將該第五電阻器、該第山 益 茨弟Α私阻态、該第七電阻器及 該第八電阻器中每個電阻器的該電阻值乘以除〖以外之一 值而獲得的一電阻值。 (9) 一 D類放大器,其包含: 一積分器,其對構成一類比輸入信號之一加側輸入信號 與一減側輸入信號間的一差異積分; 一二角波產生電路,其包括一電流源及一電容; 一比較器,其比較該積分器之一輸出與該三角波產生電 路之一輸出; 一緩衝器’其輸入該比較器之一輸出;以及 一回饋電路,其將該緩衝器之一輸出回饋至該積分器之 一輸入侧。 95456.doc -13- I257765 (10) 依據(9)之D類放大器,其中 該電容之一末端與該比較器之輸入端子之一連接,以及 該電流源切換輸出電流之一方向,以便重複該電容之充 電及放電。 (11) 依據(10)之D類放大器,其中: 该黾流源之一末端與該電容之該一末端連接, 該電流源在該電容之一電位低於一第一電位時沿對該電 容充電之一方向流動電流,在該電容之該電位高於一第二 電位時沿對該電容放電之一方向流動電流,以及 · 該第二電位局於該第一電位。 (12) 依據(9)之D類放大器,其中: 該比較器包括一第一比較器,其用於比較該積分器之一 減側輸出與該三角波產生電路之該輸出,以及一第二比較 器,其用於比較該積分器之一加側輸出與該三角波產生電 路之該輸出, 該緩衝器包括一第一緩衝器,其用於計算該第一比較器 之-輸出的-反相值與該第二比較器之一輸出之一邏輯乘· 積;以及-第二緩衝器,其用於計算該第一比較器與該第 二比較器之一反相值的一邏輯乘積,以及 該回饋電路包括一第一回饋電路,其用於將該第一緩衝 °。之輸出回饋至该積分器之一減側輸入,以及一第二回 饋電路,其用於將該第二緩衝器之_輸出回镇至該積分器 之一加側輸入。 根據本發明,可提供能在低失真及較小功率損失下操作 95456.doc -14- 1257765 白勺d類放大器。 另外’本發明可提供能在低失真及較小功率損失下操 作,同時不使用變壓器之〇類放大器,並且其輸出内之 電壓成分可減小至實質為零伏特。 【實施方式】 現在參考圖式說明本發明之各種具體實施例模式。 具體實施例1 圖1為用於指示依據本發明之具體實施例丨 之結構範例的電路圖。 此D類放大器配置有電阻器R1、R2、R3、R4、、R6、 Μ、R8、R9、Rl〇、RU及R12,電容器以及^、運算放大 器11、比較器12及13、延遲電路21及22、編電路(低活動) 3!及另-AND電路32。此圖式中將預定三角波信號「a」及 「b」分別應用於電阻器R9&RU之一端子。三角波信號「a」 及二角波信號「b」為具有相同波形之此類信號,其相位彼 此相差180度。 電阻器R1及R2之-端子分別構成类員比輸入信號之差動 輸入端子。因此’電㈣R1之-料構成加騎入端子 (+IN)’電阻器R2之-端子構成減側輪人端子(_iN)。運 大為11及電容為C1及C2構成積分器。此積 不貝刀态對電阻器R1 及R2已用差動方式輸入的類比輸入信 现知分,將積分作 輸出至電阻器R5、R6、R7及R8。 °儿 電阻器 R5、R6、R7、R8、R9、Rl〇、ρ 7 Ώ R11及R12構成人忠 笔路’其合成二角波^號「a’」或「b,血 」共此積分器之輸出 95456.doc -15- 1257765 信號。藉由將三角波信?虎ra」及三角波信號「b」延 極小角度「Θ」(即θ<<180度)而產生三角波信號、,」」及「b,一 此合成電路產生第一至第四共四種合成波形「㊁「」° 「g」、「h」。 」、f」、 藉由合成構成積分器的運算放大器u之減側輸 二角波信號「a」(第一三角波)而產生第一合成波「e」二 由合成構成積分器的運算放大器η之加側輸出信號:」三: 波佗唬b」(第二三角波)而產生第二合成波「f」。藉由八 成構成積分器的運算放大器n之減侧輸出信號與三角波= f b」。而產生第三合成波「g」。藉由合成構成積分器的運 算放大器11之加側輸出信號與藉由延遲三角波信號「叼所 產生之二角波信號ra’」而產生第四合成波「匕」。 比較器12(第一比較器)比較第一合成波「〜與第二合成 波「f」,以輸出一比較結果。當第一合成波「e」大於第二 合成波「f」日夺,第一比較器12輸出預定「低」位準信號(例 士令位準)’而當第一合成波「e」小於第二合成波「f」 時,第一比較器12輸出預定「高」位準信號。比較器13(第 -比較器)比較第三合成波「g」與第四合成波「h」,以輸 :一比較結果。當第三合成纟「g」大於第四合成波「h」 日^第一比較器1 3輸出預定「低」位準信號(例如,零位準), 而§第二合成波r g」小於第四合成波「h」時,第二比較 為13輪出預定「高」位準信號。比較器12及13亦可藉由使 用運算放大器加以實現。 AND電路3 1對應於具有負邏輯輸入之AND閘控功能的緩 95456.doc 1257765 衝器電路。接著,娜電路31執行—侧計算(低活動), ^中當第—比較器12之輸出及第二比較器13之輸出為「低」 時,此AND電路31於Φ 「古 _ 包塔31輸ώ同」位準信號,並輸出作為此d 類放^器之減側輪出「撕」的此計算結果。電阻器们構 成一第—回饋電路。第—回镇電路將用作緩衝器之AND電 路31的輸出回饋至運算放大器^之加側輸入。 and電路32對應於具有AND計算功能之緩衝器電路,並 執行比較S12之輸出與比較^ 13之輸出間的ΑΝβ計算摔 作’然後將計算結果輸出為Μ類放Α||之加側輸出 +OUT」。電阻器R4構成一第二回饋電路。第二回饋電路 將用作緩衝态之AND電路32的輸出回饋至運算放大器丨丨之 減侧輸入。 「經由此D類放大器之加側輸出「+〇υτ」與其減側輸出 「-OUT」間的低通濾波器連接負載(揚聲器等)。由於使用 該等電路配置,此D類放大器可在低失真下放大類比輸入信 號「+IN」及「-INj,而不使用變壓器,另外可驅動負載, 同時減小功率損失。 接下來,茶考圖2至圖4說明依據此具體實施例丨而使用上 述配置的D類放大器之操作的範例。圖2至圖4為用於表示圖 1所示之D類放大器的個別電路部分之操作的波形圖。接 著,圖2頒示當類比輸入信號「+IN」之值等於類比輪入信 號「-IN」之值時,即當差動輸入變為零伏特值時(無輪入 信號)’ D類放大器之個別電路部分的波形。圖3代表當(類 比輸入信號「+IN」)>(類比輸入信號「_IN」),即當差動輸 95456.doc -17- 1257765 :變為正時,D類放大器之個別電路部分的波形 虽(類比輸人信號「+IN」)<(類比輸人信號「為 二 差動輸入變為負時,_放大器之個別電路部分的波开/當 首先,將說明關於圖2之操作,即無差動輸入之情十 伏特值輸入)。三角波作择「 (令 肖皮“虎"」之相位與三角波信號「b 之相位相差1 8 0度。二自、、由# %「 」 #「 —角波仏號a」構成藉由將三角浊# 號 a」延遲極小角度「㊀而吝;ψ AA ° f卢「,嫌士一 」產生的此一信號。三角波信 …」構成猎由將三角波信號「a」延遲極小角度「㊀ f生:此一信號。此情形中,亦可將稱為「顫化」之預定 布隹汛分別應用於二角法 、 訊應用…一 a、b及b’。由於將此顫化雜 三角波信號a、a,、Wb,外,…皮之失真。除該等 等。 亦可使用鋸齒波形、積分波形 哭^波信號「〜〜」以及積分器之加側輸出(運算放大 :之加側輪出)「d」間的相位關係實質上彼此相等。: 角波信號「b」、「M以这拄八抑、、 一 」及矛貝刀裔之減側輸出(運算放大界i J 之減側輸出)「c „ α , _ 口 J」間的相位關係實質上彼此相等。 二Hi2。及13之輸入,即第一至第四合成波e、f、g及h :’、貝分益之輪出合成的波形。因此’第一合成波「 之相位與第二人 」 、、 —口戚波f」之相位相差大約180度。第三合 ^皮之相位與“合成波「h」之相位相差大約180 度。第一合成浊r 上 ^ ^ e」之波形實質上等於第四合成波「h」 之波形,該望哲 ,寺弟—及第四合成波「〇」及「h」之相位彼此 相呈極小角声「β ^ 又 」。弟二合成波「f」之波形實質上等於第 95456.doc -18 - 1257765 三合成波「g」之波形,該等第二及第三合成波「f」及「 之相位彼此相差極小角度「Q 。 比較器12之輸出「j」在(第一合成波「e」)>(第二合成波 「W時變為「低」,在(第一合成波「e」)<(第二合成 時變為「高」。比較器13之輸出「k」在(第三合成波「g」)>(第 四合成波「h」)時變為「低 合成波「h」)時變為「古。/ g」)<(第四 「 」)才义為回」。當比較器之輸出「乜及 1為「低」時,AND電路31之輸出(-0UT)變為「言。 當比較器12及13之輸出「j」及「 古 °」 路32之輸出(+OUT)變為「高」。〜同」日守,娜電 換言之,此D類放大器内之加侧輪出 週期過程中變為高位準,該時 守間 「〜與第二合成波「f」之門^ 合成波 」之間的父又點(時刻「t -成波「g」與第四合成波「 弟二 「〜)。此_放大器内之減側輪出間厂的交又點(時刻 期過程中變為含仂i β 出-〇UT」在一時間週 與第二合成波「f」之間的山7 我為攸弟一合成波「e」 、由「 父又點(時刻「t3丨)至第二A杰 波g」與第四合成波、 」)至弟一口成 此情形中,加側輸出「+0UT ;:又點(時刻A)。 為高位準的此-時間週期可取決;;=側輸出「观丁厂變 波信號b、b,間的相位差(_^ ^ /皮Μ”3'與三角 電路21及22内之延遲時 又θ」)。因此,由於延遲 角波信號a、a,:-:充分縮短至所需值,以便降低三 A),力-輪出= I, 」厂側輪出「-OUT」變為高位 95456.d〇< -19- 1257765 準的時間週期可充分縮短至所需值。此時,積分器之減側 輪出「C」及加側輪出「d」皆變為極低電壓。 換5之’在無輸入信號(即,將應用於下述情形之零伏特 值)之情形中,加側輸出+OUT及減側輸出-OUT内之高位準 、β / 了 °又疋為〇至數個%的負何比。例如,經由低通濾波器 將加側輸出「+ου丁」及減側輸出「_ουτ」供應至負載, 例如揚耸為。因此,在無輸入信號之情形中,由於加側輸 出+OUT及減側輸出-〇υτ内之高位準週期為〇至數個%的負 何比’穿過低通濾波器及負載之電流變為極小值。因而, 在此具體實施例之D類放大器用於小信號之此一情形中,可 省略配置於輸出端子與負載間之上述低通濾波器(LC濾波 器等)。 使用上述配置時,根據具體實施例1之]〇類放大器,在無 頒比輸入信號的此一情形中(即零伏特值輸入之情形),由於 將輸出信號變為高位準之時間週期充分縮短至所需值,與 先前技術D類放大器相比,可大大減小功率損失。 接下來,說明(類比輸入信號「+IN」)>(類比輸入信號「_IN」) 1*月幵y中即當其差動輸入如圖3所示變為正時,此D類放 。-之作。應注意二角波信號a、a,、b、b,與圖2所示之 h形中的二角波信號相同。三角波信號a、a,、b、b,與積分 輸出C d(即運异放大器1 1之輸出)間的相位關係與圖2 所表不之情形中的關係相同。圖3中,第—至第四合成波e、 f_、g、h具有與積分器之輪出合成的此類波形。因此,第一 合成波「6」之相位與第二合成纟「f」之相位相差大約180 95456.doc 1257765 〈相位與第四合錢「h」之相位 度’而第三合成波「各 相差大約180度。 圖3中,相同時間的積分器之 w日,认bJ輸出c」與積分器之 加側輸出d」間的差異大於如圖2所示之情形的差異。因 而,第-合成波「e」與第四合成波%」間之相位差,以 合成波I與第三合成波、」間之另-相位差大 ^圖2所示之情形的相位差。因此,定義為從第-合成波 e」士與弟二合成波「f」之間的交又點(時刻U,)至另一交叉 (以口 )之蚪間週期長於圖2之情形中的時間週期(從時 刻U至時刻⑺,加側輸出「+〇u 丁」變為高位準之時間 長於圖2所示之情形的時間週期。圖3中,定義為從時和, 後的第三合成波「g」與第四合 反h」之間的父又點(時 Jt3)至弟-合成波「e」與第二合成波%之間的另一交 叉點(時刻…之此一時間週期長於圖仏情形的時間週 =加側輸出「+〇UT」變為高位準,隨後重複實施該等操 比較器12之輸出「』·」從第一合成波、」與第二合成波 二」之間的交又點(時刻tr)至下-第-合成波「ej與下— 弟一合成波「f」之間的交叉點(時刻t4,)變為「高」。接下來, 1 匕較:12之輪出「j」從時卿,至下一第一合成波「e」與 ,一 σ成波「fj之間的另一交又點(時刻t5,)變為「低」,隨 佼重複M施上述操作。換言之,比較器12之輪出「 % 一合成波厂p ^ 與弟二合成波「f」之間的每個交叉點將 /、狀恶k「咼」改變至「低」或從「低」改變至「高」。 95456.doc -21 - 1257765 仁匕罕父為I3之輸出「k」從第三合成波「g」與第四合成波 「h」之間的交叉點(時刻t2,)至下一第三合成破「g」與下 /第四合成波「h」之間的交叉點(時刻t3,)變為「低」。接 下來,比較器13之輸出「k」從時刻t3 ’至下一第三合成波「g」 與第四合成波「h」之間的另一交叉點(時刻t6,)變為「高」, 隨後,重複實施上述操作。換言之,比較器13之輸出「k」 在第二合成波「g」與第四合成波r h」之間的每個交叉點 將其狀態從「高」?文變至「低」或從「低」改變至「高」。 接著,由於加側輸出r+〇UT」=(輸出j)AND(輸出「k」), 此加侧輸出「+0UT」在從時刻丨丨,至時刻⑵之時間週期、從 時刻t3’至時刻t4,之時間週期以及從時刻t5,至時刻…之時 間週期中變為「高」位準。因此,加側輸出「+〇υτ」變為 同位準之日守間週期的負荷比實質上與類比 集:的大小成正比。換言之,加側輸出「+== 成此^5虎,其係藉由以脈衝寬度調變(ρ 比輸入信號内之正值(差動值)而獲得。 周㈣ :-方面,減側輸出「撕」連續變為低位準 於畜如圖3所示(類比輸入信號「+ΐΝ '、 「-IN」)時,不;、匕輪入信號 不存在比較器12及13之輸出 為低的時間週期。 k」皆變 接下來’說明(類比輸入信號「+ 「-IN」)之情形中,即當其差動輸入如圖怖卞^入信號 此D類放大器之操作。應注意三角波信號^為負時’ 所示之情形中的二角喻n 、^1)’與圖2 角波蝴目同。三角波信 d Λ η x Kf 95456.doc -22- 1257765 \ 之輪出c、d(即運算放大器11之輸出)間的相位 «與圖2所表示之情形中的關係相同。 &月白在圖4所不之情形中,與圖2及圖3之上述情形相 ^私刀、如之輸出「c」及「d」的相位反轉(即偏移180度)。 2 a成波與第二合成波「f」間之交叉點以及第三 口成波g」與第四合成波「h」間之交叉點的時間關係與 圖3所示之情形相反。 比較器12之輪出r ;锋 * L ^ r u ^ 别出J」攸弟一合成波「e」與第二合成波 「\」之間的交又點(時刻t2")至下一第一合成波「e」與下 第一合成波「f」之間的交叉點(時刻t3,,)變為「高」。接 下來,比較裔12之輸出「|」從時刻t3M至下一第一合成波「e」 與第一合成波「f」之間的另一交叉點(時刻丨6,,)變為「低」, k後,重複實施上述操作。換言之,比較器12之輸出「』」 在第一合成波「e」與第二合成波「f」之間的每個交叉點 將其狀態從「高」改變至「低」或從「低」改變至「高」。 比較器13之輸出「k」從第三合成波「g」與第四合成波 「h」之間的交又點(時刻tl”)至下一第三合成波「g」與下 一第四合成波「h」之間的交叉點(時刻t4”)變為「低」。接 下來’比較器13之輸出r k」從時刻t4”至下一第三合成波 「g」與第四合成波「h」之間的另一交叉點(時刻t5 ’’)變為 「高」’隨後’重複實施上述操作。換言之,比較器13之輸 出「k」在第二合成波「g」與第四合成波「h」之間的每個 父叉點將其狀悲攸「南」改變至「低」或從「低」改變至 「高」。 95456.doc -23- !257765 接著’由於加側輸出「+ουτ」=(輸出胸D(輸出k),此 :側輸出「+〇UT」連續變為低位準。當(輸出州輸出幻 ,、问變為「低」時’減側輸出「顿」變為「高」,減側 輸出「-OUT」變為高位準之時間週期的負荷比實質上與類 :輪入信號之負值(差動值)大小成正比。換言之:減側輸: .T」可構成此一㈣,其係藉由以脈衝寬度調變(ρ·) 方式調變類比輸入信號之負值(差動值)而獲得。 。因而,根據具體實施例丨之!)類放大器,可將類比輸入信 號轉換為具有三個值(由零伏特值、正值及負值構成)之 P WM& 5虎’然後可將該等轉換得到的p WM信號輪出。根據 具體實施例1之D類放大器,在類比輸入信號值高於或等於 預定值的情形中,其輸出信號變為如圖3及圖4代表之加侧 輸出「+OUT」及減側輪出「_0UT」之任一項的僅一側信 旒之此一切換波形。因而,依據具體實施例丨之D類放大器, 其切換損失大約可為在加側及減側切換之傳統〇類放大哭 的切換損失之一半。 根據具體實施例1之D類放大器,由於藉由使用電阻器们 及R4實現類比回饋,D類放大器可在較佳線性狀況下放大 類比輸入信號,而不實施上述專利公開案2中說明的此一數 位處理操作。根據具體實施例1之D類放大器,與上述專利 公開案1中說明的放大器不同,不再需要用於阻抗轉換及用 以切斷DC電壓之變壓器,可提供具有低功率損失及低失直 之此一D類放大器,其DC輸出成分幾乎等於零伏特。 具體實施例2 95456.doc -24- 1257765 接下來’將參考圖5說明本發明之具體實施例2。圖5為用 於指不依據本發明之具體實施例2的D類放大器之結構範例 的電路圖。此D類放大器配置有電阻器R51、R52、R53、R54、 R5 5及R56、電谷器C5 1、運算放大器6 1及64、比較器62及 63、AND電路(低活動)71及另一 AND電路72。將三角波信 唬「a」應用於比較器62之加側輸入端子,將另一三角波信 號「b’」應用於比較器63之加側輸入端子。Forming the wave; the first-compositing portion includes a first resistor's one terminal and the integral 95456.doc 1257765 benefiting the minus side wheel connection, and a first wave applied to its terminal; The first-resistor = :: = = is connected to the first - + M knife to the other terminal of the resistor-resistance, so as to constitute its device:: the two-composite part includes - the third resistor, its - terminal and :: a split/plus side output connection, and a fourth resistor, wherein the triangle is applied: its one terminal; and the other terminal of the third resistor is connected to: the other end of the fourth resistor Forming an output terminal thereof; the crying brother two synthesizing portion includes a fifth resistor 'the terminal thereof and the integral; the money side output connection, and a sixth resistor, wherein the opposite eye triangle wave is applied to one of the terminals And connecting the child of the fifth resistor to the other terminal of the sixth resistor to form an output terminal thereof; the fourth composite portion includes a seventh resistor, a terminal of the _ terminal and the integral Add a side output connection, and an eighth resistor, Applying the triangular skin to its one terminal; and connecting the other terminal of the seventh resistor to the other terminal of the 4-person resistor to constitute its output terminal; the comparison includes the -first comparator 'It has an input terminal connected to the first synthesis portion, and an additional input terminal connected to the wheel terminal of the second synthesis portion; and - a second comparison\ (d) an input of the three-synthesis portion of the wheel terminal connection, such as a sub-' and another input terminal connected to the output terminal of the fourth synthesis portion; the buffer includes a first buffer for calculating the a comparator-output and a logical product outputted by one of the second comparators; and a 95456.doc -12 - 1257765 second buffer for calculating the t-seat And the output is a logical product of the output of the second ratio ;; the feedback circuit includes a -th feedback circuit, the output of the device is fed back to the plus side input of the integrator; : a feed circuit for The second buffer is less w" recognizes that the output is fed back to the off-side input of the integrator; and the 5 Hz first resistor, the second resistor, the second resistor, and the fourth package One of the "electrical" % 弟 五 five resistors, the sixth resistor, the seventh resistor, and one of the eighth resistors has a resistance value of 0 =) according to the class D amplifier of (7), The resistance value of each of the _ resistor, the second resistor, the third resistor, and the fourth resistor is the fifth resistor, and the second resistor And the resistance value of each of the seventh resistor and the eighth resistor is multiplied by a resistance value obtained by dividing one value. (9) A class D amplifier comprising: an integrator that forms a difference integral between one of the analog input signals and a side input signal and a subtraction side input signal; a two-dimensional wave generating circuit including one a current source and a capacitor; a comparator that compares one of the output of the integrator with an output of the triangular wave generating circuit; a buffer 'which inputs an output of the comparator; and a feedback circuit that buffers the buffer One of the outputs is fed back to one of the input sides of the integrator. 95456.doc -13- I257765 (10) The class D amplifier of (9), wherein one end of the capacitor is connected to one of the input terminals of the comparator, and the current source switches one direction of the output current to repeat the Charging and discharging of capacitors. (11) The class D amplifier according to (10), wherein: one end of the turbulent current source is connected to the one end of the capacitor, and the current source is along the capacitor when a potential of the capacitor is lower than a first potential A current flows in one direction of charging, a current flows in one direction of discharging the capacitor when the potential of the capacitor is higher than a second potential, and the second potential is at the first potential. (12) The class D amplifier of (9), wherein: the comparator includes a first comparator for comparing one of the inverting outputs of the integrator with the output of the triangular wave generating circuit, and a second comparison And comparing the output of one of the integrators to the output of the triangular wave generating circuit, the buffer comprising a first buffer for calculating an -inverted value of the output of the first comparator And a logical multiplication product of one of the outputs of the second comparator; and a second buffer for calculating a logical product of an inverted value of one of the first comparator and the second comparator, and the The feedback circuit includes a first feedback circuit for buffering the first buffer. The output is fed back to one of the inverting inputs of the integrator, and a second feedback circuit for outputting the output of the second buffer back to one of the integrators plus the side input. According to the present invention, it is possible to provide a class D amplifier capable of operating at low distortion and with low power loss, 95456.doc -14 - 1257765. In addition, the present invention can provide a 〇-type amplifier that can operate with low distortion and low power loss without using a transformer, and the voltage component in its output can be reduced to substantially zero volts. [Embodiment] Various specific embodiment modes of the present invention will now be described with reference to the drawings. DETAILED DESCRIPTION OF THE INVENTION Fig. 1 is a circuit diagram for showing an example of the structure of a specific embodiment according to the present invention. The class D amplifier is provided with resistors R1, R2, R3, R4, R6, Μ, R8, R9, R1 〇, RU and R12, a capacitor and an operational amplifier 11, comparators 12 and 13, a delay circuit 21 and 22. Edit the circuit (low activity) 3! and the other-AND circuit 32. In this figure, the predetermined triangular wave signals "a" and "b" are respectively applied to one of the terminals of the resistor R9 & RU. The triangular wave signal "a" and the two-corner signal "b" are such signals having the same waveform, and their phases are different by 180 degrees from each other. The terminals of the resistors R1 and R2 respectively constitute a differential input terminal of the class member than the input signal. Therefore, the electric (four) R1 material constitutes the terminal (+IN) of the resistor R2, and the terminal constitutes the side wheel terminal (_iN). The large 11 and the capacitors C1 and C2 form an integrator. This product is divided into analog input signals for which the resistors R1 and R2 have been differentially input, and the integral is output to the resistors R5, R6, R7 and R8. °Rener resistors R5, R6, R7, R8, R9, Rl〇, ρ 7 Ώ R11 and R12 form the integrator of the human loyalty road 'the synthetic two-dimensional wave ^ number "a'" or "b, blood" The output is 95456.doc -15- 1257765 signal. A triangular wave signal, "" and "b" are generated by extending the triangular wave letter "hu" and the triangular wave signal "b" by a small angle "Θ" (ie, θ << 180 degrees), and the synthesis circuit generates the first to The fourth total of four synthetic waveforms "two" ° "g", "h". ", f", by synthesizing the subtraction side binary wave signal "a" (first triangular wave) of the operational amplifier u constituting the integrator to generate the first composite wave "e" and synthesizing the operational amplifier η which constitutes the integrator The side combined output signal: "three: wave b" (second triangle wave) produces a second composite wave "f". The reduced side output signal of the operational amplifier n which constitutes the integrator is 80% and the triangular wave = f b". The third synthesized wave "g" is generated. The fourth synthesized wave "匕" is generated by synthesizing the added side output signal of the operational amplifier 11 constituting the integrator and by delaying the triangular wave signal "the generated binary wave signal ra'". The comparator 12 (first comparator) compares the first synthesized wave "~ with the second synthesized wave "f" to output a comparison result. When the first synthesized wave "e" is greater than the second synthesized wave "f", the first comparator 12 outputs a predetermined "low" level signal (the regular level) and when the first synthesized wave "e" is smaller than When the second synthesized wave "f", the first comparator 12 outputs a predetermined "high" level signal. The comparator 13 (the first comparator) compares the third synthesized wave "g" with the fourth synthesized wave "h" to input a comparison result. When the third synthesized 纟 "g" is greater than the fourth synthesized wave "h", the first comparator 13 outputs a predetermined "low" level signal (for example, a zero level), and the § second synthesized wave rg" is smaller than the first When the four synthetic waves "h", the second comparison is 13 rounds of a predetermined "high" level signal. Comparators 12 and 13 can also be implemented by using an operational amplifier. The AND circuit 3 1 corresponds to a buffer 95456.doc 1257765 buffer circuit having an AND gate function of a negative logic input. Next, the circuit 31 performs a side calculation (low activity), and when the output of the first comparator 12 and the output of the second comparator 13 are "low", the AND circuit 31 is at Φ "古_包塔31" The same level signal is output, and the result of this calculation is output as the tearing of the side of the d-type device. The resistors form a first-feedback circuit. The first-return circuit feeds the output of the AND circuit 31, which serves as a buffer, to the add-side input of the operational amplifier. And circuit 32 corresponds to a buffer circuit having an AND calculation function, and performs ΑΝβ calculation between the output of the comparison S12 and the output of the comparison ^13, and then outputs the calculation result as the side output of the Α class Α|| OUT". Resistor R4 forms a second feedback circuit. The second feedback circuit feeds the output of the AND circuit 32, which serves as a buffer state, to the subtraction side input of the operational amplifier 丨丨. "Connect the load (speaker, etc.) via the low-pass filter between the + side 输出τ of the class D amplifier and the minus side output "-OUT". Due to the use of these circuit configurations, this Class D amplifier can amplify the analog input signals "+IN" and "-INj with low distortion without using a transformer, and can also drive the load while reducing power loss. Next, the tea test 2 to 4 illustrate an example of the operation of the class D amplifier using the above configuration in accordance with this embodiment. Fig. 2 to Fig. 4 are waveforms for explaining the operation of the individual circuit portions of the class D amplifier shown in Fig. 1. Figure 2. Next, when the value of the analog input signal "+IN" is equal to the value of the analog rounding signal "-IN", that is, when the differential input becomes zero volts (no rounding signal) 'D The waveform of the individual circuit part of the class amplifier. Figure 3 represents the individual circuit part of the class D amplifier when (analog input signal "+IN") > (analog input signal "_IN"), that is, when the differential input 95456.doc -17 - 1257765 becomes positive Although the waveform (analog input signal "+IN") < (the analog input signal "is two differential input becomes negative, the wave of the individual circuit part of the _ amplifier / when first, will explain the operation of Figure 2 , that is, no differential input, 10 volts input). Triangle wave selection "(The phase of the "Tiger"" and the triangle signal "b phase difference of 180 degrees. Two since, by # %" #"—Angle wave 仏 a" constitutes a signal generated by delaying the triangle ## a" by a very small angle "ψ一ψ;ψAA ° f卢", suspected one". Triangle wave letter..." Hunting delays the triangular wave signal "a" by a very small angle "one f: this signal. In this case, a predetermined cloth called "fibrillation" can also be applied to the two-corner method, the application of the signal... , b and b'. Because of this, the distortion of the triangular wave signal a, a, Wb, ..., the skin distortion. It is also possible to use the sawtooth waveform, the integrated waveform crying wave signal "~~", and the integrator output side (operational amplification: plus side wheeling). The phase relationship between "d" is substantially equal to each other. The phase relationship between the signal "b", "M with this 拄 抑 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The two inputs are equal to each other. The inputs of Hi2 and 13 are the first to fourth synthetic waves e, f, g, and h: ', and the waveforms of the rounds of the Bianyi are synthesized. Therefore, the phase of the 'first synthesized wave' The phase difference between the second person and the mouth f f f is about 180 degrees. The phase of the third combination is about 180 degrees from the phase of the synthetic wave "h". The first synthetic turbidity r is ^ ^ e" The waveform is substantially equal to the waveform of the fourth synthetic wave "h", and the phases of the Wangzhe, Sidi- and the fourth synthetic wave "〇" and "h" are very small and angular "β ^ again". The waveform of the synthesized wave "f" is substantially equal to the waveform of the three composite waves "g" of the 95456.doc -18 - 1257765, the second and third The phases of the synthesized waves "f" and "the phase are different from each other by a small angle "Q. The output "j" of the comparator 12 is (first synthesized wave "e")> (the second synthesized wave "W" becomes "low". In the (first synthesized wave "e") < (the second synthesis becomes "high". The output "k" of the comparator 13 is (the third synthesized wave "g") > (the fourth synthesized wave "h" ") becomes "his. / g" when it becomes "low composite wave "h") < (fourth "") is called "back". When the output of the comparator is "乜 and 1 is "low" At the time, the output (-0UT) of the AND circuit 31 becomes "words." When the outputs "j" of the comparators 12 and 13 and the output (+OUT) of the "古°" path 32 become "high". ~同同日守,娜电 In other words, the class side of the class D amplifier becomes a high level during the side-rounding cycle, when the keeper "~ and the second synthetic wave "f" gate ^synthesis wave" The father is again (the time "t - wave "g" and the fourth composite wave " brother 2" ~). This _ amplifier in the side of the reduction wheel out of the factory point (the time period becomes 仂i β 出 -〇 UT" Mountain between the time of the week and the second synthetic wave "f". I am a composite wave "e" for the younger brother, and "the father is again (time "t3丨") to the second A "Jebo g" and the fourth synthetic wave, ") to the younger brother into this case, add side output "+0UT;: point (time A). This high-level this time period can be determined;; = side output "The phase difference between the buckling signals b and b, and the delay between the triangle circuits 21 and 22 and θ"). Therefore, since the delayed angular wave signals a, a, :-: are sufficiently shortened to the required value to reduce the three A), the force-rounding = I, "the factory side turns "-OUT" to the high position 95456.d〇 < -19- 1257765 The time period can be shortened to the required value. At this time, the "C" on the minus side of the integrator and the "d" on the side of the adder become extremely low voltage. In the case of 5's without input signal (ie, it will be applied to the zero volt value of the following case), the high level in the plus side output +OUT and the minus side output -OUT, β / ° is again 〇 To a few percent of the negative ratio. For example, the plus side output "+ου丁" and the minus side output "_ουτ" are supplied to the load via a low-pass filter, for example, as a rising tower. Therefore, in the case of no input signal, the high level period in the plus side output +OUT and the minus side output - 〇υτ is 〇 to several % of the negative ratio than the current passing through the low pass filter and the load It is a minimum value. Therefore, in the case where the class D amplifier of this embodiment is used for a small signal, the above-described low pass filter (LC filter or the like) disposed between the output terminal and the load can be omitted. When the above configuration is used, according to the 〇-type amplifier of the specific embodiment 1, in the case of the unsigned input signal (that is, the case of zero volt input), the time period due to the high level of the output signal is sufficiently shortened. To the desired value, the power loss can be greatly reduced compared to prior art Class D amplifiers. Next, the description (analog input signal "+IN")> (analog input signal "_IN") 1* month 幵 y, that is, when the differential input becomes positive as shown in Fig. 3, this D class is placed. - The work. It should be noted that the two-dimensional wave signals a, a, b, b are the same as the two-wave signals in the h-shape shown in FIG. The phase relationship between the triangular wave signals a, a, b, b and the integrated output Cd (i.e., the output of the operational amplifier 1 1) is the same as that in the case shown in Fig. 2. In Fig. 3, the first to fourth synthesized waves e, f_, g, h have such waveforms synthesized with the rounds of the integrator. Therefore, the phase of the first synthesized wave "6" differs from the phase of the second synthesized 纟 "f" by about 180 95456.doc 1257765 <the phase degree of the phase and the fourth bond "h" and the third synthesized wave "the phase difference" About 180 degrees. In Fig. 3, the difference between the bJ output c" and the adder side output d" of the integrator is greater than the difference shown in Fig. 2 on the w day of the integrator at the same time. Therefore, the phase difference between the first synthesized wave "e" and the fourth synthesized wave %" is such that the phase difference between the synthesized wave I and the third synthesized wave and the other phase difference is larger than that shown in Fig. 2. Therefore, it is defined as the period between the intersection of the first-composite wave e" and the second synthetic wave "f" (time U,) to the other intersection (by the mouth) is longer than in the case of FIG. The time period (from time U to time (7), the time when the side output "+〇u 丁" becomes the high level is longer than the time period shown in Fig. 2. In Fig. 3, it is defined as the slave time and the third time. The other point between the parent point (time Jt3) and the brother-synthesis wave "e" between the synthesized wave "g" and the fourth combined inverse h" and the second synthetic wave % (this time of time... The period of time longer than the period of the graph = = the side output "+〇UT" becomes the high level, and then the output of the comparator 12 is repeatedly executed ""·" from the first synthesized wave," and the second synthesized wave The intersection between the intersection point (time tr) and the lower-first-composite wave "ej" and the lower-different wave "f" (time t4,) becomes "high". Next, 1匕 :: 12 rounds out "j" from Shiqing, to the next first synthetic wave "e" and, σ into wave "fj between another point (time t5,) becomes "low" With weight M applies the above operation. In other words, each intersection between the "% one synthetic wave factory p^ and the second synthetic wave "f" of the comparator 12 turns "/" to "low" or Change from "low" to "high". 95456.doc -21 - 1257765 The equivalent of the output "k" of I3 from the intersection of the third composite wave "g" and the fourth composite wave "h" The intersection (time t3) between the time t2, and the next third synthetic broken "g" and the lower/fourth synthesized wave "h" becomes "low". Next, the output of the comparator 13 is "k". The other intersection (time t6) from the time t3' to the next third synthesized wave "g" and the fourth synthesized wave "h" becomes "high", and then the above operation is repeated. In other words, The output "k" of the comparator 13 changes its state from "high" to "low" or from "low" to each intersection between the second synthesized wave "g" and the fourth synthesized wave rh" "High." Then, since the side output r + 〇 UT" = (output j) AND (output "k"), the side output "+0UT" is from the time 丨丨 to the time (2). The inter-period, the time period from time t3' to time t4, and the time period from time t5 to time ... become "high" level. Therefore, the side output "+〇υτ" becomes the same level. The duty ratio of the custodial period is substantially proportional to the size of the analog set: in other words, the side output "+== becomes this ^5 tiger, which is modulated by the pulse width (ρ is positive than the input signal) (Differential value) is obtained. Week (4): - Aspect, the minus side output "Tear" continuously becomes lower in the position as shown in Figure 3 (analog input signals "+ΐΝ ', "-IN"), no; The 匕 wheeling signal does not have the output of the comparators 12 and 13 for a low period of time. k" is changed Next. In the case of the analog input signal "+ "-IN"), that is, when the differential input is as shown in the figure, the operation of the class D amplifier. It should be noted that the dimorphism n, ^1)' in the case where the triangular wave signal ^ is negative is the same as the angular wave of Fig. 2. The triangular wave letter d Λ η x Kf 95456.doc -22- 1257765 \ The phase « between the c and d (ie, the output of the operational amplifier 11) is the same as the relationship in the case shown in FIG. 2. In the case of Figure 4 and Figure 3, the phase of the output of "c" and "d" is reversed (i.e., offset by 180 degrees). The time relationship between the intersection of the 2 a wave and the second composite wave "f" and the intersection between the third wave forming g" and the fourth composite wave "h" is opposite to that shown in Fig. 3. Comparator 12's turn r; front * L ^ ru ^ Don't make J's brother's intersection between the synthetic wave "e" and the second synthetic wave "\" (time t2") to the next first The intersection (time t3,) between the synthesized wave "e" and the next first synthesized wave "f" becomes "high". Next, the output "|" of the comparison 12 is changed from the time t3M to another intersection (time 丨6,) between the next first synthesized wave "e" and the first synthesized wave "f". After k, repeat the above operation. In other words, the output "" of the comparator 12 changes its state from "high" to "low" or from "low" at each intersection between the first composite wave "e" and the second composite wave "f". To "high". The output "k" of the comparator 13 is from the point of intersection (time t1) between the third synthesized wave "g" and the fourth synthesized wave "h" to the next third synthesized wave "g" and the next fourth The intersection (time t4) between the synthesized waves "h" becomes "low". Next, the output rk of the comparator 13 changes from the time t4" to another intersection (the time t5 '') between the next third synthesized wave "g" and the fourth synthesized wave "h" becomes "high". 'Subsequent' repeats the above operation. In other words, the output "k" of the comparator 13 changes its sorrow "South" to "Low" or from "Low" between the second composite wave "g" and the fourth composite wave "h". Change to "high". 95456.doc -23- !257765 Then 'Because the side output "+ουτ" = (output chest D (output k), this: side output "+〇UT" continuously becomes low level. When (output state output magic, When the question becomes "low", the "minus side output" is changed to "high", and the load ratio of the time period when the minus side output "-OUT" becomes high is substantially the same as the negative value of the class: rounding signal ( The differential value is proportional to the size. In other words: the minus side input: .T" can constitute this (4), which is a negative value (differential value) of the analog input signal by pulse width modulation (ρ·). And thus, according to a specific embodiment!) class amplifier, the analog input signal can be converted into a PW & 5 tiger' with three values (consisting of zero volts, positive and negative values) The p WM signal obtained by the conversion is rotated. According to the class D amplifier of the specific embodiment 1, in the case where the analog input signal value is higher than or equal to a predetermined value, the output signal becomes representative as shown in FIGS. 3 and 4 . Add one side of the "+OUT" and reduce the side of the "_0UT" to the switching signal of only one side of the signal. However, according to the specific embodiment, the switching loss of the class D amplifier can be approximately one-half of the switching loss of the conventional analog-type amplification crying in the side-by-side and side-by-side switching. The class D amplifier according to the specific embodiment 1 Using analog resistors and R4 to achieve analog feedback, the class D amplifier can amplify the analog input signal in a better linear condition without performing the digital processing operation described in the above-mentioned Patent Publication 2. The class D according to the specific embodiment 1 The amplifier, unlike the amplifier described in the above Patent Publication 1, eliminates the need for a transformer for impedance conversion and for cutting off the DC voltage, and can provide a class D amplifier with low power loss and low loss of directness, and its DC output. The composition is almost equal to zero volts. Specific Embodiment 2 95456.doc -24- 1257765 Next, a specific embodiment 2 of the present invention will be described with reference to Fig. 5. Fig. 5 is a diagram showing a class D not according to the specific embodiment 2 of the present invention. A circuit diagram of an example of the structure of an amplifier. The class D amplifier is provided with resistors R51, R52, R53, R54, R5 5 and R56, a battery C5 1, an operational amplifier 6 1 and 64, and a comparator 62. And an AND circuit (low activity) 71 and another AND circuit 72. The triangular wave signal "a" is applied to the add-side input terminal of the comparator 62, and the other triangular wave signal "b'" is applied to the comparator 63. Add side input terminals.
二角波信號「V」對應於此一三角波信號,其係藉由將 藉由反轉二角波信號「a」(即,延遲相位180度)獲得之三角 波化唬「b」的相位進一步延遲一極小角度「㊀」而產生。 因此,三角波信號ra」及三角波信號「b,」皆為相同波形 之信號,其相位彼此相差(18〇度+極小角度「㊀」)。此情形 中亦可將稱為「顫化」之預定雜訊分別應用於三角波信 號a及b由於將此顫化雜訊應用於每個三角波信號,可修 輸出波之失真。除該等二角波信號a及b,外,亦可使用雜 齒波形、積分波形等。The binary wave signal "V" corresponds to the triangular wave signal, which is further delayed by the phase of the triangular wave 唬 "b" obtained by inverting the binary wave signal "a" (that is, the delay phase is 180 degrees). Produced by a very small angle of "one." Therefore, the triangular wave signal ra" and the triangular wave signal "b," are signals of the same waveform, and their phases are different from each other (18 degrees + minimum angle "one"). In this case, predetermined noise called "fibrillation" can also be applied to the triangular wave signals a and b, respectively. Since the chattering noise is applied to each triangular wave signal, the distortion of the output wave can be repaired. In addition to the two-corner signals a and b, a noise waveform, an integrated waveform, or the like can be used.
毛阻為R5 1之一端子構成類比輸入信號之輸入端子。接 者’山將電阻器R51之另一端子連接至運算放大器“之減側輸 入端子。運算放大器61及電容器⑶兩者構成—積分器。比 較器邮較三角波信號「a」與積分器之輸出「^」,然後輸 出比較、〜果(輪出r j」)。比較器63比較三角波信號「b,」 與積分器之輪出「c」,然後輸出比較結果(輸出「k」)。 and電路71對應於具有低活動之and閘控功能的緩衝器 電路。接著’當第-比較器62之輸出「】」及第二比較器Ο 95456.doc -25- 1257765 之輸出「k」為「低」時,此AND電路7 i輸出「高」位準信 號’並輸出作為此D類放大器之減側輸出「_〇υτ」的此呀 算信號。AND電路72對應於具有AND閘控功能的緩衝器電 路。接著,當第一比較器62之輸出「j」及第二比較器63^ 輸出「k」為「高」時,此AND電路72輸出「高」位準信號, 並輸出作為此D類放大器之加側輸出「+〇υτ」的此計算俨 運算放大器64及電阻HR53、R54、⑽㈣構成一差動 放大器,其放大加側輸出r+〇UT」與減侧輸出「_贿」 之間的-差異。經由電阻器R52將此差動放大器之輸出「:」 回饋至運算放大器61之輸入側(即D類放大器之輸入側)。因 而,運算放大器64與電阻器R52、R53、R54、r55、r5^ 成一回饋電路。 接下來’說明依據使用上述電路配置之此 施 請員放f ^之操作。在類_人信料於零伏特(無輸入 4谠)之情形中,即「IN等 r +〇TJT , y J手於1/2 VDD」時,加側輸出 :及減側輸出「撕」皆如圖6所示, 週射之負荷比幾乎等於零至數個%。因此,當類比輸^ Uu寻於零伏特(無輸入信 别 器流至負载的電流變為極小值。由4波類放大 在類比輸入信號為正的愔 側輸出「撕」變得二: 側輸出「+〇UT」及減 其藉由以脈衝寬度調變方式調變類比輸入 a之正值(即’使用零伏特作為參考值時為「正」)而產1。 95456.doc -26 - 1257765 面,減側輪出Γ_ουτ」連續變為低位準。 在類比輸入信號為負的情形中,加側輸出 3出「撕,與㈣㈣。_,—「樣」 二:、此一化唬’其藉由以脈衝寬度調變方式調變類比輸入 ^虎之負值(即,使用1/2VDD作為參考值料「負」)而產 生。另-方面,加側輸出「+ουτ」連續變為低位準。 j依據上述具體實施例丨之0類放大器相同,使用上述配 置根據具體實施例2之_放大器,纟無類比輸入信號 2此-情形中(即零伏特值輸入之情形),由於將輸出信號 交為向位準之時間週期充分縮短至所需值,與先前技術D 類放大器相比,可大大減小功率損失。 因而,根據具體實施例2之D類放大器,可將類比輸入信 號轉換為具有三個值(由零伏特值、正值及負值構成)之 pWM信號,然後可將該等轉換得到的pWM信號輸出。根據 具體貫施例2之D類放大器,在類比輸入信號值高於或等於 預定值的情形中,其輸出信號變為與圖3及圖4代表之方式 相同的加側輸出「+0UT」及減側輸出Γ-〇υτ」之任一項 的僅一側信號之此一切換波形。因而,依據具體實施例2 之D力員放大為,其切換損失大約可為在加側及減側切換之傳 統D類放大器的切換損失之一半。 根據具體實施例2之D類放大器,由於藉由使用運算放大 器64、電阻器R52、R53、R54、R55、R56實現類比回饋, D類放大器可在較佳線性狀況下放大類比輸入信號,而不實 方也上述專利公開案2中說明的此一數位處理操作。根據呈體 95456.doc -27- 5 1257765 -例2之D類放大态’與上述專利公開案工中說明的放大器 I同’不再需要用於阻抗轉換及用以切斷dc電壓之變壓 杰’可提供具有低功率損失及低失真之此放大器,其 DC輸出成分幾乎等於零伏特。 ,主接下來’ SI7A至7C顯示_情形中之輸出波形的範例,此 h心為依據圖1或圖5顯示之具體實施例i或具體實施例:將 弦波輸入D類放大之類比信號輸入端子。具體實施例工 及具體實施例2中’在將正弦波輸人類比信號輸人端子的情 形:,輸丨波形彼此相圖7⑷顯示低通濾波器及負載(電 阻态R)’其與依據具體實施例1或具體實施例2之D類放大器 的加側輸出「+〇UT」及減側輸出「_〇υτ」兩者連接。圖 7(b)指示此d類放大器的加側輸出「+〇υτ」已穿過低通濾 波器後將此一波形顯示為輸出Γρ〇υτ」。圖7(1^中,此〇類 放大器的減側輸出「-0UT」已穿過低通濾波器後將此一波 形顯示為輸出「NOUT」。輸出P0UT及輸出N〇UI^^變為僅 有正弦波之上半部波形的此類波形。然而,對應於應用 於如圖7(c)所示之負載的信號之輸出「〇υτ」變為正弦波。 此原因如下給出:即,由於負載(揚聲器等)連接在輸出ρ〇υτ 與輸出NOUT間(即,低通渡波器之加側輸出端子「ρ〇υ丁」 與減側輸出端子「NOUT」間),如圖7(c)所表示,對應於應 用於此負載之此一信號的輸出「OUT」變為輸出P0UT與輸 出NOUT間的差異(〇UT=POUT-NOUT),從而構成正弦波。 在依據圖1及圖5所示的具體實施例1及具體實施例2之D 類放大器中,至少使用三角波信號「a」及三角波信號「b, 95456.doc -28- 1257765 兩者,三角波信號「b,」藉由反轉三角波㈣「a」並進一 步將此反轉三角波信號「a」延遲而獲得。因此,即使當依 據具體實施例!及具體實施例2之〇類放大器内不存在類比 輸入信號時,與圖2及圖6相同,加側輸出「+〇υτ」及減側 輸出「-OUT」皆在短時間内輸出(高位準週期之負荷比設定 為零至數個%),使得輸出至低通濾波器之電壓稍小(輸出 POUT、NOUT)。此時,由於將輸出ρ〇υτ_輸出Ν〇υτ定義 的此-電壓施加於負載,對應於應用於此負载之信號的輸 :OUT變為零伏特。因而’在將類比輸入端子從無信號狀 態改變至輸入較小信號之此一狀態的此一情形中,即使其 狀態改變,依據具體實施例丨及具體實施例2之D類放大器可 向負載供應具有低失真之放大信號。 具鱧實施例3 接下來,將參考圖8至圖U說明本發明之具體實施例3。 圖8為用於表示依據本發明之具體實施例3的d類放大器之 結構範例的電路圖。與依據具體實施例丨之D類放大器不 同,於此D類放大器中,延遲電路21及22並非用作結構元 件。此D類放大器中,將三角波信號「a」應用於電阻器ri 〇 之一端子,而將另一三角波信號「b」應用於另一電阻器 之一端子。除圖8所示之D類放大器中的上述電路配置外, 結構電路配置與依據圖丨所示之具體實施例丨的D類放大器 相同。應明白構成此D類放大器内之合成電路的電阻器 R5、R6、R7、R8、R9、R1〇、RU及R12之個別電阻值已在 一狀況下設定,此狀況並非定義於依據具體實施例丨之^類 95456.doc 1257765 放大器的電阻器 R5、R6、R7、R8、R9、R1Q、RU AR12 内。此D類放大之結構電路配置將予以詳細說明。 此D類放大器配置有電阻器ri、R2、μ、r4、r5、R6、 、R8、R9、H10、R11 及 R12 ’ 電容器 C1&C2、運算放大 态11、比較裔12及13、AND電路(低活動)31及另一 AND電 路3 2。此圖式中將預定二角波信號「a」分別應用於電阻器 R9及Rl 1之一端子。此圖式中將預定三角波信號分別應用於 電阻器R11及R12之一端子。三角波信號r a」及三角波信號 「b」為具有相同波形之此類信號,其相位彼此相差1 8 〇度。 現在假定本發明中三角波信號「a」設定為如請求項6之此 一三角波,則本發明中三角波信號「b」對應於具有相反相 位之三角波。 電阻器R1及R2之一端子分別構成類比輸入信號之差動 輸入端子。因此,電阻器R1之一端子構成加側輸入端子 (+IN) ’電阻器R2之一端子構成減側輸入端子(_IN)。運算放 大器11及電容器C1及C2構成積分器。此積分器對電阻器R1 及R2已用差動方式輸入的類比輸入信號積分,將積分信號 輸出至電阻器R5、R6、R7及R8。 電阻器 R5、R6、R7、R8、R9、RIO、R11 及R12構成合成 電路,其合成三角波信號「a’」或「b,」與積分器之輸出信 號。此合成電路產生第一至第四共四種合成波形「e」、rf」、 「g」、「h」。 構成合成電路之電阻器R5、R6、R7、R8、R9、、R11 及Rl 2的個別電阻值以一方式加以決定,此方式為第一合成 95456.doc -30- 1257765 波「e」與第二合成波「f」之間以及第三合成波「g」與第 四合成波「h」之間產生時間差(相位差),其對應於此合成 電路根據該等電阻值之輸出信號、關於比較器12(第一比較 器)及比較器13(第二比較器)之輸入電容。 此電路中,電阻器R5對應於本發明中與請求項7相關之第 一電阻器,電阻器R6對應於本發明中之第五電阻器。電阻 器R7對應於本發明中之第三電阻器。電阻器R9對應於本發 明中之第二電阻器。電阻器R10對應於本發明中之第八電阻 器。電阻器R11對應於本發明中之第四電阻器。電阻器R12 對應於本發明中之第六電阻器。 上述合成電路包含第一合成單元至第四合成單元。第一 合成單元合成構成積分器之運算放大器11的減側輸出與三 角波信號「a」,以產生第一合成波「e」。接著,第一合成 單元具有電阻器R5(第一電阻器),其一個端子與運算放大 器11之減側輸出連接,以及電阻器R9(第二電阻器)。將三 角波信號「a」應用於此電阻器R9之一端子。電阻器R5之另 一端子與電阻器R9之另一端子連接,以構成輸出端子。 第二合成單元合成運算放大器11的加側輸出與三角波信 號「b」,以產生第二合成波「f」。接著,第二合成單元具 有電阻器R7(第三電阻器),其一個端子與運算放大器11之 加側輸出連接,以及電阻器R11 (第四電阻器)。將三角波信 號「b」應用於此電阻器Rl 1之一端子。電阻器R7之另一端 子與電阻器Rl 1之另一端子連接,以構成輸出端子。 第三合成單元合成運算放大器11的減側輸出與三角波信 95456.doc -31 - 1257765 號「b」,以產生第三合成波「 取氣g」接者,第三合成單元具 有電阻器R6(第五電阻),盆一徊山 、、 ^ 其個^子與運算放大器11之 減側輸出連接,以及電阻哭R12f篦山+ |電阻器)。將三角波信 號「b」應用於此電阻器R12之—端子。電阻器以之另一端 子與電阻器im之另-端子連接,以構成輸出端子。 u第四合成單元合成運算放大㈣的加側輸出與三角波信 號a」,以產生第四合成波「h」。接著,第四合成單元具 有電阻㈣(第七電阻器),其—個端子與運算放大器& 加側輸出連接,以及電阻器R1〇(第人電阻器)。將三角波信 號「a」應用於此電阻器㈣之一端子。電阻器以之另—端 子與電阻器R10之另一端子連接,以構成輸出端子。 與比較器12連接之電阻器R5、R7、以及如(第一至第四 電阻器)的個別電阻值較佳的係設定成此類電阻值,其係藉 由將與比較器13連接的電阻器R6、R8、R10及Rl2(第五至 第八電阻器)之個別電阻值乘以除㈧」外之此類值而獲得。 例如,電阻器R5、R7、尺9及R1 i之電阻值及電阻器汉6、 R8、R10及R12之電阻值如下設定: R6=R8=R5Xa,R5=R7, R10=R12=R9Xa,R9=Rii, 該等公式中,符號ra」不等於!。 從上述公式之條件可看出,以下電阻值設定條件亦可建 立: R5=R7=R9=Rli,或 R5=R7 不等於 R9=R11。 95456.doc -32- 1257765 接著,在(R6=R8)及(R10=R12)的此一條件下,假定(R6、r8 、RIO、R12)等於(R5、R7、R9、R11)乘以「α」(否則係 l/α)。 舉例說明,現在假定電阻器R5、R7、R9、R11之個別電 阻值設定為1 [ΚΩ],R6、R8、RIO、R12之個別電阻值亦可 設定為2 [ΚΩ]或500 [Ω]。此時,符號「α」等於〇.5。 現在假定電阻器R5、R7、R9、Rl 1之個別電阻值設定為 20 [ΚΩ],電阻器R6、R8、R10、r12之個別電阻值亦可設 定為30 [ΚΩ]。此時,符號「α」等於1.5。 現在假定電阻器R5、R7、R9、Rl 1之個別電阻值設定為i [ΚΩ] ’ R6、R8、R1 〇、R12之個別電阻值亦可設定為3〇 [ΚΩ]。 此時,符號「α」等於30。 從丽述說明可看出,上述合成電路可藉由利用與比較器 12連接之電阻器R5、R7、R9、RU以及與比較器η連接之 電阻器R6、R8、R1〇、R12的電阻值間之差異以及比較器η 及13之輸入電容在第-合成波「e」與第二合成波「f」之 間以及第三合成波「g」與第四合成波%之間建立時間 差(相位差)。 /「 2(第—比較器)比較第一合成波、」與第二合成 :心’「Γ輪广比較結果。當第—合成波「e」大於第二 ό成波 f」時,第一比齡哭1 Ϊ 如,零位準),而1 預定「低」位準信號(例 日士 s弟一5成波「e」小於第二合成波「f」 二二 輸出預定「高」位準信號。比_第 一比車父裔)比較繁二人}、、士「 弟一口成波「趵與第四合成波「h」,以輸 95456.doc -33- 1257765 軚結果。當第三合成波「g」大於第四合成波「h」 比較為13輪出預定「低」位準信號(例如,零位準), 而远弟三合忠、、由「 ,皮g」小於第四合成波「h」時,第二比較 為13輸出預定「高」位準信號。 ^路31對應於具有負邏輯輸人之AND閘控功能的緩 :器電路。接著,娜電路31執行—娜計算(低活^ :中當弟-比較器12之輸出及第二比較器13之輸出為「低」 此^ND電路31輸出「高」位準信號,並輸出作為此D 颏放:态之減側輪出「-〇υτ」的此計算結果。電阻器们構 成一弟―回饋電路。第一回饋電路將用作緩衝器之AND電 路31的輸出回饋至運算放大器11之加側輸入。 助包路32對應於具有AND計算功能之緩衝器電路,並 執行比較器12之輸出與比較器13之輸出間的細計算操 ^,然後將計算結果輸出為此D類放大器之加側輸出 一 +OUT」。電阻器R4構成一第二回饋電路。第二回饋電路 將用作緩衝窃之AND電路32的輸出回饋至運算放大器丨丨之 減侧輸入。 「經由此D類放大器之加侧輸出「+〇u丁」與其減側輸出 厂-ουτ」間的低通濾波器連接負載(揚聲器等)。由於使用 孩等電路配置,此D類放大器可在低失真下放大類比輸入信 唬「+IN」及「-IN」,而不使用變壓器,另外可驅動負載, 同時減小功率損失。 接下來,參考圖9至圖π說明依據使用上述配置之此具體 實施例3的D類放大器之操作的範例。圖9至圖u為用於表示 95456.doc -34- 1257765 圖8所示之D類放大器的個別電路部分之操作的波形圖。接 著’圖9顯示當類比輸入信號「地」之值等於類比輸入信 5虎IN」之值%,即备差動輸入變為零伏特值時(無輸入 信號類放大器之個別電路部分的波形。圖ι〇代表當(類 比輸入信號「+IN」)>(類比給人# &「 」)U貝比輸入<吕唬「-IN」),即當差動輸 入變為正時,D類放大器之個別電路部分的波形。圖U代表 當(類比輸入信號「+IN」)<(類比輸入信號「_in」),即當 差動輸入變為負時,苜充* 4* , 义巧貝丁 員放大為之個別電路部分的波形。 如圖9至圖U所示’依據此具體實施例3之D類放大器.令的 们別电路。|5刀之主要知作部分與依據圖2至圖4所示之呈體 實施m的D類放大器中的個別電路部分相同。然而,:d 類放大器具有以下不同操作。即’兩組三角波信號、及 b」用作二角波仏號,此不同於依據具體實施例a。類放 大器,其使用4組三角波信號a、am,。接下來, 細說明此D類放大器之個別電路部分的操作。 ° 首先’將說明如圖9之操作’即無差動輸入之情形(零伏 寸值輸岭三角波信號「a」之相位與三角波信號「匕之 ^相1180度。此情形中,亦可將稱為「顫化」之預定雜 刀別應用於二角波信號_。由於將此顫化雜訊應用於 波信號,可修正輸出波之失真。除該等三角波信 夕亦可使用鋸齒波形、積分波形等。 角波“5虎aj與積分器之加側輪出(運算放大器丨丨之 加側輸出)「d」間的如 」間的相位關係實質上彼此相等。三角波信The one with the gross resistance of R5 1 constitutes the input terminal of the analog input signal. The receiver 'mountain connects the other terminal of the resistor R51 to the subtraction side input terminal of the operational amplifier. The operational amplifier 61 and the capacitor (3) constitute an integrator. The comparator compares the triangular wave signal "a" with the output of the integrator. "^", then output comparison, ~ fruit (round rj). The comparator 63 compares the triangular wave signal "b," with the integrator "c", and outputs a comparison result (output "k"). The and circuit 71 corresponds to a buffer circuit having a low activity and gate function. Then, when the output "@" of the first comparator 62 and the output "k" of the second comparator Ο 95456.doc -25 - 1257765 are "low", the AND circuit 7 i outputs a "high" level signal ' And output this signal as the subtraction side output "_〇υτ" of this class D amplifier. The AND circuit 72 corresponds to a buffer circuit having an AND gate function. Then, when the output "j" of the first comparator 62 and the second comparator 63^ output "k" to "high", the AND circuit 72 outputs a "high" level signal and outputs it as the class D amplifier. This calculation of adding the side output "+〇υτ", the operational amplifier 64 and the resistors HR53, R54, and (10) (4) constitute a difference amplifier, and the difference between the amplified side output r + 〇UT" and the reduced side output "_ bribe" . The output ":" of the differential amplifier is fed back to the input side of the operational amplifier 61 via the resistor R52 (i.e., the input side of the class D amplifier). Therefore, the operational amplifier 64 and the resistors R52, R53, R54, r55, and r5 are formed into a feedback circuit. Next, the operation of the apparatus according to the above-described circuit configuration is explained. In the case where the class_people is at zero volts (no input 4谠), that is, "IN is equal to r + 〇TJT, y J is at 1/2 VDD", the side output is added: and the minus side output is "tear". As shown in Fig. 6, the load ratio of the shot is almost equal to zero to several %. Therefore, when the analog output Uu finds zero volts (the current flowing to the load without the input signal is reduced to a minimum value. The four-wave type amplification is “tear” on the side of the analog input signal that is positive. Output "+〇UT" and reduce it by generating a positive value of the analog input a in a pulse width modulation mode (ie, 'positive when using zero volts as a reference value). 95456.doc -26 - 1257765 face, reduce side wheel Γ _ουτ" continuously becomes low level. In the case of analog input signal is negative, add side output 3 out "Tear, and (4) (four). _, - "sample" 2: This one 唬 ' It is generated by modulating the negative value of the analog input ^ tiger by pulse width modulation (that is, using 1/2 VDD as the reference value "negative"). On the other hand, the side output "+ουτ" is continuously changed. The low level is the same as the class 0 amplifier according to the above specific embodiment, and the above configuration is used according to the amplifier of the specific embodiment 2, 纟 no analog input signal 2 in this case (ie, the case of zero volt input), since The time period during which the output signal is delivered to the level is sufficiently shortened to the required value The power loss can be greatly reduced compared to prior art Class D amplifiers. Thus, according to the Class D amplifier of Embodiment 2, the analog input signal can be converted to have three values (by zero volts, positive and negative values). The pWM signal is configured to be output, and then the converted pWM signal can be output. According to the specific class D amplifier of Example 2, in the case where the analog input signal value is higher than or equal to a predetermined value, the output signal becomes 3 and 4 represent the switching waveform of only one side signal of any one of the side output "+0UT" and the subtraction side output Γ-〇υτ" in the same manner. Therefore, according to the specific embodiment 2, D The power is amplified so that the switching loss can be approximately one-half of the switching loss of the conventional class D amplifier switching between the plus side and the minus side. According to the class D amplifier of the second embodiment, since the operational amplifier 64 and the resistor R52 are used. R53, R54, R55, and R56 implement analogy feedback, and the class D amplifier can amplify the analog input signal under a better linear condition, and the actual digital processing operation described in the above Patent Publication 2 is not real. Body 95456.doc -27- 5 1257765 - The Class D amplified state of Example 2 is the same as the amplifier I described in the above patent publication. It is no longer needed for impedance conversion and to change the dc voltage. This amplifier can be provided with low power loss and low distortion, and its DC output component is almost equal to zero volts. The main next 'SI7A to 7C display' is an example of the output waveform in the case, which is shown in Figure 1 or Figure 5. The specific embodiment i or the specific embodiment: the sine wave is input into the analog signal input terminal of the class D. In the specific embodiment and the specific embodiment 2, the case where the sine wave is input into the human terminal signal is input to the terminal:丨 Waveform phase diagram 7(4) shows the low-pass filter and the load (resistance state R)' with the side output "+〇UT" and the subtraction side output of the class D amplifier according to the specific embodiment 1 or embodiment 2. 〇υτ" is connected. Figure 7(b) indicates that the add-side output "+〇υτ" of this class D amplifier has passed through the low-pass filter and this waveform is shown as output Γρ〇υτ". In Figure 7 (1^, the minus-side output "-0UT" of this 〇-type amplifier has passed through the low-pass filter and this waveform is displayed as the output "NOUT". The output P0UT and the output N〇UI^^ become only Such a waveform having a waveform of the upper half of the sine wave. However, the output "〇υτ" corresponding to the signal applied to the load as shown in Fig. 7(c) becomes a sine wave. This reason is given as follows: Since the load (speaker, etc.) is connected between the output ρ〇υτ and the output NOUT (that is, between the add-side output terminal “ρ〇υ丁” and the minus-side output terminal “NOUT” of the low-pass ferropole), as shown in Fig. 7(c) It is shown that the output "OUT" corresponding to the signal applied to the load becomes a difference (〇UT=POUT-NOUT) between the output POUT and the output NOUT, thereby forming a sine wave. In accordance with Figs. 1 and 5 In the specific embodiment 1 and the class D amplifier of the second embodiment, at least the triangular wave signal "a" and the triangular wave signal "b, 95456.doc -28 - 1257765 are used, and the triangular wave signal "b," is reversed. The triangular wave (4) "a" is further obtained by delaying the inverted triangular wave signal "a". Therefore, Even when there is no analog input signal in the 放大器 class amplifier according to the specific embodiment! and the specific embodiment 2, as in the case of FIG. 2 and FIG. 6, the side output "+〇υτ" and the minus side output "-OUT" are both Output in a short time (the load ratio of the high level period is set to zero to several %), so that the voltage output to the low pass filter is slightly smaller (outputs POUT, NOUT). At this time, since the output ρ 〇υ τ_ output Ν This voltage defined by 〇υτ is applied to the load, corresponding to the signal applied to the load: OUT becomes zero volts. Thus 'in the state where the analog input terminal is changed from the no-signal state to the input smaller signal. In this case, even if the state thereof changes, the class D amplifier according to the specific embodiment and the specific embodiment 2 can supply an amplified signal having low distortion to the load. 鳢 Embodiment 3 Next, reference will be made to FIG. 8 to FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 3 is a circuit diagram showing an example of the structure of a class D amplifier according to a third embodiment of the present invention. Unlike a class D amplifier according to a specific embodiment, the class D amplifier is used. The delay circuits 21 and 22 are not used as structural elements. In the class D amplifier, the triangular wave signal "a" is applied to one terminal of the resistor ri 〇, and the other triangular wave signal "b" is applied to the other resistor. A terminal structure is the same as the class D amplifier according to the specific embodiment shown in FIG. 8 except for the above circuit configuration in the class D amplifier shown in FIG. 8. It should be understood that the composite circuit constituting the class D amplifier is understood. The individual resistance values of the resistors R5, R6, R7, R8, R9, R1〇, RU and R12 have been set under a condition, and this condition is not defined in the resistor of the amplifier according to the specific example 95456.doc 1257765 In R5, R6, R7, R8, R9, R1Q, and RU AR12. The structural circuit configuration of this class D amplification will be described in detail. This class D amplifier is equipped with resistors ri, R2, μ, r4, r5, R6, R8, R9, H10, R11 and R12 'capacitor C1 & C2, operational amplification state 11, comparator 12 and 13, AND circuit ( Low activity 31 and another AND circuit 3 2 . In this figure, the predetermined two-dimensional wave signal "a" is applied to one of the terminals of the resistors R9 and Rl1, respectively. In this figure, a predetermined triangular wave signal is applied to one of the terminals of the resistors R11 and R12, respectively. The triangular wave signal r a" and the triangular wave signal "b" are such signals having the same waveform, and their phases are different from each other by 18 degrees. Assume now that the triangular wave signal "a" in the present invention is set to such a triangular wave as in the claim 6, the triangular wave signal "b" in the present invention corresponds to a triangular wave having an opposite phase. One of the terminals of the resistors R1 and R2 constitutes a differential input terminal of an analog input signal. Therefore, one of the terminals of the resistor R1 constitutes a side input terminal (+IN). One of the terminals of the resistor R2 constitutes a minus side input terminal (_IN). The operational amplifier 11 and the capacitors C1 and C2 constitute an integrator. The integrator integrates the analog input signals of the differential inputs of the resistors R1 and R2, and outputs the integrated signals to the resistors R5, R6, R7 and R8. Resistors R5, R6, R7, R8, R9, RIO, R11 and R12 form a synthesizing circuit that synthesizes the triangular wave signal "a'" or "b," and the output signal of the integrator. The synthesizing circuit generates four first to fourth composite waveforms "e", rf", "g", and "h". The individual resistance values of the resistors R5, R6, R7, R8, R9, R11 and Rl 2 constituting the synthesizing circuit are determined in a manner which is the first synthesis 95456.doc -30 - 1257765 wave "e" and A time difference (phase difference) is generated between the second synthesized wave "f" and between the third synthesized wave "g" and the fourth synthesized wave "h", which corresponds to an output signal of the composite circuit based on the resistance values, and is compared The input capacitance of the 12 (first comparator) and comparator 13 (second comparator). In this circuit, the resistor R5 corresponds to the first resistor associated with the claim 7 in the present invention, and the resistor R6 corresponds to the fifth resistor in the present invention. The resistor R7 corresponds to the third resistor in the present invention. Resistor R9 corresponds to the second resistor in the present invention. The resistor R10 corresponds to the eighth resistor in the present invention. The resistor R11 corresponds to the fourth resistor in the present invention. The resistor R12 corresponds to the sixth resistor in the present invention. The above synthesizing circuit includes first to fourth synthesizing units. The first synthesizing unit synthesizes the reduced side output of the operational amplifier 11 constituting the integrator and the triangular wave signal "a" to generate the first synthesized wave "e". Next, the first synthesizing unit has a resistor R5 (first resistor) having one terminal connected to the subtraction side output of the operational amplifier 11, and a resistor R9 (second resistor). Apply the triangular signal "a" to one of the terminals of this resistor R9. The other terminal of the resistor R5 is connected to the other terminal of the resistor R9 to constitute an output terminal. The second synthesizing unit synthesizes the added side output of the operational amplifier 11 and the triangular wave signal "b" to generate a second synthesized wave "f". Next, the second synthesizing unit has a resistor R7 (third resistor), one terminal of which is connected to the add-side output of the operational amplifier 11, and a resistor R11 (fourth resistor). The triangular wave signal "b" is applied to one of the terminals of the resistor R11. The other terminal of the resistor R7 is connected to the other terminal of the resistor R11 to constitute an output terminal. The third synthesizing unit synthesizes the subtraction side output of the operational amplifier 11 and the triangular wave letter 95456.doc -31 - 1257765 "b" to generate the third synthesized wave "taken gas g", and the third synthesizing unit has the resistor R6 ( The fifth resistor), the basin is a mountain, and its ^ is connected to the side of the operational amplifier 11 minus the output, and the resistor is crying R12f篦山+ | resistor). The triangular wave signal "b" is applied to the terminal of this resistor R12. The other end of the resistor is connected to the other terminal of the resistor im to form an output terminal. The fourth synthesizing unit synthesizes the added side output of the operation (4) and the triangular wave signal a" to generate the fourth synthesized wave "h". Next, the fourth synthesizing unit has a resistor (four) (seventh resistor) having a terminal connected to the operational amplifier & plus side output, and a resistor R1 〇 (first resistor). Apply the triangular wave signal "a" to one of the terminals of this resistor (4). The resistor is further connected to the other terminal of the resistor R10 to form an output terminal. The resistors R5, R7 connected to the comparator 12, and the individual resistance values such as (first to fourth resistors) are preferably set to such resistance values by connecting the resistors connected to the comparator 13. The individual resistance values of the R6, R8, R10, and R12 (fifth to eighth resistors) are multiplied by such values other than (8). For example, the resistance values of resistors R5, R7, 尺 9 and R1 i and the resistance values of resistors 6, R8, R10 and R12 are set as follows: R6 = R8 = R5Xa, R5 = R7, R10 = R12 = R9Xa, R9 =Rii, in these formulas, the symbol ra" is not equal! . It can be seen from the conditions of the above formula that the following resistance value setting conditions can also be established: R5 = R7 = R9 = Rli, or R5 = R7 is not equal to R9 = R11. 95456.doc -32- 1257765 Next, under this condition of (R6=R8) and (R10=R12), it is assumed that (R6, r8, RIO, R12) is equal to (R5, R7, R9, R11) multiplied by " α" (otherwise l/α). For example, it is assumed that the individual resistance values of resistors R5, R7, R9, and R11 are set to 1 [ΚΩ], and the individual resistance values of R6, R8, RIO, and R12 can also be set to 2 [ΚΩ] or 500 [Ω]. At this time, the symbol "α" is equal to 〇.5. Now assume that the individual resistance values of resistors R5, R7, R9, and Rl 1 are set to 20 [ΚΩ], and the individual resistance values of resistors R6, R8, R10, and r12 can also be set to 30 [ΚΩ]. At this time, the symbol "α" is equal to 1.5. Now assume that the individual resistance values of the resistors R5, R7, R9, and Rl 1 are set to i [ΚΩ] ’. The individual resistance values of R6, R8, R1 〇, and R12 can also be set to 3 〇 [ΚΩ]. At this time, the symbol "α" is equal to 30. As can be seen from the description of the Li, the above synthesizing circuit can be obtained by using the resistors R5, R7, R9, RU connected to the comparator 12 and the resistors R6, R8, R1, R12 connected to the comparator n. The difference between the comparators η and the input capacitance of the comparators η and 13 establishes a time difference between the first synthesized wave "e" and the second synthesized wave "f" and between the third synthesized wave "g" and the fourth synthesized wave % (phase) difference). / "2 (first-comparator) compares the first synthesized wave," and the second synthesis: the heart'" is a comparison result. When the first-composite wave "e" is greater than the second ό-forming wave f", the first Chou is crying 1 Ϊ, for example, zero is accurate), and 1 is scheduled to be "low" level signal (eg, a Japanese s brother, a 50-wave "e" is smaller than the second synthetic wave "f", and the second output is scheduled to be "high". The quasi-signal. More than the _ first than the car father's family) more complex people},, "the younger brother into a wave of "趵 and the fourth synthetic wave "h", to lose 95456.doc -33 - 1257765 軚 results. When the third composite wave "g" is greater than the fourth composite wave "h", the predetermined "low" level signal (for example, zero level) is 13 rounds, and the far-reaching Sanhezhong, and ", skin g" When it is smaller than the fourth synthesized wave "h", the second comparison 13 outputs a predetermined "high" level signal. The way 31 corresponds to a buffer circuit having an AND gate function of a negative logic input. Next, the circuit 31 performs the ana-calculation (low activity ^: the output of the middle-of-the-comparator 12 and the output of the second comparator 13 is "low". The ND circuit 31 outputs a "high" level signal and outputs As a result of this D : : : 态 态 : : 态 态 态 态 态 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The side of the amplifier 11 is input. The helper path 32 corresponds to a buffer circuit having an AND calculation function, and performs a fine calculation operation between the output of the comparator 12 and the output of the comparator 13, and then outputs the calculation result to this D. The adder side of the class amplifier outputs a +OUT. The resistor R4 forms a second feedback circuit, and the second feedback circuit feeds the output of the AND circuit 32 used as a buffer to the subtraction side input of the operational amplifier 。. The low-pass filter between the side output of the class D amplifier and the side output factory - ουτ is connected to the load (speaker, etc.). This class D amplifier can be used with low distortion due to the circuit configuration of the child. Zoom in analog input signal "+IN And "-IN", without using a transformer, can additionally drive the load while reducing the power loss. Next, the operation of the class D amplifier according to this specific embodiment 3 using the above configuration will be described with reference to Figs. Example 9 to Figure 9 are waveform diagrams showing the operation of the individual circuit portions of the class D amplifier shown in Figure 8 of 95456.doc -34-1252765. Next, Figure 9 shows the value of the analog input signal "ground". It is equal to the value of the analog input signal 5 tiger IN", that is, when the differential input becomes zero volts (the waveform of the individual circuit part of the input signal amplifier is not shown. Figure ι〇 represents when (the analog input signal "+IN") > (analog to # & " ") U Bebe input < 吕唬 "-IN"), that is, the waveform of the individual circuit part of the class D amplifier when the differential input becomes positive. Figure U represents (The analog input signal "+IN") < (analog input signal "_in"), that is, when the differential input becomes negative, the charge * 4 *, the magic bellber is amplified into the waveform of the individual circuit parts. As shown in Figure 9 to Figure U, the class D amplifier according to this specific embodiment 3. The other part of the circuit is the same as the individual circuit part of the class D amplifier according to the embodiment shown in Figures 2 to 4. However, the class d amplifier has the following different operations. The two sets of triangular wave signals, and b" are used as the two-dimensional apostrophes, which is different from the specific embodiment a. The class amplifier uses four sets of triangular wave signals a, am. Next, the individual parts of the class D amplifier are described in detail. The operation of the circuit section. ° First, the operation of Figure 9 will be described, that is, the case of no differential input (the phase of the zero-volt value of the triangular wave signal "a" and the triangular wave signal "the phase of the triangle is 1180 degrees. In the meantime, a predetermined chisel called "fibrillation" can also be applied to the two-dimensional signal _. Since the chattering noise is applied to the wave signal, the distortion of the output wave can be corrected. In addition to these triangular wave signals, a sawtooth waveform, an integrated waveform, or the like can be used. The angular relationship between the angular wave "5 tiger aj and the integrator plus side output (the operational amplifier 加 plus side output) "d" is substantially equal to each other. Triangle wave letter
;J b」與積分器之減側輸出(運算放大器u之減側輸出)「c 95456.doc -35- 1257765 間的相位關係實質上彼此相等。 比較态12及13之輸入,即第一至第四合成波e、f、g及h 具有與積分器之輸出合成的波形。接著,第一合成波「e」 相位14苐一合成波r f」之相位相差大約1 $ 〇度。第三合 成波g」之相位與第四合成波「h」之相位相差大約i 8〇 度。第一合成波「e」之波形實質上等於第四合成波「h」 之波形,該等第_及第四合成波「e」A「h」之相位彼此 相差極小角度「θ,」。第二合成波「f」之波形實質上等於第 三合成波「g」之波形,該等第二及第三合成波「f」及「q」 之相位彼此相差極小角度「㊀,」。 士先則所述,第-合成波形「e」與第四合成波形「h」 之間以及第二合成波形「f」與第三合成波形「g」之間產 生極小角度θ’的原因如下。即是說,與比較器12連接之電 阻器R5、R7、奶及1111的個別電阻值已設定成此類電阻值, 其係藉由將與比較器13連接的電阻器R6、R8、及 之個別電阻值乘以除「!」外之此類值而獲得。換言之,根 據該等電阻值及比㈣12及13之輸人電容,產生上述極^ 角度θ’之相位差。應明白此極小角度㊀,對應於依據圖2所示 之具體實施例刚類放大器之操作波形内出現的極小角度 θ。接著,可藉由調節電阻器RUR12之電阻值以簡單方= 调郎此極小角度㊀’。 比較器12及13之輸出「j」&「k」具有與依據圖2所示之 具體實施例⑽類放大器之比較器12及13的輪出「』」及「k 相同之波形。此D類放大器之加側輸出「+〇υτ」及減側輪 95456.doc -36- 1257765 出「-OUT」具有與依據圖2所示之具體實施例1的D類放大 器之加側輸出「+〇UT」及減側輸出「-OUT」相同的波形。 如上所述’用於此D類放大器之比較器丨2及丨3與and電路 31、32的操作與依據具體實施例1之〇類放大器的比較器12 及13與AND電路3 1、32相同。用於此D類放大器之回饋電路 (電阻器R3&R4)與積分器(運算放大器11及電容器Cl、C2) 的操作與用於依據具體實施例1之D類放大器内的回饋電路 與積分器之操作相同。 因而’舆依據具體實施例1之D類放大器相同,此D類放 大-中田不供應輸入信號時,加侧輸出+〇υτ及減側輸出 -OUT内之高位準週期可設定為〇至數個%的負荷比。因而, 在此具體實施例之0類放大器用於小信號之此一情形中,可 省略配置於輪出端子與負載間之上述低通濾波器(I。濾波 器等)。 ^ 使用此D類放大器之上述配置時,與具體實施例1之d類 放大器相同’在無類比輸人信號的此—情形中(即零伏特值 3之U形)由於將輸出信號變為高位準之時間週期可充 刀縮短至所需值,與先前技術D類放大器相比,可大大減小 接下來,說明(類比輪入作 厂 〇 儿 」/ 、π…彌-八信 」)之丨月形中,即當其差動輸入如圖1〇所示 此舰大器之操作。當_與圖3比較時,不同黑^ _放大器内之三角波使用兩組三角波信號、及「b 因而’即使在差動輸入為正之此一情形中,除合成電路 95456.doc I257765 :外’此D類放Ai§可採用與依據具體實施例u類放大 ☆相同的方式力v p 士 知作。因此,此D類放大器中,當差動輸 二;:,加側輸出「卿」變為此-信號,其係藉由以 脈衝見度調變方—、% " 、、 式调、交類比輸入信號之正值(差動值)而產 以及減侧輸出Γ·〇υτ」連續變為低位準。 「ΙΝ來υ兄日月(類比輸入信號「+ΙΝ」)<(類比輸入信號 ·Ν」)之情形中,即當其差動輸入如圖丨丨所示變為負時, 類放^器之操作°當圖11與圖4比較時,不同點僅為此 颌放大為内之二角波使用兩組三角波信號「a」及「b」。 八「使在差動輸人為負之此—情形中,除合成電路部 刀外,此D類放大器可採用與依據具體實施例1之D類放大 Μ同的方式加以操作。因此,此D類放大器中,#差動輸 入為㈣’減侧輸出「撕」變為此一信號,其係藉由以 脈衝見度調變方式調變類比輸入信號之負值(差動值)而產 生,以及加側輸出「+ουτ」連續變為低位準。 因而,與具體實施例㈣類放大器相同,根據具體實施 :3之峨大器,可將類比輪入信號轉換為具有三個值(由 :伏4寸值、正值及負值中之任一項構成)之PWM信號,然後 亥等轉換得到的pwM信號輸出。根據具體實施例3之◦ 、、大的在頮比輸入信號值高於或等於預定值的情形 卜其輸出信號變為如圖10及圖叫表之加侧輸出「+〇υτ」 咸侧輪出-OUT」之任一項的僅一側信號之此一切換波 形因而,依據具體實施例3之D類放大器,其切換損失大 約可為在加側及減側切換之傳統〇類放大器的切換損失之 95456.doc -38- 1257765 一半。 根據具體實施例3之D類放大器,由於藉由使用電阻器们 及R4實現類比回饋,D類放大器可在較佳線性狀況下放大 類比輸入信號,而不實施上述專利公開案2中說明的此一數 位處理操作。根據具體實施例3之D類放大器,與上述專利 公開案1中說明的放大器不同,不再需要用於阻抗轉換及用 以切斷DC電壓之變壓器,可提供具有低功率損失及低失真 之此一 D類放大裔,其DC輪出成分幾乎等於零伏特。 此外’根據此具體實施例3之D類放大器,雖然延遲電路 21 Μ及81並未用作結構元件,由於調節電阻器μ至r 12 之電阻值,第一合成波「e」與第二合成波「f」間、第三 合成波「g」與第四合成波「h」間可產生時間差(相位差), 其不同於上述具體實施例丨及2之D類放大器。因而,此具體 實施例3之D類放大器可採用簡單方式加以設計及製造,並 且可提供具有高性能之D類放大器。 具體實施例4 接下來’將參考圖12至圖17說明依據本發明之具體實施 例4。圖12為顯示依據本發明之具體實施例4的〇類放大器之 組態的電路圖。依據具體實施例1之D類放大器中使用的共 同疋件採用相同參考數字。依據具體實施例4的本D類放大 裔與依據具體實施例1及2之D類放大器的差異在於提供單 一二角波產生電路。以下將詳細說明本D類放大器。 D類放大器包括電阻器Rl、R2、R3及R4、電容器Cl、C2 及0100、運算放大器11、比較器112及113、反相器121及 95456.doc -39- 1257765 122、AND電路131及132及電流源140。電容器100及電流源 構成三角波產生電路,其將三角波輸出至比較器112及113 之減輸入側。 每個電阻器R1及R2之一端係用於類比輸入信號之差動 輸入端。電阻器R1之一末端為加側輸入端子(+IN),電阻器 R2之一末端為減側輸入端子(-IN)。運算放大器11及電容器 C1及C2構成積分器。積分器對以差動方式輸入電阻器R1及 R2之類比輸入信號積分,以將其輸出至比較器112及113。 運算放大器11之減側輸出與比較器112(第一比較器)之加 側輸入端子連接。運算放大器丨丨之加側輸出與比較器 113(第二比較器)之加側輸入端子連接。比較器U2&丨13之 減側輸入端子分別與電容器1〇〇(電容器)之一末端連接。電 谷為100之另一末端與接地連接,電流源之另一端與接地連 接。使用此配置,比較器112比較運算放大器丨丨之減側輸出 與三角波產生電路之輸出並輸出比較結果。比較器113比較 運异放大益11之加側輸出與三角波產生電路之輸出並輸出 比較結果。 比較器112之輸出與反相器121之輸人端子及侧電路 132(第二緩衝器)之輸人端子之—連接。比較器⑴之輸出與 反相器122之輸入端子及AND電路(第—緩衝器。之輸入端 子之-連接。反相器121之輸出與侧電路i3i之另一輸入 端子連接。反相器122之輸出與娜電路132之另—輸入端 子連接。使用該配置,and帝故m A丄… ND^*路U1計算從比較器112之輸 出反轉的信號與比較器113之輸出之邏輯乘積,並輸出計算 95456.doc -40- 1257765 結果。AND電路132計算從比較器113之輸出反轉的信號與 比車父器112之輸出之邏輯乘積,並輸出計算結果。 AND電路13 1之輸出為〇類放大器之加側輸出+〇υτ。透過 電阻器R4將加側輸出+0UT回饋至運算放大器之減側輸 入。AND電路132之輸出為D類放大器之減側輸出-〇υτ。透 過電阻器R3將減側輸出-0UT回饋至運算放大器之加側輸 入0 圖13為顯示電流源14〇之特定組態的電路圖。電流源14〇 及電容器1〇〇構成三角波產生電路。電晶體丁丨及丁2、開關si 及S2、比較141及142以及NAND電路143及144構成電流 源 140。 電晶體T1 及T2由場效電晶體(field_effect transist〇r; FET) 構成。將用於控制電容器100之充電電流值的電壓施加 於電晶體T1之閘極。將用於控制電容器之放電電流值的電 壓VBN施加於電晶體T2之閉極。開關31及32包含類比開 關,亚且可由FET構成。開關81及82切換來自電流源14〇之 电流輸出的流動方向,即切換電容器i 〇〇之充電與放電。電 晶體τι之電流輸入/輸出端子、開關§1及82以及電晶體 之電流輸入/輸出端子彼此串聯連接,如圖13所示。比較器 Η1之減側輸入端子及比較器142之加側輸入端子與開關以 及S2之連接點連接。連接點亦與電容器1〇〇連接並構成三角 波產生電路之輸出端子。 比較為142比較期望第一電位¥;1與連接點之電位,並輸 出比較結果。比較器141比較期望第二電位vh與連接點之 95456.doc -41 - 1257765 電位,並輪出比較結果。假定第二電位VH高於第一電位 VL。第二電位¥11與第一電位VL間之差異設定三角波之振 幅。連接NAND電路143及144,以構成正反器電路。正反哭 電路具有輸入,其為比較器14丨及142之輸出。正反器電路 之輸出控制開關S1及S2之斷開/閉合。即,正反器電路之輸 出切換電容器100之充電與放電,以切換三角波之升與降。 圖14為解說電流源140之操作的圖式。; J b" and the inductor's reduced side output (the reduced side output of the operational amplifier u) "c 95456.doc -35 - 1257765 are substantially equal to each other. The inputs of the comparison states 12 and 13 are the first to The fourth synthesized waves e, f, g, and h have waveforms synthesized with the output of the integrator. Then, the phase of the first synthesized wave "e" phase 14 苐 a composite wave rf" differs by about 1 〇. The phase of the third synthetic wave g" differs from the phase of the fourth synthesized wave "h" by about i 8 degrees. The waveform of the first synthesized wave "e" is substantially equal to the waveform of the fourth synthesized wave "h", and the phases of the first and fourth synthesized waves "e" A "h" are different from each other by an extremely small angle "θ,". The waveform of the second synthesized wave "f" is substantially equal to the waveform of the third synthesized wave "g", and the phases of the second and third synthesized waves "f" and "q" are different from each other by a very small angle "one". As described above, the reason why the minimum angle θ' is generated between the first synthesized waveform "e" and the fourth synthesized waveform "h" and between the second synthesized waveform "f" and the third synthesized waveform "g" is as follows. That is to say, the individual resistance values of the resistors R5, R7, milk and 1111 connected to the comparator 12 have been set to such resistance values by the resistors R6, R8 connected to the comparator 13, and The individual resistance values are multiplied by such values other than "!". In other words, the phase difference of the above-mentioned pole angle θ' is generated based on the resistance values and the input capacitances of (4) 12 and 13. It should be understood that this very small angle one corresponds to a very small angle θ occurring within the operational waveform of the amplifier according to the embodiment shown in Fig. 2. Then, by adjusting the resistance value of the resistor RUR12, the minimum angle is adjusted by one. The outputs "j" & "k" of the comparators 12 and 13 have the same waveforms as "k" and "k" of the comparators 12 and 13 of the amplifier according to the specific embodiment (10) shown in Fig. 2. This D Adding side output "+〇υτ" and reducing side wheel 95456.doc -36 - 1257765 of the class amplifier have "+OUT" with the side output "+〇" of the class D amplifier according to the specific embodiment 1 shown in Fig. 2. UT" and the subtraction side output "-OUT" the same waveform. As described above, the operation of the comparators 丨2 and 丨3 and the circuits 31, 32 for the class D amplifier and the comparators 12 and 13 of the sigma amplifier according to the first embodiment are the same as the AND circuits 31, 32. . Operation of the feedback circuit (resistor R3 & R4) and integrator (operating amplifier 11 and capacitors C1, C2) for this class D amplifier and the feedback circuit and integrator for the class D amplifier according to the specific embodiment 1. The operation is the same. Therefore, '舆 is the same as the class D amplifier of the specific embodiment 1. When the class D amplification - Zhongtian does not supply the input signal, the high level period in the plus side output + 〇υ τ and the minus side output - OUT can be set to 〇 to several % load ratio. Therefore, in the case where the class 0 amplifier of this embodiment is used for a small signal, the above-described low pass filter (I, filter, etc.) disposed between the wheel terminal and the load can be omitted. ^ When using the above configuration of this class D amplifier, it is the same as the class D amplifier of the specific embodiment 1 'in the case of the analogless input signal (ie, the U shape of zero volt value 3) due to the output signal becoming high The quasi-time cycle can be shortened to the required value, which can be greatly reduced compared with the prior art class D amplifier. The description is based on the analogy of the incarnation of the factory / π... In the shape of the moon, that is, when the differential input is as shown in Figure 1〇, the operation of the ship. When compared with Figure 3, the triangular waves in different black ^ _ amplifiers use two sets of triangular wave signals, and "b thus 'even in the case where the differential input is positive, except for the synthesis circuit 95456.doc I257765: outside' Class D Ai § can be used in the same way as the specific example u class amplification ☆ force vp. Therefore, in this class D amplifier, when the differential input two;:, plus side output "Qing" becomes this a signal which is continuously changed by the positive value (differential value) of the input signal and the negative side output Γ·〇υτ by the pulse-modulation--, % ", , and the analog input signal. Low level. "In the case of the brother-in-law (analog input signal "+ΙΝ") < (analog input signal · Ν"), that is, when the differential input becomes negative as shown in the figure ,, the class is placed ^ Operation of the device ° When comparing Fig. 11 with Fig. 4, the difference between the two points is that the two triangular waves are "a" and "b". In the case where the differential input is negative, the class D amplifier can be operated in the same manner as the class D amplification according to the specific embodiment 1 except for the synthetic circuit portion knife. Therefore, this class D In the amplifier, the #differential input is (4) 'minus side output "tear" becomes this signal, which is generated by modulating the negative value (differential value) of the analog input signal by the pulse modulation modulation method, and The side output "+ουτ" is continuously changed to the low level. Therefore, similar to the amplifier of the specific embodiment (4), according to the specific implementation: 3, the analog wheeled signal can be converted into three values (by: volt 4 inch value, positive value and negative value The PWM signal of the term constitutes a PWM signal, and then the pwM signal obtained by the conversion of the sea is output. According to the specific embodiment 3, the large output signal value is higher than or equal to the predetermined value, and the output signal becomes the side output "+〇υτ" as shown in FIG. 10 and the table. The switching waveform of only one side signal of any one of -OUT", therefore, according to the class D amplifier of the third embodiment, the switching loss can be approximately the switching of the conventional sinusoidal amplifier switching between the side and the side. Loss of 95456.doc -38 - 1257765 half. According to the class D amplifier of the third embodiment, since the analog feedback is realized by using the resistors and R4, the class D amplifier can amplify the analog input signal under a better linear condition without implementing the above described in the above Patent Publication 2. A digital processing operation. According to the class D amplifier of the specific embodiment 3, unlike the amplifier described in the above Patent Publication 1, the transformer for impedance conversion and for cutting off the DC voltage is no longer required, and the present invention can provide low power loss and low distortion. A class D magnified, whose DC turn-out component is almost equal to zero volts. Further, according to the class D amplifier of the third embodiment, although the delay circuits 21 and 81 are not used as structural elements, the first synthesized wave "e" and the second composite are adjusted by adjusting the resistance values of the resistors μ to r12. A time difference (phase difference) may be generated between the wave "f", the third synthesized wave "g", and the fourth synthesized wave "h", which is different from the class D amplifier of the above-described embodiments. Thus, the Class D amplifier of this specific embodiment 3 can be designed and manufactured in a simple manner, and can provide a Class D amplifier with high performance. BEST MODE FOR CARRYING OUT THE INVENTION Next, a specific embodiment 4 according to the present invention will be described with reference to Figs. 12 to 17 . Figure 12 is a circuit diagram showing the configuration of a oxime amplifier according to a specific embodiment 4 of the present invention. The same reference numerals are used for the common components used in the class D amplifier of the specific embodiment 1. The difference between the present class D amplifier according to the specific embodiment 4 and the class D amplifier according to the specific embodiments 1 and 2 is that a single binary wave generating circuit is provided. This class D amplifier will be described in detail below. Class D amplifiers include resistors R1, R2, R3 and R4, capacitors C1, C2 and 0100, operational amplifier 11, comparators 112 and 113, inverters 121 and 95456.doc - 39 - 1257765 122, AND circuits 131 and 132 And current source 140. The capacitor 100 and the current source constitute a triangular wave generating circuit that outputs a triangular wave to the subtraction input side of the comparators 112 and 113. One of each of the resistors R1 and R2 is used for the differential input of the analog input signal. One end of the resistor R1 is a plus side input terminal (+IN), and one end of the resistor R2 is a minus side input terminal (-IN). The operational amplifier 11 and the capacitors C1 and C2 constitute an integrator. The integrator integrates the analog input signals of the differential input resistors R1 and R2 to output them to the comparators 112 and 113. The reduced side output of the operational amplifier 11 is connected to the add side input terminal of the comparator 112 (first comparator). The add-side output of the operational amplifier 连接 is connected to the add-side input terminal of the comparator 113 (second comparator). The subtraction side input terminals of the comparator U2 & 丨 13 are respectively connected to one end of the capacitor 1 电容器 (capacitor). The other end of the valley is connected to the ground, and the other end of the current source is connected to the ground. With this configuration, the comparator 112 compares the output of the subtraction side of the operational amplifier 与 with the output of the triangular wave generating circuit and outputs a comparison result. The comparator 113 compares the side output of the differential gain amplifier 11 with the output of the triangular wave generating circuit and outputs a comparison result. The output of the comparator 112 is connected to the input terminal of the inverter 121 and the input terminal of the side circuit 132 (second buffer). The output of the comparator (1) is connected to the input terminal of the inverter 122 and the AND circuit (the input terminal of the first buffer). The output of the inverter 121 is connected to the other input terminal of the side circuit i3i. The inverter 122 The output is connected to the other input terminal of the circuit 132. With this configuration, the ND^* path U1 calculates the logical product of the signal inverted from the output of the comparator 112 and the output of the comparator 113. And the result of the calculation 95456.doc -40 - 1257765 is output. The AND circuit 132 calculates the logical product of the signal inverted from the output of the comparator 113 and the output of the parent device 112, and outputs the calculation result. The output of the AND circuit 13 1 is The side output of the 放大器 class amplifier is + 〇υτ. The plus side output +0UT is fed back to the subtraction side input of the operational amplifier through the resistor R4. The output of the AND circuit 132 is the reduced side output of the class D amplifier - 〇υτ. R3 feeds the minus side output -0UT to the plus side input of the op amp. Figure 13 shows the circuit diagram for the specific configuration of the current source 14〇. The current source 14〇 and the capacitor 1〇〇 form a triangular wave generating circuit. D2, switch si And S2, comparisons 141 and 142, and NAND circuits 143 and 144 constitute current source 140. Transistors T1 and T2 are composed of field effect transistors (FETs). Voltages for controlling the charging current value of capacitor 100. Applied to the gate of transistor T1. Voltage VBN for controlling the discharge current value of the capacitor is applied to the closed end of transistor T2. Switches 31 and 32 comprise analog switches, and may be comprised of FETs. Switches 81 and 82 are switched from The flow direction of the current output of the current source 14〇, that is, the charging and discharging of the switching capacitor i 。. The current input/output terminal of the transistor τι, the switches § 1 and 82, and the current input/output terminals of the transistor are connected in series to each other, As shown in Fig. 13, the minus side input terminal of the comparator Η1 and the adder side input terminal of the comparator 142 are connected to the connection point of the switch and S2. The connection point is also connected to the capacitor 1A to constitute an output terminal of the triangular wave generating circuit. Comparing 142 to compare the desired first potential ¥;1 with the potential of the connection point, and outputting the comparison result. The comparator 141 compares the desired second potential vh with the connection point of 95456.doc -41 - 1257765 potential, and take the comparison result. It is assumed that the second potential VH is higher than the first potential VL. The difference between the second potential ¥11 and the first potential VL sets the amplitude of the triangular wave. The NAND circuits 143 and 144 are connected to form a positive The reverse circuit has an input which is an output of the comparators 14A and 142. The output of the flip-flop circuit controls the opening/closing of the switches S1 and S2, that is, the output switching capacitor 100 of the flip-flop circuit. Charging and discharging to switch the rise and fall of the triangular wave. FIG. 14 is a diagram illustrating the operation of current source 140.
百先,說明作為連接點之電位的三角波G低於第一電位 VL(在虛線幻之情形中)時的操作。在虛線^之情形中,比 較器142之輸出變低,導致開關S1開啟,開關s2關閉。從而 充私電流流過電晶體丁丨及開關S1進入電容器1〇〇。因此,作 為電容器100之電位的三角波G上升。 當三角波F超過第一電位VL並到達第二電位¥11時,比較 = 之輸出變低,導致開關S2開啟,開關si關閉。從而電 容器10G之放電電流透過電晶㈣及開關s2流動至接地。因 此,三角波G下降。First, the operation when the triangular wave G as the potential of the connection point is lower than the first potential VL (in the case of a dotted line illusion) will be described. In the case of the dashed line ^, the output of comparator 142 goes low, causing switch S1 to turn on and switch s2 to turn off. Thus, the charging current flows through the transistor and the switch S1 into the capacitor 1〇〇. Therefore, the triangular wave G which is the potential of the capacitor 100 rises. When the triangular wave F exceeds the first potential VL and reaches the second potential ¥11, the output of the comparison = becomes low, causing the switch S2 to be turned on and the switch si to be turned off. Thereby, the discharge current of the capacitor 10G flows to the ground through the electric crystal (4) and the switch s2. Therefore, the triangular wave G is lowered.
…當三角波G到達第一電位VL時,比較器142之輸出變低, 導致開關Si開啟,開關82關閉。&而充電電流再次流動, :角波G上升。—藉由之後重複該等操作,產生如圖14所示之 二角波G。可藉由用於控制放電電流及電容器100之電容的 電壓νΒΝ設定三角波(3下降時的傾斜。 …,丨—私m 即屣綠Κ2之 時的操作。在虛線K2之情形中,比較器⑷之輸出變低 致開關S2開啟’開關S1關閉。從而電容器⑽之放電電: 95456.doc -42- 1257765 過電晶體T2及開關S2。因此,作為電容器1〇〇之電位的三角 波G下降。之後,如上所述,電容器1〇〇之充電及放電重複 並產生如圖14所示之三角波G。 相應地’使用本具體貫施例之D類放大器,可提供具有電 容器100及電流源140構成之簡單結構的三角波產生電路。 因此,效率較高,並且可提供具有低成本之低失真D類放大 器。 接下來,將參考圖15至17說明依據具體實施例4之〇類放 大器的操作。圖丨5至17為波形圖,其顯示圖12所示之d類放 大器的每一部分之操作。 、,圖I5顯示(類比輸入信號+IN)>(類比輸入信號,時,即 差動輸入為正時,_放大器每_部分之波形。三角波⑽ 弟一電位VL最小且第二電位VH最大之三角波。 … 由於孝貝刀為之差動輸入為正,積分器之減側輸出Α與積分 器之加側輸出B相比為低位準。圖15顯示電流源14〇之開關 。及S2的驅動波形。電流源14〇之開闕w對高位準信號作出 ° ;角波〇之上升區段開啟。開關S 1對低位準信號作 出回應,於三自、、由^ > '之下降區段關閉。電流源140之開闕 對低位準信號作屮门虛 汗1 S2M - ^ m 〇 α,於二角波G之上升區段關閉。開關 S2對回位準信號作出 本 α 於二角波G之下降區段開啟。 ::刀:之減側輪“與三角波〇之比較結果為a>g,比 較态112之輪出C變古 ^ 積分器之加側輪出二、比較結果為A<G’輪出C變低。當 器U3之輸出1三角波G之比較結果變為㈣,比較 阿,^比較結果變為B<G,輸出D變低。 95456.doc -43- 1257765 當從比較器112之輸出C反轉的值及比較器113之輪出D 皆較高時,AND電路131之輸出(+〇UT)E變高。因而,當加 侧輸出+OUT為高位準時的週期之負荷比實質上與類比輸 入k號之正值(差動值)振幅成正比。換言之,加側輸出+〇u丁 為類比輸入信號之正值(差動值)的脈衝寬度調變信號。 另方面’當比較為112之輸出及從比較器113之輸出D 反轉的值皆較高時,AND電路132之輸出(-OUT)F變高。此 處’減側輸出-OUT始終為低位準。 圖16顯示(類比輸入信號+INM類比輸入信號-IN)時,即 差動輪入為零時(〇伏特輸入),!)類放大器每一部分之波 形。圖16所示之三角波G與圖15所示之三角波G相同。由於 電流源140之開關S1及S2關於三角波F的操作與圖15所示之 操作相同,圖16中省略了開關S1&S2之驅動信號。 由於積分器之差動輸入為(+IN)==(_in),積分器之減側輸 出A與積分器之加側輸出B具有相同位準。由於輸出A等於 輸出B,比較器112之輸出c與比較器113之輸出〇具有相同 波形以及相同相位。 由於AND電路丨3丨之輸出(+〇UT)E為(輸出c之反相 值)*(輸出D),輸出E在整個週期之大部分中為低位準。由 於輸出(_0UT)F為(輸出〇*(輸出〇之反相值),輸出F在整個 週期之大部分中為低位準。如圖16所示,由於運算放大突 12卜構成比較器112及114之元件以及反相^⑵及⑵之偏 移電壓非全同引起的延遲時間之差異,加側輸出及減 側輸出德具有一些高位準週期。因此,可將加側輸出 95456.doc -44- 1257765 + OUT及減側輸出_〇υτ簡單地假定為在整個週期中為嚴格 的低位準。 如上所述,依據具體實施例4之0類放大器,由於未應用 類比輸入信號時(0伏特值之輸入情形中),輸出信號為高位 準之週期可極為容易地縮短,與具有簡單結構之傳統設備 相比,可大大降低功率損失。 圖17顯示(類比輸入信號+丨州义(類比輸入信號·IN)時,即 差動輸入為負時,D類放大器每一部分之波形。三角波?與 圖15所示之三角波G相同。由於電流源14〇之開關S1及Μ關 於二角波G的操作與圖15所示之操作相同,圖17中省略了開 關S 1及S 2之驅動波形。 積分裔之減側輸出Α與積分器之加側輸出Β相比為高位 準。當積分裔之減側輸出Α與三角波G之比較結果為A>G, 比較為112之輸出C變高,當比較結果為A<G,輸出c變低。 當積分器之加側輸出B與三角波G為B>G,比較gU3之輸出 E變高,當比較結果變為b<G,輸出e變低。 當比較器112之輸出C及比較器in之輸出D的反轉值皆 較高時,AND電路132之輸出(-〇UT)F變高。因而,減側輸 出-OUT為高位準時的週期之負荷比實質上與類比輸入信 號之負值(差動值)振幅成正比。換言之,減側輸出_〇UT為 類比輸入信號之負值(差動值)的脈衝寬度調變信號。 另 方面’當比較器112之輸出C的反轉值及比較器113 之輸出D皆較高時,AND電路131之輸出(+〇υτ)Ε變高。此 處’加側輸出+OUT始終為低。 95456.doc -45- 1257765 如上所述,依據具體實施例4之D類放大器,可藉由將類 比輸入信號轉換為由0伏特值、正值及負值組成的3值PWM 信號而將其輸出。依據具體實施例4之D類放大器,當類比 輸入信號變為除〇伏特值外的一值時,切換波形僅出現於如 圖15及17所示之加側輸出+〇υτ及減側輸出-OUT之一上。 依據具體實施例4之D類放大器,由於電阻R3及R4構成類 比回饋電路,可在良好線性下放大類比輸入信號,而不執 行如日本專利揭示内容第2000-500625號所說明的數位處 理。另外,根據依據具體實施例4之D類放大器,實質上可 消除直接輸出組件,不提供用於阻抗轉換及直接電壓切斷 (例如日本專利公開案第Sho-56-27001號所說明)之變塵 為。因此’可提供低失真、高功率效率之D類放大器。 雖然已參考圖式詳細說明了本發明之具體實施例模式, 其具體結構並不僅限於此具體實施例模式,而顯然可涵蓋 不背離本發明之技術精神的範圍内定義的結構。 例如’儘管上述具體實施例之D類放大器中,積分器由初 級和分杰加以構成,然而本發明並不限於此,積分器可由 咼、、及%刀态加以構成。藉由如此構成,可增加迴路增益並 進一步減小失真率。 上述說明中,本發明已說明為D類放大器,但本發明並不 僅限於此。相應地,本發明可應用於除D類放大器外之信號 處理電路,以及各種脈衝寬度調變放大器。 【圖式簡單說明】 圖1為用於指不依據本發明之具體實施例模式丨的D類放 95456.doc !257765 大為之結構範例的電路圖。 圖2為用於指示在向圖丨所示之〇類放大器施加零伏特時 该〇類放大器之操作的波形圖。 圖3為用於指示在向圖丨所示之〇類放大器施加一正值時 該D類放大器之操作的波形圖。 圖4為用於指示在向圖丨所示之〇類放大器施加一負值時 该D類放大器之操作的波形圖。 圖5為用於表示依據本發明之具體實施例2的〇類放大哭 之結構範例的電路圖。 圖6為用於指示在向圖5所示之〇類放大器施加零伏特時 该D類放大器之操作的波形圖。 圖7 Α至7 C為用於顯示在向依據本發明之具體實施例工或 具體實施例2的D類放大器輸入正弦波時負載内出現之波形 的範例之圖式。 圖8為用於表示依據本發明之具體實施例3的〇類放大器 之結構範例的電路圖。 圖9為用於指示在向圖8所示之1)類放大器施加零伏特時 該D類放大器之操作的波形圖。 圖10為用於指示在向圖8所示之D類放大器施加一正值時 該D類放大器之操作的波形圖。 圖11為用於指示在向圖1所示之D類放大器施加一負值時 該D類放大器之操作的波形圖。 圖12為用於表示依據本發明之具體實施例4的〇類放大器 之結構範例的電路圖。 95456.doc -47- 1257765 圖13為用於表示D類放大器之電流源的結構範例之電路 圖。 圖14為顯示電流源之操作的波形圖。 正值時的操作之波形圖。 伏特時的操作之波形圖。 負值時的操作之波形圖。 圖15為顯示向D類放大器施加一 圖16為顯示向d類放大器施加零 圖17為顯示向d類放大器施加— 【主要元件符號說明】 1 輸出 11 運算放大器 12 比較器 13 比較器 21 延遲電路 22 延遲電路 31 AND電路 32 AND電路 61 運算放大器 62 比較器 63 比較器 64 運算放大器 71 AND電路 72 AND電路 100 電容器 112 比較器 113 比較器 95456.doc -48- 1257765 121 反相器 122 反相器 131 AND電路 132 AND電路 140 電流源 141 比較器 142 比較器 143 NAND電路 144 N AND電路 VL 第一電位 VH 第二電位 e 第一合成波 f 第二合成波 g 第三合成波 h 第四合成波 T1 包曰日涯 T2 電晶體 Cl 電容器 C2 電容器 C51 電容器 C100 電容器 V BH 電壓 VBn 電壓 VBp 電壓When the triangular wave G reaches the first potential VL, the output of the comparator 142 goes low, causing the switch Si to open and the switch 82 to be closed. & and the charging current flows again: the angular wave G rises. - By repeating these operations thereafter, a dihedral wave G as shown in Fig. 14 is produced. The operation of the triangular wave (the tilt at the time of the fall) is set by the voltage νΒΝ for controlling the discharge current and the capacitance of the capacitor 100. In the case of the dotted line K2, the comparator (4) The output becomes low and the switch S2 is turned on. 'The switch S1 is turned off. Thus the discharge of the capacitor (10): 95456.doc -42 - 1257765 The transistor T2 and the switch S2. Therefore, the triangular wave G which is the potential of the capacitor 1 下降 falls. As described above, the charging and discharging of the capacitor 1 重复 repeats and generates a triangular wave G as shown in FIG. 14. Accordingly, the capacitor 100 and the current source 140 can be provided by using the D-type amplifier of the present embodiment. A triangular wave generating circuit of a simple structure is therefore high in efficiency and can provide a low distortion class D amplifier having a low cost. Next, the operation of the 〇 class amplifier according to the specific embodiment 4 will be explained with reference to Figs. 5 to 17 are waveform diagrams showing the operation of each part of the class D amplifier shown in Fig. 12. Fig. I5 shows (analog input signal + IN) > (analog input signal, time, that is, differential When the input is positive, the waveform of each _ section of the _ amplifier is triangular wave (10) The triangular wave with the lowest potential VL and the second potential VH is the largest.... Since the differential input of the filial knife is positive, the output of the integrator is reduced. The integrator's side-side output B is lower than the level. Figure 15 shows the current source 14〇 switch and the S2 drive waveform. The current source 14〇's opening w is used to make a high level signal; The segment S1 is turned on. The switch S1 responds to the low level signal, and is turned off by the falling section of the ^^, '^ > '. The opening of the current source 140 acts as a tricky sweat for the low level signal 1 S2M - ^ m 〇α , in the rising section of the two-dimensional wave G is closed. The switch S2 makes the return of the leveling signal to the falling section of the two-dimensional wave G. :: knife: the side wheel of the reduction is compared with the triangular wave a a> ;g, the round of the comparison state 112 is changed to C. The side of the integrator is rounded out, and the comparison result is A<G', and C is low. When the output of the U3 is changed, the result of the comparison is changed to (4). Comparing, the comparison result becomes B<G, and the output D goes low. 95456.doc -43- 1257765 When from the comparator 112 When the value of the output C inversion and the rounding D of the comparator 113 are both high, the output (+〇UT)E of the AND circuit 131 becomes high. Therefore, the duty ratio of the period when the side output +OUT is high is high. It is substantially proportional to the amplitude of the positive value (differential value) of the analog input k. In other words, the plus side output + 〇u is a pulse width modulation signal that is analogous to the positive value (differential value) of the input signal. When the value of the comparison 112 is inverted and the value inverted from the output D of the comparator 113 is higher, the output (-OUT) F of the AND circuit 132 goes high. Here, the minus side output - OUT is always low. Figure 16 shows (analog input signal + INM analog input signal - IN), that is, when the differential wheel is zero (〇 volt input)! ) The waveform of each part of the class amplifier. The triangular wave G shown in Fig. 16 is the same as the triangular wave G shown in Fig. 15. Since the operations of the switches S1 and S2 of the current source 140 with respect to the triangular wave F are the same as those shown in Fig. 15, the drive signals of the switches S1 & S2 are omitted in Fig. 16. Since the differential input of the integrator is (+IN) == (_in), the reduced side output A of the integrator has the same level as the added side output B of the integrator. Since the output A is equal to the output B, the output c of the comparator 112 has the same waveform and the same phase as the output 比较 of the comparator 113. Since the output of the AND circuit (3丨 (+〇UT)E is (inverted value of output c)* (output D), the output E is low in most of the entire cycle. Since the output (_0UT)F is (output 〇* (inverted value of the output 〇), the output F is low in most of the entire cycle. As shown in FIG. 16, the operational amplifier 12 constitutes the comparator 112 and The difference between the delay time caused by the components of 114 and the offset voltages of the inverting ^(2) and (2), the side output and the side output have some high level periods. Therefore, the side output can be 95456.doc -44 - 1257765 + OUT and the subtraction side output _〇υτ are simply assumed to be strictly low levels throughout the cycle. As described above, according to the class 0 amplifier of the specific embodiment 4, since the analog input signal is not applied (0 volt value) In the case of the input), the period in which the output signal is at a high level can be extremely easily shortened, and the power loss can be greatly reduced as compared with the conventional device having a simple structure. Figure 17 shows (analog input signal + 丨州义 (analog input signal) ·IN), that is, when the differential input is negative, the waveform of each part of the class D amplifier. The triangular wave is the same as the triangular wave G shown in Fig. 15. The operation of the switch S1 and Μ of the current source 14〇 with respect to the two-dimensional wave G versus The operation shown in Fig. 15 is the same, and the driving waveforms of the switches S 1 and S 2 are omitted in Fig. 17. The reduced side output 积分 of the integral person is higher than the added side output Β of the integrator. The comparison result of Α and triangular wave G is A>G, the output C of comparison is higher, and when the comparison result is A<G, the output c becomes lower. When the adder side of the integrator B and the triangle wave G are B>G, Comparing the output E of gU3 becomes high, when the comparison result becomes b<G, the output e goes low. When the output C of the comparator 112 and the inverted value of the output D of the comparator in are both high, the output of the AND circuit 132 (-〇UT)F becomes high. Therefore, the duty ratio of the period when the minus-side output -OUT is high is proportional to the amplitude of the negative value (differential value) of the analog input signal. In other words, the side output _〇UT The pulse width modulation signal is a negative value (differential value) of the analog input signal. On the other hand, when the inverted value of the output C of the comparator 112 and the output D of the comparator 113 are both high, the output of the AND circuit 131 (+〇υτ)Ε becomes high. Here, the plus side output +OUT is always low. 95456.doc -45- 1257765 As described, the class D amplifier of the fourth embodiment can be output by converting the analog input signal into a 3-valued PWM signal consisting of 0 volts, positive and negative values. The amplifier, when the analog input signal becomes a value other than the 〇 volt value, the switching waveform appears only on one of the plus side output + 〇υ τ and the minus side output - OUT as shown in FIGS. 15 and 17 . In the class D amplifier of the example 4, since the resistors R3 and R4 constitute an analog feedback circuit, the analog input signal can be amplified in a good linearity without performing the digital processing as explained in Japanese Patent Laid-Open Publication No. 2000-500625. Further, according to the class D amplifier according to the specific embodiment 4, the direct output module can be substantially eliminated, and the change for impedance conversion and direct voltage cut (for example, as described in Japanese Patent Laid-Open No. Sho-56-27001) is not provided. Dust is. Therefore, a Class D amplifier with low distortion and high power efficiency can be provided. While the specific mode of the present invention has been described in detail with reference to the drawings, the specific structure is not limited to the specific embodiment mode, and it is obvious that the structure defined in the scope of the technical spirit of the present invention can be covered. For example, although in the class D amplifier of the above specific embodiment, the integrator is composed of primary and secondary, the present invention is not limited thereto, and the integrator may be constituted by 咼, , and %. With this configuration, the loop gain can be increased and the distortion rate can be further reduced. In the above description, the present invention has been described as a class D amplifier, but the present invention is not limited thereto. Accordingly, the present invention is applicable to signal processing circuits other than class D amplifiers, as well as various pulse width modulation amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram for an example of a structure in which a class D of a specific embodiment of the present invention is not used in accordance with the mode of the present invention. Fig. 2 is a waveform diagram for indicating the operation of the scorpion amplifier when zero volts is applied to the sigma type amplifier shown in Fig. 。. Fig. 3 is a waveform diagram for indicating the operation of the class D amplifier when a positive value is applied to the thyristor shown in Fig. 。. Fig. 4 is a waveform diagram for indicating the operation of the class D amplifier when a negative value is applied to the thyristor shown in Fig. 。. Fig. 5 is a circuit diagram showing an example of a structure for amplifying a crying of a scorpion according to a second embodiment of the present invention. Fig. 6 is a waveform diagram for indicating the operation of the class D amplifier when zero volts is applied to the steroid type amplifier shown in Fig. 5. 7 to 7C are diagrams for showing an example of a waveform appearing in a load when a sine wave is input to a class D amplifier according to a specific embodiment of the present invention or the specific embodiment 2. Fig. 8 is a circuit diagram showing an example of the structure of a thyristor amplifier according to a third embodiment of the present invention. Fig. 9 is a waveform diagram for indicating the operation of the class D amplifier when zero volts is applied to the class 1) amplifier shown in Fig. 8. Figure 10 is a waveform diagram for indicating the operation of the class D amplifier when a positive value is applied to the class D amplifier shown in Figure 8. Figure 11 is a waveform diagram for indicating the operation of the class D amplifier when a negative value is applied to the class D amplifier shown in Figure 1. Fig. 12 is a circuit diagram showing an example of the structure of a thyristor amplifier according to a fourth embodiment of the present invention. 95456.doc -47- 1257765 FIG. 13 is a circuit diagram showing an example of the structure of a current source of a class D amplifier. Figure 14 is a waveform diagram showing the operation of a current source. Waveform of the operation at positive values. Waveform of operation at volts. Waveform of operation at negative values. Figure 15 shows the application to the Class D amplifier. Figure 16 shows the application of zero to the class D amplifier. Figure 17 shows the application to the class D amplifier. [Main component symbol description] 1 Output 11 Operational amplifier 12 Comparator 13 Comparator 21 Delay circuit 22 delay circuit 31 AND circuit 32 AND circuit 61 operational amplifier 62 comparator 63 comparator 64 operational amplifier 71 AND circuit 72 AND circuit 100 capacitor 112 comparator 113 comparator 95456.doc -48- 1257765 121 inverter 122 inverter 131 AND circuit 132 AND circuit 140 Current source 141 Comparator 142 Comparator 143 NAND circuit 144 N AND circuit VL First potential VH Second potential e First synthesized wave f Second synthesized wave g Third synthesized wave h Fourth synthesized wave T1 package 曰 涯 T2 transistor Cl capacitor C2 capacitor C51 capacitor C100 capacitor V BH voltage VBn voltage VBp voltage
95456.doc -49- 1257765 R 電阻器 R1-R12 電阻器 R51-R56 電阻器 + OUT 加側輸出 +IN 加側輸入端子 -OUT 減側輸出 -IN 減側輸入端子 A 減側輸出 B 加側輸出 SI 開關 S2 開關 F 三角波 G 三角波 a 三角波信號 b 三角波信號 a丨 三角波信號 bf 三角波信號 tl 時刻 tl, 時刻 tl’, 時刻 t2 時刻 t2f 時刻 t2,f 時刻 t3 時刻 95456.doc -50- 1257765 t3, 時刻 t3’’ 時刻 t4 時刻 t4f 時刻 t4ff 時刻 t5, 時刻 t5M 時刻 t6f 時刻 t6,f 時刻 c 輸出 d 輸出 C 輸出 D 輸出 E 輸出 j 輸出 k 輸出 NOUT 輸出 POUT 輸出95456.doc -49- 1257765 R Resistor R1-R12 Resistor R51-R56 Resistor + OUT plus side output +IN plus side input terminal -OUT minus side output -IN minus side input terminal A minus side output B plus side output SI switch S2 switch F triangle wave G triangle wave a triangle wave signal b triangle wave signal a 丨 triangle wave signal bf triangle wave signal tl time t1, time t1, time t2 time t2f time t2, f time t3 time 95456.doc -50 - 1257765 t3, time T3'' time t4 time t4f time t4ff time t5, time t5M time t6f time t6, f time c output d output C output D output E output j output k output NOUT output POUT output
95456.doc -51 -95456.doc -51 -
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TW93136627A TWI257765B (en) | 2003-11-26 | 2004-11-26 | Class-D amplifier |
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ATE521133T1 (en) | 2005-09-28 | 2011-09-15 | Yamaha Corp | CLASS D AMPLIFIER |
US7778324B2 (en) * | 2005-11-18 | 2010-08-17 | Harman International Industries, Incorporated | System for dynamic time offsetting in interleaved power amplifiers |
CN100586008C (en) * | 2007-05-09 | 2010-01-27 | 埃派克森微电子有限公司 | Switch amplifier and its modulation method |
JP4466695B2 (en) * | 2007-08-08 | 2010-05-26 | ヤマハ株式会社 | Class D amplifier circuit |
CN101453194B (en) * | 2007-11-30 | 2011-05-04 | 无锡华润矽科微电子有限公司 | Non-filter circuit construction for D type power amplifier and processing method thereof |
CN101615893B (en) * | 2008-06-24 | 2011-11-09 | 瑞昱半导体股份有限公司 | Amplifier using delta-sigma modulation and method for adjusting errors of same |
JP2011066558A (en) * | 2009-09-15 | 2011-03-31 | Yamaha Corp | Class-d amplifier |
CN101710824B (en) * | 2009-12-17 | 2013-03-20 | 智原科技股份有限公司 | Class D amplifier |
JP5388362B2 (en) * | 2010-03-11 | 2014-01-15 | パナソニック株式会社 | Digital amplifier |
CN101977025A (en) * | 2010-11-02 | 2011-02-16 | 苏州顺芯半导体有限公司 | Method and device for eliminating noise in class-D power amplifier |
CN102082553B (en) * | 2011-02-28 | 2014-04-09 | 中国科学院等离子体物理研究所 | Integrator of differential input |
US8330541B2 (en) * | 2011-03-01 | 2012-12-11 | Maxim Integrated Products, Inc. | Multilevel class-D amplifier |
EP2654205B1 (en) * | 2012-04-16 | 2016-08-17 | Nxp B.V. | Class D Amplifiers |
CN104604127B (en) * | 2012-09-04 | 2017-05-31 | 康塔普罗纳特有限公司 | Sine and cosine modulator |
CN104641552B (en) * | 2012-09-21 | 2017-06-16 | 三菱电机株式会社 | Analog feedback amplifier |
CN102832894B (en) * | 2012-09-25 | 2015-09-30 | 上海贝岭股份有限公司 | A kind of D class power-magnifying method |
CN102832893B (en) * | 2012-09-25 | 2015-07-08 | 上海贝岭股份有限公司 | D-type power amplifier |
CN104065353A (en) * | 2013-03-22 | 2014-09-24 | 意法半导体研发(深圳)有限公司 | Mute-starting class-D amplifier |
CN110708022A (en) * | 2015-05-08 | 2020-01-17 | 意法半导体研发(深圳)有限公司 | High efficiency class D amplifier with reduced EMI generation |
CN105953917B (en) * | 2016-05-12 | 2017-11-24 | 中国科学院武汉物理与数学研究所 | Differential type signal screening circuit for mercury ion microwave frequency marking fluorescence detection |
KR102093022B1 (en) * | 2018-05-17 | 2020-03-24 | 한양대학교 산학협력단 | Time domain continuous-time delta-sigma modulator and method of driving the same |
CN112910427A (en) * | 2021-01-13 | 2021-06-04 | 上海艾为电子技术股份有限公司 | Class D audio amplifier, adaptive pulse width adjusting method thereof and electronic equipment |
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JPS54107661A (en) * | 1978-02-13 | 1979-08-23 | Michio Morimoto | Pulse duration modulator |
JPS62186607A (en) * | 1986-02-12 | 1987-08-15 | Yokogawa Electric Corp | Triangular wave generator |
JPH0728181B2 (en) * | 1988-12-28 | 1995-03-29 | パイオニア株式会社 | Pulse width modulation amplifier circuit |
JPH0570019U (en) * | 1992-02-27 | 1993-09-21 | 日本ビクター株式会社 | Pulse width modulation power amplifier |
JP3250468B2 (en) * | 1996-10-17 | 2002-01-28 | 日本電気株式会社 | OSD circuit |
JP3516878B2 (en) * | 1999-03-16 | 2004-04-05 | シャープ株式会社 | Switching amplifier using ΔΣ modulation |
JP4161545B2 (en) * | 2001-06-07 | 2008-10-08 | サンケン電気株式会社 | Switching amplifier |
-
2004
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CN100468960C (en) | 2009-03-11 |
JP5229298B2 (en) | 2013-07-03 |
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