TWI257765B - Class-D amplifier - Google Patents

Abstract

The present invention discloses a class-D amplifier, which includes an operational amplifier and a capacitor that jointly constitutes an integrator for generating an integral of difference between an input signal from a plus side and a input signal from a minus side forming an analog input signal, a delay circuit for delaying a phase of a triangular wave a desired infinitesimal angle, a resistor for constituting a synthesizing circuit for synthesizing a output of the integrator, the triangular wave and an output of the delay circuit, a comparator for mutually comparing outputs of the synthesizing circuit, an AND circuit constituting a buffer for inputting an output of the comparator, and a feedback resistor feeding an output of the buffer back to an input side of the integrator.

Description

1257765 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a class D amplifier. [Prior Art] Class D amplification performs power amplification by pulse-width modulation (PWM), and is used to perform power amplification of the voice signal. As a conventional class D amplifier, one such class D amplifier is configured as an integrator for integrating an analog input signal, a comparator for comparing the output signal of the integrator with a predetermined triangular wave, and for amplifying the output of the comparator 5 tigers to output a pulse signal buffer (pulse amplifier). In this conventional D-maximum, the pulse signal output from the buffer is fed back to the input side of the integrator. Next, a low-pass filter constructed of coils and capacitors filters the output signal for the analog signal to obtain an analog signal such as a speaker. As a conventional pulse width modulation amplifier, one such PWM amplifier is configured to compare a comparator input signal with a triangular wave comparator, to amplify an amplifier that is more than a wheel, and to configure between the amplifier and the load. [(for example, 'Mcco Japanese Patent Publication No. Sho-56-27001). In addition, as a conventional digital amplifying circuit using a digital signal processing circuit, such a digital amplifying circuit is provided with a noise shaping device, a converter, a logic circuit, a switch, and a filter (for example, refer to Japanese Patent Publication No. No. 2 00_5〇〇 625). The noise shaper performs frequency shaping on the quantization of the digital input signal. The converter converts the PCM (Pulse Code Modulation) signal corresponding to the output of the noise shaper into a PWM (Pulse Width Modulation) signal. 95456.doc 1257765 i Logic circuit compensates for the linearity of the round-out signal of the converter. The switch is controlled by the rotation of the logic circuit. Connect the input side of the filter to the power supply with a switch. In the above conventional class D amplifier, the buffer is composed of two buffers, that is, a side buffer and a side buffer. Even when there is no input signal, the two buffer outputs, such as X, have signals of opposite polarity with a duty ratio of 50/〇. Therefore, in a conventional class D amplifier, even in the absence of an input signal, current can pass through the low pass filter, which results in a large loss. In the Japanese Patent Publication No. Sho_56-27001, the technical concept of turning off the output amplifying element when there is no input signal is explained in order to avoid power loss without input signal 2. However, the conventional pulse-sensing amplifier described in the above patent publication has a problem that a transformer is required to convert the impedance and cut off the DC voltage, which increases the scale of the device and increases its cost. In addition, the conventional pulse width modulation amplifier described in the Japanese Patent Publication No. Sho-56-27001 has another problem that the distortion of the output signal is large due to the relatively simple triangular wave and the input signal of the comparator. On the other hand, the digital amplifier circuit described in Japanese Patent Laid-Open Publication No. 2-5-625 uses an output state of three values or four values (switching state), and amplifies the digital input signal, and the logic circuit Equal-digit circuits are used to improve linearity. Therefore, the digital amplifying circuit described in Japanese Patent Laid-Open No. Hei. No. 255-625 has a problem in that the digital amplifying circuit cannot be configured by using an analog circuit, so that the analog input signal cannot be amplified while maintaining More linear. In other words, in this conventional digital amplifying circuit, when a smaller signal pulse is input, the output switching distortion in the circuit is compensated for by adding a compensation pulse to the smaller signal pulse. However, it is used to compensate the φ mu, ..., bristle path by only using a digital circuit such as a logic circuit, so the conventional digital amplifying circuit cannot amplify the analog input signal under a better linear condition. SUMMARY OF THE INVENTION The above problems are solved on the following day, and thus a class D amplifier that can operate with low distortion and low power loss will be provided. Another two: The present invention will provide a class D amplifier that can operate with low distortion and low power loss. ^ 卜 ⁄ 明 将 将 将 将 ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ 将 ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ = In view of the above problems, the class d amplifier of the present invention has the following structure. (1)-D-class amplifier, comprising: an integrator that integrates an analog input signal;: a rut that is compared to the integrator-round and - second angular wave; the taster is, which compares the integral The output of the device is a second three-wave, and the second triangular turbidity-one-one angle wave temple is hunted by the angle of one of the first-triangle waves by an angle (180 degrees plus _ pole waveform; ) angle, or a very small negative angle obtained by the device, which outputs the output according to the output of the first comparator and the second ratio - the side output signal and the minus side wheel output signal; a feedback circuit, The 输出 趑 , t ^ one of the lambda door clock, ° ° ° Bay 'output signal and the minus side output signal are fed back to the input side of the integrator. 95456.doc 1257765 (2) A first buffer of the class D amplifier according to (1), which calculates a logical product of the output of the first comparator, a result of one of the numbers; and wherein the buffer includes The output of the comparator, the second output, is the logical product of the output of the output-disk comparator of the first-comparator, and the output is for the side: One of the calculation results. The example rounds out k (7) according to the class D amplifier of (1) where the feedback circuit includes a differential amplifier which is used to amplify a difference between the added side output signal and the reduced side output signal. (4) A class D amplifier comprising: an integrator that forms a difference integral between an analog input signal and a subtraction side input signal; a delay circuit that delays a phase of one of the triangular waves; The side input signal is predetermined to be a very small angle, one of the synthesis circuit delay circuits is input to a comparator, and the comparison is performed; the synthesis is performed to output a plurality of output signals; and the plurality of output circuits of the synthesis circuit are rotated: It inputs an output of the comparator; and a feedback circuit that feeds one of the buffer outputs back to the input side. The integrator (5) is based on the class D amplifier of (4), wherein: the triangular wave is composed of a first triangular wave and a second binary wave. The second 95456.doc 1257765 triangular wave corresponds to the first triangular wave Phase shift (10) A waveform generated at an angle; further the delay circuit includes a first delay circuit for delaying the phase of the first wave by the predetermined minimum degree, and - a second delay ^ The angle is used to delay the phase of one of the third triangular waves by the predetermined minimum angle ', and the synthesizing circuit synthesizes the minus side wheel of the integrator and the third: wave to generate a synthesized wave; synthesizing the integral to cry a second triangular wave to generate a second person into a wave: a class output and a wave of the king's mouth, synthesizing the output of the integrator and reducing the output of one of the second delay circuits to generate a third Synthesizing the wave; and synthesizing the added side output of the integrator with the first delay circuit: an output to generate a fourth composite wave; privately = the comparator includes a comparator for comparing the first synthesized wave with The second composite wave; and one a comparator for comparing the third composite wave with the fourth composite wave; the buffer includes a first buffer for calculating an output of the first comparator and the second comparator a logical product of the output; and a first buffer for calculating a logical product of the output of the first comparator and the output of the second comparator; and the readback circuit includes a first feedback circuit And the second feedback loop is used to feed the output of the second buffer to the integrator. (6) - Class D amplifier, comprising: an integrator pairing one of an analog input signal with a side input signal 95456.doc -10- 1257765 and a subtraction side input signal a composite circuit that synthesizes one of the integrator outputs and a triangular wave, and synthesizes the output of the integrator and a triangular wave having a phase opposite to the first mentioned triangular wave to output a plurality of signals, wherein The opposite phase The triangular wave corresponds to a waveform whose phase is shifted by 180 degrees with respect to the phase of the first mentioned triangular wave; a comparator which compares the output signals of the combining circuit with each other; a buffer which outputs one of the outputs of the comparator Wherein; and a feedback circuit that outputs one of the buffers back to the input side of the integrator;

And configured to generate a phase difference between the signals corresponding to the composite circuit based on one of the plurality of resistors. The resistance value of the temple and the complex number of the output of the comparison path (7) according to the class 6 amplifier of (6), wherein:

a minus side output and the triangular wave to produce the integral for synthesizing the integral

Forming the wave; the first-compositing portion includes a first resistor's one terminal and the integral 95456.doc 1257765 benefiting the minus side wheel connection, and a first wave applied to its terminal; The first-resistor = :: = = is connected to the first - + M knife to the other terminal of the resistor-resistance, so as to constitute its device:: the two-composite part includes - the third resistor, its - terminal and :: a split/plus side output connection, and a fourth resistor, wherein the triangle is applied: its one terminal; and the other terminal of the third resistor is connected to: the other end of the fourth resistor Forming an output terminal thereof; the crying brother two synthesizing portion includes a fifth resistor 'the terminal thereof and the integral; the money side output connection, and a sixth resistor, wherein the opposite eye triangle wave is applied to one of the terminals And connecting the child of the fifth resistor to the other terminal of the sixth resistor to form an output terminal thereof; the fourth composite portion includes a seventh resistor, a terminal of the _ terminal and the integral Add a side output connection, and an eighth resistor, Applying the triangular skin to its one terminal; and connecting the other terminal of the seventh resistor to the other terminal of the 4-person resistor to constitute its output terminal; the comparison includes the -first comparator 'It has an input terminal connected to the first synthesis portion, and an additional input terminal connected to the wheel terminal of the second synthesis portion; and - a second comparison\ (d) an input of the three-synthesis portion of the wheel terminal connection, such as a sub-' and another input terminal connected to the output terminal of the fourth synthesis portion; the buffer includes a first buffer for calculating the a comparator-output and a logical product outputted by one of the second comparators; and a 95456.doc -12 - 1257765 second buffer for calculating the t-seat And the output is a logical product of the output of the second ratio ;; the feedback circuit includes a -th feedback circuit, the output of the device is fed back to the plus side input of the integrator; : a feed circuit for The second buffer is less w&quot; recognizes that the output is fed back to the off-side input of the integrator; and the 5 Hz first resistor, the second resistor, the second resistor, and the fourth package One of the "electrical" % 弟 五 five resistors, the sixth resistor, the seventh resistor, and one of the eighth resistors has a resistance value of 0 =) according to the class D amplifier of (7), The resistance value of each of the _ resistor, the second resistor, the third resistor, and the fourth resistor is the fifth resistor, and the second resistor And the resistance value of each of the seventh resistor and the eighth resistor is multiplied by a resistance value obtained by dividing one value. (9) A class D amplifier comprising: an integrator that forms a difference integral between one of the analog input signals and a side input signal and a subtraction side input signal; a two-dimensional wave generating circuit including one a current source and a capacitor; a comparator that compares one of the output of the integrator with an output of the triangular wave generating circuit; a buffer 'which inputs an output of the comparator; and a feedback circuit that buffers the buffer One of the outputs is fed back to one of the input sides of the integrator. 95456.doc -13- I257765 (10) The class D amplifier of (9), wherein one end of the capacitor is connected to one of the input terminals of the comparator, and the current source switches one direction of the output current to repeat the Charging and discharging of capacitors. (11) The class D amplifier according to (10), wherein: one end of the turbulent current source is connected to the one end of the capacitor, and the current source is along the capacitor when a potential of the capacitor is lower than a first potential A current flows in one direction of charging, a current flows in one direction of discharging the capacitor when the potential of the capacitor is higher than a second potential, and the second potential is at the first potential. (12) The class D amplifier of (9), wherein: the comparator includes a first comparator for comparing one of the inverting outputs of the integrator with the output of the triangular wave generating circuit, and a second comparison And comparing the output of one of the integrators to the output of the triangular wave generating circuit, the buffer comprising a first buffer for calculating an -inverted value of the output of the first comparator And a logical multiplication product of one of the outputs of the second comparator; and a second buffer for calculating a logical product of an inverted value of one of the first comparator and the second comparator, and the The feedback circuit includes a first feedback circuit for buffering the first buffer. The output is fed back to one of the inverting inputs of the integrator, and a second feedback circuit for outputting the output of the second buffer back to one of the integrators plus the side input. According to the present invention, it is possible to provide a class D amplifier capable of operating at low distortion and with low power loss, 95456.doc -14 - 1257765. In addition, the present invention can provide a 〇-type amplifier that can operate with low distortion and low power loss without using a transformer, and the voltage component in its output can be reduced to substantially zero volts. [Embodiment] Various specific embodiment modes of the present invention will now be described with reference to the drawings. DETAILED DESCRIPTION OF THE INVENTION Fig. 1 is a circuit diagram for showing an example of the structure of a specific embodiment according to the present invention. The class D amplifier is provided with resistors R1, R2, R3, R4, R6, Μ, R8, R9, R1 〇, RU and R12, a capacitor and an operational amplifier 11, comparators 12 and 13, a delay circuit 21 and 22. Edit the circuit (low activity) 3! and the other-AND circuit 32. In this figure, the predetermined triangular wave signals "a" and "b" are respectively applied to one of the terminals of the resistor R9 & RU. The triangular wave signal "a" and the two-corner signal "b" are such signals having the same waveform, and their phases are different by 180 degrees from each other. The terminals of the resistors R1 and R2 respectively constitute a differential input terminal of the class member than the input signal. Therefore, the electric (four) R1 material constitutes the terminal (+IN) of the resistor R2, and the terminal constitutes the side wheel terminal (_iN). The large 11 and the capacitors C1 and C2 form an integrator. This product is divided into analog input signals for which the resistors R1 and R2 have been differentially input, and the integral is output to the resistors R5, R6, R7 and R8. °Rener resistors R5, R6, R7, R8, R9, Rl〇, ρ 7 Ώ R11 and R12 form the integrator of the human loyalty road 'the synthetic two-dimensional wave ^ number "a'" or "b, blood" The output is 95456.doc -15- 1257765 signal. A triangular wave signal, "" and "b" are generated by extending the triangular wave letter "hu" and the triangular wave signal "b" by a small angle "Θ" (ie, θ &lt;&lt; 180 degrees), and the synthesis circuit generates the first to The fourth total of four synthetic waveforms "two" ° "g", "h". ", f", by synthesizing the subtraction side binary wave signal "a" (first triangular wave) of the operational amplifier u constituting the integrator to generate the first composite wave "e" and synthesizing the operational amplifier η which constitutes the integrator The side combined output signal: "three: wave b" (second triangle wave) produces a second composite wave "f". The reduced side output signal of the operational amplifier n which constitutes the integrator is 80% and the triangular wave = f b". The third synthesized wave "g" is generated. The fourth synthesized wave "匕" is generated by synthesizing the added side output signal of the operational amplifier 11 constituting the integrator and by delaying the triangular wave signal "the generated binary wave signal ra'". The comparator 12 (first comparator) compares the first synthesized wave "~ with the second synthesized wave "f" to output a comparison result. When the first synthesized wave "e" is greater than the second synthesized wave "f", the first comparator 12 outputs a predetermined "low" level signal (the regular level) and when the first synthesized wave "e" is smaller than When the second synthesized wave "f", the first comparator 12 outputs a predetermined "high" level signal. The comparator 13 (the first comparator) compares the third synthesized wave "g" with the fourth synthesized wave "h" to input a comparison result. When the third synthesized 纟 "g" is greater than the fourth synthesized wave "h", the first comparator 13 outputs a predetermined "low" level signal (for example, a zero level), and the § second synthesized wave rg" is smaller than the first When the four synthetic waves "h", the second comparison is 13 rounds of a predetermined "high" level signal. Comparators 12 and 13 can also be implemented by using an operational amplifier. The AND circuit 3 1 corresponds to a buffer 95456.doc 1257765 buffer circuit having an AND gate function of a negative logic input. Next, the circuit 31 performs a side calculation (low activity), and when the output of the first comparator 12 and the output of the second comparator 13 are "low", the AND circuit 31 is at Φ "古_包塔31" The same level signal is output, and the result of this calculation is output as the tearing of the side of the d-type device. The resistors form a first-feedback circuit. The first-return circuit feeds the output of the AND circuit 31, which serves as a buffer, to the add-side input of the operational amplifier. And circuit 32 corresponds to a buffer circuit having an AND calculation function, and performs ΑΝβ calculation between the output of the comparison S12 and the output of the comparison ^13, and then outputs the calculation result as the side output of the Α class Α|| OUT". Resistor R4 forms a second feedback circuit. The second feedback circuit feeds the output of the AND circuit 32, which serves as a buffer state, to the subtraction side input of the operational amplifier 丨丨. "Connect the load (speaker, etc.) via the low-pass filter between the + side 输出τ of the class D amplifier and the minus side output "-OUT". Due to the use of these circuit configurations, this Class D amplifier can amplify the analog input signals "+IN" and "-INj with low distortion without using a transformer, and can also drive the load while reducing power loss. Next, the tea test 2 to 4 illustrate an example of the operation of the class D amplifier using the above configuration in accordance with this embodiment. Fig. 2 to Fig. 4 are waveforms for explaining the operation of the individual circuit portions of the class D amplifier shown in Fig. 1. Figure 2. Next, when the value of the analog input signal "+IN" is equal to the value of the analog rounding signal "-IN", that is, when the differential input becomes zero volts (no rounding signal) 'D The waveform of the individual circuit part of the class amplifier. Figure 3 represents the individual circuit part of the class D amplifier when (analog input signal "+IN") &gt; (analog input signal "_IN"), that is, when the differential input 95456.doc -17 - 1257765 becomes positive Although the waveform (analog input signal "+IN") &lt; (the analog input signal "is two differential input becomes negative, the wave of the individual circuit part of the _ amplifier / when first, will explain the operation of Figure 2 , that is, no differential input, 10 volts input). Triangle wave selection "(The phase of the "Tiger"" and the triangle signal "b phase difference of 180 degrees. Two since, by # %" #"—Angle wave 仏 a" constitutes a signal generated by delaying the triangle ## a" by a very small angle "ψ一ψ;ψAA ° f卢", suspected one". Triangle wave letter..." Hunting delays the triangular wave signal "a" by a very small angle "one f: this signal. In this case, a predetermined cloth called "fibrillation" can also be applied to the two-corner method, the application of the signal... , b and b'. Because of this, the distortion of the triangular wave signal a, a, Wb, ..., the skin distortion. It is also possible to use the sawtooth waveform, the integrated waveform crying wave signal "~~", and the integrator output side (operational amplification: plus side wheeling). The phase relationship between "d" is substantially equal to each other. The phase relationship between the signal "b", "M with this 拄 抑 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The two inputs are equal to each other. The inputs of Hi2 and 13 are the first to fourth synthetic waves e, f, g, and h: ', and the waveforms of the rounds of the Bianyi are synthesized. Therefore, the phase of the 'first synthesized wave' The phase difference between the second person and the mouth f f f is about 180 degrees. The phase of the third combination is about 180 degrees from the phase of the synthetic wave "h". The first synthetic turbidity r is ^ ^ e" The waveform is substantially equal to the waveform of the fourth synthetic wave "h", and the phases of the Wangzhe, Sidi- and the fourth synthetic wave "〇" and "h" are very small and angular "β ^ again". The waveform of the synthesized wave "f" is substantially equal to the waveform of the three composite waves "g" of the 95456.doc -18 - 1257765, the second and third The phases of the synthesized waves "f" and "the phase are different from each other by a small angle "Q. The output "j" of the comparator 12 is (first synthesized wave "e")&gt; (the second synthesized wave "W" becomes "low". In the (first synthesized wave "e") &lt; (the second synthesis becomes "high". The output "k" of the comparator 13 is (the third synthesized wave "g") &gt; (the fourth synthesized wave "h" ") becomes "his. / g" when it becomes "low composite wave "h") &lt; (fourth "") is called "back". When the output of the comparator is "乜 and 1 is "low" At the time, the output (-0UT) of the AND circuit 31 becomes "words." When the outputs "j" of the comparators 12 and 13 and the output (+OUT) of the "古°" path 32 become "high". ~同同日守,娜电 In other words, the class side of the class D amplifier becomes a high level during the side-rounding cycle, when the keeper "~ and the second synthetic wave "f" gate ^synthesis wave" The father is again (the time "t - wave "g" and the fourth composite wave " brother 2" ~). This _ amplifier in the side of the reduction wheel out of the factory point (the time period becomes 仂i β 出 -〇 UT" Mountain between the time of the week and the second synthetic wave "f". I am a composite wave "e" for the younger brother, and "the father is again (time "t3丨") to the second A "Jebo g" and the fourth synthetic wave, ") to the younger brother into this case, add side output "+0UT;: point (time A). This high-level this time period can be determined;; = side output "The phase difference between the buckling signals b and b, and the delay between the triangle circuits 21 and 22 and θ"). Therefore, since the delayed angular wave signals a, a, :-: are sufficiently shortened to the required value to reduce the three A), the force-rounding = I, "the factory side turns "-OUT" to the high position 95456.d〇 &lt; -19- 1257765 The time period can be shortened to the required value. At this time, the "C" on the minus side of the integrator and the "d" on the side of the adder become extremely low voltage. In the case of 5's without input signal (ie, it will be applied to the zero volt value of the following case), the high level in the plus side output +OUT and the minus side output -OUT, β / ° is again 〇 To a few percent of the negative ratio. For example, the plus side output "+ου丁" and the minus side output "_ουτ" are supplied to the load via a low-pass filter, for example, as a rising tower. Therefore, in the case of no input signal, the high level period in the plus side output +OUT and the minus side output - 〇υτ is 〇 to several % of the negative ratio than the current passing through the low pass filter and the load It is a minimum value. Therefore, in the case where the class D amplifier of this embodiment is used for a small signal, the above-described low pass filter (LC filter or the like) disposed between the output terminal and the load can be omitted. When the above configuration is used, according to the 〇-type amplifier of the specific embodiment 1, in the case of the unsigned input signal (that is, the case of zero volt input), the time period due to the high level of the output signal is sufficiently shortened. To the desired value, the power loss can be greatly reduced compared to prior art Class D amplifiers. Next, the description (analog input signal "+IN")&gt; (analog input signal "_IN") 1* month 幵 y, that is, when the differential input becomes positive as shown in Fig. 3, this D class is placed. - The work. It should be noted that the two-dimensional wave signals a, a, b, b are the same as the two-wave signals in the h-shape shown in FIG. The phase relationship between the triangular wave signals a, a, b, b and the integrated output Cd (i.e., the output of the operational amplifier 1 1) is the same as that in the case shown in Fig. 2. In Fig. 3, the first to fourth synthesized waves e, f_, g, h have such waveforms synthesized with the rounds of the integrator. Therefore, the phase of the first synthesized wave "6" differs from the phase of the second synthesized 纟 "f" by about 180 95456.doc 1257765 <the phase degree of the phase and the fourth bond "h" and the third synthesized wave "the phase difference" About 180 degrees. In Fig. 3, the difference between the bJ output c" and the adder side output d" of the integrator is greater than the difference shown in Fig. 2 on the w day of the integrator at the same time. Therefore, the phase difference between the first synthesized wave "e" and the fourth synthesized wave %" is such that the phase difference between the synthesized wave I and the third synthesized wave and the other phase difference is larger than that shown in Fig. 2. Therefore, it is defined as the period between the intersection of the first-composite wave e" and the second synthetic wave "f" (time U,) to the other intersection (by the mouth) is longer than in the case of FIG. The time period (from time U to time (7), the time when the side output "+〇u 丁" becomes the high level is longer than the time period shown in Fig. 2. In Fig. 3, it is defined as the slave time and the third time. The other point between the parent point (time Jt3) and the brother-synthesis wave "e" between the synthesized wave "g" and the fourth combined inverse h" and the second synthetic wave % (this time of time... The period of time longer than the period of the graph = = the side output "+〇UT" becomes the high level, and then the output of the comparator 12 is repeatedly executed ""·" from the first synthesized wave," and the second synthesized wave The intersection between the intersection point (time tr) and the lower-first-composite wave "ej" and the lower-different wave "f" (time t4,) becomes "high". Next, 1匕 :: 12 rounds out "j" from Shiqing, to the next first synthetic wave "e" and, σ into wave "fj between another point (time t5,) becomes "low" With weight M applies the above operation. In other words, each intersection between the "% one synthetic wave factory p^ and the second synthetic wave "f" of the comparator 12 turns "/" to "low" or Change from "low" to "high". 95456.doc -21 - 1257765 The equivalent of the output "k" of I3 from the intersection of the third composite wave "g" and the fourth composite wave "h" The intersection (time t3) between the time t2, and the next third synthetic broken "g" and the lower/fourth synthesized wave "h" becomes "low". Next, the output of the comparator 13 is "k". The other intersection (time t6) from the time t3' to the next third synthesized wave "g" and the fourth synthesized wave "h" becomes "high", and then the above operation is repeated. In other words, The output "k" of the comparator 13 changes its state from "high" to "low" or from "low" to each intersection between the second synthesized wave "g" and the fourth synthesized wave rh" "High." Then, since the side output r + 〇 UT" = (output j) AND (output "k"), the side output "+0UT" is from the time 丨丨 to the time (2). The inter-period, the time period from time t3' to time t4, and the time period from time t5 to time ... become "high" level. Therefore, the side output "+〇υτ" becomes the same level. The duty ratio of the custodial period is substantially proportional to the size of the analog set: in other words, the side output "+== becomes this ^5 tiger, which is modulated by the pulse width (ρ is positive than the input signal) (Differential value) is obtained. Week (4): - Aspect, the minus side output "Tear" continuously becomes lower in the position as shown in Figure 3 (analog input signals "+ΐΝ ', "-IN"), no; The 匕 wheeling signal does not have the output of the comparators 12 and 13 for a low period of time. k" is changed Next. In the case of the analog input signal "+ "-IN"), that is, when the differential input is as shown in the figure, the operation of the class D amplifier. It should be noted that the dimorphism n, ^1)' in the case where the triangular wave signal ^ is negative is the same as the angular wave of Fig. 2. The triangular wave letter d Λ η x Kf 95456.doc -22- 1257765 \ The phase « between the c and d (ie, the output of the operational amplifier 11) is the same as the relationship in the case shown in FIG. 2. In the case of Figure 4 and Figure 3, the phase of the output of "c" and "d" is reversed (i.e., offset by 180 degrees). The time relationship between the intersection of the 2 a wave and the second composite wave "f" and the intersection between the third wave forming g" and the fourth composite wave "h" is opposite to that shown in Fig. 3. Comparator 12's turn r; front * L ^ ru ^ Don't make J's brother's intersection between the synthetic wave "e" and the second synthetic wave "\" (time t2&quot;) to the next first The intersection (time t3,) between the synthesized wave "e" and the next first synthesized wave "f" becomes "high". Next, the output "|" of the comparison 12 is changed from the time t3M to another intersection (time 丨6,) between the next first synthesized wave "e" and the first synthesized wave "f". After k, repeat the above operation. In other words, the output "" of the comparator 12 changes its state from "high" to "low" or from "low" at each intersection between the first composite wave "e" and the second composite wave "f". To "high". The output "k" of the comparator 13 is from the point of intersection (time t1) between the third synthesized wave "g" and the fourth synthesized wave "h" to the next third synthesized wave "g" and the next fourth The intersection (time t4) between the synthesized waves "h" becomes "low". Next, the output rk of the comparator 13 changes from the time t4" to another intersection (the time t5 '') between the next third synthesized wave "g" and the fourth synthesized wave "h" becomes "high". 'Subsequent' repeats the above operation. In other words, the output "k" of the comparator 13 changes its sorrow "South" to "Low" or from "Low" between the second composite wave "g" and the fourth composite wave "h". Change to "high". 95456.doc -23- !257765 Then 'Because the side output "+ουτ" = (output chest D (output k), this: side output "+〇UT" continuously becomes low level. When (output state output magic, When the question becomes "low", the "minus side output" is changed to "high", and the load ratio of the time period when the minus side output "-OUT" becomes high is substantially the same as the negative value of the class: rounding signal ( The differential value is proportional to the size. In other words: the minus side input: .T" can constitute this (4), which is a negative value (differential value) of the analog input signal by pulse width modulation (ρ·). And thus, according to a specific embodiment!) class amplifier, the analog input signal can be converted into a PW &amp; 5 tiger' with three values (consisting of zero volts, positive and negative values) The p WM signal obtained by the conversion is rotated. According to the class D amplifier of the specific embodiment 1, in the case where the analog input signal value is higher than or equal to a predetermined value, the output signal becomes representative as shown in FIGS. 3 and 4 . Add one side of the "+OUT" and reduce the side of the "_0UT" to the switching signal of only one side of the signal. However, according to the specific embodiment, the switching loss of the class D amplifier can be approximately one-half of the switching loss of the conventional analog-type amplification crying in the side-by-side and side-by-side switching. The class D amplifier according to the specific embodiment 1 Using analog resistors and R4 to achieve analog feedback, the class D amplifier can amplify the analog input signal in a better linear condition without performing the digital processing operation described in the above-mentioned Patent Publication 2. The class D according to the specific embodiment 1 The amplifier, unlike the amplifier described in the above Patent Publication 1, eliminates the need for a transformer for impedance conversion and for cutting off the DC voltage, and can provide a class D amplifier with low power loss and low loss of directness, and its DC output. The composition is almost equal to zero volts. Specific Embodiment 2 95456.doc -24- 1257765 Next, a specific embodiment 2 of the present invention will be described with reference to Fig. 5. Fig. 5 is a diagram showing a class D not according to the specific embodiment 2 of the present invention. A circuit diagram of an example of the structure of an amplifier. The class D amplifier is provided with resistors R51, R52, R53, R54, R5 5 and R56, a battery C5 1, an operational amplifier 6 1 and 64, and a comparator 62. And an AND circuit (low activity) 71 and another AND circuit 72. The triangular wave signal "a" is applied to the add-side input terminal of the comparator 62, and the other triangular wave signal "b'" is applied to the comparator 63. Add side input terminals.

The binary wave signal "V" corresponds to the triangular wave signal, which is further delayed by the phase of the triangular wave 唬 "b" obtained by inverting the binary wave signal "a" (that is, the delay phase is 180 degrees). Produced by a very small angle of "one." Therefore, the triangular wave signal ra" and the triangular wave signal "b," are signals of the same waveform, and their phases are different from each other (18 degrees + minimum angle "one"). In this case, predetermined noise called "fibrillation" can also be applied to the triangular wave signals a and b, respectively. Since the chattering noise is applied to each triangular wave signal, the distortion of the output wave can be repaired. In addition to the two-corner signals a and b, a noise waveform, an integrated waveform, or the like can be used.

The one with the gross resistance of R5 1 constitutes the input terminal of the analog input signal. The receiver 'mountain connects the other terminal of the resistor R51 to the subtraction side input terminal of the operational amplifier. The operational amplifier 61 and the capacitor (3) constitute an integrator. The comparator compares the triangular wave signal "a" with the output of the integrator. "^", then output comparison, ~ fruit (round rj). The comparator 63 compares the triangular wave signal "b," with the integrator "c", and outputs a comparison result (output "k"). The and circuit 71 corresponds to a buffer circuit having a low activity and gate function. Then, when the output "@" of the first comparator 62 and the output "k" of the second comparator Ο 95456.doc -25 - 1257765 are "low", the AND circuit 7 i outputs a "high" level signal ' And output this signal as the subtraction side output "_〇υτ" of this class D amplifier. The AND circuit 72 corresponds to a buffer circuit having an AND gate function. Then, when the output "j" of the first comparator 62 and the second comparator 63^ output "k" to "high", the AND circuit 72 outputs a "high" level signal and outputs it as the class D amplifier. This calculation of adding the side output "+〇υτ", the operational amplifier 64 and the resistors HR53, R54, and (10) (4) constitute a difference amplifier, and the difference between the amplified side output r + 〇UT" and the reduced side output "_ bribe" . The output ":" of the differential amplifier is fed back to the input side of the operational amplifier 61 via the resistor R52 (i.e., the input side of the class D amplifier). Therefore, the operational amplifier 64 and the resistors R52, R53, R54, r55, and r5 are formed into a feedback circuit. Next, the operation of the apparatus according to the above-described circuit configuration is explained. In the case where the class_people is at zero volts (no input 4谠), that is, "IN is equal to r + 〇TJT, y J is at 1/2 VDD", the side output is added: and the minus side output is "tear". As shown in Fig. 6, the load ratio of the shot is almost equal to zero to several %. Therefore, when the analog output Uu finds zero volts (the current flowing to the load without the input signal is reduced to a minimum value. The four-wave type amplification is “tear” on the side of the analog input signal that is positive. Output "+〇UT" and reduce it by generating a positive value of the analog input a in a pulse width modulation mode (ie, 'positive when using zero volts as a reference value). 95456.doc -26 - 1257765 face, reduce side wheel Γ _ουτ" continuously becomes low level. In the case of analog input signal is negative, add side output 3 out "Tear, and (4) (four). _, - "sample" 2: This one 唬 ' It is generated by modulating the negative value of the analog input ^ tiger by pulse width modulation (that is, using 1/2 VDD as the reference value "negative"). On the other hand, the side output "+ουτ" is continuously changed. The low level is the same as the class 0 amplifier according to the above specific embodiment, and the above configuration is used according to the amplifier of the specific embodiment 2, 纟 no analog input signal 2 in this case (ie, the case of zero volt input), since The time period during which the output signal is delivered to the level is sufficiently shortened to the required value The power loss can be greatly reduced compared to prior art Class D amplifiers. Thus, according to the Class D amplifier of Embodiment 2, the analog input signal can be converted to have three values (by zero volts, positive and negative values). The pWM signal is configured to be output, and then the converted pWM signal can be output. According to the specific class D amplifier of Example 2, in the case where the analog input signal value is higher than or equal to a predetermined value, the output signal becomes 3 and 4 represent the switching waveform of only one side signal of any one of the side output "+0UT" and the subtraction side output Γ-〇υτ" in the same manner. Therefore, according to the specific embodiment 2, D The power is amplified so that the switching loss can be approximately one-half of the switching loss of the conventional class D amplifier switching between the plus side and the minus side. According to the class D amplifier of the second embodiment, since the operational amplifier 64 and the resistor R52 are used. R53, R54, R55, and R56 implement analogy feedback, and the class D amplifier can amplify the analog input signal under a better linear condition, and the actual digital processing operation described in the above Patent Publication 2 is not real. Body 95456.doc -27- 5 1257765 - The Class D amplified state of Example 2 is the same as the amplifier I described in the above patent publication. It is no longer needed for impedance conversion and to change the dc voltage. This amplifier can be provided with low power loss and low distortion, and its DC output component is almost equal to zero volts. The main next 'SI7A to 7C display' is an example of the output waveform in the case, which is shown in Figure 1 or Figure 5. The specific embodiment i or the specific embodiment: the sine wave is input into the analog signal input terminal of the class D. In the specific embodiment and the specific embodiment 2, the case where the sine wave is input into the human terminal signal is input to the terminal:丨 Waveform phase diagram 7(4) shows the low-pass filter and the load (resistance state R)' with the side output "+〇UT" and the subtraction side output of the class D amplifier according to the specific embodiment 1 or embodiment 2. 〇υτ" is connected. Figure 7(b) indicates that the add-side output "+〇υτ" of this class D amplifier has passed through the low-pass filter and this waveform is shown as output Γρ〇υτ". In Figure 7 (1^, the minus-side output "-0UT" of this 〇-type amplifier has passed through the low-pass filter and this waveform is displayed as the output "NOUT". The output P0UT and the output N〇UI^^ become only Such a waveform having a waveform of the upper half of the sine wave. However, the output "〇υτ" corresponding to the signal applied to the load as shown in Fig. 7(c) becomes a sine wave. This reason is given as follows: Since the load (speaker, etc.) is connected between the output ρ〇υτ and the output NOUT (that is, between the add-side output terminal “ρ〇υ丁” and the minus-side output terminal “NOUT” of the low-pass ferropole), as shown in Fig. 7(c) It is shown that the output "OUT" corresponding to the signal applied to the load becomes a difference (〇UT=POUT-NOUT) between the output POUT and the output NOUT, thereby forming a sine wave. In accordance with Figs. 1 and 5 In the specific embodiment 1 and the class D amplifier of the second embodiment, at least the triangular wave signal "a" and the triangular wave signal "b, 95456.doc -28 - 1257765 are used, and the triangular wave signal "b," is reversed. The triangular wave (4) "a" is further obtained by delaying the inverted triangular wave signal "a". Therefore, Even when there is no analog input signal in the 放大器 class amplifier according to the specific embodiment! and the specific embodiment 2, as in the case of FIG. 2 and FIG. 6, the side output "+〇υτ" and the minus side output "-OUT" are both Output in a short time (the load ratio of the high level period is set to zero to several %), so that the voltage output to the low pass filter is slightly smaller (outputs POUT, NOUT). At this time, since the output ρ 〇υ τ_ output Ν This voltage defined by 〇υτ is applied to the load, corresponding to the signal applied to the load: OUT becomes zero volts. Thus 'in the state where the analog input terminal is changed from the no-signal state to the input smaller signal. In this case, even if the state thereof changes, the class D amplifier according to the specific embodiment and the specific embodiment 2 can supply an amplified signal having low distortion to the load. 鳢 Embodiment 3 Next, reference will be made to FIG. 8 to FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 3 is a circuit diagram showing an example of the structure of a class D amplifier according to a third embodiment of the present invention. Unlike a class D amplifier according to a specific embodiment, the class D amplifier is used. The delay circuits 21 and 22 are not used as structural elements. In the class D amplifier, the triangular wave signal "a" is applied to one terminal of the resistor ri 〇, and the other triangular wave signal "b" is applied to the other resistor. A terminal structure is the same as the class D amplifier according to the specific embodiment shown in FIG. 8 except for the above circuit configuration in the class D amplifier shown in FIG. 8. It should be understood that the composite circuit constituting the class D amplifier is understood. The individual resistance values of the resistors R5, R6, R7, R8, R9, R1〇, RU and R12 have been set under a condition, and this condition is not defined in the resistor of the amplifier according to the specific example 95456.doc 1257765 In R5, R6, R7, R8, R9, R1Q, and RU AR12. The structural circuit configuration of this class D amplification will be described in detail. This class D amplifier is equipped with resistors ri, R2, μ, r4, r5, R6, R8, R9, H10, R11 and R12 'capacitor C1 &amp; C2, operational amplification state 11, comparator 12 and 13, AND circuit ( Low activity 31 and another AND circuit 3 2 . In this figure, the predetermined two-dimensional wave signal "a" is applied to one of the terminals of the resistors R9 and Rl1, respectively. In this figure, a predetermined triangular wave signal is applied to one of the terminals of the resistors R11 and R12, respectively. The triangular wave signal r a" and the triangular wave signal "b" are such signals having the same waveform, and their phases are different from each other by 18 degrees. Assume now that the triangular wave signal "a" in the present invention is set to such a triangular wave as in the claim 6, the triangular wave signal "b" in the present invention corresponds to a triangular wave having an opposite phase. One of the terminals of the resistors R1 and R2 constitutes a differential input terminal of an analog input signal. Therefore, one of the terminals of the resistor R1 constitutes a side input terminal (+IN). One of the terminals of the resistor R2 constitutes a minus side input terminal (_IN). The operational amplifier 11 and the capacitors C1 and C2 constitute an integrator. The integrator integrates the analog input signals of the differential inputs of the resistors R1 and R2, and outputs the integrated signals to the resistors R5, R6, R7 and R8. Resistors R5, R6, R7, R8, R9, RIO, R11 and R12 form a synthesizing circuit that synthesizes the triangular wave signal "a'" or "b," and the output signal of the integrator. The synthesizing circuit generates four first to fourth composite waveforms "e", rf", "g", and "h". The individual resistance values of the resistors R5, R6, R7, R8, R9, R11 and Rl 2 constituting the synthesizing circuit are determined in a manner which is the first synthesis 95456.doc -30 - 1257765 wave "e" and A time difference (phase difference) is generated between the second synthesized wave "f" and between the third synthesized wave "g" and the fourth synthesized wave "h", which corresponds to an output signal of the composite circuit based on the resistance values, and is compared The input capacitance of the 12 (first comparator) and comparator 13 (second comparator). In this circuit, the resistor R5 corresponds to the first resistor associated with the claim 7 in the present invention, and the resistor R6 corresponds to the fifth resistor in the present invention. The resistor R7 corresponds to the third resistor in the present invention. Resistor R9 corresponds to the second resistor in the present invention. The resistor R10 corresponds to the eighth resistor in the present invention. The resistor R11 corresponds to the fourth resistor in the present invention. The resistor R12 corresponds to the sixth resistor in the present invention. The above synthesizing circuit includes first to fourth synthesizing units. The first synthesizing unit synthesizes the reduced side output of the operational amplifier 11 constituting the integrator and the triangular wave signal "a" to generate the first synthesized wave "e". Next, the first synthesizing unit has a resistor R5 (first resistor) having one terminal connected to the subtraction side output of the operational amplifier 11, and a resistor R9 (second resistor). Apply the triangular signal "a" to one of the terminals of this resistor R9. The other terminal of the resistor R5 is connected to the other terminal of the resistor R9 to constitute an output terminal. The second synthesizing unit synthesizes the added side output of the operational amplifier 11 and the triangular wave signal "b" to generate a second synthesized wave "f". Next, the second synthesizing unit has a resistor R7 (third resistor), one terminal of which is connected to the add-side output of the operational amplifier 11, and a resistor R11 (fourth resistor). The triangular wave signal "b" is applied to one of the terminals of the resistor R11. The other terminal of the resistor R7 is connected to the other terminal of the resistor R11 to constitute an output terminal. The third synthesizing unit synthesizes the subtraction side output of the operational amplifier 11 and the triangular wave letter 95456.doc -31 - 1257765 "b" to generate the third synthesized wave "taken gas g", and the third synthesizing unit has the resistor R6 ( The fifth resistor), the basin is a mountain, and its ^ is connected to the side of the operational amplifier 11 minus the output, and the resistor is crying R12f篦山+ | resistor). The triangular wave signal "b" is applied to the terminal of this resistor R12. The other end of the resistor is connected to the other terminal of the resistor im to form an output terminal. The fourth synthesizing unit synthesizes the added side output of the operation (4) and the triangular wave signal a" to generate the fourth synthesized wave "h". Next, the fourth synthesizing unit has a resistor (four) (seventh resistor) having a terminal connected to the operational amplifier &amp; plus side output, and a resistor R1 〇 (first resistor). Apply the triangular wave signal "a" to one of the terminals of this resistor (4). The resistor is further connected to the other terminal of the resistor R10 to form an output terminal. The resistors R5, R7 connected to the comparator 12, and the individual resistance values such as (first to fourth resistors) are preferably set to such resistance values by connecting the resistors connected to the comparator 13. The individual resistance values of the R6, R8, R10, and R12 (fifth to eighth resistors) are multiplied by such values other than (8). For example, the resistance values of resistors R5, R7, 尺 9 and R1 i and the resistance values of resistors 6, R8, R10 and R12 are set as follows: R6 = R8 = R5Xa, R5 = R7, R10 = R12 = R9Xa, R9 =Rii, in these formulas, the symbol ra" is not equal! . It can be seen from the conditions of the above formula that the following resistance value setting conditions can also be established: R5 = R7 = R9 = Rli, or R5 = R7 is not equal to R9 = R11. 95456.doc -32- 1257765 Next, under this condition of (R6=R8) and (R10=R12), it is assumed that (R6, r8, RIO, R12) is equal to (R5, R7, R9, R11) multiplied by " α" (otherwise l/α). For example, it is assumed that the individual resistance values of resistors R5, R7, R9, and R11 are set to 1 [ΚΩ], and the individual resistance values of R6, R8, RIO, and R12 can also be set to 2 [ΚΩ] or 500 [Ω]. At this time, the symbol "α" is equal to 〇.5. Now assume that the individual resistance values of resistors R5, R7, R9, and Rl 1 are set to 20 [ΚΩ], and the individual resistance values of resistors R6, R8, R10, and r12 can also be set to 30 [ΚΩ]. At this time, the symbol "α" is equal to 1.5. Now assume that the individual resistance values of the resistors R5, R7, R9, and Rl 1 are set to i [ΚΩ] ’. The individual resistance values of R6, R8, R1 〇, and R12 can also be set to 3 〇 [ΚΩ]. At this time, the symbol "α" is equal to 30. As can be seen from the description of the Li, the above synthesizing circuit can be obtained by using the resistors R5, R7, R9, RU connected to the comparator 12 and the resistors R6, R8, R1, R12 connected to the comparator n. The difference between the comparators η and the input capacitance of the comparators η and 13 establishes a time difference between the first synthesized wave "e" and the second synthesized wave "f" and between the third synthesized wave "g" and the fourth synthesized wave % (phase) difference). / "2 (first-comparator) compares the first synthesized wave," and the second synthesis: the heart'" is a comparison result. When the first-composite wave "e" is greater than the second ό-forming wave f", the first Chou is crying 1 Ϊ, for example, zero is accurate), and 1 is scheduled to be "low" level signal (eg, a Japanese s brother, a 50-wave "e" is smaller than the second synthetic wave "f", and the second output is scheduled to be "high". The quasi-signal. More than the _ first than the car father's family) more complex people},, "the younger brother into a wave of "趵 and the fourth synthetic wave "h", to lose 95456.doc -33 - 1257765 軚 results. When the third composite wave "g" is greater than the fourth composite wave "h", the predetermined "low" level signal (for example, zero level) is 13 rounds, and the far-reaching Sanhezhong, and ", skin g" When it is smaller than the fourth synthesized wave "h", the second comparison 13 outputs a predetermined "high" level signal. The way 31 corresponds to a buffer circuit having an AND gate function of a negative logic input. Next, the circuit 31 performs the ana-calculation (low activity ^: the output of the middle-of-the-comparator 12 and the output of the second comparator 13 is "low". The ND circuit 31 outputs a "high" level signal and outputs As a result of this D : : : 态 态 : : 态 态 态 态 态 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The side of the amplifier 11 is input. The helper path 32 corresponds to a buffer circuit having an AND calculation function, and performs a fine calculation operation between the output of the comparator 12 and the output of the comparator 13, and then outputs the calculation result to this D. The adder side of the class amplifier outputs a +OUT. The resistor R4 forms a second feedback circuit, and the second feedback circuit feeds the output of the AND circuit 32 used as a buffer to the subtraction side input of the operational amplifier 。. The low-pass filter between the side output of the class D amplifier and the side output factory - ουτ is connected to the load (speaker, etc.). This class D amplifier can be used with low distortion due to the circuit configuration of the child. Zoom in analog input signal "+IN And "-IN", without using a transformer, can additionally drive the load while reducing the power loss. Next, the operation of the class D amplifier according to this specific embodiment 3 using the above configuration will be described with reference to Figs. Example 9 to Figure 9 are waveform diagrams showing the operation of the individual circuit portions of the class D amplifier shown in Figure 8 of 95456.doc -34-1252765. Next, Figure 9 shows the value of the analog input signal "ground". It is equal to the value of the analog input signal 5 tiger IN", that is, when the differential input becomes zero volts (the waveform of the individual circuit part of the input signal amplifier is not shown. Figure ι〇 represents when (the analog input signal "+IN") &gt; (analog to # &amp; " ") U Bebe input &lt; 吕唬 "-IN"), that is, the waveform of the individual circuit part of the class D amplifier when the differential input becomes positive. Figure U represents (The analog input signal "+IN") &lt; (analog input signal "_in"), that is, when the differential input becomes negative, the charge * 4 *, the magic bellber is amplified into the waveform of the individual circuit parts. As shown in Figure 9 to Figure U, the class D amplifier according to this specific embodiment 3. The other part of the circuit is the same as the individual circuit part of the class D amplifier according to the embodiment shown in Figures 2 to 4. However, the class d amplifier has the following different operations. The two sets of triangular wave signals, and b" are used as the two-dimensional apostrophes, which is different from the specific embodiment a. The class amplifier uses four sets of triangular wave signals a, am. Next, the individual parts of the class D amplifier are described in detail. The operation of the circuit section. ° First, the operation of Figure 9 will be described, that is, the case of no differential input (the phase of the zero-volt value of the triangular wave signal "a" and the triangular wave signal "the phase of the triangle is 1180 degrees. In the meantime, a predetermined chisel called "fibrillation" can also be applied to the two-dimensional signal _. Since the chattering noise is applied to the wave signal, the distortion of the output wave can be corrected. In addition to these triangular wave signals, a sawtooth waveform, an integrated waveform, or the like can be used. The angular relationship between the angular wave "5 tiger aj and the integrator plus side output (the operational amplifier 加 plus side output) "d" is substantially equal to each other. Triangle wave letter

; J b" and the inductor's reduced side output (the reduced side output of the operational amplifier u) "c 95456.doc -35 - 1257765 are substantially equal to each other. The inputs of the comparison states 12 and 13 are the first to The fourth synthesized waves e, f, g, and h have waveforms synthesized with the output of the integrator. Then, the phase of the first synthesized wave "e" phase 14 苐 a composite wave rf" differs by about 1 〇. The phase of the third synthetic wave g" differs from the phase of the fourth synthesized wave "h" by about i 8 degrees. The waveform of the first synthesized wave "e" is substantially equal to the waveform of the fourth synthesized wave "h", and the phases of the first and fourth synthesized waves "e" A "h" are different from each other by an extremely small angle "θ,". The waveform of the second synthesized wave "f" is substantially equal to the waveform of the third synthesized wave "g", and the phases of the second and third synthesized waves "f" and "q" are different from each other by a very small angle "one". As described above, the reason why the minimum angle θ' is generated between the first synthesized waveform "e" and the fourth synthesized waveform "h" and between the second synthesized waveform "f" and the third synthesized waveform "g" is as follows. That is to say, the individual resistance values of the resistors R5, R7, milk and 1111 connected to the comparator 12 have been set to such resistance values by the resistors R6, R8 connected to the comparator 13, and The individual resistance values are multiplied by such values other than "!". In other words, the phase difference of the above-mentioned pole angle θ' is generated based on the resistance values and the input capacitances of (4) 12 and 13. It should be understood that this very small angle one corresponds to a very small angle θ occurring within the operational waveform of the amplifier according to the embodiment shown in Fig. 2. Then, by adjusting the resistance value of the resistor RUR12, the minimum angle is adjusted by one. The outputs "j" & "k" of the comparators 12 and 13 have the same waveforms as "k" and "k" of the comparators 12 and 13 of the amplifier according to the specific embodiment (10) shown in Fig. 2. This D Adding side output "+〇υτ" and reducing side wheel 95456.doc -36 - 1257765 of the class amplifier have "+OUT" with the side output "+〇" of the class D amplifier according to the specific embodiment 1 shown in Fig. 2. UT" and the subtraction side output "-OUT" the same waveform. As described above, the operation of the comparators 丨2 and 丨3 and the circuits 31, 32 for the class D amplifier and the comparators 12 and 13 of the sigma amplifier according to the first embodiment are the same as the AND circuits 31, 32. . Operation of the feedback circuit (resistor R3 &amp; R4) and integrator (operating amplifier 11 and capacitors C1, C2) for this class D amplifier and the feedback circuit and integrator for the class D amplifier according to the specific embodiment 1. The operation is the same. Therefore, '舆 is the same as the class D amplifier of the specific embodiment 1. When the class D amplification - Zhongtian does not supply the input signal, the high level period in the plus side output + 〇υ τ and the minus side output - OUT can be set to 〇 to several % load ratio. Therefore, in the case where the class 0 amplifier of this embodiment is used for a small signal, the above-described low pass filter (I, filter, etc.) disposed between the wheel terminal and the load can be omitted. ^ When using the above configuration of this class D amplifier, it is the same as the class D amplifier of the specific embodiment 1 'in the case of the analogless input signal (ie, the U shape of zero volt value 3) due to the output signal becoming high The quasi-time cycle can be shortened to the required value, which can be greatly reduced compared with the prior art class D amplifier. The description is based on the analogy of the incarnation of the factory / π... In the shape of the moon, that is, when the differential input is as shown in Figure 1〇, the operation of the ship. When compared with Figure 3, the triangular waves in different black ^ _ amplifiers use two sets of triangular wave signals, and "b thus 'even in the case where the differential input is positive, except for the synthesis circuit 95456.doc I257765: outside' Class D Ai § can be used in the same way as the specific example u class amplification ☆ force vp. Therefore, in this class D amplifier, when the differential input two;:, plus side output "Qing" becomes this a signal which is continuously changed by the positive value (differential value) of the input signal and the negative side output Γ·〇υτ by the pulse-modulation--, % &quot;, , and the analog input signal. Low level. "In the case of the brother-in-law (analog input signal "+ΙΝ") &lt; (analog input signal · Ν"), that is, when the differential input becomes negative as shown in the figure ,, the class is placed ^ Operation of the device ° When comparing Fig. 11 with Fig. 4, the difference between the two points is that the two triangular waves are "a" and "b". In the case where the differential input is negative, the class D amplifier can be operated in the same manner as the class D amplification according to the specific embodiment 1 except for the synthetic circuit portion knife. Therefore, this class D In the amplifier, the #differential input is (4) 'minus side output "tear" becomes this signal, which is generated by modulating the negative value (differential value) of the analog input signal by the pulse modulation modulation method, and The side output "+ουτ" is continuously changed to the low level. Therefore, similar to the amplifier of the specific embodiment (4), according to the specific implementation: 3, the analog wheeled signal can be converted into three values (by: volt 4 inch value, positive value and negative value The PWM signal of the term constitutes a PWM signal, and then the pwM signal obtained by the conversion of the sea is output. According to the specific embodiment 3, the large output signal value is higher than or equal to the predetermined value, and the output signal becomes the side output "+〇υτ" as shown in FIG. 10 and the table. The switching waveform of only one side signal of any one of -OUT", therefore, according to the class D amplifier of the third embodiment, the switching loss can be approximately the switching of the conventional sinusoidal amplifier switching between the side and the side. Loss of 95456.doc -38 - 1257765 half. According to the class D amplifier of the third embodiment, since the analog feedback is realized by using the resistors and R4, the class D amplifier can amplify the analog input signal under a better linear condition without implementing the above described in the above Patent Publication 2. A digital processing operation. According to the class D amplifier of the specific embodiment 3, unlike the amplifier described in the above Patent Publication 1, the transformer for impedance conversion and for cutting off the DC voltage is no longer required, and the present invention can provide low power loss and low distortion. A class D magnified, whose DC turn-out component is almost equal to zero volts. Further, according to the class D amplifier of the third embodiment, although the delay circuits 21 and 81 are not used as structural elements, the first synthesized wave "e" and the second composite are adjusted by adjusting the resistance values of the resistors μ to r12. A time difference (phase difference) may be generated between the wave "f", the third synthesized wave "g", and the fourth synthesized wave "h", which is different from the class D amplifier of the above-described embodiments. Thus, the Class D amplifier of this specific embodiment 3 can be designed and manufactured in a simple manner, and can provide a Class D amplifier with high performance. BEST MODE FOR CARRYING OUT THE INVENTION Next, a specific embodiment 4 according to the present invention will be described with reference to Figs. 12 to 17 . Figure 12 is a circuit diagram showing the configuration of a oxime amplifier according to a specific embodiment 4 of the present invention. The same reference numerals are used for the common components used in the class D amplifier of the specific embodiment 1. The difference between the present class D amplifier according to the specific embodiment 4 and the class D amplifier according to the specific embodiments 1 and 2 is that a single binary wave generating circuit is provided. This class D amplifier will be described in detail below. Class D amplifiers include resistors R1, R2, R3 and R4, capacitors C1, C2 and 0100, operational amplifier 11, comparators 112 and 113, inverters 121 and 95456.doc - 39 - 1257765 122, AND circuits 131 and 132 And current source 140. The capacitor 100 and the current source constitute a triangular wave generating circuit that outputs a triangular wave to the subtraction input side of the comparators 112 and 113. One of each of the resistors R1 and R2 is used for the differential input of the analog input signal. One end of the resistor R1 is a plus side input terminal (+IN), and one end of the resistor R2 is a minus side input terminal (-IN). The operational amplifier 11 and the capacitors C1 and C2 constitute an integrator. The integrator integrates the analog input signals of the differential input resistors R1 and R2 to output them to the comparators 112 and 113. The reduced side output of the operational amplifier 11 is connected to the add side input terminal of the comparator 112 (first comparator). The add-side output of the operational amplifier 连接 is connected to the add-side input terminal of the comparator 113 (second comparator). The subtraction side input terminals of the comparator U2 &amp; 丨 13 are respectively connected to one end of the capacitor 1 电容器 (capacitor). The other end of the valley is connected to the ground, and the other end of the current source is connected to the ground. With this configuration, the comparator 112 compares the output of the subtraction side of the operational amplifier 与 with the output of the triangular wave generating circuit and outputs a comparison result. The comparator 113 compares the side output of the differential gain amplifier 11 with the output of the triangular wave generating circuit and outputs a comparison result. The output of the comparator 112 is connected to the input terminal of the inverter 121 and the input terminal of the side circuit 132 (second buffer). The output of the comparator (1) is connected to the input terminal of the inverter 122 and the AND circuit (the input terminal of the first buffer). The output of the inverter 121 is connected to the other input terminal of the side circuit i3i. The inverter 122 The output is connected to the other input terminal of the circuit 132. With this configuration, the ND^* path U1 calculates the logical product of the signal inverted from the output of the comparator 112 and the output of the comparator 113. And the result of the calculation 95456.doc -40 - 1257765 is output. The AND circuit 132 calculates the logical product of the signal inverted from the output of the comparator 113 and the output of the parent device 112, and outputs the calculation result. The output of the AND circuit 13 1 is The side output of the 放大器 class amplifier is + 〇υτ. The plus side output +0UT is fed back to the subtraction side input of the operational amplifier through the resistor R4. The output of the AND circuit 132 is the reduced side output of the class D amplifier - 〇υτ. R3 feeds the minus side output -0UT to the plus side input of the op amp. Figure 13 shows the circuit diagram for the specific configuration of the current source 14〇. The current source 14〇 and the capacitor 1〇〇 form a triangular wave generating circuit. D2, switch si And S2, comparisons 141 and 142, and NAND circuits 143 and 144 constitute current source 140. Transistors T1 and T2 are composed of field effect transistors (FETs). Voltages for controlling the charging current value of capacitor 100. Applied to the gate of transistor T1. Voltage VBN for controlling the discharge current value of the capacitor is applied to the closed end of transistor T2. Switches 31 and 32 comprise analog switches, and may be comprised of FETs. Switches 81 and 82 are switched from The flow direction of the current output of the current source 14〇, that is, the charging and discharging of the switching capacitor i 。. The current input/output terminal of the transistor τι, the switches § 1 and 82, and the current input/output terminals of the transistor are connected in series to each other, As shown in Fig. 13, the minus side input terminal of the comparator Η1 and the adder side input terminal of the comparator 142 are connected to the connection point of the switch and S2. The connection point is also connected to the capacitor 1A to constitute an output terminal of the triangular wave generating circuit. Comparing 142 to compare the desired first potential ¥;1 with the potential of the connection point, and outputting the comparison result. The comparator 141 compares the desired second potential vh with the connection point of 95456.doc -41 - 1257765 potential, and take the comparison result. It is assumed that the second potential VH is higher than the first potential VL. The difference between the second potential ¥11 and the first potential VL sets the amplitude of the triangular wave. The NAND circuits 143 and 144 are connected to form a positive The reverse circuit has an input which is an output of the comparators 14A and 142. The output of the flip-flop circuit controls the opening/closing of the switches S1 and S2, that is, the output switching capacitor 100 of the flip-flop circuit. Charging and discharging to switch the rise and fall of the triangular wave. FIG. 14 is a diagram illustrating the operation of current source 140.

First, the operation when the triangular wave G as the potential of the connection point is lower than the first potential VL (in the case of a dotted line illusion) will be described. In the case of the dashed line ^, the output of comparator 142 goes low, causing switch S1 to turn on and switch s2 to turn off. Thus, the charging current flows through the transistor and the switch S1 into the capacitor 1〇〇. Therefore, the triangular wave G which is the potential of the capacitor 100 rises. When the triangular wave F exceeds the first potential VL and reaches the second potential ¥11, the output of the comparison = becomes low, causing the switch S2 to be turned on and the switch si to be turned off. Thereby, the discharge current of the capacitor 10G flows to the ground through the electric crystal (4) and the switch s2. Therefore, the triangular wave G is lowered.

When the triangular wave G reaches the first potential VL, the output of the comparator 142 goes low, causing the switch Si to open and the switch 82 to be closed. &amp; and the charging current flows again: the angular wave G rises. - By repeating these operations thereafter, a dihedral wave G as shown in Fig. 14 is produced. The operation of the triangular wave (the tilt at the time of the fall) is set by the voltage νΒΝ for controlling the discharge current and the capacitance of the capacitor 100. In the case of the dotted line K2, the comparator (4) The output becomes low and the switch S2 is turned on. 'The switch S1 is turned off. Thus the discharge of the capacitor (10): 95456.doc -42 - 1257765 The transistor T2 and the switch S2. Therefore, the triangular wave G which is the potential of the capacitor 1 下降 falls. As described above, the charging and discharging of the capacitor 1 重复 repeats and generates a triangular wave G as shown in FIG. 14. Accordingly, the capacitor 100 and the current source 140 can be provided by using the D-type amplifier of the present embodiment. A triangular wave generating circuit of a simple structure is therefore high in efficiency and can provide a low distortion class D amplifier having a low cost. Next, the operation of the 〇 class amplifier according to the specific embodiment 4 will be explained with reference to Figs. 5 to 17 are waveform diagrams showing the operation of each part of the class D amplifier shown in Fig. 12. Fig. I5 shows (analog input signal + IN) &gt; (analog input signal, time, that is, differential When the input is positive, the waveform of each _ section of the _ amplifier is triangular wave (10) The triangular wave with the lowest potential VL and the second potential VH is the largest.... Since the differential input of the filial knife is positive, the output of the integrator is reduced. The integrator's side-side output B is lower than the level. Figure 15 shows the current source 14〇 switch and the S2 drive waveform. The current source 14〇's opening w is used to make a high level signal; The segment S1 is turned on. The switch S1 responds to the low level signal, and is turned off by the falling section of the ^^, '^ &gt; '. The opening of the current source 140 acts as a tricky sweat for the low level signal 1 S2M - ^ m 〇α , in the rising section of the two-dimensional wave G is closed. The switch S2 makes the return of the leveling signal to the falling section of the two-dimensional wave G. :: knife: the side wheel of the reduction is compared with the triangular wave a a&gt ;g, the round of the comparison state 112 is changed to C. The side of the integrator is rounded out, and the comparison result is A&lt;G', and C is low. When the output of the U3 is changed, the result of the comparison is changed to (4). Comparing, the comparison result becomes B&lt;G, and the output D goes low. 95456.doc -43- 1257765 When from the comparator 112 When the value of the output C inversion and the rounding D of the comparator 113 are both high, the output (+〇UT)E of the AND circuit 131 becomes high. Therefore, the duty ratio of the period when the side output +OUT is high is high. It is substantially proportional to the amplitude of the positive value (differential value) of the analog input k. In other words, the plus side output + 〇u is a pulse width modulation signal that is analogous to the positive value (differential value) of the input signal. When the value of the comparison 112 is inverted and the value inverted from the output D of the comparator 113 is higher, the output (-OUT) F of the AND circuit 132 goes high. Here, the minus side output - OUT is always low. Figure 16 shows (analog input signal + INM analog input signal - IN), that is, when the differential wheel is zero (〇 volt input)! ) The waveform of each part of the class amplifier. The triangular wave G shown in Fig. 16 is the same as the triangular wave G shown in Fig. 15. Since the operations of the switches S1 and S2 of the current source 140 with respect to the triangular wave F are the same as those shown in Fig. 15, the drive signals of the switches S1 & S2 are omitted in Fig. 16. Since the differential input of the integrator is (+IN) == (_in), the reduced side output A of the integrator has the same level as the added side output B of the integrator. Since the output A is equal to the output B, the output c of the comparator 112 has the same waveform and the same phase as the output 比较 of the comparator 113. Since the output of the AND circuit (3丨 (+〇UT)E is (inverted value of output c)* (output D), the output E is low in most of the entire cycle. Since the output (_0UT)F is (output 〇* (inverted value of the output 〇), the output F is low in most of the entire cycle. As shown in FIG. 16, the operational amplifier 12 constitutes the comparator 112 and The difference between the delay time caused by the components of 114 and the offset voltages of the inverting ^(2) and (2), the side output and the side output have some high level periods. Therefore, the side output can be 95456.doc -44 - 1257765 + OUT and the subtraction side output _〇υτ are simply assumed to be strictly low levels throughout the cycle. As described above, according to the class 0 amplifier of the specific embodiment 4, since the analog input signal is not applied (0 volt value) In the case of the input), the period in which the output signal is at a high level can be extremely easily shortened, and the power loss can be greatly reduced as compared with the conventional device having a simple structure. Figure 17 shows (analog input signal + 丨州义 (analog input signal) ·IN), that is, when the differential input is negative, the waveform of each part of the class D amplifier. The triangular wave is the same as the triangular wave G shown in Fig. 15. The operation of the switch S1 and Μ of the current source 14〇 with respect to the two-dimensional wave G versus The operation shown in Fig. 15 is the same, and the driving waveforms of the switches S 1 and S 2 are omitted in Fig. 17. The reduced side output 积分 of the integral person is higher than the added side output Β of the integrator. The comparison result of Α and triangular wave G is A&gt;G, the output C of comparison is higher, and when the comparison result is A&lt;G, the output c becomes lower. When the adder side of the integrator B and the triangle wave G are B&gt;G, Comparing the output E of gU3 becomes high, when the comparison result becomes b&lt;G, the output e goes low. When the output C of the comparator 112 and the inverted value of the output D of the comparator in are both high, the output of the AND circuit 132 (-〇UT)F becomes high. Therefore, the duty ratio of the period when the minus-side output -OUT is high is proportional to the amplitude of the negative value (differential value) of the analog input signal. In other words, the side output _〇UT The pulse width modulation signal is a negative value (differential value) of the analog input signal. On the other hand, when the inverted value of the output C of the comparator 112 and the output D of the comparator 113 are both high, the output of the AND circuit 131 (+〇υτ)Ε becomes high. Here, the plus side output +OUT is always low. 95456.doc -45- 1257765 As described, the class D amplifier of the fourth embodiment can be output by converting the analog input signal into a 3-valued PWM signal consisting of 0 volts, positive and negative values. The amplifier, when the analog input signal becomes a value other than the 〇 volt value, the switching waveform appears only on one of the plus side output + 〇υ τ and the minus side output - OUT as shown in FIGS. 15 and 17 . In the class D amplifier of the example 4, since the resistors R3 and R4 constitute an analog feedback circuit, the analog input signal can be amplified in a good linearity without performing the digital processing as explained in Japanese Patent Laid-Open Publication No. 2000-500625. Further, according to the class D amplifier according to the specific embodiment 4, the direct output module can be substantially eliminated, and the change for impedance conversion and direct voltage cut (for example, as described in Japanese Patent Laid-Open No. Sho-56-27001) is not provided. Dust is. Therefore, a Class D amplifier with low distortion and high power efficiency can be provided. While the specific mode of the present invention has been described in detail with reference to the drawings, the specific structure is not limited to the specific embodiment mode, and it is obvious that the structure defined in the scope of the technical spirit of the present invention can be covered. For example, although in the class D amplifier of the above specific embodiment, the integrator is composed of primary and secondary, the present invention is not limited thereto, and the integrator may be constituted by 咼, , and %. With this configuration, the loop gain can be increased and the distortion rate can be further reduced. In the above description, the present invention has been described as a class D amplifier, but the present invention is not limited thereto. Accordingly, the present invention is applicable to signal processing circuits other than class D amplifiers, as well as various pulse width modulation amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram for an example of a structure in which a class D of a specific embodiment of the present invention is not used in accordance with the mode of the present invention. Fig. 2 is a waveform diagram for indicating the operation of the scorpion amplifier when zero volts is applied to the sigma type amplifier shown in Fig. 。. Fig. 3 is a waveform diagram for indicating the operation of the class D amplifier when a positive value is applied to the thyristor shown in Fig. 。. Fig. 4 is a waveform diagram for indicating the operation of the class D amplifier when a negative value is applied to the thyristor shown in Fig. 。. Fig. 5 is a circuit diagram showing an example of a structure for amplifying a crying of a scorpion according to a second embodiment of the present invention. Fig. 6 is a waveform diagram for indicating the operation of the class D amplifier when zero volts is applied to the steroid type amplifier shown in Fig. 5. 7 to 7C are diagrams for showing an example of a waveform appearing in a load when a sine wave is input to a class D amplifier according to a specific embodiment of the present invention or the specific embodiment 2. Fig. 8 is a circuit diagram showing an example of the structure of a thyristor amplifier according to a third embodiment of the present invention. Fig. 9 is a waveform diagram for indicating the operation of the class D amplifier when zero volts is applied to the class 1) amplifier shown in Fig. 8. Figure 10 is a waveform diagram for indicating the operation of the class D amplifier when a positive value is applied to the class D amplifier shown in Figure 8. Figure 11 is a waveform diagram for indicating the operation of the class D amplifier when a negative value is applied to the class D amplifier shown in Figure 1. Fig. 12 is a circuit diagram showing an example of the structure of a thyristor amplifier according to a fourth embodiment of the present invention. 95456.doc -47- 1257765 FIG. 13 is a circuit diagram showing an example of the structure of a current source of a class D amplifier. Figure 14 is a waveform diagram showing the operation of a current source. Waveform of the operation at positive values. Waveform of operation at volts. Waveform of operation at negative values. Figure 15 shows the application to the Class D amplifier. Figure 16 shows the application of zero to the class D amplifier. Figure 17 shows the application to the class D amplifier. [Main component symbol description] 1 Output 11 Operational amplifier 12 Comparator 13 Comparator 21 Delay circuit 22 delay circuit 31 AND circuit 32 AND circuit 61 operational amplifier 62 comparator 63 comparator 64 operational amplifier 71 AND circuit 72 AND circuit 100 capacitor 112 comparator 113 comparator 95456.doc -48- 1257765 121 inverter 122 inverter 131 AND circuit 132 AND circuit 140 Current source 141 Comparator 142 Comparator 143 NAND circuit 144 N AND circuit VL First potential VH Second potential e First synthesized wave f Second synthesized wave g Third synthesized wave h Fourth synthesized wave T1 package 曰 涯 T2 transistor Cl capacitor C2 capacitor C51 capacitor C100 capacitor V BH voltage VBn voltage VBp voltage

95456.doc -49- 1257765 R Resistor R1-R12 Resistor R51-R56 Resistor + OUT plus side output +IN plus side input terminal -OUT minus side output -IN minus side input terminal A minus side output B plus side output SI switch S2 switch F triangle wave G triangle wave a triangle wave signal b triangle wave signal a 丨 triangle wave signal bf triangle wave signal tl time t1, time t1, time t2 time t2f time t2, f time t3 time 95456.doc -50 - 1257765 t3, time T3'' time t4 time t4f time t4ff time t5, time t5M time t6f time t6, f time c output d output C output D output E output j output k output NOUT output POUT output

95456.doc -51 -

Claims (1)

1257765, patent application scope L A class D amplifier comprising: - an integrator for integrating an analog input signal; - a first comparator for comparing one of the integrator outputs with a first binary wave; a second comparator that compares the output of the integrator with a second triangular wave equal to a slight angle by adding a first angle to the first triangular wave offset by 180 degrees * a waveform of the minimum angle of the negative angle; the buffer 'which is based on the first comparison ' „ ± one of the pregnant states and one of the second than the rudder is output and outputs a side rim output仏唬 and - minus side output signal, Μ and a feedback circuit, which is added to the integrator by one of the side wheel 茬 gates 2. The request item 放大器 class amplifier, wherein the buffer comprises a - a: buffer, which calculates one of a logical multiplication signal of the output of the _tt (four) and the output of the comparison state Resulting; and subtracting a second buffer, Calculating a logical multiplication of the output of the _ comparator two comparators and calculating the result of one of the first signals. @ ' appears as the 侧 class amplifier of claim 1 The feedback circuit includes a large unit for amplifying the difference between the side wheel and the differential wheel. The wheeling signal and the side wheel output signal are 95456.doc 1257765 4. A class D amplifier comprising: Jie, which is a difference integral between the input signal and the input signal of one side of the analog input signal ;k; - the delay circuit, which will be a triangular wave: the phase delay is extremely small; a synthesis circuit , the integrator Α the two angle waves and one of the delay % road outputs are combined with each other, and the mouth force is outputted to output a plurality of output signals; a comparator that compares the synthesized circuit with the same; Hai Temple knows a number of round-out signals and a buffer's input to one of the comparator outputs; and a feedback circuit that feeds the output of the buffer ^^ to one of the input sides of the integral crying. 5·such as The class D amplifier of claim 4, wherein: the triangular wave is composed of a first triangular wave and a second triangular wave, wherein the first two-dimensional wave corresponds to a phase by the second vertice a waveform generated by shifting an angle of one degree of 180 degrees, the delay circuit including a first extension for delaying the phase of the first binary wave by the predetermined minimum angle, two paths for the first a triangular wave-delayed power, a skin-phase delay of the job-minimum angle, the synthesis circuit synthesizes the integrator, the subtraction side wheel and the first two self-waves to generate a first composite wave, a single corner, the first--&amp;;,士u 战°海积刀为' the plus side wheel out of the disciple to generate a second eight-yard, the circuit-output to produce a minus side output and the second extension... 50% of the object 95456.doc 1257765 wave 'and synthesizes the add side of the integrator and outputs one of the first delay circuits to generate a fourth composite wave, the comparator includes a first comparator for comparing the a first synthesized wave and the second synthesized wave; and a a second comparator for comparing the third composite wave with the fourth composite wave, the buffer body comprising a first buffer for calculating a logical product of the output of the first comparator and the output of the second ratio parent device And a first buffer state for differentiating a logical product of the output of the first comparator and the output of the second ratio first buffer comparator, and the feedback circuit includes a first feedback mine The output is fed back to the plus side input of the integrator; and a second feedback circuit is configured to feed the wheel of the second buffer back to the subtraction input of the integrator. 6. A class D amplifier comprising: an integrator, a differential integral between a side input signal and a subtraction side input signal constituting an m input signal; a synthesis circuit 'which synthesizes the integrator - outputting a - triangular wave, and synthesizing the round of the integrator and a triangular wave having a phase opposite to the phase of the first mentioned triangular wave, so as to rotate a plurality of signals, = the triangular wave of the opposite phase corresponds to - the waveform , the phase is offset by 18 degrees with respect to the phase shift of the triangular wave; a comparator, a buffer, a feedback circuit that compares the round-trip signals of the composite circuit with each other; and outputs one of the comparators Wheeling in; and 'which polls one of the buffers for feedback to one of the input sides of the integrator 95456.doc 1257765, wherein the synthesizing circuit includes a plurality of resistors having at least two resistance values' and is configured And the plurality of signals corresponding to the output of the composite circuit and the wind circuit according to the resistance values of the plurality of resistors and the input capacitance of one of the comparators A phase difference is generated. The class D amplifier of claim 6, wherein the synthesizing circuit comprises: a first synthesizing Qiu Ba Pak σ into a sub-division for synthesizing one of the integrators to reduce the side output and the triangular wave to generate a first a composite wave; a second synthesis portion for synthesizing the triangular wave of the opposite phase of the one of the mouthpieces of the cymbal blade and the opposite output phase to generate a first - 罘 合成 synthetic wave; a third compositing portion, It is used to synthesize the singularity of the singularity, the sigma of the sigma, and the triangular wave of the opposite phase, to generate a second person, a smash, a U and a fourth synthetic knife In the synthesis of the integral crying squad square ^ 乂丨 凡 / 不 刀 之 之 孩 加 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 / / / / / a terminal and the product are connected to the reduced side output and a resistor and a resistor, wherein the two-wave is applied to one of the terminals, and the other one of the resistors The terminal is connected to the second resistor crying package I and the other state a scorpion so as to constitute a terminal thereof; a syncymetic portion including a third resistor, a side turn-out connection of a terminal splitter, and a fourth resistor triangle wave applied to the And the other terminal of the third resistor is connected to the fourth electrical outlet terminal; the other one is unobstructed to form a round 95456.doc 1257765, the third composite portion includes a a fifth resistor having a side turn-off connection of a terminal splitter and a sixth resistor, wherein: a triangular wave of opposite phase is applied to its terminal; and the fifth resistor is a terminal is connected to the other terminal of the sixth resistor to: form an output terminal thereof; the fourth composite portion includes a seventh resistor, a terminal of which is connected to the side output of the integrator, and An eighth resistor, wherein the triangular wave is applied to one of the terminals; and the other terminal of the seventh resistor is connected to the eighth thunder and the other terminal of the crying 2^^ resistance is formed to constitute one of the Output The comparator includes a first comparator having an input terminal connected to the output terminal of the first synthesis portion, and another input terminal connected to the output terminal of the second synthesis portion; More than a car, having an input terminal connected to the wheel terminal of the third composite portion, and another input terminal connected to the output terminal of the fourth composite portion; . The buffer includes a -first buffer 'which is used to calculate a logical product of the output of the first comparator and an output of the second comparator; and a second buffer 'which is used to calculate the first a logical product of the output of the comparator and the output of the second comparator; the feedback circuit includes a first feedback circuit for feeding back the output of the first buffer to the adder of the integrator a side input, and a first return circuit for feeding the wheel of the second buffer back to the subtraction input of the integrator; and 95456.doc 1257765 the first resistor, the second resistor One of the resistance of the third resistor and the fourth resistor is different from any one of the fifth resistor, the sixth resistor, the seventh resistor, and the eighth resistor One of the resistance values. 8. The class D amplifier of claim 7, wherein the resistance value of each of the first resistor, the second resistor, the third resistor, and the fourth resistor is the fifth resistor The resistance value of each of the sixth resistor, the seventh resistor, and the eighth resistor is multiplied by a value obtained by dividing one value other than one. 9. A class D amplifier comprising: an integrator that integrates a differential input between a side input signal and a subtraction side input signal; and a triangular wave generating circuit including a current source and a capacitor; a comparator that compares one of the output of the integrator with an output of the triangular wave generating circuit; a buffer that inputs one of the outputs of the comparator; and a feedback circuit that one of the buffers The output is fed back to one of the input sides of the integrator. 10. The class D amplifier of claim 9, wherein: one of the ends of the capacitor is coupled to one of the input terminals of the comparator; and the current source switches one direction of the output current to repeat charging and discharging of the capacitor. 11. The class D amplifier of claim 10, wherein: one of the ends of the current source is coupled to the one end of the capacitor, 95456.doc 1257765 the current source is paired when the potential of one of the capacitors is lower than a first potential The capacitor charges a current flowing in one direction, and when the potential of the capacitor is higher than a second potential, a current flows in a direction of discharging the capacitor, and the second potential is higher than the first potential. 12. The class D amplifier of claim 9, wherein: the comparator comprises a first comparator for comparing one of the inverting outputs of the integrator to the output of the triangular wave generating circuit; and a second comparator And comparing the output of one of the integrators to the output of the triangular wave generating circuit, the buffer comprising a first buffer for calculating an inverted value of the output of one of the first comparators One of the second comparator outputs a logical product; and a second buffer for calculating a logical product of an inverted value of one of the first comparator and the second comparator, and the feedback circuit a first feedback circuit for outputting one of the first buffers to one of the inverting inputs of the integrator, and a second feedback circuit for outputting one of the second buffers Add one side input to one of the integrators. 95456.doc