TWI257157B - Flip chip ball grid array package assemblies - Google Patents
Flip chip ball grid array package assembliesInfo
- Publication number
- TWI257157B TWI257157B TW094115540A TW94115540A TWI257157B TW I257157 B TWI257157 B TW I257157B TW 094115540 A TW094115540 A TW 094115540A TW 94115540 A TW94115540 A TW 94115540A TW I257157 B TWI257157 B TW I257157B
- Authority
- TW
- Taiwan
- Prior art keywords
- grid array
- ball grid
- flip chip
- chip
- array package
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/002,240 US20060118969A1 (en) | 2004-12-03 | 2004-12-03 | Flip chip ball grid array package assemblies and electronic devices with heat dissipation capability |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200620594A TW200620594A (en) | 2006-06-16 |
TWI257157B true TWI257157B (en) | 2006-06-21 |
Family
ID=36573285
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094115540A TWI257157B (en) | 2004-12-03 | 2005-05-13 | Flip chip ball grid array package assemblies |
Country Status (3)
Country | Link |
---|---|
US (1) | US20060118969A1 (zh) |
CN (1) | CN100378971C (zh) |
TW (1) | TWI257157B (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI302821B (en) * | 2005-08-18 | 2008-11-01 | Ind Tech Res Inst | Flexible circuit board with heat sink |
JP5103863B2 (ja) * | 2006-10-16 | 2012-12-19 | 富士電機株式会社 | 半導体装置 |
US20110073294A1 (en) * | 2009-09-25 | 2011-03-31 | Macdonald Mark | System, method and apparatus of cool touch housings |
EP2509103A1 (en) * | 2011-04-04 | 2012-10-10 | ABB Oy | Apparatus and method for thermal connection |
US20130250522A1 (en) * | 2012-03-22 | 2013-09-26 | Varian Medical Systems, Inc. | Heat sink profile for interface to thermally conductive material |
US20130291555A1 (en) | 2012-05-07 | 2013-11-07 | Phononic Devices, Inc. | Thermoelectric refrigeration system control scheme for high efficiency performance |
JP6403664B2 (ja) * | 2012-05-07 | 2018-10-10 | フォノニック デバイセズ、インク | 保護用熱拡散蓋および最適な熱界面抵抗を含む熱電熱交換器部品 |
US9041192B2 (en) * | 2012-08-29 | 2015-05-26 | Broadcom Corporation | Hybrid thermal interface material for IC packages with integrated heat spreader |
CN102856273A (zh) * | 2012-09-06 | 2013-01-02 | 日月光半导体制造股份有限公司 | 具有散热片的半导体组装构造及其组装方法 |
WO2015111242A1 (ja) * | 2014-01-21 | 2015-07-30 | 富士通株式会社 | 放熱部品、放熱部品の製造方法、電子装置、電子装置の製造方法、一体型モジュール、情報処理システム |
US10458683B2 (en) | 2014-07-21 | 2019-10-29 | Phononic, Inc. | Systems and methods for mitigating heat rejection limitations of a thermoelectric module |
US9593871B2 (en) | 2014-07-21 | 2017-03-14 | Phononic Devices, Inc. | Systems and methods for operating a thermoelectric module to increase efficiency |
US9653373B2 (en) * | 2015-04-09 | 2017-05-16 | Samsung Electronics Co., Ltd. | Semiconductor package including heat spreader and method for manufacturing the same |
JP6382784B2 (ja) * | 2015-11-26 | 2018-08-29 | 株式会社Soken | 半導体装置の製造方法 |
US10177060B2 (en) * | 2016-10-21 | 2019-01-08 | Powertech Technology Inc. | Chip package structure and manufacturing method thereof |
JP2019161773A (ja) * | 2018-03-09 | 2019-09-19 | 株式会社デンソー | 回転電機 |
US11823972B2 (en) * | 2018-07-20 | 2023-11-21 | Intel Corporation | Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices |
US11621208B2 (en) | 2018-07-20 | 2023-04-04 | Intel Corporation | Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices |
US11177192B2 (en) * | 2018-09-27 | 2021-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including heat dissipation structure and fabricating method of the same |
CN111092062B (zh) * | 2018-10-24 | 2021-06-08 | 欣兴电子股份有限公司 | 晶片封装结构及其制造方法 |
CN115831772B (zh) * | 2023-02-23 | 2023-05-26 | 江苏元核芯技术有限责任公司 | 一种半导体封装结构及封装方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5838064A (en) * | 1994-04-22 | 1998-11-17 | Nec Corporation | Supporting member for cooling means and electronic package using the same |
US6506681B2 (en) * | 2000-12-06 | 2003-01-14 | Micron Technology, Inc. | Thin flip—chip method |
JP2003031744A (ja) * | 2001-07-12 | 2003-01-31 | Mitsubishi Electric Corp | 半導体装置 |
US6757170B2 (en) * | 2002-07-26 | 2004-06-29 | Intel Corporation | Heat sink and package surface design |
-
2004
- 2004-12-03 US US11/002,240 patent/US20060118969A1/en not_active Abandoned
-
2005
- 2005-05-13 TW TW094115540A patent/TWI257157B/zh active
- 2005-06-23 CN CNB2005100774662A patent/CN100378971C/zh active Active
Also Published As
Publication number | Publication date |
---|---|
TW200620594A (en) | 2006-06-16 |
US20060118969A1 (en) | 2006-06-08 |
CN100378971C (zh) | 2008-04-02 |
CN1783461A (zh) | 2006-06-07 |
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