TWI257132B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
TWI257132B
TWI257132B TW093119277A TW93119277A TWI257132B TW I257132 B TWI257132 B TW I257132B TW 093119277 A TW093119277 A TW 093119277A TW 93119277 A TW93119277 A TW 93119277A TW I257132 B TWI257132 B TW I257132B
Authority
TW
Taiwan
Prior art keywords
oxide film
semiconductor device
high voltage
gate oxide
voltage region
Prior art date
Application number
TW093119277A
Other languages
English (en)
Other versions
TW200522217A (en
Inventor
Sang-Wook Park
Seung-Cheol Lee
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200522217A publication Critical patent/TW200522217A/zh
Application granted granted Critical
Publication of TWI257132B publication Critical patent/TWI257132B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)
  • Local Oxidation Of Silicon (AREA)
TW093119277A 2003-12-29 2004-06-30 Method for manufacturing semiconductor device TWI257132B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030098846A KR100612557B1 (ko) 2003-12-29 2003-12-29 반도체 소자의 제조 방법

Publications (2)

Publication Number Publication Date
TW200522217A TW200522217A (en) 2005-07-01
TWI257132B true TWI257132B (en) 2006-06-21

Family

ID=34698659

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093119277A TWI257132B (en) 2003-12-29 2004-06-30 Method for manufacturing semiconductor device

Country Status (5)

Country Link
US (1) US20050142764A1 (zh)
JP (1) JP4401250B2 (zh)
KR (1) KR100612557B1 (zh)
CN (1) CN100355041C (zh)
TW (1) TWI257132B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100539083C (zh) * 2007-05-21 2009-09-09 中芯国际集成电路制造(上海)有限公司 闪存器件的制造方法
KR101175148B1 (ko) * 2010-10-14 2012-08-20 주식회사 유진테크 3차원 구조의 메모리 소자를 제조하는 방법 및 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023085A (en) * 1997-12-18 2000-02-08 Advanced Micro Devices, Inc. Core cell structure and corresponding process for NAND-type high performance flash memory device
TW374939B (en) * 1997-12-19 1999-11-21 Promos Technologies Inc Method of formation of 2 gate oxide layers of different thickness in an IC
JP3194370B2 (ja) * 1998-05-11 2001-07-30 日本電気株式会社 半導体装置とその製造方法
US6165918A (en) * 1999-05-06 2000-12-26 Integrated Device Technology, Inc. Method for forming gate oxides of different thicknesses
KR100414211B1 (ko) * 2001-03-17 2004-01-07 삼성전자주식회사 모노스 게이트 구조를 갖는 비휘발성 메모리소자 및 그제조방법
JP3719192B2 (ja) * 2001-10-26 2005-11-24 セイコーエプソン株式会社 半導体装置の製造方法
US6818514B2 (en) * 2003-02-26 2004-11-16 Silterra Malaysia Sdn. Bhd. Semiconductor device with dual gate oxides

Also Published As

Publication number Publication date
CN1638063A (zh) 2005-07-13
CN100355041C (zh) 2007-12-12
TW200522217A (en) 2005-07-01
US20050142764A1 (en) 2005-06-30
JP4401250B2 (ja) 2010-01-20
KR100612557B1 (ko) 2006-08-11
KR20050067824A (ko) 2005-07-05
JP2005197636A (ja) 2005-07-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees