1254393 九、發明說明： 【發明所屬之技術領域】 本發明係關於積體電路晶片的一階構裝，尤其是有關於 一階構裝所用基板一種製程方法，係於基板的金手指與接觸 墊的外側表面電鍍有一層鎳金的製程與結構，提供金手指與 接觸墊良好的電性連接和耐磨耗的品質。 【先前技術】 積體電路晶片必須經過構裝程序與電子系統整合才能發 其功能。在積體電路晶片構裝的產業裡，一般將晶片本身的 製作稱為所謂的零階構裝，將晶片安裝到基板（或稱載板、 substrate )或導線架（lead frame )的程序稱為一階構裝（pdmary level package )’ 一階構裝兀成的晶片安裝到模組或介面卡的 印刷電路板上料m最後將模組或介面卡安裝到母 板或系統板的過程稱為三階構裝。 一階構裝中所㈣基板，除了設置有細密的線路外，還 有許多電性接觸塾（或稱1/0接點，像是bonding pad'bmnp pad、baU pad、c〇ntact pad # )。這些ι/〇接點通常在表面鐘 有一層錄金（Ni/Au)層，以確保與晶片電性連接的穩定性， 或保護金屬鋼f㈣體核氧化。Μ接㈣上鍍上這層錄 金層’通常必須在基板上另外佈置眾多的電錢導線 ，以供電 鑛時導通電流之用。這些電鍍導線的佈置不僅占據基板的面 積，還易在财高頻晶片時，容易對高頻晶片造成雜訊的困 1254393 擾。因此，近年來，業界有提出數種所謂無電鍍導線（buss less) 的基板製程方法，以解決電鍍導線的佈置所造成的問題。 其中，業界提出的一種名為GPP ( Gold Pattern Plating ) 製程方法，是不另外佈設電鍍用的導線，而是在基板本身的 線路上（也因此包含了所有接觸墊）全部鍍上鎳金。此一習 知技術雖然避免了電鍍導線的佈設，但是所有線路的表面都 有鍍上鎳金，因此生產成本相當高昂，此外，最後塗覆於基 板表面的防焊阻劑（solder mask)因其材質特性與鎳金層相 異以致不能穩定的密合。另外在中華民國專利公告號515,061 號專利揭露了另外一種製程技術，這一製程技術是在已經定 義有線路層的基板上，覆蓋一層導電膜，再用影像轉移的方 式定義出I/O接點的區域，再以電鍍方式將鎳金層鍍於接觸 墊的表面，導電膜提供了電鍍時電流的傳導路徑，因此也避 免了電鍍導線的佈設。還有一種製程技術，係揭露於中華民 國專利公告號538，152號，這一製程技術是先在基板表面佈 設一薄銅層，再用二次影像轉移的方式，先後定義出線路的 鍍銅區域和接觸墊的鍍鎳金區域，然後將二次影像轉移的光 阻以及薄銅層移除，最後再塗覆上防焊阻劑。 上述的製程方法雖然都避免了 GPP的鍍鎳金區域過大、 鎳金與防焊阻劑大面積接觸的問題，但是都有流程步驟都過 於冗長、不適用於基板兩面金屬表面處理（metal finish)不 1254393 同的應用等缺點。例如現在流行的消費性電子產品如數位相 機、數位錄影機、MP3隨身聽、電子字典、PDA、多媒體手 機等不可或缺的小體積快閃記憶體卡（例如MMC卡），其在 基板的一面具有作為插拔的金手指，在基板的另一面具有電 性接觸塾作為打線之用（wire bonding )，習知的無電鐘導線 製程技術並不適用於這類產品。 【發明内容】 本發明的主要目的係提供一種一階構裝機板的製程方 法，這個製程方法適用於需要基板兩面有不同金屬處理的應 用（例如MMC卡的構裝）。 本發明所提出的製程方法最主要的特徵是先在基板的上 表面以酸性蝕刻的方式形成線路，再於基板的下表面以第二 次的影像轉移以定義所需電鍍的金手指部份，然後先在金手 指上鍍上鎳金層，再於接觸墊上鍍上鎳金層。 本發明所提出的製程方法，以無電鍍導線的方式在接觸 墊與金手指上鍍上鎳金層，可以增加基板表面有效的佈線面 積，同時避免因為佈設電鍍導線而致的雜訊干擾。 本發明所提出的製程方法，可以避免習知技術的鎳金面 積過大、流程冗長、信賴度低的缺點。 茲配合所附圖示、實施例之詳細說明及申請專利範圍， 將上述及本發明之其他目的與優點詳述於後。然而，當可了 1254393 解所附圖示純係為解說本發明之精神而設，不當視為本發明 範疇之定義。有關本發明範疇之定義，請參照所附之申請專 利範圍。 【實施方式】 有關本發明的具體實施方式，請參閱第1圖。第1圖係 本發明各步驟之剖面結構示意圖。 首先提供一基板100，如第la圖所示，該基板100的上 下表面分別已經佈設有線路層110，並具有若干導通孔120。 接著在基板100的上表面，以乾膜（dry film)或液態光 阻影像轉移以及酸性蝕刻的方式形成導體線路112,其結果如 第lb圖所示。 然後，在基板100的下表面，同樣以乾膜（dry film)或 液態光阻的方式進行第二次影像轉移，以定義出需要鍍鎳金 的金手指區域，其結果如第lc圖所示。 接著，再以電鍍的方式，利用線路層110作為電鍍電流 的導通，在前一步驟所定義出來的金手指區域，鑛上鎳金層 114，其結果如第Id圖所示。請注意到導通孔壁與部份連通 之導體線路112上亦鍍有鎳金層。 流程接著將第二次影像轉移的光阻移除，再以乾膜（dry film)或液態光阻的方式進行第三次影像轉移，並以驗性餘刻 形成需要鍍鎳金的接觸墊區域，其結果如第le圖所示。 1254393 接著，再以電鐘的方式，在前一步驟所定義出來的接觸 墊區域，鍍上鎳金層116，其結果如第If圖所示。最後再印 製圖案化的的防焊阻劑以完成此基板的製作。 藉由以上較佳具體實施例之詳述，係希望能更加清楚描 述本創作之特徵與精神，而並非以上述所揭露的較佳具體實 施例來對本創作之範舜加以限制。相反地，其目的是希望能 涵蓋各種改變及具相等性的安排於本創作所欲申請之專利範 圍的範疇内。 【圖式簡單說明】 第la圖至If圖係依據本發明各個步驟實施後基板之剖面結 構示意圖。 【主要元件符號說明】 100 基板 110 線路層 112 導體線路 114 鎳金層 116 鎳金層 130 導通孔1254393 IX. Description of the Invention: [Technical Field] The present invention relates to a first-order structure of an integrated circuit wafer, and more particularly to a method for manufacturing a substrate for a first-order structure, which is a gold finger and a contact pad of a substrate The outer surface is plated with a layer of nickel gold in a process and structure to provide good electrical connection and wear resistance of the gold finger and the contact pad. [Prior Art] Integrated circuit chips must be integrated with an electronic system to perform their functions. In the industry of integrated circuit chip assembly, the fabrication of the wafer itself is generally referred to as a so-called zero-order configuration, and the process of mounting the wafer to a substrate (or carrier board, substrate) or lead frame is called a program. Pdmary level package 'The process of mounting the wafer of the first-order structure to the printed circuit board of the module or interface card, and finally mounting the module or interface card to the motherboard or system board is called Third-order construction. In the first-order structure, in addition to the fine lines, there are many electrical contacts (or 1/0 contacts, such as bonding pad'bmnp pad, baU pad, c〇ntact pad #). . These ι/〇 contacts usually have a layer of gold (Ni/Au) on the surface of the surface to ensure the stability of the electrical connection to the wafer, or to protect the metal nucleus of the metal (f). The splicing (4) is plated with this layer of gold deposits. Usually, a large number of electric money wires must be arranged on the substrate to supply current for conducting electricity. The arrangement of these electroplated wires not only occupies the area of the substrate, but also easily interferes with the high frequency wafers when the high frequency wafer is used. Therefore, in recent years, there have been several substrate processing methods for so-called electroless wires (buss less) in order to solve the problems caused by the arrangement of electroplated wires. Among them, a method proposed by the industry called GPP (Gold Pattern Plating) is not to arranging wires for electroplating, but to plate all nickel gold on the wires of the substrate itself (and thus all contact pads). Although this prior art avoids the layout of the electroplated wires, the surface of all the lines is plated with nickel gold, so the production cost is quite high, and in addition, the solder mask finally applied to the surface of the substrate is The material properties are different from those of the nickel-gold layer so that they cannot be stably adhered. In addition, in the Republic of China Patent Publication No. 515,061, another process technology is disclosed. The process technology is to cover a layer of conductive film on a substrate on which a circuit layer has been defined, and then define an I/O contact by means of image transfer. The region is then plated with a nickel-gold layer on the surface of the contact pad. The conductive film provides a conductive path for the current during plating, thus avoiding the routing of the plated wire. There is also a process technology, which is disclosed in the Republic of China Patent Bulletin No. 538,152. This process technology is to first lay a thin copper layer on the surface of the substrate, and then use secondary image transfer to define the copper plating of the line. The area and the nickel-plated gold area of the contact pad are then removed from the secondary image transfer photoresist and the thin copper layer, and finally coated with a solder resist. Although the above-mentioned process method avoids the problem that the nickel plating gold area of the GPP is too large, and the nickel gold and the solder resist are in contact with a large area, the process steps are too long and are not suitable for the metal finish of the substrate. Not the disadvantages of the same application of 1254393. For example, popular consumer electronic products such as digital cameras, digital video recorders, MP3 players, electronic dictionaries, PDAs, multimedia mobile phones, etc. are indispensable small-sized flash memory cards (such as MMC cards) on one side of the substrate. It has a gold finger as a plug and has an electrical contact on the other side of the substrate as a wire bond. The conventional electroless wire process technology is not suitable for such products. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a process method for a first-order fabric board that is suitable for applications requiring different metal treatments on both sides of the substrate (e.g., MMC card mounting). The most important feature of the process method proposed by the present invention is that the circuit is formed by acid etching on the upper surface of the substrate, and the second image transfer is performed on the lower surface of the substrate to define the gold finger portion of the desired plating. Then, the gold finger is first plated with a layer of nickel gold, and then the contact pad is plated with a layer of nickel gold. The process method proposed by the present invention coats the contact pad and the gold finger with a nickel-gold layer by means of an electroless wire, thereby increasing the effective wiring area of the substrate surface and avoiding noise interference caused by the plating of the plating wire. The process method proposed by the invention can avoid the disadvantages of the prior art that the nickel-gold area is too large, the process is tedious, and the reliability is low. The above and other objects and advantages of the present invention will be described in detail with reference to the accompanying drawings and claims. However, it is to be understood that the appended drawings are purely illustrative of the spirit of the invention, and are not considered as a definition of the scope of the invention. For the definition of the scope of the invention, please refer to the attached patent application. [Embodiment] Referring to Figure 1 for a specific embodiment of the present invention. Fig. 1 is a schematic cross-sectional view showing the steps of the present invention. First, a substrate 100 is provided. As shown in FIG. 1a, the upper and lower surfaces of the substrate 100 are respectively provided with a wiring layer 110 and have a plurality of via holes 120. Next, on the upper surface of the substrate 100, the conductor wiring 112 is formed by dry film or liquid photoresist image transfer and acid etching, and the result is as shown in Fig. 1b. Then, on the lower surface of the substrate 100, the second image transfer is also performed in the form of a dry film or a liquid photoresist to define a gold finger region requiring nickel plating, and the result is as shown in FIG. . Next, the wiring layer 110 is used as the conduction of the plating current by electroplating, and the nickel-gold layer 114 is deposited on the gold finger region defined in the previous step, and the result is as shown in Fig. Id. Please note that the via hole wall and the partially connected conductor line 112 are also plated with a layer of nickel gold. The process then removes the photoresist from the second image transfer, and then performs a third image transfer in the form of a dry film or a liquid photoresist, and forms a contact pad region that needs to be plated with nickel in an illustrative manner. The result is shown in the figure le. 1254393 Next, in the form of an electric clock, the nickel pad layer 116 is plated on the contact pad region defined in the previous step, and the result is as shown in Fig. If. Finally, a patterned solder resist is printed to complete the fabrication of the substrate. The features and spirit of the present invention are intended to be more apparent from the detailed description of the preferred embodiments. On the contrary, the purpose is to cover a variety of changes and equivalence arrangements within the scope of the patent application to which this creative is intended. BRIEF DESCRIPTION OF THE DRAWINGS The first to the Fig. diagrams are schematic views showing the structure of a substrate after the steps of the present invention are carried out. [Main component symbol description] 100 Substrate 110 Circuit layer 112 Conductor line 114 Nickel gold layer 116 Nickel gold layer 130 Via hole