TWI254353B - Solid-state of micro-light-emitting-device array - Google Patents

Solid-state of micro-light-emitting-device array Download PDF

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TWI254353B
TWI254353B TW94121435A TW94121435A TWI254353B TW I254353 B TWI254353 B TW I254353B TW 94121435 A TW94121435 A TW 94121435A TW 94121435 A TW94121435 A TW 94121435A TW I254353 B TWI254353 B TW I254353B
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light
emitting
solid
substrate
layer
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TW94121435A
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TW200701320A (en
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Dong-Sing Wuu
Ray-Hua Horng
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Univ Nat Chunghsing
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Abstract

A solid-state of micro-light-emitting-device array comprises a substrate, and a plurality of light emitting chips set on the substrate apart from each other. Each of the light emitting chips has a plurality of light emitting protrusions set on the substrate apart from each other and respectively having a surrounding surface. Each of the light emitting chips is defined a plurality of channels crossing each other by the light emitting protrusions and the substrate. Each of the light chips further has an insulator covered the substrate and the surrounding surfaces, and a current spreading layer formed on the insulator and the light emitting protrusions, so as to sandwich the light emitting protrusions and the insulator between the current spreading layer and the substrate.

Description

1254353 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種固態發光元件(s〇lid state light emitting device),特別是指一種固態微發光元件 陣列。 【先前技術】 參閱圖 1,H. W. Choi 及 C. W· Jeon 等人於 IEEE PHOTONIC TECHNOLOGY LETTERS, VOL. 15, NO. 4, APRIL 2003揭露一種並列設置之氮化銦鎵(InGaN)微發光二極體 陣列(Micro-LED arrays) 1的製法及其性能。 首先,於一藍寶石(sapphire)基板1〇上形成一磊晶體 (epitaxial crystal)11。該磊晶體n由該藍寶石基板1〇 向上依序具有一厚度為〇· 025 μιη的GaN緩衝膜111、一厚 度為3· 2 μιη的矽摻雜GaN(亦即;Si-doped GaN)膜112、 尽度為0.47 μπι的多層置子井(mui ti-quantum wal 1,簡 稱MQW)膜113 ’及一厚度為0.25 μπι的鎂摻雜GaN膜114。 利用電感耦式電漿(inductively c〇upled plas,簡 % ICP)乾式蝕刻對該磊晶體丨丨施予一乾式蝕刻製程。該乾 式蝕刻衣耘的彳呆作條件是分別通入流量為3〇 的氣氣 (Cl2)及10 SCCffl的氬氣(Ar)作為蝕刻氣體源,並在25°C的 蝕刻度及20 mT〇rr的工作壓力下分別提供一 4〇〇 w的 IPC功率及一 200 w的反應式離子蝕刻(reactive ion— etching簡稱RIE)功率,以—〇·5 的姓刻速度對 4视日日肢11貫施乾式蝕刻,並使覆蓋有一遮罩(mask)的該 1254353 成曰曰體11經該乾式钱刻製程後形成複數相間隔設置的發光 凸柱U。值得—提的是’該藍寶石基板1G上是形成有複 數間隔設置的晶粒(ehip)1,,其中,m t,具有前述相 間iw置的發光凸柱(i ’ (圖i中僅顯示一晶粒r說明。1254353 IX. Description of the Invention: [Technical Field] The present invention relates to a solid state light emitting device, and more particularly to an array of solid state light emitting elements. [Prior Art] Referring to Figure 1, HW Choi and C. W. Jeon et al., IEEE PHOTONIC TECHNOLOGY LETTERS, VOL. 15, NO. 4, APRIL 2003, disclose a side-by-side arrangement of indium gallium nitride (InGaN) micro-emitting dipoles. The method of micro-LED arrays 1 and its performance. First, an epitaxial crystal 11 is formed on a sapphire substrate. The epitaxial crystal n has a GaN buffer film 111 having a thickness of 〇·025 μm and a ytterbium doped GaN (ie, Si-doped GaN) film 112 having a thickness of 3.2 μm. A micro-titanium well (mui ti-quantum wal 1, referred to as MQW) film 113' and a magnesium-doped GaN film 114 having a thickness of 0.25 μm. The epitaxial germanium is subjected to a dry etching process by inductively c〇upled plas (simplified % ICP) dry etching. The dry etching condition of the dry etching enamel is that an air gas (Cl2) having a flow rate of 3 Torr and an argon gas (Ar) of 10 SCCffl are respectively used as an etching gas source, and an etching degree at 25 ° C and 20 mT 〇 Under the working pressure of rr, a 4 〇〇w IPC power and a 200 watt reactive ion etch (RIE) power are respectively provided, and the speed of the 姓·5 is 4 The dry etching is performed, and the 1254353 formed body 11 covered with a mask is subjected to the dry etching process to form a plurality of spaced-apart light-emitting posts U. It is worth mentioning that 'the sapphire substrate 1G is formed with a plurality of spaced-apart crystals (ehip) 1 , wherein mt has the above-mentioned inter-phase iw-shaped light-emitting studs (i ' (only one crystal is shown in FIG. Description of the grain r.

者利用電子束蒸鍍(electron-beam evaporation) ,每一晶粒Γ的該等發光凸柱11,上形成-厚度為40 nm的 氧化夕(Si〇2)膜12以作為隔絕(is〇latic)n)用,並於每一晶 粒1’裸露出局部的石夕摻雜GaN膜112以供電極接觸用,^ 中,位於每—發光&柱11,最上方的鎂摻雜GaN膜1U未 被》亥氧化秒膜12覆蓋。另外,於每一晶粒i,的氧化石夕膜η 上繼續形成-傳導(reading)貞13,其中,每—傳導膜 13是由-形成於該氧切膜12上且厚度為3() μ的錄㈤ 金屬層,及一形成於該鎳金屬層上且厚度為3〇㈣的金 (Au)金屬層所構成。Using electron-beam evaporation, the light-emitting studs 11 of each of the crystal grains are formed, and a 40 nm-thickness yttrium (Si〇2) film 12 is formed as an isolation (is〇latic). ))), and in each of the crystal grains 1' bare exposed local shi-doped GaN film 112 for electrode contact, in each of the - luminescence & column 11, the uppermost magnesium-doped GaN film 1U is not covered by the "Hee Oxide Second Film" 12. Further, a read 贞 13 is continuously formed on the oxidized oxide film η of each of the crystal grains i, wherein each of the conductive films 13 is formed by - on the oxygen cut film 12 and has a thickness of 3 () A recording layer of (5) metal layers and a gold (Au) metal layer formed on the nickel metal layer and having a thickness of 3 Å (four).

最後,於每一裸露出局部的矽摻雜GaN膜 一傳導膜13處分別形成一 n—接觸電極工4及一 H2處及每 P-接觸電極 15,進而完成該並列設置之氮化銦鎵微發光二極體陣列i。 其中’每- η-型接觸電14是由一形成於該矽摻雜GaN膜 H2且厚度為20 nm的鈦㈤金屬層,及一形成於該欽金屬 層上且厚度為200 nm的鋁(A1)金屬層所構成,此外,每一 P-接觸電極15的結構是與該傳導膜13相同,其不同處僅 在於該錄金屬層的厚度| 2Gnm’且該金金屬層的厚度為 200 nm 〇 ” 雖然可藉由該等發光凸柱 11 ’的側部以增加該並列設置 1254353 之氮化鋼鎵微發光二極體陣列1之整體的外部量子效率 (external quantum effect),進而避免光源因橫向傳遞所 構成的吸收及衰減等問題而影響LED整體的外部量子效率 〇 然而’針對監光發光二極體而言,由於藍光的能隙 (energy bandgap)較大所需激發能高,因此施加於藍光發 光一極體之驅動電流(driving current)值也相對提高。當 長:供於監光發光二極體上的注入電流(in jecti〇n current) 值越大時,所產生的累積熱能也相對地增加。因此,由該 並列設置之氮化銦鎵微發光二極體陣列1的結構可知,形 成於元件内部的熱應力(thermal stress)將隨著該屋晶體 Π與該藍寶石基板1 〇之間的接觸面積增加並降低其元件整 體的信賴性。 热悉固悲舍光元件之晶圓貼合技術bonding technology)的相關領域者皆知,該並列設置之氮化銦鎵微 發光二極體陣列1雖然可藉由晶圓貼合技術提供一散熱性 佳的基板’但仍將因熱膨脹係數(让ermal eXpansi〇n coefficient)差異過大而導致信賴性不穩等問題。 此外’該並列設置之氮化銦鎵微發光二極體陣列1是 屬於水平導通(horizontal feedthrough)式的固態發光元 件,一旦單一晶.(chip)l,上的η-接觸電極14損毁時,該 等發光凸柱1 Γ則無法獨自發光,因此,單一晶粒丨,的有效 使用率低。 由上所述’在考量提昇固態發光元件之外部量子效率 1254353 =同日:’亦需降低元件@熱應力的問題而使得整體元件可 付合㈣性的要求並增加單—晶粒的有效使用帛,是開發 固態發光元件相關領域者所需共同克服的難題。 ^ 【發明内容】 因此,本發明之目的,即在提供一種固態微發光 陣列’特別是指一種外部量子效率高、元件熱應力問題少Finally, an n-contact electrode 4 and an H2 and a P-contact electrode 15 are respectively formed at each of the exposed germanium-doped GaN film-conducting films 13, thereby completing the parallel arrangement of indium gallium nitride. Micro-lighting diode array i. Wherein the 'per-n-type contact current 14 is a titanium (five) metal layer formed on the germanium-doped GaN film H2 and having a thickness of 20 nm, and an aluminum formed on the metal layer and having a thickness of 200 nm ( A1) is composed of a metal layer. Further, the structure of each P-contact electrode 15 is the same as that of the conductive film 13, except that the thickness of the metal layer is 2 Gnm' and the thickness of the gold metal layer is 200 nm. 〇” Although the external quantum effect of the nitrided gallium micro-light emitting diode array 1 of the parallel arrangement of 1,254,353 can be increased by the side portions of the light-emitting studs 11 ′, thereby avoiding the light source Problems such as absorption and attenuation caused by lateral transmission affect the external quantum efficiency of the LED as a whole. However, for the light-emitting diode, the excitation energy is high because the energy bandgap of the blue light is large, so The driving current value of the blue light emitting body is also relatively increased. When the length of the injection current (injecti〇n current) applied to the light-emitting diode is larger, the generated cumulative heat energy is generated. It also increased relatively. Therefore, the structure of the indium gallium nitride micro-light-emitting diode array 1 arranged in parallel is such that the thermal stress formed inside the element will follow the contact between the house crystal Π and the sapphire substrate 1 〇. The area is increased and the reliability of the entire component is reduced. It is known in the related art of the bonding technology of the chip bonding technology that the parallel arrangement of the indium gallium nitride micro-light emitting diode array 1 is A substrate with good heat dissipation can be provided by the wafer bonding technology, but the problem of unstable reliability due to the difference in thermal expansion coefficient (the ermal eXpansi〇n coefficient) is still exceeded. The gallium micro-light emitting diode array 1 is a horizontal feedthrough type solid-state light-emitting element. Once the single crystal chip 14 is damaged, the light-emitting studs 1 cannot be It emits light by itself, so the effective use rate of single crystal ruthenium is low. From the above, the external quantum efficiency of the solid-state light-emitting element is raised in consideration of 1,254,353 = the same day: 'the component also needs to be lowered @热应The problem that the overall component can meet the requirements of (4) and increase the effective use of the single-grain is a problem that must be overcome by the related fields in the development of solid-state light-emitting components. [Invention] Therefore, the object of the present invention That is, providing a solid-state micro-luminescence array' means, in particular, an external quantum efficiency is high, and the component thermal stress problem is small.

:符合信賴性要求且單一晶粒的有效使用率高之固態微發 光元件陣列。 毅、尤70仵陣列 w疋,桊發明 板及複數相間隔設置於該基板的發光晶粒 母一發光晶粒具有複數相間隔地設置於該基板上並分 別具有-圍繞面的發光凸塊。每一發光晶粒藉該等發光凸 塊及該基板界定出複數相 _ 又粗日7逋迢。母一發光晶粒更 - 復盍5亥基板及該等圍繞面的絕緣體,及一形成於該 絕緣體及該等發光凸塊上的電气 、 7包/瓜政佈層,致使該等發光凸 塊及該絕緣體被夾置於該電流散佈層及該基板之間。 【實施方式】 〈發明概要〉 * 一般而言,形成於兩種不同材料内部的熱應力,可推 :到兩大原因:一是兩不同材質之間熱膨脹係數差異大, 另一則是兩不同材質之間的接觸 償過大。當兩不同材料 之間的熱膨脹係數差異越大時,則# 介碎# 幻形成於其内部的熱應力 亦隧者施予其中的溫度增加而提高 ^ 此外,當兩不同材料 之間的接觸面積越大時亦然。 8 1254353 =久以來’Ml態發光元件有待解決的問題即在於 基材散熱不易的現象。雖然藉由晶圓貼合技術可提供 土熱傳性佳的基材’但礙於水平導通式之設計,該熱傳性 佳的基材與蠢晶體之間的熱膨服係數差異大,且接觸面積 過大,因此,累積於遙晶體處的大量熱應力仍將因裂損 (crackmg)或基材分離而影響固態發光元 ,本發明藉由配合使用晶圓貼合二: A solid-state micro-emission device array that meets the reliability requirements and has a high effective use rate of a single die. The y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y Each of the illuminating dies defines a complex phase _ and a coarse day by the illuminating bumps and the substrate. a mother-emitting illuminating crystal - a ruthenium substrate and an insulating body surrounding the surface, and an electrical, 7-pack/guar fabric layer formed on the insulator and the illuminating bumps, thereby causing the illuminating bumps And the insulator is sandwiched between the current spreading layer and the substrate. [Embodiment] <Summary of Invention> * In general, the thermal stress formed inside two different materials can be pushed to two main reasons: one is that the difference in thermal expansion coefficient between two different materials is large, and the other is two different materials. The contact between the two is overpaid. When the difference in thermal expansion coefficient between two different materials is greater, then the thermal stress formed in the interior of the crease is also increased by the temperature applied by the tunneler. Furthermore, when the contact area between the two different materials is increased The bigger the time is. 8 1254353 = The problem that the 'Ml state light-emitting element has to solve for a long time is that the substrate is not easy to dissipate heat. Although the substrate heat-carrying substrate can be provided by the wafer bonding technology, the thermal expansion coefficient between the heat-transfer substrate and the stray crystal is greatly different due to the horizontal conductive design. The contact area is too large. Therefore, a large amount of thermal stress accumulated in the remote crystal will still affect the solid state light-emitting element due to cracking or separation of the substrate, and the present invention is bonded by using the wafer.

基材契说曰曰體之間的接觸面積,以降低蠢晶體本身所產生 的熱能累積對基材的影響,並藉以提高固態發光 賴性。 〈發明詳細說明〉 有關本發明之前述及其他技術内容、特點與功效,在 以下配合參考圖式之兩個較佳實施例的詳細說明中,將可 清楚的呈現。 在本發明被詳細描述之前,要注意的是,在以下的說 明内容中,類似的元件是以相同的編號來表示。 苓閱圖2及圖3,本發明之固態微發光元件陣列的一第 一杈佳貫施例,包含:一基板2及複數相間隔設置於該基 板2的發光晶粒3(圖2僅以一發光晶粒說明之)。 每一發光晶粒3具有複數相間隔地設置於該基板2上 亚分別具有一圍繞面31〇的發光凸塊31。每一發光晶粒3 藉名等發光凸塊31及該基板2界定出複數相互交錯的通道 2母發光晶粒3更具有一覆蓋該基板2及該等圍繞面 310的絕緣體33,及一形成於該絕緣體33及該等發光凸塊 9 1254353 及該絕緣體 31上的電流散佈層34,致使該等發光凸塊31 33被夾置於该電流散佈層34及該基板2之間。 較佳地,每—發光凸塊31是一凸柱及一環柱其中一者 。在-具體實施例中’每一發光凸塊31是一凸柱。 較佳地,該基板2具有-板本體21及-形成於該板本 體21上並被夾置於該板本體21及該等發光晶粒3之間的 電性導通貼合膜22。The substrate refers to the contact area between the steroids to reduce the influence of the accumulation of thermal energy generated by the stray crystal itself on the substrate, and thereby improve the solid-state luminescence. DETAILED DESCRIPTION OF THE INVENTION The foregoing and other objects, features, and advantages of the invention will be apparent from the Detailed Description Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals. Referring to FIG. 2 and FIG. 3, a first preferred embodiment of the solid-state micro-light-emitting device array of the present invention comprises: a substrate 2 and a plurality of light-emitting dies 3 disposed at intervals of the substrate 2 (FIG. 2 only A luminescent crystal is illustrated). Each of the illuminating crystal grains 3 has a plurality of illuminating bumps 31 which are disposed on the substrate 2 at intervals and have a surrounding surface 31 分别. Each of the light-emitting dies 3 and the light-emitting bumps 31 and the substrate 2 define a plurality of mutually interlaced channels 2, and the mother light-emitting die 3 further has an insulator 33 covering the substrate 2 and the surrounding faces 310, and a formation The insulator 33 and the light-emitting bumps 9 1254353 and the current spreading layer 34 on the insulator 31 cause the light-emitting bumps 31 33 to be sandwiched between the current spreading layer 34 and the substrate 2. Preferably, each of the light-emitting bumps 31 is one of a stud and a ring. In the specific embodiment, each of the light-emitting bumps 31 is a stud. Preferably, the substrate 2 has a plate body 21 and an electrically conductive bonding film 22 formed on the plate body 21 and sandwiched between the plate body 21 and the illuminating crystal grains 3.

適用於本發明之該電性導通貼合膜22具有至少一選自 於下列所構成之群組的金屬層:金(Au)、鋁(A1)、鈦㈤ 錫(Sn)鉑(Pt)、銦(In)、銀(Ag)、鈹(Be)及含金之合 金。在-具體實施例中,該電性導通貼合膜22具有一銘層 、一鈦層及一金層(亦即,該電性導通貼合膜22結構為Ai 層/Ti層/Au層)。 適用於本务明之该板本體21是由一選自於下列所構成 之群組的材料所製成··銅(Cu)、含銅之合金、銅鎢 (copper-tungsten)合金、鎳(Ni)、含鎳之合金、鎢鉬 (tungsten-molybdenum)合金及經摻雜(d〇ped)的矽(Si)。 在该第一較佳實施例中,該板本體2丨是由銅所製成, 每一發光晶粒3更具有複數與該電流散佈層34接觸且是分 別由一鈦層、一鉑層及一金層所構成(亦即,Ti層汴七層 /Au層)的第一接觸電極35,該基板2更具有一夾置於該電 性導通貼合膜22及該等發光晶粒3之間的反射膜23。適用 於本發明之该反射膜23具有至少一選自於下列所構成之群 組的金屬層··鉑(pt)、銀(Ag)、鈦(Ti)、金(Au)、鋁(A1) 10 1254353 、銦(In)及鈀(Pd)。在一具體實施例中,該反射膜23具有 ' 一顧金屬層。 杈佳地,每一發光晶粒3的每一發光凸塊31具有一夾 置於該基板2與該電流散佈層34之間的第一型半導體層 3H、-夾置於該第-型半導體層311與該基板2之間的發 光層312,及-夾置於該發光層312及該基板2之間的第: 型半導體層313。在-具體實施例中,該第一型半導體層 311是一 n型半導體層,該第二型半導體層313是-p型半 — 導體層。 參閱圖6,本發明之固態微發光元件陣列的一第二較佳 貫施例,大致上是與該第一較佳實施例相同,其不同處僅 在於該板本體21是由經摻雜的矽所製成,且該基板2更具 有一接觸該板本體21的第二接觸電極24。 〈具體實施例一〉 參閱圖2與圖3,在本發明之固態微發光元件陣列的一 • 具體實施例-中,該板本體21是由銅所製成,該電性導通 貼合膜22的結構為A1層/Ti層/Au層,該反射膜23是由 一鉑層所構成。此外,在該具體實施例一中,每一發光凸 塊31是一凸柱,該等第一接觸電極35是分別由η層外七 層/Au層所構成,該第一型半導體層311是一由n—GaN所構 成的η型半導體層,該第二型半導體層313是一由 斤構成的ρ型半導體層,該發光層312是由一連接於該第 一型半導體層(n-Gal\i)311的n—A1GaN膜、一連接於該第二 型半導體層(p-GaN)313❸p-AlGalV膜,及一被夾置於該n — 11 1254353The electrically conductive bonding film 22 suitable for use in the present invention has at least one metal layer selected from the group consisting of gold (Au), aluminum (A1), titanium (f) tin (Sn) platinum (Pt), Indium (In), silver (Ag), beryllium (Be) and alloys containing gold. In a specific embodiment, the electrical conductive bonding film 22 has an inscription layer, a titanium layer, and a gold layer (that is, the electrically conductive bonding film 22 has an Ai layer/Ti layer/Au layer). . The board body 21 suitable for use in the present invention is made of a material selected from the group consisting of copper (Cu), copper-containing alloy, copper-tungsten alloy, nickel (Ni). ), a nickel-containing alloy, a tungsten-molybdenum alloy, and doped (Si). In the first preferred embodiment, the board body 2 is made of copper, and each of the light-emitting crystals 3 has a plurality of contacts with the current spreading layer 34 and is respectively composed of a titanium layer and a platinum layer. a first contact electrode 35 composed of a gold layer (that is, a Ti layer, a seventh layer/Au layer), and the substrate 2 is further sandwiched between the electrically conductive bonding film 22 and the luminescent crystal grains 3 The reflective film 23 between. The reflective film 23 suitable for use in the present invention has at least one metal layer selected from the group consisting of platinum (pt), silver (Ag), titanium (Ti), gold (Au), and aluminum (A1). 10 1254353, indium (In) and palladium (Pd). In a specific embodiment, the reflective film 23 has a 'metal layer'. Preferably, each of the light-emitting bumps 31 of each of the light-emitting dies 3 has a first-type semiconductor layer 3H sandwiched between the substrate 2 and the current spreading layer 34, and is sandwiched between the first-type semiconductors. A light-emitting layer 312 between the layer 311 and the substrate 2, and a first-type semiconductor layer 313 sandwiched between the light-emitting layer 312 and the substrate 2. In a specific embodiment, the first type semiconductor layer 311 is an n-type semiconductor layer, and the second type semiconductor layer 313 is a -p type semi-conductor layer. Referring to FIG. 6, a second preferred embodiment of the solid-state micro-light-emitting device array of the present invention is substantially the same as the first preferred embodiment except that the plate body 21 is doped. The substrate 2 is further provided with a second contact electrode 24 contacting the plate body 21. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 2 and FIG. 3, in a specific embodiment of the solid-state micro-light-emitting element array of the present invention, the board body 21 is made of copper, and the electrically conductive bonding film 22 is formed. The structure is an A1 layer/Ti layer/Au layer, and the reflective film 23 is composed of a platinum layer. In addition, in the first embodiment, each of the light-emitting bumps 31 is a protrusion, and the first contact electrodes 35 are respectively formed by an outer layer of seven layers/Au layers, and the first type semiconductor layer 311 is An n-type semiconductor layer composed of n-GaN, the second type semiconductor layer 313 is a p-type semiconductor layer composed of jin, and the light-emitting layer 312 is connected to the first-type semiconductor layer (n-Gal) \i) 311 n-A1GaN film, one connected to the second type semiconductor layer (p-GaN) 313❸p-AlGalV film, and one is sandwiched between the n-11 1254353

AlGaN膜與ρ-MGaN膜之間的多層量子井(multi_Quantum wa 11,間稱MQW)所構成(圖未示)’其中,該多層量子井的 結構為(InGaN/GaN)n。 本發明固態微發光元件陣列之具體實施例一的製作方 法,簡單地說明於下。 參閱圖4 ’該具體實施例一之元件製作流程圖。首先, 提供一暫時用之藍寶石基板4,並於該藍寶石基板4上依序 形成一 GaN緩衝層310,、一 n-GaN層311,、一發光層312, 及一 P-GaN層313,,藉以構成一磊晶體31,。進一步地,對 該磊晶體31’施予乾式蝕刻,致使該磊晶體31,形成複數由 該GaN緩衝層310 ’凸伸而出的凸柱31,,。 利用高密度電漿化學氣相沉積法(high density plasma chemical vapor deposition,簡稱 HDPCVD)於該磊 晶體31’上形成一氧化矽層33,並覆蓋該等凸柱31,,,後續, 並對該氧化矽層33,施予化學機械研磨(chemical mechanical polishing,簡稱 CMP)直至裸露出該 p—GaN 層 313’為止,並藉此定義出該絕緣體33。 於該絕緣體33及該等凸柱31,,上形成一鉑層,藉以定 義出該反射膜23,後續,利用一貼合膜並透過晶圓貼合技 術將一銅基板貼合於該反射膜23上,藉以定義出該電性導 通貼合膜22及该板本體21並完成一初步層狀結構5。 芩閱圖5,反置前述所完成之初步層狀結構5,並利用 雷射(laser)照射該藍寶石基板4藉以分解該—緩衝層 310’,致使該藍寶石基板4與該GaN緩衝層31〇,相互分離。 12 1254353 CMP直至裸露出每一 定義出該等發光凸塊 進步地,對該GaN緩衝層310,施予 凸柱31,,的n—GaN層311,為止,進而 3卜 、口次哥努、无凸塊υ丄从成、吧卜# 士、 ^ (ΙΤΟ)透明導♦屏 &gt; 成一氧化銦錫 電極3S,並於該透明導電層34,形成複數接觸 ^ —圖5僅以一接觸電極35,說明之)。最後,利用雷 、切割法藉以定義出該等發光晶粒3,並定義出每 曰A multilayer quantum well (multi_Quantum wa 11, inter-called MQW) between the AlGaN film and the ρ-MGaN film is formed (not shown), wherein the structure of the multilayer quantum well is (InGaN/GaN)n. A method of fabricating the first embodiment of the solid-state micro-light-emitting device array of the present invention will be briefly described below. Referring to Figure 4, a component fabrication flow chart of the first embodiment is shown. First, a temporary sapphire substrate 4 is provided, and a GaN buffer layer 310, an n-GaN layer 311, an luminescent layer 312, and a P-GaN layer 313 are sequentially formed on the sapphire substrate 4, Thereby forming a crystal 33. Further, the epitaxial crystal 31' is subjected to dry etching so that the epitaxial crystal 31 forms a plurality of studs 31 projecting from the GaN buffer layer 310'. Forming a ruthenium oxide layer 33 on the epitaxial crystal 31' by high density plasma chemical vapor deposition (HDPCVD), covering the protrusions 31, and subsequently, and The ruthenium oxide layer 33 is subjected to chemical mechanical polishing (CMP) until the p-GaN layer 313' is exposed, and the insulator 33 is defined thereby. Forming a platinum layer on the insulator 33 and the studs 31 to define the reflective film 23, and subsequently bonding a copper substrate to the reflective film by using a bonding film and through a wafer bonding technique. At 23, the electrically conductive bonding film 22 and the plate body 21 are defined and a preliminary layered structure 5 is completed. Referring to FIG. 5, the preliminary layer structure 5 completed as described above is reversed, and the sapphire substrate 4 is irradiated with a laser to decompose the buffer layer 310', so that the sapphire substrate 4 and the GaN buffer layer 31 are folded. , separated from each other. 12 1254353 CMP until each of the defined illuminating bumps is exposed, and the n-GaN layer 311 of the GaN buffer layer 310 is applied to the GaN buffer layer 310, and further, 3, and No bumps υ丄 成 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 35, explain it). Finally, the ray and the cutting method are used to define the luminescent crystal grains 3, and each 定义 is defined.

粒3的電流散佈層34及第一接觸電極如(即,如圖二斤: Ο / 〈具體實施例二〉 _參閱圖6,本發明之固態微發光元件陣列的一具體實施 彳大致上疋與该具體實施例一相同,其不同處僅在於該 板本體21是由經換雜且呈低阻值㈣所製成。在該具體實 施例二中’前述⑪所摻雜的摻質(dopant)為濃度介於 1〇16〜1〇18 cm2的删(B)。此外,該基板2的第二接觸電極24 是由銀(Ag)所製成。 參閱圖7,由本發明固態微發光元件陣列的光致螢光光 瑨(electr〇l_inescence spectrum;簡稱虹光譜)強度之 信賴性分析顯示’於室溫環境且注入電流值為2。4 :測 試條件下,隨著測試時間持續1〇〇〇小時後,乩光詳 低未超過20 %。 又牛 參閱圖8,由本發明固態微發光元件陣列的順向電壓 (forward voltage)值之信賴性分析顯示,於室溫環境且注 入電流值為20 mA的測試條件下,隨著濁試時間持續 13The current spreading layer 34 of the particle 3 and the first contact electrode are as follows (ie, as shown in FIG. 2: Ο / <Specific Embodiment 2> Referring to FIG. 6, a specific implementation of the solid-state micro-light-emitting element array of the present invention is substantially The same as the first embodiment, the difference is only that the board body 21 is made of a modified and low resistance (four). In the second embodiment, the above 11 doped dopants (dopant) It is a deletion (B) having a concentration of 1〇16~1〇18 cm2. Further, the second contact electrode 24 of the substrate 2 is made of silver (Ag). Referring to Fig. 7, the solid-state micro-light-emitting element of the present invention The reliability analysis of the intensity of the optical fluorescence spectroscopy (electr〇l_inescence spectrum; referred to as the rainbow spectrum) of the array shows 'at room temperature environment and the injection current value is 2-4. Under the test conditions, the test time lasts 1〇〇. After 〇 hours, the 乩 light detail is less than 20%. In addition, referring to Fig. 8, the reliability analysis of the forward voltage value of the solid-state micro illuminating element array of the present invention shows that the room temperature environment and the injection current value are Under the test condition of 20 mA, the turbidity test time lasts 13

說明本發明固態微發光元 1254353 小時後,順向電壓值皆穩定地維持在3·2 v〜3 3 V之間。 在本發明之固態微發光元件陣列中,由於每一^光晶 粒3是具有該等發光凸塊31並藉由該等通道&amp;相間隔開 ’致使每-發m 3與該基板2之間的接觸面積減少, 以降低元件於運作過程中因熱膨脹係數差所累積的熱應力 ,並增加元件的側向外部量子效率。因此,累積於每;;發 光凸塊3K即,前述的蟲晶體31,)處的熱應力降低,將可^ 少该等發光晶粒31裂損或基材分離等問題,進而提昇本發 明固態微發光it件陣列的信賴性並增加單—晶粒的有效 用率及外部量子效率。 綜上所述,本發明固態微發光元件陣列具有外部量子 效率高、元件熱應力問題少、符合信賴性要求及單一晶粒 的有效使料高等特點,確實達到本發明之目的。 &amp; f隹以上所述者,僅為本發明之較佳實施例而已,當不 从乂此限疋本發明實施之範圍,即大凡依本發明申請專利 關及發明說明内容所作之簡單的等效變化與修飾,皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 ^圖1疋一正視示意圖,說明一並列設置之氮化銦鎵微 兔光二極體陣列; 圖2是一局部立體示意圖 件陣列的一第一較佳實施例; 圖3是該第—較佳實施例之一正視示意圖; 圖4疋一 70件製作流程圖,說明該第一較佳實施例之 14 1254353 前半段製作流程; 說明該第—較佳 圖5是延續該圖4之一元件製作圖 實施例之後半段製作流程; 圖6是一正視示意圖,說明本發明固態微發光元 列的一第二較佳實施例; 圖7是-EL光譜強度變化量對老化時間曲線圖,說明After the solid-state micro-luminous element of the present invention is 1,254,353 hours, the forward voltage values are stably maintained between 3·2 v and 3 3 V. In the solid-state micro-light-emitting device array of the present invention, since each of the optical crystal grains 3 has the light-emitting bumps 31 and is spaced apart by the channels &amp; The contact area between the contacts is reduced to reduce the thermal stress accumulated by the difference in thermal expansion coefficient of the component during operation, and to increase the lateral external quantum efficiency of the component. Therefore, the thermal stress at the light-emitting bumps 3K, that is, the aforementioned insect crystals 31, is reduced, and the problem that the light-emitting crystal grains 31 are cracked or the substrate is separated can be reduced, thereby improving the solid state of the present invention. The reliability of the micro-illuminated device array increases the effective utilization of the single-grain and the external quantum efficiency. In summary, the solid-state micro-light-emitting device array of the present invention has the characteristics of high external quantum efficiency, less thermal stress of components, compliance with reliability requirements, and high effective material of a single crystal grain, and indeed achieves the object of the present invention. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the simple application of the patent application and the description of the invention according to the present invention. Both effect changes and modifications are still within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a front view schematically showing an indium gallium nitride micro-rabbit photodiode array arranged in parallel; FIG. 2 is a first preferred embodiment of a partial stereoscopic image array; FIG. FIG. 4 is a flow chart showing the fabrication process of the first half of the first preferred embodiment. FIG. Figure 4 is a front view showing the second half of the embodiment of the solid-state micro-illuminator column of the present invention; Figure 7 is a second embodiment of the solid-state micro-illuminator column of the present invention; Time curve

本發明固悲微發光元件陣列的F Μ卞I平別的EL先譜強度之信賴性分析; 及Reliability analysis of the EL pre-spectral intensity of the F Μ卞I level of the solid-light micro-light element array of the present invention; and

,說明本發明固 圖8是一順向電壓對老化時間曲線圖 態微發光元件陣列的麻a + 〜曰〕順向電壓之信賴性分析FIG. 8 is a reliability analysis of the forward voltage of a micro-light-emitting element array with a forward voltage versus an aging time curve.

15 1254353 【主要元件符號說明】 2 *…基板 21………板本體 22………電性導通貼合膜 2 3………反射膜 24 *…弟二接觸電極 3 * *.........發光晶粒 31………發光凸塊 31’ 蠢晶體 31 ”……·凸柱 310 .•…··圍繞面 310’……GaN緩衝層 311…·…第一型半導體層 311,……η-GaN層 312 &quot;••…發光層 312’……發光層 313……*第二型半導體層 313,……p-GaN層 32………通道 33 ··•…·♦•絕緣體 33’…··…氧化矽層 34 ........♦電流散佈層 34’........透明導電層 35’··……接觸電極 35………第一接觸電極 4........…監實石基板 5-……·…初步層狀結構15 1254353 [Description of main component symbols] 2 *...substrate 21......board body 22.........electrically conductive bonding film 2 3.........reflecting film 24*...different contact electrode 3 * *..... ... illuminating crystal 31... illuminating bump 31' stupid crystal 31" ... ... stud 310. ..... ... surrounding surface 310' ... GaN buffer layer 311 ... ... ... first type semiconductor layer 311 , η-GaN layer 312 &quot;••... luminescent layer 312'... luminescent layer 313...* second type semiconductor layer 313, ... p-GaN layer 32... channel 33 ··•...·♦ • Insulator 33'...··...Oxide layer 34........♦ Current spreading layer 34'........Transparent conductive layer 35'... contact electrode 35......... A contact electrode 4 ........... supervised stone substrate 5 - ... · ... preliminary layered structure

1616

Claims (1)

1254353 十、申請專利範圍: 1. 一種固態微發光元件陣列,包含: 一基板;及 複數相間隔設置於該基板的發光晶粒,每一發光 晶粒具有複數相間隔地設置於該基板上並分別具有一圍 繞面的發光凸塊,每一發光晶粒藉該等發光凸塊及該基 板界定出複數相互交錯的通道,每一發光晶粒更具有一 覆盍该基板及該等圍繞面的絕緣體及一形成於該絕緣體 ί 及該等發光凸塊上的電流散佈層,致使該等發光凸塊及 該絕緣體被夹置於該電流散佈層及該基板之間。 2·依據申請專利範圍第丨項所述之固態微發光元件陣列, 其中,母一發光凸塊是一凸柱及一環柱其中一者。 3.依據申請專利範圍第2項所述之固態微發光元件陣列, 其中,每一發光凸塊是一凸柱。 4·依據申請專利範圍第丨項所述之固態微發光元件陣列, &gt; 其中,該基板具有一板本體及一形成於該板本體上並被 夾置於該板本體及該等發光晶粒之間的電性導通貼合膜 〇 5·依據申請專利範圍第4項所述之固態微發光元件陣列, /、中,省私性導通貼合膜具有至少一選自於下列所構成 之群組的金屬層:金、銘、鈦、錫、翻、銦、銀、皱及 含金之合金。 6.依據申請專利範圍第4項所述之固態微發光元件陣列, 其中,該板本體是由一選自於下列所構成之群組的材料 17 1254353 所製成:銅、含鋼之合金、銅鎢合金、鎳、含鎳之合金 、鎢鉬合金及經摻雜的石夕。 7·依據申請專利範圍第6項所述之固態微發光元件陣列, 其中,該板本體是由銅所製成。1254353 X. Patent Application Range: 1. An array of solid-state micro-light-emitting elements, comprising: a substrate; and a plurality of light-emitting crystal grains spaced apart from each other on the substrate, each of the light-emitting crystal grains having a plurality of spaced-apart intervals and disposed on the substrate Each of the illuminating dies has a plurality of light-emitting bumps surrounding the surface, and each of the illuminating dies defines a plurality of interdigitated channels through the illuminating bumps, and each of the illuminating dies further has a covering surface of the substrate and the surrounding surfaces. An insulator and a current spreading layer formed on the insulator and the light-emitting bumps cause the light-emitting bumps and the insulator to be sandwiched between the current spreading layer and the substrate. 2. The solid-state micro-light-emitting device array according to the invention of claim 2, wherein the mother-emitting bump is one of a pillar and a ring. 3. The solid-state micro-light-emitting element array according to claim 2, wherein each of the light-emitting bumps is a stud. 4. The solid-state micro-light-emitting device array according to the above application, wherein the substrate has a plate body and is formed on the plate body and sandwiched between the plate body and the light-emitting dies In the case of the solid-state micro-light-emitting element array according to the fourth aspect of the patent application, the medium-conducting conductive bonding film has at least one selected from the group consisting of Group of metal layers: gold, Ming, titanium, tin, turn, indium, silver, wrinkle and alloys containing gold. 6. The solid-state micro-light-emitting element array according to claim 4, wherein the plate body is made of a material 17 1254353 selected from the group consisting of copper, a steel containing alloy, Copper-tungsten alloy, nickel, nickel-containing alloy, tungsten-molybdenum alloy and doped shixi. The solid-state micro-light-emitting element array according to claim 6, wherein the plate body is made of copper. 8·依據申請專利範圍第7項所述之固態微發光元件陣列, 其中,每一發光晶粒更具有至少一與該電流散佈層接觸 的第一接觸電極,該基板更具有一夾置於該電性導通貼 合膜及該等發光晶粒之間的反射膜。 9.依據申請專利範圍第8項所述之固態微發光元件陣列, 其中’該反射膜具有至少—選自於下列所構成之群組的 金屬層:鉑、銀、!太、金、鋁、銦及鈀。 1 〇·依據中w專利範圍第6項所述之固態微發光元件陣列, 其中,忒板本體是由經摻雜的矽所製成。 11·依=巾請專利範圍第lQ㉟所述之固態微發光元件陣列 /、中每發光晶粒更具有至少一與該電流散佈層接 觸的第一接觸電極,該基板更具有一夾置於該電性導通 、口膜及σ亥等發光晶粒之間的反射膜,及一接觸該板本 體的第二接觸電極。 據申明專利範圍第11項所述之固態微發光元并陣 ,具有至少—選自於下列所構成之群組 金屬層:鉑、銀、鈦、金、鋁、銦及鈀。 13·^據巾料利範圍第1項所述之固態微發光元件陣列 /、中母發光晶粒的每一發光凸塊具有一夾置於該 板與該電流散佈層之間的第一型半導體層、一央置於; 18 1254353 第一型半導體層與該基板之間的發光層,及一夾置於該 發光層及該基板之間的第二型半導體層。 14.依據申請專利範圍第13項所述之固態微發光元件陣列 ,其中,該第一型半導體層是一 η型半導體層,該第二 型半導體層是一 Ρ型半導體層。The solid-state micro-light-emitting device array of claim 7, wherein each of the light-emitting crystal grains further has at least one first contact electrode in contact with the current spreading layer, the substrate further having a clip Conductively bonding the film and a reflective film between the luminescent crystal grains. 9. The solid-state micro-light-emitting element array according to claim 8, wherein the reflective film has at least a metal layer selected from the group consisting of platinum, silver, !, gold, aluminum, Indium and palladium. The solid-state micro-light-emitting element array according to item 6, wherein the raft body is made of doped yttrium. 11. The solid-state micro-light-emitting element array/in the illuminating crystal grain of the invention, wherein each of the illuminating dies further has at least one first contact electrode in contact with the current spreading layer, the substrate further having a clip a conductive film between the conductive film, the oral film, and the illuminating crystal grains, and a second contact electrode contacting the body of the plate. The solid-state micro-emitters according to claim 11 have at least one selected from the group consisting of platinum, silver, titanium, gold, aluminum, indium and palladium. 13·^ According to the scope of the invention, each of the solid-state micro-light-emitting element arrays/, the mother-emitting light-emitting die, has a first type sandwiched between the plate and the current spreading layer. a semiconductor layer, a central portion; 18 1254353 a light-emitting layer between the first-type semiconductor layer and the substrate, and a second-type semiconductor layer sandwiched between the light-emitting layer and the substrate. The solid-state micro-light-emitting device array according to claim 13, wherein the first-type semiconductor layer is an n-type semiconductor layer, and the second-type semiconductor layer is a germanium-type semiconductor layer. 1919
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112310136A (en) * 2019-07-23 2021-02-02 薛富盛 Passive micro light-emitting diode array device with uniform brightness

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112310136A (en) * 2019-07-23 2021-02-02 薛富盛 Passive micro light-emitting diode array device with uniform brightness
CN112310136B (en) * 2019-07-23 2024-03-19 薛富盛 Passive micro-LED array device with uniform brightness

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