TWI253739B - IC packaging process with non-tape die attachment - Google Patents

IC packaging process with non-tape die attachment Download PDF

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Publication number
TWI253739B
TWI253739B TW094111884A TW94111884A TWI253739B TW I253739 B TWI253739 B TW I253739B TW 094111884 A TW094111884 A TW 094111884A TW 94111884 A TW94111884 A TW 94111884A TW I253739 B TWI253739 B TW I253739B
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Taiwan
Prior art keywords
substrate
die
bonding
packaging process
liquid
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TW094111884A
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Chinese (zh)
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TW200636965A (en
Inventor
Yung-Hsiang Chen
Shih-Yang Yang
Chan-Chang Kuo
Pi-Hung Kao
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Walton Advanced Eng Inc
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Priority to TW094111884A priority Critical patent/TWI253739B/en
Priority to JP2006108781A priority patent/JP2006295186A/en
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Publication of TWI253739B publication Critical patent/TWI253739B/en
Publication of TW200636965A publication Critical patent/TW200636965A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

An IC packaging process with Non-Tape die attachment is disclosed. Initially, a liquid die-bonding material is coated on a substrate. In a debubbling step, the substrate is placed in a vacuum condition to remove tiny bubbles inside the liquid die-bonding material. Next, a first curing is performed to partially cure the liquid die-bonding material to be transformed into a compact die-bonding film on the substrate. A chip can be attached to the substrate through the compact die-bonding film. Next, a second curing is performed to fully cure the compact die-bonding film. Since no bubble exists between the substrate and the chip, die-bonding strength can be increase to solve chip delamination.

Description

1253739 九、發明說明： 【發明所屬之技術領域】 一本發明係有關於-種積體電路封裝過程，特別係有關 於一種無膠帶黏晶方式之積體電路封裝過程。 【先前技術】 在積體電路封裝過程中，黏晶（‘-attaching)之步驟係 為重要之-環，好的黏晶操作條件可以確實將晶片黏接至 基板，能降低封裝成本與提昇封褒品質。並且為符合先進 積體電路封裝，對於黏晶材料有嚴格之要求，例如黏晶強 度、導熱性與可作業性均應有一定之要求。 在美國專利第6,385,049號專利案中揭示一種積體電 路封裝構造。請參閱第1與2圖，—種習知積體電路封裝 構造主要包含有至少一基板11〇、—黏晶材料m、 曰曰 130、複數個銲線14G、—封膠體15()以及複數個辉球 160。在黏晶時’該黏晶材_ m係黏接該基板⑽之一 上表面ill與該晶片130之一主動面131。在封膠之前， 該基板no之一開口槽113係顯露該晶片13〇之銲墊132, 以使該些銲線mo電性連接該些銲墊132至該基板ιι〇。 該封膠體150係填充於該開口槽113以密封該些銲線 140。該些銲球I60係接合至該基板110之一下表面112， 以對外連接。在上述積體電路封裝構造中，該黏晶材料12〇 係不可使用液態黏膠，否則會有污染至該些銲墊之 虞。一種已知黏晶材料120係為兩面黏性膠帶，例如聚亞 醯胺膠π，其成本較南且需要正確機械操作的膠帶貼附， 5 1253739 以避免遮擋該開口槽113。另一種已知黏晶材料12〇係可 使用B階(B_stage)黏性膠膜，如美國專利第6 689 638號 專利案所揭示般，-液態黏晶材料係先塗敷於一基板上， 再供烤成B階黏性膠膜，以利黏接該晶片；但該種b階黏 晶材料120會殘留有微細氣泡121，使基板與晶片之黏著 面間存有微細氣泡121而產生空洞之間隙，影響黏晶強 度’甚至會導致該晶片13〇之分層剝離。 【發明内容】 ► 本發明之主要目的在於提供一種無膠帶黏晶方式之 積體電路封裝過程，在塗敷一液態黏晶材料於一基板之 後，藉由一脫泡之步驟，去除該液態黏晶材料内之微細氣 泡，以利在第一烘烤之步驟中將該液態黏晶材料半固化成 一密實黏晶膜，藉由該密實黏晶膜可黏接一晶片至該基 板達到6強黏晶強度及避免晶片分層剝離之功效。 本發明之次一目的在於提供一種無膠帶黏晶方式之 •積體電路封裝過程，在第一烘烤之前執行一脫泡之步驟， 將一基板係置於一真空狀態（例如不大於2 T〇rr之壓力）並 輔以震盪方式，使去除在該基板上一液態黏晶材料内之微 細氣泡，以利烘烤成一密實黏晶膜。 依據本發明之無膠帶黏晶方式之積體電路封裝過 程，首先，提供至少一基板，其係具有一上表面、一下表 面及至少一開口槽。之後，塗敷一液態黏晶材料於該基板 之該上表面。之後，進行一脫泡之步驟，以去除該液態黏 晶材料内之微細氣泡。之後，進行第一次烘烤之步驟，使 6 1253739 該液態黏晶材料為半固化狀態而成為—密實黏晶膜。 藉由該密實黏晶膜黏接-晶片之-主動面至該基板之該 上表面上，該晶片係具有複數個位於該主動面之銲墊，‘ 些銲墊係顯露於該開口槽。另’可進行第二次烘烤之： 驟，以固化該密實黏晶膜。該第二次供烤之步驟係可執^ 在黏晶之後或是在後續封膠之步驟中。 【實施方式】1253739 IX. Description of the invention: [Technical field to which the invention pertains] One invention relates to an integrated circuit packaging process, and in particular to an integrated circuit packaging process for a tapeless die bonding method. [Prior Art] In the integrated circuit packaging process, the step of '-attaching' is an important ring, and the good bonding operation conditions can surely bond the wafer to the substrate, which can reduce the packaging cost and enhance the sealing.褒 quality. In order to meet the advanced integrated circuit package, there are strict requirements for the die-bonding material, such as the bond strength, thermal conductivity and workability. An integrated circuit package construction is disclosed in U.S. Patent No. 6,385,049. Referring to FIGS. 1 and 2, the conventional integrated circuit package structure mainly includes at least one substrate 11A, a die-bonding material m, a crucible 130, a plurality of bonding wires 14G, a sealing body 15 (), and a plurality Glow balls 160. In the case of die bonding, the adhesive layer _ m adheres to one of the upper surface ill of the substrate (10) and one of the active faces 131 of the wafer 130. Before the encapsulation, one of the openings 103 of the substrate no reveals the pads 132 of the wafer 13 so that the bonding wires mo electrically connect the pads 132 to the substrate. The encapsulant 150 is filled in the open groove 113 to seal the bonding wires 140. The solder balls I60 are bonded to one of the lower surfaces 112 of the substrate 110 for external connection. In the above-mentioned integrated circuit package structure, the adhesive material 12 cannot be used as a liquid adhesive, otherwise it may contaminate the solder pads. One known viscous material 120 is a two-sided adhesive tape, such as polyamidamide π, which is costly to the south and requires a properly mechanically operated tape to be attached, 5 1253739 to avoid obscuring the open slot 113. Another known viscous material 12 can be a B-stage adhesive film. As disclosed in U.S. Patent No. 6,689,638, the liquid-clay material is first applied to a substrate. Then, it is baked into a B-stage adhesive film to adhere the wafer; however, the b-stage doped crystal material 120 may have fine bubbles 121 remaining, so that fine bubbles 121 are present between the substrate and the bonding surface of the wafer to create voids. The gap, which affects the bond strength, can even lead to delamination of the wafer 13 〇. SUMMARY OF THE INVENTION The main object of the present invention is to provide an integrated circuit packaging process without a tape-bonding method. After applying a liquid adhesive material to a substrate, the liquid viscosity is removed by a defoaming step. a fine bubble in the crystal material, in order to semi-cure the liquid die-bonding material into a dense adhesive film in the first baking step, wherein the dense bonded film can adhere a wafer to the substrate to achieve 6 strong adhesion Crystal strength and the effect of avoiding delamination of the wafer. A second object of the present invention is to provide an integrated circuit packaging process without a tape-bonding method, in which a defoaming step is performed before the first baking, and a substrate is placed in a vacuum state (for example, no more than 2 T The pressure of 〇rr is supplemented by an oscillating manner to remove fine bubbles in a liquid viscous material on the substrate to facilitate baking into a dense viscous film. According to the integrated circuit package process of the tapeless die-bonding method of the present invention, first, at least one substrate is provided which has an upper surface, a lower surface and at least one open groove. Thereafter, a liquid die-bonding material is applied to the upper surface of the substrate. Thereafter, a defoaming step is performed to remove fine bubbles in the liquid viscous material. Thereafter, the first baking step is performed to make the liquid crystalline material of the semi-cured state 6 into a semi-cured state. The dense magnetic film is bonded to the active surface of the wafer to the upper surface of the substrate, and the wafer has a plurality of pads on the active surface, and some of the pads are exposed in the open trench. Alternatively, a second baking step can be performed to cure the densely bonded film. The second step of bake can be performed after the die-bonding or in the subsequent step of sealing. [Embodiment]

依據本發明之一具體實施例，如第3圖所示，一種無 膠帶黏晶方式之積體電路封裝過程係可包含：「提供一美 板」之步驟1、「塗敷一液態黏晶材料於該基板」之步驟/、 「脫泡」之步驟3、「第一次烘烤」之步驟4、「黏晶」之 步驟5、「第二次烘烤」之步驟6、「電性連接」之步驟7、 封膠」之步驟8、「銲球接合」之步驟9、以及「基板切 割」之步驟10。詳述如後。 首先，在提供一基板之步驟1中，如第4a圖所示， 提供至少一基板210，該基板21〇係具有一上表面2ιι、 一下表面212及至少一開口槽213，其中該開口槽213係 貫穿該上表面211與該下表面212。而該基板21〇係可為 一印刷電路板、一陶瓷電路板或一電路薄膜。在本實施例 中’複數個内接指214係形成於該基板210之該下表面212 且鄰近該開口槽213，且複數個球墊215係可形成於該基 板210之該下表面212。 之後’在塗敷一液態黏晶材料於該基板之步驟2中， 如第4B圖所示，將一液態黏晶材料220塗敷於該基板21〇 7 1253739 之該上表面211，JL爹數古斗π认 八 双乃式可為網板印刷、鋼板印刷、 點塗、喷塗等等，i中 T 乂、、罔板印刷為較佳。如第5圖所示， 該液態黏晶材料22〇係圖宰 丁 α系化覆盍於該基板21〇之該上表 面211 ’在適當烘烤後日 △ J勒接日日片。在本實施例中，該液 態黏晶材料220係可以亚七、士々 你1以要求有多階固化特性，甚至可以包 含有各種特性之混人朦辦 , σ膠體例如有混有矽膠以增進彈性、 混有金屬微粒子（如你伞、、、,描 卞（如銀杨）以增進導熱性、混有不同固化溫 度之…、固化膠、甚至可混有各種奈米材料以達特殊用途之 膠體。為達到良好之混合效果’在常壓下封裝時，該液態 黏晶材料220會存在有微細氣泡221。According to an embodiment of the present invention, as shown in FIG. 3, the integrated circuit packaging process of the tapeless die bonding method may include: "providing a beauty plate" step 1, "coating a liquid die bonding material" Step 3 of the substrate, Step 3 of "Defoaming", Step 4 of "First Baking", Step 5 of "Crystalline", Step 6 of "Second Baking", "Electrical Connection Step 7 of Step 7, Sealing, Step 9 of "Ball Bonding", and Step 10 of "Substrate Cutting". Details are as follows. First, in the step 1 of providing a substrate, as shown in FIG. 4a, at least one substrate 210 is provided. The substrate 21 has an upper surface 2 ιι, a lower surface 212 and at least one opening groove 213, wherein the opening groove 213 The upper surface 211 and the lower surface 212 are penetrated. The substrate 21 can be a printed circuit board, a ceramic circuit board or a circuit film. In the present embodiment, a plurality of internal fingers 214 are formed on the lower surface 212 of the substrate 210 adjacent to the opening groove 213, and a plurality of ball pads 215 are formed on the lower surface 212 of the substrate 210. Then, in step 2 of applying a liquid die-bonding material to the substrate, as shown in FIG. 4B, a liquid die-bonding material 220 is applied to the upper surface 211 of the substrate 21〇7 1253739, and the number of JL turns The ancient π acknowledgment can be stencil printing, steel plate printing, spot coating, spraying, etc., in which T 乂, 罔 plate printing is better. As shown in Fig. 5, the liquid viscous material 22 is α 宰 α α α α α 该 该 该 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In the present embodiment, the liquid die-bonding material 220 can be used for the seven-seven, the gentry, and the multi-layer curing property is required, and may even contain various characteristics, and the σ colloid may be mixed with silicone rubber to enhance Elastic, mixed with metal particles (such as your umbrella,,,, tracing (such as silver yang) to improve thermal conductivity, mixed with different curing temperatures..., curing adhesive, and even mixed with various nano materials for special purposes Colloid. In order to achieve a good mixing effect, when the package is under normal pressure, the liquid porous material 220 may have fine bubbles 221.

之後’特別執行一脫泡之步驟3。如第4C圖所示，藉 由脫泡以去除該液態黏晶材料22〇内之微細氣泡22ι。在 具體操作上，可將該基板21〇放置於一可隔離外界壓力 之脫泡機（圖未繪出）内，並抽真空使該基板21〇置於一真 空狀態，例如該真空狀態之壓力係不大於2 T〇rr，真空狀 態可維持10分鐘至60分鐘。較佳地，並輔以震盪方式， 例如超S波震盪，以有效去除該液態黏晶材料220内之微 細氣泡221，更可確保該液態黏晶材料22〇之混合均勻。 在上述脫泡之步驟3後，可進行第一次烘烤之步驟心 如第4D圖所示，該液態黏晶材料22〇為半固化狀態（例如 Β階狀態）而轉變為在該基板21〇上之一密實黏晶膜222。 在本實施例中，該密實黏晶膜222係具有Β階特性，而保 有黏晶此力。此外’原本可能在該液態黏晶材料220内之 絕大部分微細氣泡221將被排除。 1253739 在黏晶之步驟5中，請參閱第4E圖，至少一晶片230 係藉由该岔貫黏晶膜222而黏貼至該基板21〇，其係在適 當之黏晶壓力與加熱溫度下，該密實黏晶膜222變得有黏 著力，以結合該晶片230之一主動面231至該基板210之 該上表面211。在本實施例中，該晶片23〇之複數個銲墊 232係位於该主動面231，例如位於該主動面231之中央。 而在黏晶之步驟5後，該些銲墊232係顯露於該基板21〇 之該開口槽213。 之後，可執行第二次烘烤之步驟6，以完全固化該密 實黏晶膜222，例如固化成c階狀態。該第二次烘烤之步 驟6係可實施於黏晶之步驟5後或是延後至在封膠之步驟 8同時進行。#，在電性連接之步驟7中，請參閱第怀 圖，其係能以打線形成之複數個銲線24〇通過該開口槽 213，連接該晶片230之該些銲墊232與該基板21〇之該 些内接指214’達到該晶片230與該基板21〇間電性連接。 之後，在封膠之步驟8中，如第4G圖所示，一封膠 體250係形成於該基板210之該開口槽213，以密封該些 銲線24G。在本實施例中，該封膠體25()係為壓模形成， 其係更形成於該基板210之該上表面211，以密封該晶片 230與該密實黏晶膜222。 之後，在銲球接合之步驟9中，如第4H圖所示，利 用鲜料印刷與回鲜或是銲球植接之方式，將複數個銲球 260接合至在該基板210之該下表面212之球塾215，以 構成窗口球格陣列之封裝型態（wind〇w BaU G仙 9 1253739After that, a step 3 of defoaming is specifically performed. As shown in Fig. 4C, the microbubbles 22 i in the liquid viscous material 22 are removed by defoaming. In a specific operation, the substrate 21 can be placed in a defoaming machine (not shown) capable of isolating external pressure, and vacuumed to place the substrate 21 in a vacuum state, for example, the pressure of the vacuum state. It is not more than 2 T rrrr and the vacuum state can be maintained for 10 minutes to 60 minutes. Preferably, the oscillating mode, for example, the super-S wave oscillating, is used to effectively remove the fine bubbles 221 in the liquid viscous material 220, thereby ensuring uniform mixing of the liquid viscous material 22. After the step 3 of defoaming described above, the step of performing the first baking step is as shown in FIG. 4D, and the liquid die-bonding material 22 is transformed into the substrate 21 in a semi-cured state (for example, a step state). One of the densely bonded film 222 on the crucible. In the present embodiment, the densely bonded film 222 has a gradation characteristic and retains the force of the viscous crystal. Further, most of the fine bubbles 221 which may have been in the liquid crystalline material 220 will be excluded. 1253739 In step 5 of the die bonding, referring to FIG. 4E, at least one wafer 230 is adhered to the substrate 21 by the through-silicon film 222 at a suitable adhesive pressure and heating temperature. The dense die film 222 becomes adhesive to bond the active surface 231 of the wafer 230 to the upper surface 211 of the substrate 210. In the present embodiment, a plurality of pads 232 of the wafer 23 are located on the active surface 231, for example, in the center of the active surface 231. After the step 5 of the bonding, the pads 232 are exposed to the opening 213 of the substrate 21A. Thereafter, a second baking step 6 can be performed to completely cure the densely doped film 222, for example, to a c-stage state. The second baking step 6 can be carried out after the step 5 of the die bonding or after the delay to the step 8 of the sealing. In the step 7 of the electrical connection, please refer to the first drawing, which can connect the plurality of bonding wires 24 formed by wire bonding through the opening slot 213, and connect the pads 232 of the wafer 230 to the substrate 21. The inner fingers 214 ′ are electrically connected to the wafer 230 and the substrate 21 . Thereafter, in step 8 of sealing, as shown in Fig. 4G, a glue 250 is formed in the opening groove 213 of the substrate 210 to seal the bonding wires 24G. In the present embodiment, the encapsulant 25() is formed by stamping, and is formed on the upper surface 211 of the substrate 210 to seal the wafer 230 and the dense adhesive film 222. Thereafter, in step 9 of solder ball bonding, as shown in FIG. 4H, a plurality of solder balls 260 are bonded to the lower surface of the substrate 210 by means of fresh material printing and reflow or solder ball bonding. 212 ball 塾215 to form the encapsulation type of the window grid array (wind〇w BaU Gxian 9 1253739

Array，WBGA Package)。最後，進行該基板切割之步驟ι〇， 利用一切割工具270切割該基板21〇成複數個個別積體電 路封裝構造。請參Μ 5圖，在本實施例中，其切割路徑 216係通過該基板210之該開口槽213之兩端，可由該基 板210切割分離出在同一封裝構造中之兩個次基板其$ 该些次基板係與該晶片23〇黏接並以該封膠體25〇結合一 體。 。° 因此在本务明之無膠帶黏晶方式之積體電路封裝過 权中’利用在第一次烘烤之步驟4前進行脫泡之步驟3， 可以去除該液態黏晶材料22〇内之微細氣泡22ι，而能轉 變成在該基板21〇上之密實黏晶膜222，故可以增_日日日 強度及避免該晶片230之分層剝離。 故本發明之保護範圍當視後附之巾請專㈣圍所界 疋者為準’任何熟知此項技藝者，在不脫離本發明之精神 和範圍内所作之任付轡芥命炊从 7文化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 第1 @ :習知積體電路封裳構造之局部剖視立體 圖。 第2圖：習知積體電路封裝構造之載面示意圖。 第3圖：:本發明之-具體實施例，一種無膝帶黏 曰曰方式之積體電路封裝過程之方塊流程 圖。 第4Α至4H圖：依本發明一 〃體實施例，一基板在無膠 10 1253739 裝過程中之截面 帶黏晶方式積體電路封 示意圖。 ^ 5圖：依本發明之一具體實施例，該基板之上表 面示意圖。 【主要元件符號說明】Array, WBGA Package). Finally, the step of cutting the substrate is performed, and the substrate 21 is cut by a cutting tool 270 into a plurality of individual integrated circuit package structures. Referring to FIG. 5 , in the embodiment, the cutting path 216 passes through the two ends of the opening groove 213 of the substrate 210 , and the two substrates in the same package structure can be cut and separated by the substrate 210. The substrate is bonded to the wafer 23 and bonded together by the sealant 25 . . ° Therefore, in the integrated circuit packaging method of the present invention without the tape-bonding method, the step 3 of defoaming before the first baking step 4 can be used to remove the fineness of the liquid crystalline material 22 The bubbles 22i can be converted into a densely bonded film 222 on the substrate 21, so that the daily strength can be increased and the delamination of the wafer 230 can be avoided. Therefore, the scope of protection of the present invention is subject to the provisions of the four (4) enclosures. Anyone who is familiar with the art, will not be able to do anything from the spirit and scope of the present invention. Culture and modification are within the scope of protection of the present invention. [Simple description of the drawing] The first @ : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Figure 2: Schematic diagram of the carrier surface of the conventional integrated circuit package structure. Fig. 3 is a block diagram showing a process of encapsulating a package circuit of a knee-free adhesive tape in a specific embodiment of the present invention. Figures 4 to 4H are schematic views showing a cross-section of a substrate in a process of a non-adhesive 10 1253739 package according to an embodiment of the present invention. Figure 5 is a schematic representation of the surface above the substrate in accordance with an embodiment of the present invention. [Main component symbol description]

1 提供一基板 2 塗敷一液態黏晶材料於該基板 3 脫泡 4 第一次烘烤 5 黏晶 6 第二次烘烤 7 電性連接 8 封膠 9 鲜球接合 10 基板切割 110 基板 111 上表面 112 下表面 113 開口槽 120 黏晶材料 121 氣泡 130 晶片 131 主動面 132 銲墊 140 鮮線 150 封膠體 160 銲球 210 基板 211 上表面 212 下表面 213 開口槽 214 内接指 215 球墊 216 切割路徑 220 液態黏晶材料 221 氣泡 222 密實黏晶膜 11 1253739 230晶片 231主動面 232銲墊 240銲線 250封膠體 260銲球 270切割工具1 Provide a substrate 2 Apply a liquid die-bonding material to the substrate 3 Defoaming 4 First baking 5 Bonding 6 Second baking 7 Electrical connection 8 Sealing 9 Fresh ball bonding 10 Substrate cutting 110 Substrate 111 Upper surface 112 lower surface 113 open slot 120 die bonding material 121 bubble 130 wafer 131 active surface 132 solder pad 140 fresh wire 150 encapsulant 160 solder ball 210 substrate 211 upper surface 212 lower surface 213 open slot 214 internal finger 215 ball pad 216 Cutting path 220 liquid adhesive material 221 bubble 222 dense adhesive film 11 1253739 230 wafer 231 active surface 232 solder pad 240 wire 250 sealant 260 solder ball 270 cutting tool

1212

Claims (1)

1253739 十、申請專利範圍： 1、 —種無膠帶黏晶方式之積體電路封裝過程，包含： 提供至少-基板’其係具有一上表面、一下表面及至 少一開口槽； 塗敷一液態黏晶材料於該基板之該上表面； 進仃-脫泡之步驟’以去除該液態黏晶材料内之微細 氣泡； 、/亍第人烘烤之步驟，使該液態黏晶材料為半固化 • 狀態而成為一密實黏晶膜； 藉由4⑨實黏晶獏黏接—晶片之—主動面至該基板 之該上表面上，該晶片係具有複數個位於該主動面之 鲜塾’該些銲墊係顯露於該開口槽；及 進行第_次烘烤之步驟，以固化該密實黏晶膜。 2、 如申請專圍第i項所述之無膠帶黏晶方式之積體 電路封裝過程，其中在脫泡之步驟中，該基板係置於 # 真1狀態，並輔以震盪方式去除該液態黏晶材料内 之微細氣泡。 、如申請專利範圍第2項所述之無膠帶黏晶方式之積體 電路封裝過程’其中該真空狀態之壓力係不大於2 T〇rr 〇 申凊專利範圍第1項所述之無膠帶黏晶方式之積體 電路封裝過程，其中該些銲墊係位於該晶片之該主動 面之中央。 β 如申請專利範圍第1項所述之無膠帶黏晶方式之積體 13 1253739 電路封裝過程，其另包含一電性連 y 按之步驟，複數個 6 81253739 X. Patent application scope: 1. An integrated circuit packaging process without a tape-bonding method, comprising: providing at least a substrate having an upper surface, a lower surface and at least one open groove; applying a liquid viscosity a crystalline material on the upper surface of the substrate; a step of removing the defoaming to remove microbubbles in the liquid crystalline material; and a step of baking the first crystalline material to make the liquid bonded crystalline material semi-cured a state of being a densely bonded film; bonding through a 49-bonded wafer-active surface to the upper surface of the substrate, the wafer having a plurality of sinters on the active surface The pad is exposed in the open slot; and the step of baking is performed to cure the densely bonded film. 2. For the integrated circuit packaging process of the tapeless die-bonding method described in item i, in the step of defoaming, the substrate is placed in the #true 1 state, and the liquid state is removed by vibration. Fine bubbles in the die-bonding material. The integrated circuit packaging process of the non-adhesive die-bonding method described in the second paragraph of the patent application, wherein the pressure in the vacuum state is not greater than 2 T〇rr, and the non-adhesive tape described in claim 1 A crystalline integrated circuit packaging process in which the pads are located in the center of the active face of the wafer. β The unpackaged die-bonding method described in the first paragraph of the patent application 13 1253739 circuit packaging process, which further comprises an electrical connection y according to the steps, a plurality of 6 8 9 I線係經由該開口槽而電性連接該些銲塾至該基板。 如申請專利範圍第5項所述之無膠帶黏晶方式二積體 Z封裝過程，其另包含-封膠之步驟，以密封該些 如申請專利範圍第i或6項所述之無膠帶黏晶方式之 積體電路封裝過程，其另包含-銲球接合之步驟，其 係將複數個銲球接合至該基板之該下表面。 如申請專利範圍第！項所述之無膠帶黏晶方式之積體 電路封裝過程’其另包含一基板切割之步驟，其中切 割該基板之路徑係通過該開口槽之兩端。 一種無膠帶黏曰曰曰方式之積體電路封製過辛呈，包含： 提供至少一基板，其係具有一上表面以及一下表面； 塗敷一液態黏晶材料於該基板之該上表面； 進仃脫泡之步驟，以去除該液態黏晶材料内之微細 氣泡；The 9 I wire electrically connects the solder pads to the substrate via the open slots. The non-adhesive-bonding method of the two-component Z-packaging process as described in claim 5, further comprising a step of sealing the rubber to seal the non-adhesive tape as described in claim i or 6 of the patent application. The crystalline integrated circuit packaging process further includes a solder ball bonding step of bonding a plurality of solder balls to the lower surface of the substrate. Such as the scope of patent application! The integrated circuit packaging process of the tapeless die-bonding method described above further includes a substrate cutting step in which the path for cutting the substrate passes through both ends of the opening groove. The integrated circuit of the tapeless adhesive method is encapsulated and comprises: providing at least one substrate having an upper surface and a lower surface; applying a liquid adhesive material to the upper surface of the substrate; a step of defoaming to remove fine bubbles in the liquid crystalline material; 進行第一次烘烤之步驟，使該液態黏晶材料為半固化 狀態而成為一密實黏晶膜； 進打一黏晶之步驟，藉由該密實黏晶膜黏接一晶片至 乂基板之σ亥上表面上，該晶片係具有複數個銲墊； 電性連接該晶片之該些銲墊至該基板；及 進打第二次烘烤步驟，以固化該密實黏晶膜。 10、如申請專利範圍第9項所述之無膠帶黏晶方式之積體 電路封裝過程，其中在脫泡之步驟中，該基板係置於 1253739 一真空狀態 之微細氣泡 11 並輔以震盪方式去除該液態黏晶材料内 如申請專利範圍第 體電路封裝過程， Torr ° 10項所述之無膠帶黏晶方式之積 其中該真空狀態之壓力係不大於2Performing the first baking step to make the liquid die-bonding material semi-cured to become a densely bonded film; in the step of bonding a die, the dense bonded film is bonded to the substrate On the upper surface of the σ, the wafer has a plurality of pads; the pads of the wafer are electrically connected to the substrate; and a second baking step is performed to cure the dense film. 10. The integrated circuit packaging process of the tapeless die-bonding method according to claim 9, wherein in the step of defoaming, the substrate is placed in a micro-bubble 11 of a vacuum state of 1253739 and supplemented by an oscillating mode. Removing the liquid-filled material in the liquid crystal material as in the patented range of the first circuit packaging process, the Torr ° 10 item of the non-adhesive die-forming method, wherein the vacuum state of the pressure system is not more than 2 12、：=，9項所述之無膠帶…式之積想 13 雷踗私壯^ …夕π和日日乃八之積體 面之:::過程’其中該些鮮塾係位於該晶片之該主動 項所述之無勝帶黏晶方式之積艘 複數個=丄含一銲球接合之步驟，其係將 是数個鋅球接合至該基板之該下表面。12, :=, 9 items without tape... type of product thinking 13 Thunder private ^ ^ π π and the day is the eight-dimensional product of the decent::: process 'these fresh 塾 is located in the wafer The plurality of stacks of the die-bonded mode described in the active item include a step of bonding a solder ball to which a plurality of zinc balls are bonded to the lower surface of the substrate. 1515
TW094111884A 2005-04-14 2005-04-14 IC packaging process with non-tape die attachment TWI253739B (en)

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CN113345810A (en) * 2020-02-18 2021-09-03 朋程科技股份有限公司 Method for manufacturing power diode

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JP2019201045A (en) * 2018-05-14 2019-11-21 株式会社ディスコ Daf
TWI730623B (en) 2020-02-13 2021-06-11 朋程科技股份有限公司 Method for manufacturing power diode
CN113299791B (en) * 2021-04-14 2023-03-28 同心县京南惠方农林科技有限公司 Defoaming type texturing method for photovoltaic polycrystalline silicon

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113345810A (en) * 2020-02-18 2021-09-03 朋程科技股份有限公司 Method for manufacturing power diode

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