TWI251748B - System, circuitry and method for parallel processing real-time signal with open structure - Google Patents

Abstract

A system for parallel processing real-time signal with open structure comprises a host computer, a circuitry for parallel processing real-time signal with open structure, a plurality of peripheral devices and an analog signal processing device. Wherein, the host computer controls the peripheral devices and the analog signal processing device through the circuitry of the present invention. The circuitry of the present invention processes a plurality of digital echo data generated by the analog signal processing device with parallel signal processing, and generates report result reporting to the host computer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an instant signal processing circuit, system and method, and more particularly to an open signal processing circuit, system and method for an open parallel architecture. [Prior Art] In recent years, due to the rapid advancement of semiconductor technology and the advancement and popularization of digital signal processing (D S P ) components, instant (r e a 1 - t i m e ) digital signal processors have successively adopted a parallel architecture. The processing of real-time digital signals is also indispensable in the application of national defense. For example, radar signal processors are an important device. At present, for example, the US Navy Marine Patrol Aircraft P-3C AN/APS-137B(V) radar system uses RACE computer for signal processing. These signals are processed by Synthetic Aperture Radar (SAR) and Anti-Synthetic Aperture Radar (ISAR). ) processing. On the other hand, the US Navy's AEGIS AN/SPY-1 modified radar uses a RACE computer to replace the original signal processing hardware architecture with 192 SHARC processors. Conventional techniques for processing instant signals can be implemented in hardware or software, but have their drawbacks. Among them, the instant signal is processed by the hardware architecture, although the processing speed can be speeded up, and it is synchronous processing. However, when applied to different system specifications, different hardware circuits must be designed. However, if the software implements the processing of the real-time signal, although the hardware architecture has the scalability (S ca 1 abi 1 ity ), the disadvantage is that it is not easy to achieve the immediate requirement, and if the processor is an asynchronous system, it is very Difficulties are synchronized with the entire instant signal processing system. In order to overcome the above problems, in U.S. Patent No. 5,7 0 1,4 8 2

13358twf.ptd Page 7 1251748 V. Invention Description (2) proposes an array processing of multi-channel input data. However, in this patent, each node is Asynchronous Processing, and the overall architecture is a multi-processing array, which is not a parallel processing architecture. In addition, this patent does not suggest how to communicate and synchronize with the whole system. Therefore, some technologies combine hardware architecture with this patent, but they are not suitable for off-the-shelf commercial off-the-shelf (COTS) processing modules, and the hardware architecture is not fully scalable. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an open signal processing system with an open parallel architecture that achieves full system synchronization. It is still another object of the present invention to provide an open signal processing circuit of an open parallel architecture having expandable characteristics. It is still another object of the present invention to provide an instant signal processing method of an open parallel architecture that meets the requirements of instant processing. The object of the present invention is to provide an open parallel architecture real-time signal processing system including a host interface unit for connecting an instant signal processing system and a host computer of the present invention through a computer network, and a host interface The unit system also generates control signals based on the host computer. In addition, the instant signal processing system of the present invention further includes an interface control processor, an analog signal control processor, and a digital signal scheduling processor. The interface control processor is coupled to the host interface unit, and controls the peripheral device according to a control signal generated by the host interface unit. The analog signal processor is a coupled interface control processor that controls the analog signal processor according to an instruction output by the interface control processor. In addition, the digital signal scheduling processor is the same

m m

13358twf.ptd Page 8 1251748 V. INSTRUCTIONS (3) The sample is also a coupled interface control processor that also provides scheduling control signals based on instructions output by the interface control processor. In addition, the present invention further includes a digital signal processor for receiving digital 1-wave data and processing digital echo data in accordance with the scheduling control signal. In a preferred embodiment, the present invention further includes a self-test control processor for executing a self-test command transmitted by the host interface unit to generate a self-test result for transmission back to the host interface unit. In one embodiment of the invention, the digital signal processing unit includes a data injection module and a real-time data register. The data injection module is configured to receive digital echo data and convert the digital echo data from a differential type to a TTL type. The real-time data register is coupled to the data injection module for storing digital echo data. In addition, the digital signal processor further includes a plurality of vector signal processors coupled to the real-time data register for processing the digital echo data. From another point of view, the present invention provides an open parallel architecture real-time signal processing circuit, which includes a local bus and a host interface module, wherein the host interface module is coupled to the local bus and the host interface module The control signal is generated to the local bus according to the system synchronization signal. In addition, the present invention also includes an input/output buffer module, an analog signal control parameter module, and a digital signal scheduling processing module, wherein the input/output buffer module generates a control periphery according to a control signal generated by the host interface module. instruction. The analog signal control processing module generates an analog control command according to the command output by the input/output buffer module. In addition, the digital signal scheduling processing module generates a schedule control according to the command output by the input/output buffer module.

13358twf.ptd Page 9 1251748 V. INSTRUCTIONS (4) Signal to the local bus. In addition, the present invention further includes a digital signal processing unit that is also coupled to the local bus. The digital signal processing unit is configured to receive the digital echo data and read the scheduling control signal through the local bus to process the received digital echo data. From another point of view, the present invention provides an open parallel architecture instant signal processing method that can be used on a parallel instant messaging system having a host computer. The instant signal processing method of the present invention comprises the following steps: First, a system synchronization signal is generated, and then an input/output buffer main program is executed in accordance with the system synchronization signal. The input/output buffer main program is used to transfer system control commands generated by the host computer to analog signal processing programs and digital signal processing programs. The analog signal processing main program and the digital signal processing main program are then executed in accordance with the system synchronization signal. Finally, the vector program of the vector signal processing is executed to perform signal processing on the digital echo data, and a return result is generated to the host computer. In summary, in the present invention, a plurality of vector signal processors are provided, which can process a plurality of real-time digital echo signals in parallel, thereby enabling system-wide synchronization. In addition, the digital signal scheduling processor adjusts the order of processing signals based on the returned digital echo data, so that the present invention can achieve the requirements of real-time processing. However, the present invention can adjust the number of various modules according to actual needs, and thus the present invention has a high degree of expandability. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment]

13358 twf.ptd page 10 1251748 V. Description of the Invention (5) FIG. 1A is a block diagram showing the architecture of an open signal processing system of an open parallel architecture in accordance with a preferred embodiment of the present invention. Referring to FIG. 1A, the present invention provides an open parallel architecture real-time signal processing circuit 100, wherein the host interface unit 102 is coupled to a host through a computer network such as an Ethernet network (Ethernet). The computer 1 220 and sends the output to the interface control processor 104. The interface control processor 104 is used to control the peripheral system 1 300 of the instant signal processing circuit 100, and couples the output to the analog signal control processor 1 〇 6 and the digital scheduling processor 1 0 8 respectively. The analog signal control processor 106 is used to control the analog signal processing system 140, such as radar, sonar, ultrasonic medical, wireless communication and other analog circuit parts. The present invention further includes a digital signal processing unit 110, which receives the digital echo data returned by the analog signal processing system 140, and processes the digital echo according to the instruction output by the digital signal scheduling processor 108. data. Referring to FIG. 1A, the digital signal processing unit 1 10 includes a data injection module 1 1 2 for receiving digital echo data returned by the analog signal processor 140, such as an instant return of the radar system. Wave signal. Then, after the digital echo data is injected into the module 1 1 2, it is stored in the real-time data register 1 1 4 such as a flash memory, and then the vector signal processing έ 1 1 6 is temporarily stored from the real-time data. The digital echo data is read in the device 1 14 and subjected to various parallel signal processing functions, and the signal processing function of the vector signal processor 1 16 is implemented in a software manner. In addition, in the present invention, the number of the interface control processor 104 and the vector signal processor 1 16 can be determined according to actual needs, so as to facilitate simultaneous control of multiple peripheral devices.

13358twf.ptd Page 11 1251748 V. INSTRUCTIONS (6) Preparation 1 3 0 and simultaneous processing of multiple digital echo data. 1B is a block diagram showing the architecture of an instant parallel architecture of an instant parallel architecture in accordance with another embodiment of the present invention. Referring to FIG. 1B, in another alternative embodiment of the present invention, the instant signal processing circuit 100 of the present invention is further provided with a self-test control processor 118. The self-test control processor 1 18 is used to execute the self-test command generated by the host computer 120 through the host interface unit 1 〇 2, and the self-test result is transmitted back to the host computer through the host interface unit 丨〇 2 1 2 0. Figure 2 is a block diagram showing the internal function of a detailed instant signal processing circuit in accordance with Figure 1b. Referring to FIG. 2, the host interface module 2 〇 1 and the interface module groups 2 0 3 and 2 0 5 are all coupled to the local bus bar 2 1 to form a host interface unit. In this embodiment, the local bus bar 2 1 is, for example, a European General Module (VME) bus or a close peripheral component (cpci) bus. The host interface module 201 receives, for example, a system control command and a self-test command generated by the host computer 1 20 at each preset period. When the host media module 2 0 1 receives a start signal, the system control command is output from the mediation group 2 0 5 to the interface module 2 1 3, and the self-test command is output from the mediator 2 to the interface module 2 5 3. The input/output buffer module 2 1 1 , the interface module 2丨3 and the instant module 215 are all coupled to the local bus bar 21, which can constitute a sequence control processor. When the input/output buffer module 21 i receives the system synchronization, the system control command is received by the interface module 2 1 3, and the device U0 is commanded, and the system control instruction 'week group 2 2 3 and 243. In addition, the self-test module 251 and the interface ^ surface loose U - test also

1251748 V. INSTRUCTIONS (7) Lightly connect the local bus 2 1 ' to form a self-test control processor. When the self-test module 251 receives the system synchronization signal, it receives a self-test command from the interface unit 253 and executes it. After the self-test module 2 5 1 executes the self-test command, it will generate a self-test result, and return to the host through the interface module 2 5 3 to set the group 2〇1, waiting for the host computer 120 to request the return. ^ ^ Analog signal control processing module 2 2 1 and interface module 2 2 3 are both switched to local bus 2 1 ', which can constitute an analog signal control processor, when class

When the ratio control processing module 2 2 1 receives the system synchronization signal, it receives the system control command from the interface and the module 2 2 3 and sets the analog signal processing system 140 according to the system control command. In addition, the digital signal scheduling processing module 241 and the interface unit 243 are also coupled to the local bus 2, and the two can form a digital h-ranking processor. When the digital signal scheduling processing module 2 receives the system control command sent by the input/output buffer module 2 1 1 from the interface unit 243, a scheduling control signal is generated, and the data input buffer module 2 3 3 is set. And a number of vector signal processors such as 2 3 5 .

The data injection module 23 1 , the data input buffer module 233 and the plurality of signal processors, for example 235, are all coupled to the local bus 2 丨, which can be combined with a digital signal processing unit. When the data input buffer module 2 3 3 receives the digit 1, after processing the start signal, the data injection module 2 3 receives the digital echo data from, for example, the analog signal processing system 140. Then the data input rush group 2 3 3 will pre-process the digital echo data, such as frequency conversion sampling, digital filter coefficient processing, and other noise cancellation. The digital echo data is then sent to, for example, a vector signal processor 253 to simultaneously perform a plurality of signal processing on the digital echoes. Digital echo

13358twf.ptd Page 13

1251748 V. INSTRUCTIONS (8) After the data is processed, the results will be returned to the local bus. At this time, for example, the vector signal processor of 253 will notify the digital signal scheduling processing module 241, and the digital signal scheduling processing module 241 will transmit the result of the return to the interface module 241. The host interface 2 0 1, then the host interface 2 0 1 transmits the result of the reward to, for example, the host computer 1 2 0. 3 is a flow chart showing an instant signal processing method of an open parallel architecture in accordance with a preferred embodiment of the present invention. Referring to FIG. 3, the instant signal processing method disclosed in this embodiment can be applied to a parallel real-time signal processing system having a host computer, such as the hardware architecture described above. First, as described in step S310, a system synchronization instruction is generated. Then, as described in step S3 2 0, the input/output buffer main program is started. Then, as described in step S3 30, the digital signal processing main program and the analog signal processing main program are started. Finally, the vector processing main program is started as described in step S3 40. In another alternative embodiment, the input/output buffer main program is started, and the parallel real-time signal processing system applied to the present invention is also subjected to a self-test operation, and then the self-test result is reported to the host computer. 4 is a flow chart showing an input/output buffer main program in accordance with a preferred embodiment of the present invention. Referring to FIG. 4, as described in step S4 0, the instantaneous timing control and peripheral devices are set according to a preset system control command. Then, as described in step S4 0 3, the input/output buffer interrupt subroutine is started, and then it is judged whether there is an analog signal processing synchronization signal or a digital signal processing synchronization signal, that is, step S405. When the input/output buffer main program receives the analog signal processing synchronization signal or the digital signal processing synchronization signal (that is, the number indicated in step S4 0 5 is 〃), step S4 0 is started.

13358twf.ptd Page 14 1251748 V. INSTRUCTIONS (9) Dynamic instantaneous timing control. Next, as described in step S409, it is determined whether there is an interrupt signal generated by the immediate timing control. If the input/output buffer main program receives the interrupt signal generated by the immediate timing control (that is, the '' is 〃 indicated by the step S409), the input/output buffer interrupt subroutine is started as described in step S41:1. Then repeat step S4 0 9. In this embodiment, the flow of the input/output buffer interrupt subroutine is as follows: first, the system control command generated by the host computer is read, and then the immediate timing control and the peripheral device are set according to the system control command generated by the host computer. Finally, the system control commands generated by the host computer are transferred to the analog signal processing program and the digital signal processing program. FIG. 5 is a flow chart showing an analog signal processing main program according to a preferred embodiment of the present invention. Referring to Figure 5, the analog signal processing main program is mainly used to set the parameter values of the analog signal processing system. First, as described in step S501, the control parameters of the analog signal processing are set according to the preset system control command. Then start the analog signal processing interrupt subroutine, which is step S 5 0 3 . Next, step S 5 0 5 is performed to generate a synchronization signal for analog signal processing. Then, as described in step S507, it is determined whether there is an interrupt signal generated by the immediate timing control. If the analog signal processing main program receives the interrupt signal generated by the immediate timing control (that is, the step indicated by step S507), then step S509 is performed to start the analog signal processing interrupt subroutine. The processing interrupt subroutine is mainly responsible for setting the signals required by all analog signal processing system hardware, and setting the timing required for the analog signal processing system to synchronize with the whole system. In this embodiment, the flow processing interrupt subroutine flow description is described. As follows. First read the host computer

13358twf.ptd Page 15 1251748 V. INSTRUCTIONS (ίο) The generated system control instructions are then used to set the control parameters of the analog signal processing system based on the system control commands generated by the host computer. 6 is a flow chart of a digital signal processing main program in accordance with a preferred embodiment of the present invention. Referring to Fig. 6, the digital signal processing main program is used to set the initial value required for the hardware of the digital signal processing unit, and the flow is as follows. As described in step S610, the pre-processing of the digital echo data is set according to the preset system control command. Then, as described in step S630, the digital signal processing interrupt subroutine and the vector signal processing interrupt subroutine are activated. The digital signal processing synchronization signal is then generated as described in step S605. At this time, it is judged whether there is an interrupt signal generated by the immediate timing control or an interrupt signal generated by the vector signal processing. If there is an interrupt signal generated by the immediate timing control, the step S690 is started to start the digital signal processing interrupt subroutine. If there is an interrupt signal generated by the vector signal processing, the vector signal processing interrupt subroutine is started, which is step S61. In the present embodiment, the flow of the digital signal processing interrupt subroutine is as follows. First, the system control signal generated by the host computer is read, and then the vector signal processing is set according to the system control signal generated by the host computer, and the pre-processing of the digital echo data is also set. The flow of the vector signal processing interrupt subroutine includes reading and recording the interrupt information generated by the vector signal processing. FIG. 7 is a flow chart showing a main program of vector signal processing according to a preferred embodiment of the present invention. Referring to Figure 7, the vector signal processing main program is started according to digital signal processing, which includes performing n vector signal processing, wherein η is a positive integer. In this embodiment, vector signal processing

13358twf.ptd Page 16 1251748 V. INSTRUCTIONS (11) The main program consists of two parts. The first part is the part that performs the first vector signal processing, and the other part is the second one. Part of the ηth vector signal processing. When the vector signal processing main program executes the first vector signal processing, the digital signal processing instruction is first read as described in step S307, and then initialized as described in step S307. When digital echo data is sent in, as described in step S307, the digital echo data is read, and after the echo data is read, a permission signal is generated to the second vector signal processing. Next, the digital echo data is subjected to various parallel signal processing function operations, that is, step S 7 0 7 . After processing the digital echo data, it is necessary to integrate the results of various parallel signal processing in the first vector signal processing as described in step S709, and also integrate other vector signals as described in step S711. In the process, the results of the integration of various parallel signal processing. Finally, as described in step S7 131, the return result is returned to the host computer. When the vector signal processing main program executes the mth vector signal processing (m is a positive integer greater than 1 and smaller than η), the instruction generated by the digital signal processing is also read, which is described in step S7.2. Then, initialization is performed as described in step S 7 2 3 . Next, as described in step S725, the permission signal generated by the previous vector signal processing is awaited. After receiving the permission signal generated by the previous vector signal processing, the digital echo data is read as described in step S 7 27, and a permission signal is also generated to the next vector signal processing. After reading the digital echo data, various parallel signal processing functions are performed as described in step S 7 29 . Further, as described in step S731, the results of various parallel signal processing in integrating the mth vector signal processing are integrated. most

13358twf.ptd Page 17 1251748 V. Description of Invention (12) After the step S733, the integrated result is output to the first vector signal processing to perform step S 7 1 1 . While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

13358 twf.ptd Page 18 1251748 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A is a block diagram showing the architecture of an open signal processing instant signal processing system in accordance with a preferred embodiment of the present invention. 1B is a block diagram showing the architecture of an open parallel architecture real-time signal processing system in accordance with another embodiment of the present invention. Figure 2 is a block diagram showing the internal function of a detailed instant signal processing circuit in accordance with Figure 1B. 3 is a flow chart showing an instant signal processing method of an open parallel architecture in accordance with a preferred embodiment of the present invention. 4 is a flow chart showing an input/output buffer main program in accordance with a preferred embodiment of the present invention. FIG. 5 is a flow chart showing an analog signal processing main program according to a preferred embodiment of the present invention. 6 is a flow chart of a digital signal processing main program in accordance with a preferred embodiment of the present invention. FIG. 7 is a flow chart showing a main program of vector signal processing according to a preferred embodiment of the present invention. [Graphic indication] 21: Local bus 1 0 0: Open parallel architecture instant signal processing circuit 102: Host interface unit 1 0 4: Interface controller 1 0 6 : Analog signal control processor 1 0 8 : Digital Signal scheduling processor 1 1 0 : digital signal processing unit

13358twf.ptd Page 19 1251748 Simple description of the diagram 1 1 2 : Data injection module 1 1 4 · 'Instant data temporary storage 1 1 6 : Vector signal processor 1 1 8 · Self-test control processor 1 2 0 : Host computer 1 3 0 : Peripheral device 1 4 0 : Analog signal processing system 2 0 1 : Host interface module 203, 205, 213, 223, 243, 253 · Interface module 2 0 1 : Host interface module 2 11: Input and output buffer module 2 1 5 : Instant timing control module 2 2 1 : Analog signal control module 2 3 1 : Data injection module 2 2 3 : Input data buffer module 2 3 5 : Vector Signal processor 2 4 1 ··Digital signal scheduling processing module 2 5 1 : Self-test module S310, S320, S330, S340: Steps S401, S403, S405, S407 of the instant signal processing method of the open parallel architecture, S409, S411: Input and output buffer main program steps S501, S503, S505, S507, S509: analog signal processing main program

13358twf.ptd Page 20 1251748 Schematic description S601, S603, S605, S607, S609, S611: digital signal processing main program S701, S 7 0 3, S 7 0 5, S 7 0 7, S 70 9, S711 , S713, S721, S723, S725, S727, S729, S731, S733: Steps for vector signal processing main program

13358twf.ptd Page 21

Claims (1)

1251748 6. Patent application scope 1. An open parallel architecture real-time signal processing system, comprising: a host interface unit for connecting the instant signal processing system and a host computer through a computer network, wherein the host interface unit Generating a control signal according to the host computer; an interface control processor coupled to the host interface unit to control a peripheral device according to the control signal; and an analog signal control processor coupled to the interface control processor Controlling an analog signal processing system according to an instruction output by the interface control processor; a digital signal scheduling processor coupled to the interface control processor to provide a scheduling control signal according to an instruction output by the interface control processor; And a digital signal processing unit for receiving the digital echo data, and processing the digital echo data according to the scheduling control signal. 2. The instant signal processing system of the open parallel architecture according to claim 1, further comprising a self-test control processor, executing a self-test command transmitted by the host interface unit, and generating a self-test The result is passed back to the host interface unit. 3. The instant signal processing system of the open parallel architecture according to claim 1, wherein the digital signal processing unit comprises: a data injection module for receiving the digital echo data and returning the digits The wave data is converted from a differential type to a TTL type; an instant data register is coupled to the data injection module for storing the edge digital echo tribute, and 13358twf.ptd Page 22 1251748 VI. Patent Application Range Most vector signal processors are coupled to the real-time data register to process the digital echo data. 4. The instant signal processing system of the open parallel architecture of claim 3, wherein the instant data register comprises a flash memory. 5. The instant signal processing system of the open parallel architecture of claim 3, wherein the function for processing the digital echo data is implemented in a software mode on the vector signal processors. 6. The instant signal processing system of the open parallel architecture according to claim 1, wherein the computer network comprises an Ethernet (Ethernet) .7. An open parallel architecture instant signal processing circuit The method includes: a local bus module; a host interface module coupled to the local bus bar, the host interface module generates a control signal according to the system synchronization signal to the local bus bar; an input/output buffer module coupled to the The local bus bar generates an instruction for controlling the periphery according to the control signal; and the analog signal control processing module is configured to generate an analog control command according to the command output by the input/output buffer module; a digital signal scheduling processing module a group, coupled to the local bus, for generating a scheduling control signal to the local bus according to an instruction output by the input/output buffer module; and a digital signal processing unit for receiving a digital echo data, and Processing the digital echo by reading the scheduling control signal through the local bus 13358twf.ptd Page 23 1251748 VI. Application for patent coverage. 8. The instant signal processing circuit of the open parallel architecture as described in claim 7 further includes a self-test module for executing a self-test command sent by the host interface module through the local bus bar. And generate a self-test result to the local bus. 9. The instant signal processing circuit of the open parallel architecture according to claim 8, wherein the host interface module generates a synchronization message by reading the self-test result through the local bus. 10. The instant signal processing circuit of the open parallel architecture according to claim 7, wherein the digital signal processing unit comprises: ^ a poor charge injection core group handle connected to the local bus bar for receiving the digit Echo data, and converting the differential type of the digital echo data into a TTL type; an input data buffer module coupled to the local bus bar, the digit is returned according to the digital signal processing unit The wave data is processed in advance; and the plurality of vector signal processing modules are coupled to the local bus bar for processing the digital echo data transmitted by the input data buffer module. The instant signal processing circuit of the open parallel architecture of claim 1, wherein the data injection module further comprises a flash memory for storing the digital echo data. 1 2. The instant signal processing circuit of the open parallel architecture according to claim 7 of the patent application, further comprising an instant timing control module for providing a timing control signal for controlling an analog signal processor to generate the digit return 13358twf.ptd Page 24 1251748 VI. Application for patent coverage Wave data. The instant signal processing circuit of the open parallel architecture described in claim 7 further includes a plurality of interface modules, which are coupled to the local bus bar for use as the instant signal processing circuit and the outside world. And the input and output interface between the module and the module. 1 . The instant signal processing circuit of the open parallel architecture according to claim 7, wherein the local bus bar comprises a European standard module (VME) bus bar and a tight peripheral component link (CPCI) bus. One of the two. An open signal processing method for an open parallel architecture is applicable to a parallel instant signal processing system having a host computer, the instant signal processing method comprising the steps of: generating a system synchronization signal; performing according to the system synchronization signal An input/output buffer main program for transmitting system control commands generated by the host computer to an analog signal processing and a digital signal processing; performing the analog signal processing main program and the digital signal processing main program according to the system synchronization signal And executing a vector signal processing main program for signal processing a digital echo data and generating a reward result to the host computer. 1 6. The instant signal processing method of the open parallel architecture according to claim 15 wherein the input/output buffer main program is started, and the parallel instant signal processing system is further configured to perform a self-test operation. And generate a self-test result to the host computer. 13358twf.ptd Page 25 1251748 VI. Patent Application No. 1 7. The instant signal processing method of the open parallel architecture described in claim 15 of the patent application, wherein the step of executing the input/output buffer main program comprises the following steps : setting an immediate timing control and peripheral devices of the parallel instant signal processing system according to a preset system control command; starting an input/output buffer interrupt subroutine; determining whether there is one of the analog signal processing and the digital signal processing And generating the synchronization signal; starting the instant timing control, determining whether there is an interrupt signal generated by the immediate timing control; and when the interrupt signal generated by the immediate timing control is generated, starting the input/output buffer interrupt subroutine. 1 . The instant signal processing method of the open parallel architecture according to claim 17 , wherein the step of executing the input/output buffer interrupt subroutine comprises the following steps: reading system control generated by the host computer Commanding; setting the instant timing control and peripheral devices of the parallel instant signal processing system according to system control commands generated by the host computer; and transmitting system control commands generated by the host computer to the analog signal processing and the digital signal processing . 1 9. The instant signal processing method of the open parallel architecture according to claim 15 wherein the step of executing the analog signal processing main program comprises the following steps: setting analog signal processing according to a preset system control instruction Control parameter 13358twf.ptd Page 26 1251748 6. Number of patent applications; Start a class of signal processing interrupt subroutine; Generate a synchronization signal; Determine whether there is an interrupt signal generated by the immediate timing control; and when there is such immediate timing control When the interrupt signal is activated, the analog signal processing interrupt subroutine is started. The instant signal processing method of the open parallel architecture according to claim 19, wherein the step of executing the analog signal processing interrupt subroutine comprises the following steps: reading system control generated by the host computer An instruction; and setting a control parameter of the analog signal processing according to a system control command generated by the host computer. 2 1. The instant signal processing method of the open parallel architecture according to claim 15 wherein the step of executing the digital signal processing main program comprises the following steps: setting the digital back according to a preset system control instruction Preprocessing of wave data; starting a digital signal processing interrupt subroutine and a vector signal processing interrupt subroutine; generating a synchronization signal for the digital signal processing; determining whether there is an interrupt signal generated by the immediate timing control and the vector signal processing One of the generated interrupt signals; when there is an interrupt signal generated by the immediate timing control, the digital signal processing interrupt subroutine is activated; 13358twf.ptd Page 27 1251748 VI. Patent Application Range When there is an interrupt signal generated by this vector signal processing, the vector signal processing interrupt subroutine is started. 2 2. The instant signal processing method of the open parallel architecture according to claim 21, wherein the step of executing the digital signal processing interrupt subroutine comprises the following steps: reading system control generated by the host computer Signal; set and start the vector signal processing according to the system control signal generated by the host computer; and process the digital echo data before setting. 2) The method for processing an open parallel architecture according to claim 21, wherein the step of executing the vector signal processing interrupt subroutine comprises reading and recording the interrupt information sent by the vector signal processing. . 2. The instant signal processing method of the open parallel architecture according to claim 15 wherein the vector signal processing main program is started according to the digital signal main program, and the step comprises: starting n vector signal processing. And η is a positive integer number, wherein the step of performing the first vector signal processing comprises the steps of: reading an instruction issued by the digital signal processing; performing initialization; reading the digital echo data and generating a permission signal; In the first vector signal processing, a plurality of parallel signal processing functions are operated; integrating the first vector signal processing, the parallel signal processing is produced. 13358twf.ptd Page 28 1251748 VI. Scope of application for patents; Integration of other vector signal processing, the results of these parallel signal processing; and the generation of a return result to the host computer. 2 5. An instant signal processing method of an open parallel architecture as described in claim 24, wherein a step in which the in is greater than 1 and less than η is defined, and the step of performing the mth vector signal processing includes the following Step: reading the startup instruction; performing initialization; waiting for the permission signal generated by the previous vector signal processing; when the current vector signal processing issues the permission signal, reading the digital echo data and sending the permission signal to the next Vector signal processing; performing the mth vector signal processing, the parallel signal processing function operations; integrating the mth vector signal processing, the results of the parallel signal processing; and outputting the mth vector signal processing, The parallel signal processing combines the resulting results to the first vector signal processing for integration. 13358twf.ptd Page 29