JP2012139475A - Acoustic wave acquisition apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an acoustic wave acquisition apparatus that can produce a high-precision image by diminishing the effect of variation in timing of taking data in.SOLUTION: The acoustic wave acquisition apparatus for producing image data, includes: a receiving element for converting an acoustic wave propagated in a subject into an analog electrical signal; an AD converter for converting the analog electrical signal into a digital electrical signal according to a reference clock signal; and a data processor. The data processor has: a first memory for storing parallel data; a counter for starting to count a reference clock signal before starting storage; a second memory for storing a count value from the count unit; and a determiner for checking by comparison whether the stored value is within a certain range to determine timing variation.

Description

  The present invention relates to an acoustic wave acquisition apparatus.

Conventionally, it is known that when a living body is irradiated with light, an acoustic wave is generated due to a temperature rise and thermal expansion of a living tissue accompanying light absorption of the living body. A technique called photoacoustic tomography (PAT) that uses this phenomenon to visualize the inside of a living body in a non-invasive manner has recently been in the spotlight. It has been tried. Moreover, it is expected that the diagnostic accuracy in the clinical field can be greatly improved by combining a photoacoustic image acquired in real time with a general ultrasonic image.

  In the photoacoustic tomography diagnostic apparatus, a one-dimensional or two-dimensional micro-vibrator array in which a target subject is irradiated with light, and a plurality of micro-vibration elements (reception elements) are arrayed for the acoustic waves generated thereby. Receive by. As the one-dimensional or two-dimensional micro-vibrator array, one similar to a probe usually used in an ultrasonic (echo) apparatus is often used.

  The acoustic wave that reaches the probe is converted into an electrical signal by the micro-vibration element, and converted into digital data by the AD converter. Digital data is stored in a data memory in the photoacoustic tomography diagnostic apparatus. A series of processes until the acoustic wave received by the probe is stored in the data memory is almost the same between the photoacoustic tomography diagnostic apparatus and a general ultrasonic apparatus.

In image reconstruction in photoacoustic tomography, various algorithms can be applied to digital data stored in a data memory. It is possible to apply a so-called method.
As described above, the photoacoustic tomography diagnostic apparatus and the ultrasonic apparatus have many parts similar to the apparatus configuration and the data processing method, and therefore, an attempt is made to form both a photoacoustic image and a general ultrasonic image with the same system. ing.

JP 2005-21380 A US Patent Application Publication No. 2009/0187099

  When an ultrasonic device is configured using an AD converter of a type that outputs a frame clock signal together with serial data, and the output of the AD converter is captured in a data memory in the ultrasonic device, a shift in data capture timing may occur. is there. This shift in the data fetching timing into the data memory is caused by a shift in the phase relationship between the frame clock signal output from the AD converter and the reference clock inside the ultrasonic apparatus.

  Conventionally, in an ultrasonic apparatus using an AD converter of a type that outputs a frame clock signal together with serial data, photoacoustic image data or ultrasonic image data cannot be generated with high accuracy in a state in which a data acquisition timing shift occurs. There was a problem.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an acoustic wave acquisition apparatus capable of suppressing the influence of a data capture timing shift and generating highly accurate image data.

  The present invention employs the following configuration. That is, a plurality of receiving elements that receive an acoustic wave propagated through a subject and convert it into an analog electric signal, and the analog electric signal is sampled for each reference clock signal and converted into a digital electric signal as serial data. An AD converter that outputs the serial data together with a clock signal, and a data processing device that receives the frame clock signal and the serial data from the AD converter and converts the serial data into parallel data, and An acoustic wave acquisition device that generates image data using output data from a data processing device, wherein the data processing device uses the parallel data corresponding to each of the plurality of receiving elements as the frame clock signal. A plurality of first memos stored for each frequency write clock signal And counting means for starting counting of a reference clock signal having a frequency that is a multiple of the reference clock signal before the first memory starts storing the parallel data, and the count value of the counting means A second memory that stores each write clock signal; and a determination unit that determines whether the value stored in the second memory is within a predetermined range and determines a timing shift. This is an acoustic wave acquisition device.

  The present invention also employs the following configuration. That is, a plurality of receiving elements that receive an acoustic wave propagated through a subject and convert it into an analog electric signal, and the analog electric signal is sampled for each reference clock signal and converted into a digital electric signal as serial data. An AD converter that outputs the serial data together with a clock signal, and a data processing device that receives the frame clock signal and the serial data from the AD converter and converts the serial data into parallel data, and An acoustic wave acquisition device that generates image data using output data from a data processing device, wherein the data processing device uses the parallel data corresponding to each of the plurality of receiving elements as the frame clock signal. A plurality of first memos stored for each frequency write clock signal And at the same time the first memory starts storing the parallel data, the counting means for starting the counting of the write clock signal, and the count value of the counting means is set to a frequency that is a multiple of the reference clock signal. A second memory for storing each reference clock signal, and a determination unit that determines whether or not a value stored in the second memory is within a predetermined range to determine a timing shift. It is an acoustic wave acquisition device.

  According to the present invention, it is possible to provide an acoustic wave acquisition apparatus capable of suppressing the influence of a data capture timing shift and generating highly accurate image data.

The figure which shows the structure of the photoacoustic and ultrasonic device of this invention. The figure which shows the receiving beam shaping apparatus and peripheral circuit of this invention. The figure which shows the positional relationship of the target in a subject area | region and a receiving element. The figure which shows the ideal operation | movement sequence when not applying this invention. The figure which shows the operation sequence which is not ideal when not applying this invention. The figure which shows the structure of the shift | offset | difference detection circuit of 1st Embodiment. The figure which shows the ideal operation | movement sequence of 1st Embodiment. The figure which shows the non-ideal operation | movement sequence of 1st Embodiment. The figure which shows the data content difference of 1st Embodiment. The figure which shows the structure of the shift | offset | difference detection circuit of 2nd Embodiment. The figure which shows the ideal operation | movement sequence of 2nd Embodiment. The figure which shows the non-ideal operation | movement sequence of 2nd Embodiment. The figure which shows the data content difference of 2nd Embodiment. The figure which shows the correction | amendment means when deviation | shift is not detected. The figure which shows the correction | amendment means when deviation | shift is detected.

  Hereinafter, embodiments of the photoacoustic and ultrasonic apparatus according to the present invention will be described in detail with reference to the drawings. As used herein, “photoacoustic and ultrasonic apparatus” refers to an apparatus capable of performing both photoacoustic tomography diagnosis and ultrasonic diagnosis. Since the photoacoustic tomography diagnosis and the ultrasonic diagnosis are common in that the ultrasonic wave (acoustic wave) propagated through the measurement object (subject) is acquired, the “photoacoustic and ultrasonic apparatus”, the photoacoustic tomography diagnostic apparatus Both of the ultrasonic devices can be called “acoustic wave acquisition devices”. As will be described later, the acoustic wave acquisition method of the present invention can be applied not only to “photoacoustic and ultrasonic apparatus” but also to both an apparatus that performs only photoacoustic tomography diagnosis and an apparatus that performs only ultrasonic diagnosis. .

<First Embodiment>
FIG. 1A is a diagram showing a configuration of the photoacoustic and ultrasonic apparatus 1 according to the first and second embodiments of the present invention.
The photoacoustic and ultrasonic apparatus 1 includes a probe 2, an AD converter 3, a reception beam shaping device 4 as a data processing device, a signal processing unit 5, an image processing unit 6, and an image display unit 7. The photoacoustic and ultrasonic apparatus 1 further includes a data memory control circuit 8, a weighting coefficient supply circuit 9, a control CPU 10, a light irradiation unit 12, and an ultrasonic transmission unit 11.

  The light irradiation unit 12 irradiates the subject region with light at a certain timing according to the control of the control CPU 10 or the like. When the subject region is irradiated with light by the light irradiation unit 12, a photoacoustic wave is generated and propagated in the subject. The ultrasonic transmission unit 11 transmits ultrasonic waves to the subject region according to the control of the control CPU 10 or the like. The probe 2 receives the photoacoustic wave generated and propagated in the subject and the reflected wave of the ultrasonic wave transmitted to the subject.

  The received photoacoustic wave and ultrasonic wave are converted into an analog electric signal by the probe 2. The analog electric signal is digitized by the AD converter 3 and converted into a digital electric signal. The digital electric signal is subjected to phasing addition processing by the reception beam shaping device 4 which is a data processing device, and is subjected to processing such as filter processing, logarithmic compression, envelope detection, etc. The signal processing unit performs appropriate processing according to the nature of the signal to be handled.

  Further, the output data of the signal processing unit is input to the image processing unit 6 and processed as necessary for image generation, and becomes image data. The image display unit 7 displays photoacoustic and ultrasonic images according to the image data generated by the image processing unit 6. The control CPU 10 supplies data and control signals necessary for controlling each block.

  The data memory control circuits 8-1 to 8-T process the delay data of the reception signal, and perform reception data writing or reading control of the data memory in the reception beam shaping device 4. Here, T indicates the number of data memories existing in the reception beam shaping apparatus 4. The weighting coefficient supply circuits 9-1 to 9-X process weighting data for apodization and supply weighting coefficients to the multipliers in the reception beam shaping device 4. X represents the number of apodization multipliers present in the reception beam shaping apparatus 4.

  The ultrasonic transmission part 11 and the light irradiation part 12 do not necessarily have to have both. When the ultrasonic acquisition apparatus according to the present invention is used exclusively for ultrasonic image generation, only the ultrasonic transmission unit 11 may be provided. Alternatively, when the ultrasonic acquisition apparatus according to the present invention is exclusively used for photoacoustic image generation, only the light irradiation unit 12 may be provided.

FIG. 1B is a diagram showing a reception beam forming apparatus 4 and its peripheral circuits according to the first embodiment of the present invention. Here, a configuration in which phasing addition is performed in the 32ch reception beam shaping apparatus 4 is taken as an example.
The reception beam shaping apparatus 4 includes data memories 14-1 to 14-32, apodization multipliers 15-1 to 15-32, and an adder circuit 80. The data memory 14 and the multiplier 15 respectively correspond to a plurality of AD converters 3 corresponding to each element (that is, respectively correspond to a plurality of receiving elements of the probe).
In the receiving beam shaping device 4, the phasing addition is not necessarily performed. The data stored in the data memories 14-1 to 14-32 may be directly processed by the host CPU as it is to generate image data. That is, an image reconstruction method (such as back projection in the Fourier domain or an iterative method (iterative method) that performs iterative processing) other than phasing addition may be used.

  The digital electrical signal digitized by the AD converter 3 is first taken into the data memory 14. The data memory control circuit 8 supplies the data memory 14 with a data memory address in which the received digital electrical signal derived from the target pixel or the target voxel is stored based on the target pixel or target voxel coordinates in the subject region. The received digital electrical signal derived from the target pixel or target voxel in the subject region is read from the data memory 14 according to the data memory address output by the data memory control circuit 8 and output to the multiplier 15 in the reception beam shaping device 4. Is done.

  The read control block 19 and the delay table 20 are components of the data memory control circuit 8. The delay table 20 stores delay information supplied from the control CPU 10. The read control block 19 calculates a data memory address based on the delay information stored in the delay table 20 and supplies it to each data memory 14.

Data write / read control in the data memory 14 will be described in detail.
FIG. 1C shows an example of the positional relationship between the target pixel or target voxel 31 in the subject region to be targeted, the receiving element array 30, and the receiving element 32 in the array. The distance D between the target pixel or voxel 31 and the receiving element 32 is the coordinate (X1, Y1, Z1) of the target pixel or voxel 31 and the coordinates (X2, Y2, Z2) of the receiving element 32 under a certain coordinate system. ) Is immediately obtained by the three-square theorem.

Also, the acoustic wave arrival time from the target pixel or target voxel 31 to the receiving element 32 in the array is calculated by dividing the distance D between the target pixel or target voxel 31 and the receiving element 32 in the array by the speed of sound. Is done.
While receiving a photoacoustic wave or an ultrasonic wave from within the target subject region, the data memory 14 sequentially applies a digital electric signal derived from the photoacoustic wave or the ultrasonic wave to each memory address in time series, and to a certain constant. Remember according to the rules.

  In this way, the relationship between the acoustic wave arrival time from the target pixel or target voxel 31 to the receiving element 32 in the array and the rules for storing the digital electric signal in the data memory 14 becomes clear. Therefore, the data memory address in which the digital electric signal derived from the target pixel or the target voxel having this relationship is stored can be specified. In the present invention, the data memory control circuit 8 supplies the data memory address to the data memory 14. Then, the data memory 14 outputs a digital electric signal derived from the target pixel or the target voxel 31 to the multiplier 15 in accordance with the data memory address given from the data memory control circuit 8.

  The weighting coefficient supply circuit 9 supplies the multiplier 15 with a window function weighting coefficient optimum for the target pixel or target voxel based on the target pixel or target voxel coordinates in the subject region. The received digital signal output from the data memory 14 to the multiplier 15 is multiplied by the window function weighting coefficient calculated by the weighting coefficient supply circuit 9 for each channel for apodization, and is output to the adding circuit 80. Thus, the phasing addition for 32ch is finally completed.

  2A and 2B are diagrams showing an operation sequence of the AD converter 3 and the reception beam shaping device 4 in the photoacoustic and ultrasonic apparatus 1 according to the first to second embodiments of the present invention.

The AD converter 3 samples the analog electric signal at the frequency of the reference clock signal (for example, 50 MHz) and outputs a digital electric signal having a plurality of bits. However, if data having a plurality of bit widths is transferred in parallel to the reception beam shaping device 4, the wiring between the AD converter 3 and the reception beam shaping device 4 increases. Therefore, data with a certain bit width is parallel-
A type of AD that serially converts and outputs serial data to a single data line
Many converters are used in recent years. The AD converter 3 in the photoacoustic and ultrasonic apparatus 1 of the present invention is assumed to be of the type that performs parallel-serial conversion on data having a certain bit width and transfers the data to the reception beam shaping apparatus 4 as serial data. Yes.

FIG. 2A is a diagram illustrating an example of an ideal operation state of the AD converter 3 and the reception beam shaping device 4 according to the present invention.
The AD converter 3 outputs serial data and a frame clock signal generated from the reference clock signal. The receiving beam shaping device 4 is 12 for one cycle of the frame clock signal.
Serial data is converted to serial data, and sampling data (parallel data) having a 12-bit width is obtained. In addition, the reception beam shaping device 4 generates a data memory write clock having the same frequency as the frame clock signal based on the frame clock signal. The data memory in the reception beam shaping device 4 stores 12-bit width sampling data for each rising edge of the data memory write clock.

Data write start timing to the data memory is determined by a data memory write enable generated in synchronization with a reference clock signal used inside the reception beam shaping device 4.
In the example in FIG. 2A, data is written to the data memory with the data 1 after parallel conversion as the head.

  FIG. 2B is a diagram illustrating an example of a non-ideal operation state of the AD converter 3 and the reception beam shaping device 4 according to the present invention.

  The frame clock signal output from the AD converter 3 is not synchronized with the reference clock signal used inside the reception beam shaping device 4. Therefore, the phase relationship with the reference clock signal may be shifted due to the influence of the wiring length from the AD converter 3 to the reception beam shaping device 4, the ambient temperature, and the like. As a result, the phase relationship between the data memory write enable generated based on the reference clock signal and the data memory write clock generated based on the frame clock signal may also shift.

When the phase relationship between the data memory write enable and the data memory write clock is as shown in FIG. 2B, data is written into the data memory with the data 0 after parallel conversion as the head. However, the receiving beam shaping device 4 performs phased addition for photoacoustic image reconstruction and ultrasonic image data generation on the premise that data is written to the data memory with the data 1 after parallel conversion as the head. Done.

  Therefore, in the operation state as shown in FIG. 2B, image data is generated based on data with shifted data acquisition timing, and there is a concern that the image quality of the photoacoustic image or ultrasonic image may be deteriorated. Therefore, it is necessary to detect and correct such a data capture timing shift.

FIG. 3A is a diagram showing a configuration of a data capture timing shift detection circuit according to the first embodiment of the present invention.
The data capture timing shift detection circuit is composed of a dummy data memory 33, a counter 31, and a determination circuit 34.

  The dummy data memory 33 and the data memory 32 used inside the reception beam shaping device 4 share the data memory write enable and the data memory write clock. The counter value of the counter 31 is input to the dummy data memory 33 as write data at a predetermined cycle. The determination circuit 34 reads the data in the dummy data memory 33 and detects a shift in data capture timing.

  FIG. 3B shows the operation of the data capture timing shift detection circuit at an ideal data capture timing.

  In the reception beam shaping device 4, the counter enable is raised one clock before the data memory write enable rises based on the reference clock signal. This makes it possible to start counting. That is, the reference clock signal starts counting before the data memory 32 starts storing parallel data. The counter 31 increments the count value by 1 for each rising edge of the reference clock signal after the rising edge of the counter enable. That is, the count value is increased by one. As the reference clock signal, a reference clock signal multiplied (multiple times) is used.

In the dummy data memory, the counter value is stored while the write address is incremented by 1 at each rising edge of the data memory write clock. In the example of FIG. 3B, the counter value 7 is written to the address 0 of the dummy data memory, the counter value 11 is written to the address 1, and the counter value 15 is written to the address 2.

  Next, FIG. 3C shows the operation of the data capture timing shift detection circuit when a non-ideal data capture timing, that is, a data capture timing shift occurs.

  In this case, the data memory write clock rises immediately after the rise of the data memory write enable. Therefore, the counter value 4 is written to address 0 of the dummy data memory, the counter value 8 is written to address 1, and the counter value 12 is written to address 2.

  Next, FIG. 3D shows a data content difference in the dummy data memory 33 between an ideal operation situation (in the case of FIG. 3B) and a situation in which a data capture timing shift occurs (in the case of FIG. 3C).

In the operation situation in which the data capture timing shift does not occur as shown in FIG. 3B, 7 is written in address 0, 11 is written in address 1, and 15 is written in address 2.
On the other hand, in the situation shown in FIG. 3C where the data capture timing has shifted, 4 is written to address 0, 8 is written to address 1, and 12 is written to address 2.

The determination circuit 34 reads data from the dummy data memory and determines a data capture timing shift. Specifically, the data capture timing deviation is determined by comparing whether or not the data in the dummy data memory is within a predetermined range. If the data in the dummy data memory is not within the predetermined range, it is determined that a shift has occurred. If it is determined that a data capture timing shift has occurred, the shift detection flag is set to H to notify the other circuit or the host CPU that the data capture timing shift has occurred.

  The counter value that can be determined that there is no deviation is obtained based on the serial data sampling number within one period of the frame clock signal, the data memory write and counter enable timing, and the reference clock signal period. it can. When determining the presence or absence of deviation, the determination circuit may store the counter value in advance or obtain it by calculation and compare it with the count value actually written in the dummy data memory.

  5A and 5B are diagrams showing the configuration of the data capture timing deviation correction means. The data fetch timing deviation correcting means is obtained by connecting an adder 52 to the data memory control circuits 8-1 to 8-T (represented by 51 in FIGS. 5A and 5B) described in FIG. 1A. The output of the data memory control circuit 51 is connected to the adder 52, and the output of the adder 52 is supplied as a read address of the data memory 32.

FIG. 5A is a diagram illustrating a case where a data capture timing shift is not detected. The input of the adder 52 is set to 0, and the output of the adder 52 is equivalent to the output of the data memory control circuit 51.
On the other hand, FIG. 5B is a diagram illustrating a case where a data capture timing shift is detected (the shift detection flag is H). When a data capture timing shift is detected, a correction value (1 in this case) is input to the other input of the adder 52, and the output of the adder 52 is the output of the data memory control circuit 51 corresponding to the data capture shift. It will be corrected. That is, by correcting the address read from the data memory, the data capture timing shift is corrected.

As described above, even when the sampling time for taking sampling data is shifted in the data memory 33, it is possible to read out desired data (address) from the data memory 33 and use it for image data generation.
Further, when data in the data memory 33 is transferred and image data generation processing is directly performed by the host CPU, the output of the data memory control circuit 51 need not be corrected. In that case, image data may be generated in consideration of the sampling data fetch timing shift in the data memory 33 by the host CPU.

  As described above, according to the first embodiment of the present invention, the sampling data capture timing shift due to the phase shift between the frame clock signal output from the AD converter 3 and the reference clock signal in the reception beam shaping device 4 is detected. Then, it becomes possible to correct.

<Second Embodiment>
FIG. 4A is a diagram showing a configuration of a data capture timing shift detection circuit according to the second embodiment of the present invention.
The data capture timing shift detection circuit is composed of a dummy data memory 43, a counter 41, and a determination circuit 44.

The dummy data memory 43 and the data memory 42 used in the reception beam shaping device 4 (data processing device) share the data memory write enable. The counter value of the counter 41 is input to the dummy data memory 43 as write data. A reference clock signal is input to the dummy data memory 43 as a write clock.
The reference clock signal is obtained by multiplying (multiple times) the reference clock signal. In FIG. 4A, as a reference clock signal, a 200 MHz clock obtained by multiplying a 50 MHz reference clock signal by 4 is shown as an example.

The counter 41 shares a data memory write clock with the data memory 42. The counter 41 shares the data memory write enable with the data memory 42 and the dummy data memory 43.
The determination circuit 44 reads the data in the dummy data memory 43 and detects a shift in data capture timing.

  FIG. 4B shows the operation of the data capture timing shift detection circuit at an ideal data capture timing.

The reception beam shaping device 4 activates the data memory write enable based on the reference clock signal. The counter 41 increments the count value by 1 for each rising edge of the data memory write clock after the rise of the data memory write enable. That is, at the same time as the data memory 42 starts storing parallel data, the counter 41 starts counting the data memory write clock. Then, the count value is increased by one for each rising edge of the data memory write clock.
The dummy data memory 43 stores the counter value while incrementing the write address for each rising edge of the reference clock signal. In the example of FIG. 4B, counter value 0 is set at addresses 0, 1, and 2 of the dummy data memory, and counter value 1 is set at addresses 3, 4, 5, and 6.
Counter value 2 is written to addresses 7, 8, 9, and 10.

  Next, FIG. 4C shows the operation of the data capture timing shift detection circuit when a non-ideal data capture timing, that is, a data capture timing shift occurs.

In this case, the data memory write clock rises immediately after the rise of the data memory write enable. Therefore, counter value 1 is written to addresses 0, 1, 2, and 3 of dummy data memory, counter value 2 is written to addresses 4, 5, 6, and 7, and counter value 3 is written to addresses 8, 9, 10, and 11, respectively. Go.

  Next, FIG. 4D shows a data content difference in the dummy data memory 43 between an ideal operation situation (in the case of FIG. 4B) and a situation in which a data capture timing shift occurs (in the case of FIG. 4C).

As shown in FIG. 4B, in the operation situation in which the data capture timing is not shifted, 0 is written to addresses 0, 1, and 2, 1 is written to addresses 3, 4, 5, and 6, and 2 is written to addresses 7 and 8. ing.
On the other hand, in the situation shown in FIG. 4C where the data capture timing has shifted, 1 is written to addresses 0, 1, 2, and 3, 2 is written to addresses 4, 5, 6, and 7, and 3 is written to address 8. .

The determination circuit 44 reads the data in the dummy data memory and determines a data capture timing shift. If it is determined that a data capture timing shift has occurred, the shift detection flag is set to H to notify the other circuit or the host CPU that the data capture timing shift has occurred.
The judgment circuit compares the counter value in the normal (no deviation) value obtained from the cycle of the reference clock signal (multiplier), the data memory write enable timing, and the frame clock signal cycle with the value of the dummy data memory. The determination can be made.

  The configuration and correction method of the data capture timing deviation correction unit are the same as those in the first embodiment of the present invention, and thus will not be described in detail.

  As described above, according to the second embodiment of the present invention, the sampling data capturing timing shift caused by the shift in the phase relationship between the frame clock signal output from the AD converter 3 and the reference clock signal in the reception beam shaping device 4 is obtained. Can be detected and corrected.

  In the above description, the data memory corresponds to the first memory of the present invention. The dummy data memory corresponds to the second memory of the present invention. The target pixel or target voxel corresponds to the target area of the present invention.

  As mentioned above, although preferred embodiment of this invention was described, embodiment mentioned above is only a mere illustration in all the points, and does not limit the scope of the present invention.

1: photoacoustic and ultrasonic device, 2: probe, 3: AD converter, 4: reception beam shaping device, 5: signal processing unit, 6: image processing unit, 11: ultrasonic transmission unit, 12: light Irradiation part

Claims (6)

A plurality of receiving elements that receive acoustic waves propagated through the subject and convert them into analog electrical signals;
An analog-to-digital converter that samples the analog electrical signal for each reference clock signal, converts the analog electrical signal into a digital electrical signal as serial data, and outputs the serial data together with a frame clock signal;
A data processing device that receives the frame clock signal and the serial data from the AD converter and converts the serial data into parallel data;
An acoustic wave acquisition device that generates image data using output data from the data processing device,
The data processing device includes:
A plurality of first memories for storing the parallel data corresponding to each of the plurality of receiving elements for each write clock signal having the same frequency as the frame clock signal;
Count means for starting counting of a reference clock signal having a frequency multiple of the reference clock signal before the first memory starts storing the parallel data;
A second memory for storing the count value of the counting means for each write clock signal;
A determination unit that compares the value stored in the second memory to determine whether or not the predetermined value is within a predetermined range;
An acoustic wave acquisition apparatus comprising: A plurality of receiving elements that receive acoustic waves propagated through the subject and convert them into analog electrical signals;
An analog-to-digital converter that samples the analog electrical signal for each reference clock signal, converts the analog electrical signal into a digital electrical signal as serial data, and outputs the serial data together with a frame clock signal;
A data processing device that receives the frame clock signal and the serial data from the AD converter and converts the serial data into parallel data;
An acoustic wave acquisition device that generates image data using output data from the data processing device,
The data processing device includes:
A plurality of first memories for storing the parallel data corresponding to each of the plurality of receiving elements for each write clock signal having the same frequency as the frame clock signal;
Counting means for starting counting of the write clock signal at the same time as the first memory starts storing the parallel data;
A second memory for storing the count value of the counting means for each reference clock signal having a frequency multiple of the reference clock signal;
A determination unit that compares the value stored in the second memory to determine whether or not the predetermined value is within a predetermined range;
An acoustic wave acquisition apparatus comprising:   When the determination unit determines that the value stored in the second memory is not within the predetermined range, the read address from the plurality of first memories is corrected so as to correct the timing shift. The acoustic wave acquisition apparatus according to claim 1, further comprising a correction unit.   2. The image data is generated so as to correct the timing shift when the determination unit determines that a value stored in the second memory is not within the predetermined range. Or the acoustic wave acquisition apparatus of 2. The acoustic wave acquisition apparatus according to claim 1, wherein the acoustic wave propagated through the subject is an acoustic wave generated from the subject irradiated with light. The acoustic wave acquisition apparatus according to any one of claims 1 to 4, wherein the acoustic wave propagated through the subject is a reflection of the acoustic wave transmitted to the subject.

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