JP2005346674A - System, circuit, and method for parallelly processing real-time signal using open structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain synchronization of a whole system by providing a system for parallelly processing a real-time signal using an open structure. <P>SOLUTION: The system for parallelly processing the real-time signal using the open structure is provided with a host computer 120, a circuit 100 for parallelly processing the real-time signal by use of the open structure, a plurality of peripheral devices 130, and an analog signal processor 140. The host computer 120 controls the peripheral devices 130 and the analog signal processor 140 via the circuit. The circuit processes a plurality of digital echo unprocessed data generated by the analog signal processor 140 in association with the parallel signal processing to prepare report information for reporting to the host computer 120. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to circuits, systems, and methods for processing real-time signals, and more particularly to circuits, systems, and methods for processing real-time signals in parallel using an open structure.

  Recently, parallel processing structures are commonly used in real-time digital signal processing, thanks to significant advances in semiconductor technology and the improved and widespread functionality provided by digital signal processing (DSP) components. Real-time digital signal processing is unavoidable for military use. For example, a radar signal processing device is one of the most important devices in military use.

  Conventional real-time signal processing techniques are embodied in either a hardware structure or a software structure. However, both implementations are disadvantageous. When real-time signals are processed using hardware structures, the processing is accelerated and operations are operated simultaneously, but it is necessary to design different hardware circuits to handle different system specifications. If the real-time signal is processed using a software structure, it offers scalability beyond the hardware structure, but it is difficult to achieve the requirements for real-time processing. In addition, software processors are mostly asynchronous systems, which are difficult to synchronize with all real-time signal processing systems.

  In real-time signal processing applications, the built-in multicomputer is useful for realizing real-time requirements and can achieve programmable requirements. A parallel algorithm executed on the built-in multicomputer is implemented in the present invention. In signal processing, association and convolution processing is usually performed with a very large data size. The execution time of these two processes is reduced using multiple DSP processors together with the coprocessor of the present invention.

  In view of the above, it is an object of the present invention to provide a system for parallel processing real-time signals using an open structure to achieve overall system synchronization.

  Another object of the present invention is to provide a circuit for processing real-time signals in parallel using an open structure, and the circuit provided by the present invention is extendable.

  A further object of the present invention is to provide a method for parallel processing real-time signals using an open structure to achieve real-time processing requirements.

  An object of the present invention is to provide a system for processing real-time signals in parallel using an open structure.

  The system comprises a host interface unit that is used to connect the real-time signal processing system of the present invention to a host computer via several computer networks. The host interface unit changes control commands from the host computer to the real-time signal processing system and returns processing reports from the real-time signal processing system to the host computer. In addition, the real-time signal processing system of the present invention further comprises an interface control processor, an analog signal control processor, and a digital signal scheduling control processor. An interface control processor, which is a module of the general-purpose CPU or DSP chip processor type, is connected to the host interface unit and is used to control peripheral devices in accordance with control commands generated by the host interface unit. An analog signal control processor, which is a module of the general purpose CPU or DSP chip processor type, is connected to the interface control processor and is used to control an external analog signal processing system according to control commands provided by the interface control processor. The In addition, the digital signal scheduling control processor is connected to the interface control processor and is used to provide a plurality of scheduling control commands according to the control commands provided by the interface control processor. Moreover, the present invention further comprises digital signal processing equipment used to receive the digital echo raw data and to process the digital echo raw data in accordance with scheduling control commands.

  Preferably, the present invention further comprises a self-test control processor, which is a module of the type of a general purpose CPU or DSP chip processor and executes self-test instructions provided by the host interface unit. Used to generate self-test results and send them to the host interface unit.

  In one aspect of the invention, the digital signal processing equipment comprises a data injection module and an input data buffer module. The data injection module is used to receive digital echo raw data and to convert digital echo raw data from a different type to a TTL type. The input data buffer module is connected to the data injection module for storing digital echo raw data and provides a pre-process of the digital echo raw data. In addition, the digital signal processing equipment further comprises a plurality of vector signal processors, the vector signal processors being modules of the general-purpose CPU or DSP chip processor type, and an input data buffer for processing digital echo raw data in parallel Connected to the module.

  In accordance with another aspect of the present invention, the present invention provides a circuit for parallel processing real-time signals using an open structure. The circuit of the present invention includes a local bus and a host interface module. The host interface module is connected to the local bus and generates a control command and sends it to the local bus in accordance with system synchronization signals and instructions from the host computer. In addition, the present invention further includes an I / O buffer control module, an analog signal processing control module, and a digital signal scheduling control module. The I / O buffer control module generates a control command for controlling the peripheral device according to the control command generated by the host interface module. The analog signal processing control module generates a control command for controlling the analog signal processing system according to the control command provided by the I / O buffer control module. In addition, the digital signal scheduling control module generates a scheduling control command and provides it to the local bus according to the control command provided by the I / O buffer control module. Moreover, the present invention further comprises a digital signal processing device including a data eject module, an input data buffer module, and a plurality of vector signal processors, which are also connected to a local bus. The digital signal processing device receives the digital echo raw data, reads the scheduling control command via the local bus, and processes the received digital echo raw data.

  In accordance with another aspect of the present invention, the present invention provides a method for parallel processing real-time signals using an open structure, the method being applied in a real-time parallel signal processing system having a host computer. Is appropriate. The method for parallel processing real-time signals provided by the present invention includes the following steps. Initially, a system synchronization signal is generated and the I / O buffer main program is executed in accordance with the system synchronization signal and instructions from the host computer. The I / O buffer main program provides a plurality of system control instructions generated by the host computer to the analog signal processing function and the digital signal processing function. Next, the analog signal processing main program and the digital signal processing main program are executed according to the system synchronization signal. Finally, a vector signal processing main program is executed to process the digital echo raw data, a report result record is generated and provided to the host computer according to the control commands provided by the digital signal processing main program.

  In summary, the present invention provides a plurality of vector signal processors that are used to process a plurality of real-time signal records in parallel so that synchronization of the entire system is achieved. In addition, the digital signal scheduling control processor can adjust the order of the processed signals according to the returned digital echo raw data so that real-time requirements are met. Furthermore, the present invention is also highly expandable because the present invention can adjust the number of modules based on actual requirements.

  The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description of the specification, are used to explain the principles of the invention.

  FIG. 1A is a functional block diagram illustrating a system for processing real-time signals in parallel using an open structure according to a preferred embodiment of the present invention. Referring to FIG. 1A, a real-time parallel signal processing circuit 100 having an open structure is provided by the present invention. The host interface unit 102 is connected to the host computer 120 via a computer network, such as Ethernet, and its output is communicated to an interface control processor 104, which is a general purpose CPU or DSP chip processor type module. The interface control processor 104 controls several peripheral devices 130 of the real-time signal processing circuit 100, and its output is an analog signal control processor 106, which is a module of the type of general purpose CPU or DSP chip processor, and digital signal scheduling. Each is connected to a control processor. The analog signal control processor 106 controls an analog signal processing system 140, such as a radar, sonar, medical ultrasound, or wireless communication system. The present invention is further used to receive the digital echo raw data returned by the analog signal processing system 140 and to process the digital echo raw data in accordance with control commands provided by the digital signal scheduling processor 108. Digital signal processing equipment 110 is provided.

  Returning again to FIG. 1A, the digital signal processing equipment 110 is used to receive digital echo raw data returned by the analog signal processing system 140, for example, radar echo signals returned in real time in the radar system. The data injection module 112 is provided. Then, after the digital echo raw data passes through the data injection module 112, the digital echo raw data is stored in the input data buffer module 114. Next, the vector signal processor 116, which is a general-purpose CPU or DSP chip processor type module, reads digital echo raw data from the input data buffer module 114 and performs parallel signal processing thereon. The parallel signal processing operation of the vector signal processor 116 is performed by software. In addition, in the present invention, the quantity of the interface control processor 104 and the vector signal processor 116 is adjustable, allowing a plurality of peripheral devices 130 to be controlled and a plurality of digital echo raw data at the same time depending on actual requirements. The recording is made processable.

  FIG. 1B is a functional block diagram illustrating a system for parallel processing real-time signals using an open structure according to another embodiment of the present invention. Referring to FIG. 1B, in an alternative embodiment of the present invention, the real-time signal processing circuit 100 of the present invention further comprises a self-test control processor 118. The self-test control processor 118 is a general-purpose CPU or DSP chip processor type module, and executes a self-test instruction generated by the host interface unit 102. The self-test control processor 118 generates a self-test result and sends it to the host computer 120. Is provided via the host interface unit 102.

  FIG. 2 is a block diagram of the detailed internal hardware structure showing the real-time signal processing circuit of FIG. 1B. Referring to FIG. 2, the host interface module 201 and the interface modules 203 and 205 constituting the host interface unit 102 are all connected to the local bus 21 together. In this embodiment, the local bus is, for example, a VME bus or a CPCI (Compact Peripheral Component Interconnection) bus. The host interface module 201 receives a system control command and a self-test command generated by the host computer 120 every system operation cycle. After receiving the system synchronization signal and command from the host computer 120, the host interface module 201 communicates the system control command to the interface module 213 via the interface module 215, and the self test command to the interface module 253 via the interface module 205. Tell.

  The I / O buffer control module 211, the interface module 213, and the real-time timing control module 215 constituting the interface control processor 104 are all connected to the local bus 21 together. After receiving the system synchronization signal, the I / O buffer control module 211 receives a system control command from the interface module 213 and controls the peripheral device 130, the analog signal processing system 140, and the digital signal processing equipment 110. Is generated. The control command is then provided to the interface modules 223 and 243. In addition, the self-test module 251 and the interface module 253 constituting the self-test control processor 118 are both connected to the local bus 21 together. After receiving the system synchronization signal, the self test module 251 receives and executes the self test command received from the interface module 253. After execution of the self test instruction is terminated by the self test module 251, a self test result is generated and returned to the host interface module 201 via the interface module 253.

  Both the analog signal processing control module 221 and the interface module 223 constituting the analog signal control processor 106 are jointly connected to the local bus. After receiving the system synchronization signal, the analog signal processing control module 221 receives a control command from the interface module 223 and sets the analog signal processing system 140 according to the control command. In addition, the digital signal processing control module 241 and the interface module 243 constituting the digital signal scheduling control processor 108 are both connected to the local bus 21 together. After receiving the control command provided by the I / O buffer control module 211 from the interface module 243, the digital signal processing control module 241 generates a plurality of scheduling control commands to generate a data input buffer module 233 and a plurality of vector signal processors. 235 is set.

  The data injection module 231, the data input buffer module 233, and the plurality of vector signal processors 235 that constitute the digital signal processing device 110 are all connected to the local bus 21 together. After the data input buffer module 233 receives the activation signal, the data injection module 231 receives the digital echo raw data from the analog signal processing system 140. The data input buffer module 233 then performs a pre-process on the digital echo raw data, which includes various frequency sampling processes, coefficient processing with a digital filter, and other noise removal processes. Thereafter, the raw digital echo data is provided to the vector signal processor 235, which performs a plurality of parallel signal processing operations on the respective digital echo raw data records. After each digital echo raw data is processed, report information is generated and provided to the local bus 21. Meanwhile, the vector signal processing module 235 informs the digital signal processing control module 241, and then the digital signal processing control module 241 provides report information to the host interface module 201 via the interface module 243, and finally, the host interface module 201 Provides the report information to the host computer 120.

  FIG. 3 is a flowchart illustrating a method for parallel processing real-time signals using an open structure according to a preferred embodiment of the present invention. Referring to FIG. 3, the real-time signal processing method disclosed in the present invention may be applied on a real-time parallel signal processing system having a host computer, for example, on the hardware structure described above. Initially, a system synchronization command is generated after system power up in step S310. Then, the I / O buffer main program is started in step S320, and both the digital signal processing main program and the analog signal processing main program are started in step S330. Finally, the vector signal processing main program is started in step S340.

  In an alternative embodiment, at the moment when the I / O buffer main program is activated, the real-time parallel signal processing system of the present invention also performs a self-test operation, and then displays the self-test result provided to the host computer. Generate.

  4A and 4B are flowcharts illustrating an I / O buffer main program according to a preferred embodiment of the present invention. Referring to FIGS. 4A and 4B, first, real-time timing control and peripheral devices are set according to a predetermined system control command in step S401. Then, an I / O buffer interrupt processing routine is started in step S403, and it is determined whether or not an analog signal processing synchronization message and a digital signal processing synchronization message have been received in step S405. When the I / O buffer main program receives an analog signal processing synchronization message and a digital signal processing synchronization message (that is, in the case of “Yes” in step S405), a step of starting real-time timing control S407 is executed. Thereafter, it is determined whether or not the interrupt signal generated by the real-time timing control is received in step S409. When the I / O buffer main program receives an interrupt signal generated by real-time timing control (that is, in the case of “Yes” in step S409), a step of starting an I / O buffer interrupt processing routine S411 is executed, and then steps S407 and S409 are repeated indefinitely.

  In this embodiment, the flow of the I / O buffer interrupt processing routine in step S411 is as follows. First, in step S412, the system control command generated by the host computer is read. Then, in step S413, the real-time timing control and peripheral devices are reset according to the system control command generated by the host computer. In step S414, the system control command generated by the host computer is provided to the analog signal processing main program and the digital signal processing main program. Finally, the interrupt processing routine is terminated in step S415, and the process returns to the I / O buffer main program.

  5A and 5B are flowcharts showing an analog signal processing main program according to a preferred embodiment of the present invention. Referring to FIGS. 5A and 5B, the analog signal processing main program is mainly used to set a plurality of parameter values for processing analog system control signals. First, parameters for controlling analog signal processing are set in accordance with a predetermined system control command in step S501. Then, an interrupt processing routine for analog signal processing is started in step S503, a synchronization message is generated, and sent to the I / O buffer main program in step S505. Thereafter, it is determined whether or not an interrupt signal generated by real-time timing control has been received in step S507. When the analog signal processing main program receives the interrupt signal generated by the real-time timing control (that is, in the case of “Yes” in step S507), the analog signal processing interrupt processing routine is activated in step S509. Then, step S507 is repeated indefinitely.

  The analog signal processing interrupt processing routine described above is required to set up all the signals required by the hardware that processes the analog signals and to synchronize the analog signal processing to the system. Mainly used to set timing. In this embodiment, the flow of the analog signal processing interrupt processing routine in step S509 is as follows. First, in step S510, the system control command generated by the I / O buffer main program is read. Then, in step S511, parameters for controlling analog signal processing are set according to the system control command generated by the I / O buffer main program. Finally, in step S512, the interrupt processing routine is terminated and the process returns to the analog signal processing main program.

  6A and 6B are flowcharts showing a digital signal processing main program according to a preferred embodiment of the present invention. Referring to FIGS. 6A and 6B, the digital signal processing main program is mainly used to set initial values required by hardware processing digital signals, and the flow thereof will be described later. First, the preprocess of the digital echo raw data is set in accordance with a predetermined system control command in step S601. Then, in step S603, both the digital signal processing interrupt processing routine and the vector signal processing interrupt processing routine are activated to generate a digital signal processing synchronization message. In step S605, the I / O buffer main program is executed. Sent. On the other hand, it is determined whether an interrupt signal generated by real-time timing control or an interrupt signal generated by vector signal processing has been received in step S607. When an interrupt signal generated by real-time timing control is received, step S609 for starting an interrupt processing routine for digital signal processing is executed, and thereafter step S607 is repeated infinitely. When an interrupt signal generated by vector signal processing is received, step S611 for starting the interrupt processing routine of vector signal processing is executed, and then step S607 is repeated infinitely.

  In this embodiment, the flow of an interrupt processing routine for digital signal processing in step S609 is as follows. First, in step S611, the control command generated by the I / O buffer main program is read. Then, an appropriate vector signal processor is scheduled and selected, and in step S612, vector signal processing is started according to the control command generated by the I / O buffer main program. In step S613, the previous process of the digital echo raw data is reset. To do. Finally, in step S614, the interrupt processing routine is terminated and the process returns to the digital signal processing main program. The flow of the interrupt processing routine for vector signal processing consists of reading and recording interrupt information generated by vector signal processing.

  FIG. 7 is a flowchart showing a vector signal processing main program according to a preferred embodiment of the present invention. Referring to FIG. 7, the vector signal processing main program includes a large number of n vector signal processes (n is a positive integer), and each of these vector signal processes is started according to the digital signal processing main program. In this embodiment, the vector signal processing main program has two large portions, the first portion performs the first vector signal processing, and the second portion performs the second to n-th vector signal processing. Execute.

  When the vector signal processing main program is executing the first vector signal processing, an instruction from the digital signal processing main program is read in step S701, and then initialization is executed in step S703. When the digital echo raw data is provided, the digital echo raw data is read in step S705, a permission signal is generated, and provided to the second vector signal processing after the digital echo raw data is read. Then, parallel signal processing is performed on the digital echo raw data in step S707. After the digital echo raw report data is processed, the results generated by the parallel signal processing are summarized in step S709, and the results generated by the other parallel signal processing are summarized in step S711. Finally, a report result is generated, and the process returns to the digital signal processing main program in step S713.

  Similarly, when the vector signal processing main program is executing the m-th vector signal processing (m is a positive integer larger than 1 and smaller than n), similarly, an instruction generated by the digital signal processing main program is issued in step S721. Then, the initialization operation is performed in step S723. Then it waits for the permission signal generated by the previous vector signal processing in step S725. After receiving the permission signal generated by the previous vector signal processing, digital echo raw data is read in step S727, after which the permission signal is generated and provided to the next vector signal processing. After completion of reading the digital echo unprocessed data, parallel signal processing is executed in step S729, and the results generated by the m-th parallel signal processing are summarized in step S731. Finally, in step S733, the summarized result is provided to the first vector signal processing for performing step S711.

  Although the invention has been described with reference to specific embodiments thereof, it will be apparent to those skilled in the art that modifications may be made to the embodiments described above without departing from the spirit of the invention. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description.

1 is a functional block diagram illustrating a system for parallel processing real-time signals using an open structure according to a preferred embodiment of the present invention. It is a functional block diagram which shows the system which processes a real-time signal in parallel using the open structure by other embodiment of this invention. 1B is a block diagram of a detailed internal hardware structure showing the real-time signal processing circuit of FIG. 1B. FIG. 5 is a flowchart illustrating a method for parallel processing real-time signals using an open structure according to a preferred embodiment of the present invention. It is a flowchart which shows the I / O buffer main program by preferable embodiment of this invention. It is a flowchart which shows the I / O buffer main program by preferable embodiment of this invention. It is a flowchart which shows the analog signal processing main program by preferable embodiment of this invention. It is a flowchart which shows the analog signal processing main program by preferable embodiment of this invention. It is a flowchart which shows the digital signal processing main program by preferable embodiment of this invention. It is a flowchart which shows the digital signal processing main program by preferable embodiment of this invention. It is a flowchart which shows the vector signal processing main program by preferable embodiment of this invention.

Explanation of symbols

100 real-time parallel signal processing circuit 102 host interface unit 104 interface control processor 106 analog signal control processor 108 digital signal scheduling control processor 110 digital signal processing equipment 112 data injection module 114 input data buffer module 116 vector signal processor 120 host computer 130 peripheral device 140 Analog signal processing system

Claims (24)

A system that processes real-time signals in parallel using an open structure,
A host interface unit for connecting a real-time signal processing system and a host computer via a computer network and generating a plurality of control commands according to the host computer;
A general-purpose CPU or DSP chip processor type module connected to the host interface unit to control a plurality of peripheral devices according to the control command provided by the host interface unit;
A general-purpose CPU or DSP chip processor type module connected to the interface control processor to control the analog signal processing system in accordance with the control command provided by the interface control processor; and
A module of the type of a general purpose CPU or DSP chip processor, and a digital signal scheduling control processor connected to the interface control processor to provide a plurality of scheduling control commands according to the control command provided by the interface control processor; ,
Using an open structure comprising: digital signal processing equipment receiving digital echo raw data and processing the digital echo raw data in accordance with the scheduling control command provided by the digital signal scheduling control processor A system that processes real-time signals in parallel. In the system which processes a real-time signal in parallel using the open structure of Claim 1,
A module of the type of a general purpose CPU or DSP chip processor, further comprising a self-test control processor for executing a self-test instruction provided by the host interface unit, generating a self-test result and providing it to the host interface unit A system for parallel processing real-time signals using an open structure characterized by having In the system which processes a real-time signal in parallel using the open structure of Claim 1,
A data injection module for receiving the digital echo raw data and converting the digital echo raw data from a different type to a TTL type;
An input data buffer module connected to the data injection module for storing the digital echo raw data and performing a pre-process on the digital echo raw data;
A number of general purpose CPU or DSP chip processor type modules, comprising a plurality of vector signal processors connected to the input data buffer module for parallel processing of the digital echo raw data A system that processes real-time signals in parallel using an open structure. In the system which processes a real-time signal in parallel using the open structure of Claim 3,
A system for parallel processing real-time signals using an open structure, wherein the function of parallel processing the digital echo raw data is executed by the vector signal processor by software. In the system which processes a real-time signal in parallel using the open structure of Claim 1,
A system for processing real-time signals in parallel using an open structure, wherein the computer network is one of Ethernet and Fast Ethernet. A circuit that processes real-time signals in parallel using an open structure,
A local bus,
A host interface module connected to the local bus to generate a plurality of control commands and provide them to the local bus according to a system synchronization signal;
An I / O buffer control module connected to the local bus for generating the control command for controlling a plurality of peripheral devices according to the control command provided by the host interface module;
An analog signal processing control module for generating the control command for controlling the analog signal processing system according to the control command provided by the I / O buffer control module;
A digital control connected to the local bus for generating a scheduling control command for controlling the digital signal processing equipment and providing it to the local bus according to the control command generated by the I / O buffer control command A signal processing control module;
Receiving digital echo raw data and processing the digital echo raw data by reading the control command provided by the digital signal processing control module via the local bus. A circuit that processes real-time signals in parallel using a characteristic open structure. A circuit for processing real-time signals in parallel using the open structure according to claim 6,
A self-test module that executes a self-test instruction provided by the host interface module via the local bus, generates a self-test result and provides it to the host interface module via the local bus; A circuit that processes real-time signals in parallel using a characteristic open structure. A circuit for processing real-time signals in parallel using the open structure according to claim 7,
A circuit for parallel processing real-time signals using an open structure in which the host interface module reads the self-test result from the local bus. A circuit for processing real-time signals in parallel using the open structure according to claim 6,
A data injection module connected to the local bus for receiving the digital echo raw data and converting the digital echo raw data from a different type to a TTL type;
An input data buffer module connected to the local bus to perform a pre-process on the digital echo raw data according to the control command provided by the digital signal processing control module;
Parallel real-time signals using an open structure having a plurality of vector signal processors connected to the local bus for parallel processing the digital echo raw data provided by the input data buffer module The circuit to process. A circuit for processing real-time signals in parallel using the open structure according to claim 9,
The circuit for parallel processing real-time signals using an open structure, wherein the data injection module further comprises a flash memory for storing the digital echo raw data. A circuit for processing real-time signals in parallel using the open structure according to claim 6,
Further comprising a real-time timing control module for generating the digital echo raw data by providing a plurality of timing control signals that control the synchronization of the entire system, the peripheral device, the circuit, and the analog signal processing system A circuit that processes real-time signals in parallel using an open structure characterized by A circuit for processing real-time signals in parallel using the open structure according to claim 6,
A plurality of interface modules;
An open structure in which the interface module is connected to the local bus used as an I / O interface between a real-time signal processing circuit outside the module and a real-time signal processing circuit between the modules A circuit that processes real-time signals in parallel. A circuit for processing real-time signals in parallel using the open structure according to claim 6,
A circuit for processing real-time signals in parallel using an open structure, wherein the local bus is either a VME bus or a CPCI (Compact Peripheral Component Interconnection) bus. A method for parallel processing real-time signals using an open structure suitable for a real-time parallel signal processing system equipped with a host computer,
Generate a system synchronization signal,
An I / O buffer main program that provides a plurality of control commands generated by the host computer to an analog signal processing function and a digital signal processing function in accordance with the system synchronization signal and command from the host computer is executed. ,
Executing an analog signal processing main program and a digital signal processing main program according to the system synchronization signal and the control command provided by the I / O buffer main program;
Execute parallel signal processing with unprocessed digital echo data, generate a report result, and execute a vector signal processing main program provided to the host computer in accordance with the control command generated by the digital signal processing main program A method for parallel processing of real-time signals using an open structure characterized by: A method for parallel processing real time signals using the open structure of claim 14, comprising:
At the moment when the I / O buffer main program is started, the real-time parallel signal processing system executes a self-test operation, generates a self-test result, and provides it to the real-time parallel signal processing system. A method of parallel processing real-time signals using an open structure. A method for parallel processing real-time signals using the open structure of claim 14, comprising:
The step of executing the I / O buffer main program sets real-time timing control and peripheral devices of the real-time parallel signal processing system according to a plurality of predetermined system control instructions.
Start the I / O buffer interrupt processing routine,
Determining whether a synchronization message generated by one of the function of the analog signal processing main program and the function of the digital signal processing main program is received;
Activate the real-time timing control,
Determining whether an interrupt signal generated by the real-time timing control is received;
A method for parallel processing real-time signals using an open structure, wherein the I / O buffer interrupt processing routine is activated when the interrupt signal generated by the real-time timing control is received. A method for parallel processing real-time signals using the open structure of claim 16,
The step of executing the I / O buffer interrupt processing routine reads a system control command generated by the host computer,
Reconfiguring the real-time timing control and peripheral devices of the real-time parallel signal processing system according to the system control command generated by the host computer;
A method of parallel processing real-time signals using an open structure, wherein the system control command generated by the host computer is provided to the analog signal processing function and the digital signal processing function. A method for parallel processing real-time signals using the open structure of claim 14,
The step of executing the analog signal processing main program sets a plurality of parameters for controlling the analog signal processing according to a predetermined system control instruction,
Start analog signal processing interrupt processing routine
Generating a synchronization message for the I / O buffer main program;
Determining whether an interrupt signal generated by the real-time timing control is received;
A method for parallel processing real-time signals using an open structure, wherein the analog signal processing interrupt processing routine is activated when the interrupt signal generated by the real-time timing control is received. A method for parallel processing real-time signals using the open structure of claim 18,
The step of executing the analog signal processing interrupt processing routine reads a control command generated by the I / O buffer main program,
A method for parallel processing real-time signals using an open structure, wherein a parameter for controlling the function of the analog signal processing is set according to the control command generated by the I / O buffer main program. A method for parallel processing real-time signals using the open structure of claim 14,
The step of executing the digital signal processing main program sets a pre-process of the digital echo unprocessed data according to a predetermined system control instruction,
Start the digital signal processing interrupt processing routine and vector signal processing interrupt processing routine,
Generating the synchronization message for the I / O buffer main program;
Determining which one of the interrupt signal generated by the real-time timing control or the interrupt signal generated by the function of the vector signal processing is received;
When the interrupt signal generated by the real-time timing control is received, the digital signal processing interrupt processing routine is started,
A method for parallel processing real-time signals using an open structure, wherein an interrupt processing routine of the vector signal processing is activated when the interrupt signal generated by the vector signal processing function is received. A method for parallel processing real-time signals using the open structure of claim 20,
The step of executing the digital signal processing interrupt processing routine reads the control command generated by the I / O buffer main program,
Set and activate the vector signal processing function according to the control command generated by the I / O buffer main program,
A method of parallel processing real-time signals using an open structure, wherein a pre-process of the digital echo raw data is reset. A method for parallel processing real-time signals using the open structure of claim 21,
The step of executing the vector signal processing interrupt processing routine reads and records the interrupt information provided by the vector signal processing;
A method of parallel processing real-time signals using an open structure, wherein the interrupt information is sent to the host computer. A method for parallel processing real-time signals using the open structure of claim 16,
The vector signal processing main program is started according to the digital signal processing main program,
The vector signal processing main program starts a large number of n (n is a positive integer) vector signal processing,
Performing the first vector signal processing reads a control command provided by the digital signal processing function;
Perform initialization,
Read the digital echo raw data, generate a permission signal for the second vector signal processing,
Performing a first parallel signal processing;
Summarizing the results generated by the first parallel signal processing,
Summarize the results generated by other parallel signal processing,
A method for parallel processing real-time signals using an open structure, characterized in that it produces a result and provides it to the digital signal processing main program. A method for parallel processing real-time signals using the open structure of claim 23,
A step of executing m-th (m is a positive integer greater than 1 and less than n) vector signal processing reads an activation control command provided by the digital signal processing main program;
Perform initialization,
Waiting for the permission signal provided by the previous vector signal processing;
Reading the digital echo raw data when the previous vector signal processing sent the permission signal, and then providing the next vector signal processing to the permission signal;
Perform the mth parallel signal processing;
Summarizing results generated by the m-th parallel signal processing,
To summarize, a method for parallel processing real-time signals using an open structure, wherein the result generated by the m-th parallel signal processing is provided to a first vector signal processing.

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