TWI249853B - Thin film transistor array structure - Google Patents
Thin film transistor array structure Download PDFInfo
- Publication number
- TWI249853B TWI249853B TW92114349A TW92114349A TWI249853B TW I249853 B TWI249853 B TW I249853B TW 92114349 A TW92114349 A TW 92114349A TW 92114349 A TW92114349 A TW 92114349A TW I249853 B TWI249853 B TW I249853B
- Authority
- TW
- Taiwan
- Prior art keywords
- thin film
- film transistor
- layer
- transistor array
- array substrate
- Prior art date
Links
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
Description
1249853 _案號92114349_年月日_«_ 五、發明說明(1) 發明所屬之技術領域 本發明是有關於一種液晶顯示器結構,且特別是有關 於一種薄膜電晶體陣列基板結構(T F T a r r a y )。 先前技術 針對多媒體社會之急速進步,多半受惠於半導體元件 或人機顯示裝置的飛躍性進步。就顯示器而言,陰極射線 管(Cathode Ray Tube ,CRT)因具有優異的顯示品質與其 經濟性,一直獨佔近年來的顯示器市場。然而,對於個人 在桌上操作多數終端機/顯示器裝置的環境,或是以環保 的觀點切入,若以節省能源的潮流加以預測,陰極射線管 因空間利用以及能源消耗上仍存在很多問題,而對於輕、 薄、短、小以及低消耗功率的需求無法有效提供解決之 道。因此,具有高晝質、空間利用效率加、低消耗功率、 無輻射等優越特性之薄膜電晶體液晶顯示器(Th i n F i 1 m Transistor Liquid Crystal Display ,TFT LCD)已逐漸 成為市場之主流。 薄膜電晶體陣列基板(TFT array )上,成陣列排列的 薄膜電晶體主要是藉由掃描配線(s c a η 1 i n e )與資料配線 (d a t a 1 i n e )串接,而薄膜電晶體陣列中的每一個薄膜電 晶體係用以控制一對應之晝素電極。此處之薄膜電晶體為 一具有閘極、源極/汲極三個端子的開關元件,薄膜電晶 體之閘極係與掃描配線電性連接,而薄膜電晶體之源極/ 沒極則會與資料配線與晝素電極電性連接。此外,薄膜電 晶體中,源極、汲極之間對應於閘極的半導體層(非晶矽BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a liquid crystal display structure, and more particularly to a thin film transistor array substrate structure (TFT array). . Prior Art The rapid advancement of the multimedia society has largely benefited from the dramatic advances in semiconductor components or human-machine display devices. In terms of displays, cathode ray tubes (CRTs) have always dominated the display market in recent years due to their excellent display quality and economy. However, for the environment in which most individuals operate the terminal/display device on the table, or from the perspective of environmental protection, if the energy saving trend is predicted, the cathode ray tube still has many problems due to space utilization and energy consumption. The need for light, thin, short, small, and low power consumption does not provide an effective solution. Therefore, thin-film liquid crystal displays (TFTs) with superior properties such as high enamel, space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream of the market. On a thin film transistor array substrate (TFT array), the thin film transistors arranged in an array are mainly connected in series by a scan wiring (sca η 1 ine ) and a data wiring (data 1 ine ), and each of the thin film transistor arrays The thin film electro-crystal system is used to control a corresponding halogen electrode. Here, the thin film transistor is a switching element having three terminals of a gate and a source/drain, and the gate of the thin film transistor is electrically connected to the scan wiring, and the source/bottom of the thin film transistor is It is electrically connected to the data wiring and the halogen electrode. Further, in the thin film transistor, a semiconductor layer corresponding to the gate between the source and the drain (amorphous germanium)
8538twf1.pt c 第7頁 1249853 _案號 92114349_年月日__ 五、發明說明(2) 材質或多晶矽材質)為通道層(channe 1 ),此通道層與閘 極之間通常配置有一閘極絕緣層(g a t e i n s u 1 a t i n g 1 a y e r ),而這層閘極絕緣層的薄膜品質將會直接影響到整 個薄膜電晶體的效能(performance)。 習知薄膜電晶體陣列基板在製作過程中,在閘極絕緣 層製作完畢之後,通常仍須進行其他蝕刻的步驟,這些蝕 刻步驟常會損害到閘極絕緣層。以頂閘極型態(t 〇 p g a t e ) 的薄膜電晶體為例,形成閘極時所進行的蝕刻製程便很有 可能損壞到閘極絕緣層的薄膜品質;而以底閘極型態 (b 〇 11 〇 m g a t e )的薄膜電晶體為例,雖然閘極是在閘極絕 緣層之前及製作完畢,但在定義閘極絕緣層上方的通道層 時,所進行的蝕刻製程仍會損壞到閘極絕緣層的薄膜品 質。 然而,習知技術在薄膜電晶體製作完成之後,接著便 進行後續膜層的製作,如介電層(SiOx、SiNx等無機材質 )、晝素電極之製作,並未對閘極絕緣層進行修復的動 作,故習知薄膜電晶體中的閘極絕緣層之薄膜品質並不良 好,常會影響到元件的運作。 發明内容 因此,本發明的目的在提出一種薄膜電晶體陣列基板 結構,其於閘極金屬層與其上方之金屬層間配置一層或是 多層含氫介電層,藉由含氫介電層中的氫原子對閘極絕緣 層進行修補,進而增進元件的效能。 為達本發明之上述目的,提出一種薄膜電晶體陣列基8538twf1.pt c Page 7 1249853 _ Case No. 92114349_年月日日__ V. Description of invention (2) Material or polysilicon material) is the channel layer (channe 1), which is usually equipped with a gate between the channel layer and the gate The gate insulating layer (gateinsu 1 ating 1 ayer ), and the film quality of this gate insulating layer will directly affect the performance of the entire thin film transistor. In the fabrication process of the conventional thin film transistor array substrate, after the gate insulating layer is formed, other etching steps are usually required, and these etching steps often damage the gate insulating layer. Taking the thin film transistor of the top gate type (t 〇pgate ) as an example, the etching process performed when the gate is formed is likely to damage the film quality of the gate insulating layer; and the bottom gate type (b)薄膜11 〇mgate ) is a thin film transistor. Although the gate is formed before the gate insulating layer, but the gate layer above the gate insulating layer is defined, the etching process is still damaged to the gate. Film quality of the insulating layer. However, after the fabrication of the thin film transistor is completed, the subsequent fabrication of the film layer, such as the dielectric layer (inorganic material such as SiOx, SiNx, etc.) and the preparation of the halogen electrode, does not repair the gate insulating layer. Therefore, it is known that the film quality of the gate insulating layer in the thin film transistor is not good, which often affects the operation of the device. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a thin film transistor array substrate structure in which one or more hydrogen-containing dielectric layers are disposed between a gate metal layer and a metal layer thereon, by hydrogen in a hydrogen-containing dielectric layer The atom repairs the gate insulating layer to enhance the performance of the component. In order to achieve the above object of the present invention, a thin film transistor array base is proposed.
8538twf1.ptc 第8頁 1249853 案號 92114349 _η 曰 修正 五、發明說明(3) 明基板、多個薄膜電晶體、多個 、一層或是多層的含氫介電層, 成。其中,薄膜電晶體係配置於 係配置於透明基板上,並覆蓋住 案化導體層則是配置於含氫介電 皆包含了閘極、源極/汲極三個 電性連接,而源極/汲極係與資 電性連接。 層之材質例如為有機材料層 旋塗式玻璃(Spin On Glass , 化物/氮矽化物之混合物,或是 化物/氮叾夕化物之混合物。此 可例如為含有S i - Η鍵結或是 板結構,其主要係由一透 掃描配線、多個資料配線 以及^一圖案化導電層所構 透明基板上,含氫介電層 上述之薄膜電晶體,而圖 層上。每一個薄膜電晶體 端子,閘極係與掃描配線 料配線以及圖案化導體層 本發明中,含氫介電 (organic film)、含水之 S 0 G )、有機材料層與氧矽 含水之旋塗式玻璃與氧矽 外,含氫介電層之材質亦 Si-OH鍵結之So-gel薄膜。 本發明中,含氫介電層例如可作為内介電層 (interlayer dielectric)、平坦層(planarization layer)、反射凸塊層(reflector bump layer),或是廣視 角凸塊層(wide view angle bump layer) o 本發明中,透明基板上的薄膜電晶體可以是非晶矽薄 膜電晶體(a-Si TFT)或是多晶矽薄膜電晶體(p-Si TFT)。 此外,上述之薄膜電晶體例如是頂電極型態之薄膜電晶體 或是底電極型態之薄膜電晶體。 本發明中,含氫介電層上之圖案化導體層例如為多個 晝素電極,而這些晝素電極例如為穿透式電極8538twf1.ptc Page 8 1249853 Case No. 92114349 _η 曰 Amendment V. Description of the invention (3) A substrate, a plurality of thin film transistors, a plurality of layers, or a plurality of layers of hydrogen-containing dielectric layers. Wherein, the thin film electro-crystal system is disposed on the transparent substrate, and the covered conductive layer is disposed on the hydrogen-containing dielectric, including the gate, the source/drain, and the three electrical connections, and the source / 汲 系 is connected to the power supply. The material of the layer is, for example, a spin-on glass of an organic material layer (Spin On Glass, a mixture of a compound/a nitrogen telluride, or a mixture of a compound/azepine compound. This may be, for example, a S i -Η bond or a plate. The structure is mainly composed of a transparent scanning wiring, a plurality of data wirings, and a transparent substrate on which the patterned conductive layer is formed, a hydrogen-containing dielectric layer, the above-mentioned thin film transistor, and a layer, each of the thin film transistor terminals, Gate electrode, scanning wiring material wiring, and patterned conductor layer, in the present invention, a hydrogen-containing dielectric film, a water-containing S 0 G ), an organic material layer, and an oxygen-containing water-sprayed glass and oxygen oxime, The material of the hydrogen-containing dielectric layer is also a Si-OH bonded So-gel film. In the present invention, the hydrogen-containing dielectric layer can be used, for example, as an interlayer dielectric layer, a planarization layer, a reflector bump layer, or a wide viewing angle bump layer. In the present invention, the thin film transistor on the transparent substrate may be an amorphous germanium thin film transistor (a-Si TFT) or a polycrystalline germanium thin film transistor (p-Si TFT). Further, the above-mentioned thin film transistor is, for example, a thin film transistor of a top electrode type or a thin film transistor of a bottom electrode type. In the present invention, the patterned conductor layer on the hydrogen-containing dielectric layer is, for example, a plurality of halogen electrodes, and the halogen electrodes are, for example, transmissive electrodes.
8538twf1.pt c 第9頁 1249853 _案號 92114349_年月日_« 五、發明說明(4) (transparent pixel electrode)或是反射式電極 說 易細 顯詳 明作 更, 匕匕 厶月 3 點圖 優附 和所 、 合 徵配 特並 Λ , 的例 目施 述實 上佳 之較明一 發舉 本特 讓文 為下 -Ε Λβ 下方 如施 明實 如8538twf1.pt c Page 9 1249853 _ Case No. 92114349_年月日日_« V. Invention description (4) (transparent pixel electrode) or reflective electrode said easy to detail and make more, 3 o'clock The excellent attachments and the combination of the special and the special cases are better than the ones that are better than the ones that are given by the special essays.
’ 具 層身 電本 介體 的晶 質電 材膜 機薄 無對 層雖 一 質 蓋材 覆機 方無 上之 體述 晶上 電。 膜等 薄NX 在i 彳S 式|知、 習X 摸摸 薄薄 的為 層作 緣層 絕電 極介 問氮 中含 體用 晶使 電例 膜施 薄實 於本 對, 其此 但因 ·/ ο 用益 作助 的無 護並 保質 有品 視 廣目 是的 或層 ,緣 層絕 塊極 凸閘 射補 反修 、到 層達 坦層 平電 、介 層氫 電含 介由 内藉 之, 方等 上層 體塊 晶凸 電角 的 體 晶 電 膜 薄 晶 多 之 能心 型 極 ^ul 頂 以 僅 述 下 例 施 實 本 態用態 型應型 極的極 電層電 頂電頂 在介、 用氫體 使含晶 能例電 僅施膜 明實薄 發本碎 本,晶 定中多 限構之 非結態 並體型 但晶極 ,電電 明膜底 說薄在 行矽用 進晶應 例多可 為之亦 矽此、 晶。式 非中射 的構反 膜 薄 外 透 穿 結於之 體用} 晶應ve 電可tl 膜亦ec 薄例fl 矽施ns 晶實^a hr Lr t ^ ^ ( 的,式 極知射 電應反 底者半 及術透 以技穿 ,項半 體該是 晶習或 電熟式 體 晶 電 膜 薄 例 施 實 佳 較 - 明 發 本 照 依 為 ο 示 中繪 器3 圖 示1 顯第 晶 液 圖 板 基 r—J 第明 照透 參一 請由 0 係 圖要 意主 示板 局基 佈列 之陣 板體 基晶 列電 膜晶 薄電 ,膜 中薄 例個 施多 實 、 本)0The crystalline electric film machine with the layered dielectric media is thin and has no layer. Although the quality of the cover material is not covered, the crystal is electrically charged. Membrane such as thin NX in i 彳S type | know, Xi X touch thin layer for the layer as the edge of the electrode to interrogate the nitrogen in the medium containing the crystal to make the film thinner than this pair, but this cause / ο Useless help and unprotected quality and quality have a wide-angle or layer, the edge layer is extremely convex, and the slab is repaired, the layer is flat, and the hydrogen is contained. The so-called upper body block crystal convex electric angle of the bulk crystal electric film thin crystal multi-energy type core ^ ul top only to illustrate the following example of the implementation of the state of the type of the type of pole type electric pole electric top The use of hydrogen to make the crystal-containing energy is only a thin film of the crystal, and the non-definite state of the crystal is in the form of a non-coherent shape but a crystal pole. The electric film is thin and thin. There are many examples of this, and this is also the case. The non-middle-shot structure of the anti-reflection film is used to penetrate the body of the film. The crystal should be ve, the electricity can be tl, the film is also ec, the thin case is fl, the ns crystal is ^a hr Lr t ^ ^ ( The bottom of the bottom and the technique are worn by the technique. The half of the body is the thin habit of the crystal habit or the electro-cooking type. The thin film is better than that of the body--the Mingfa is based on the picture ο. Crystal liquid plate base r-J The first light through the reference to a please from the 0 system to the main board of the board of the base board of the array of the base crystal array film thin electric, thin film in the film, Shi Duo, Ben) 0
8538twf1.pt c 第10頁 1249853 案號 92114349 年 月 曰 修正 五、發明說明(5) 體1 0 2 、多個掃描配線1 0 4、多個資料配線1 0 6,以及一晝 素電極1 0 8所構成。其中,掃描配線1 0 4的延伸方向與資料 配線1 0 6的延伸方向互相垂直,且相鄰兩條掃描配線1 0 4與 相鄰兩條資料片線1 〇 6所圍成的區域上配置有薄膜電晶體 1 0 2與晝素電極1 0 8。透明基板1 0 0上的每一個薄膜電晶體 1 0 1皆包含了閘極、源極/汲極三個端子,閘極係與掃描配 線1 0 4電性連接,而源極/汲極則與資料配線1 0 6以及晝素 電極1 0 8電性連接。掃描配線1 0 4係用以控制薄膜電晶體 1 0 2之開/關,而在薄膜電晶體1 0 2呈『開』的狀態時,資 料配線1 0 6可以將影像資訊寫入薄膜電晶體1 0 2所控制的畫 素電極1 0 8中。 第2圖繪示為依照本發明一較佳實施例穿透式薄膜電 晶體陣列基板之剖面示意圖。請參照第2圖,透明基板2 0 0 上配置有多個陣列排列之薄膜電晶體2 0 2,以頂電極型態 的多晶矽薄膜電晶體2 0 2為例,其主要是由一島狀多晶矽 2 〇 4、一閘極絕緣層2 0 6,以及一閘極2 0 8所構成。其中, 島狀多晶矽2 0 4包含了一通道層2 0 4a以及二源極/汲極摻雜 區域2 0 4b,閘極絕緣層2 0 6配置於透明基板2 0 0上,並覆蓋 住島狀多晶矽2 0 4,而對應於通道層2 0 4 a的閘極絕緣層2 0 6 上則配置有閘極2 0 8。此外,薄膜電晶體2 0 2係由一含氫介 電層2 1 0所覆蓋,而源極/汲極金屬2 1 2則是貫穿含氫介電 層2 1 0與源極/汲極摻雜區域2 0 4 b電性連接,以使得源極/ 汲極摻雜區域2 0 4 b得以對外連接。 承上述,此含氫介電層2 1 0之材質例如為有機材料層8538twf1.pt c Page 10 1249853 Case No. 92114349 Yearly Revision 5, Invention Description (5) Body 1 0 2, Multiple Scanning Wiring 1 0 4, Multiple Data Wiring 1 0 6, and a Nuclide Electrode 1 0 8 constitutes. Wherein, the extending direction of the scanning wiring 104 is perpendicular to the extending direction of the data wiring 106, and the area between the adjacent two scanning wirings 104 and the adjacent two data lines 1 and 6 is disposed. There is a thin film transistor 1 0 2 and a halogen electrode 1 0 8 . Each of the thin film transistors 110 on the transparent substrate 100 includes three terminals of a gate and a source/drain, and the gate is electrically connected to the scan wiring 104, and the source/drain is It is electrically connected to the data wiring 1 0 6 and the halogen electrode 1 0 8 . The scan wiring 1 0 4 is used to control the on/off of the thin film transistor 102, and when the thin film transistor 1 0 2 is in the "on" state, the data wiring 1 0 6 can write image information into the thin film transistor. 1 0 2 controlled pixel electrode 1 0 8 . 2 is a cross-sectional view showing a transmissive thin film transistor array substrate in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, a plurality of thin film transistors 20 2 arranged in an array are arranged on the transparent substrate 200, and a polycrystalline germanium film transistor 20 of the top electrode type is taken as an example, which is mainly composed of an island polysilicon. 2 〇 4, a gate insulating layer 2 0 6, and a gate 2 0 8 constitute. The island-shaped polysilicon 205 includes a channel layer 2 0 4a and a two-source/drain-doped region 2 0 4b. The gate insulating layer 206 is disposed on the transparent substrate 200 and covers the island. The polycrystalline silicon is 2 0 4 , and the gate insulating layer 2 0 6 corresponding to the channel layer 2 0 4 a is provided with a gate 2 0 8 . In addition, the thin film transistor 2 0 2 is covered by a hydrogen-containing dielectric layer 2 10 , and the source/drain metal 2 1 2 is penetrated through the hydrogen-containing dielectric layer 2 10 and the source/drain The impurity region 2 0 4 b is electrically connected such that the source/drain doped region 2 0 4 b is externally connected. In view of the above, the material of the hydrogen-containing dielectric layer 210 is, for example, an organic material layer.
8538twf1.pt c 第11頁 1249853 _案號92Π4349_年月曰 修正_ 五、發明說明(6) (organic film)、含水之旋塗式玻璃(Spin On Glass, S 0 G )、有機材料層與氧矽化物/氮矽化物之混合物,或是 含水之旋塗式玻璃與氧叾夕化物/氮叾夕化物之混合物。此 外,含氫介電層2 1 0之材質亦可例如是含有S 1 - Η鍵結或是 Si-〇H鍵結之S〇-gel薄膜。 同樣請參照第2圖,含氫介電層2 1 0上例如配置有一平 坦層2 1 4,此平坦層2 1 4之材質例如可與含氫介電層2 1 0之 材質相同,亦可以是氧矽化物、氮矽化物等無機介電材 質。在平坦層2 1 4上則配置有圖案化導體層2 1 6 ,圖案化導 體層2 1 6例如係藉由一開口 2 1 5與源極/汲極金屬層2 1 2電性 連接,以使得圖案化導體層2 1 6可以受薄膜便晶體2 0 2的控 制。換言之,圖案化導體層2 1 6即為所謂的穿透式畫素電 極,在本實施例中,導體層2 1 6例如為氧化銦錫(I T 0 )、氧 化銦鋅等透明材質。 第3圖繪示為依照本發明一較佳實施例反射式薄膜電 晶體陣列基板之剖面示意圖。請參照第3圖,透明基板3 0 0 上配置有多個陣列排列之薄膜電晶體3 0 2 ,以頂電極型態 的多晶矽薄膜電晶體3 0 2為例,其主要是由一島狀多晶矽 3 0 4、一閘極絕緣層3 0 6,以及一閘極3 0 8所構成。其中, 島狀多晶矽3 0 4包含了一通道層3 0 4a以及二源極/汲極摻雜 區域3 0 4 b,閘極絕緣層3 0 6配置於透明基板3 0 0上,並覆蓋 住島狀多晶矽3 0 4,而對應於通道層3 0 4 a的閘極絕緣層3 0 6 上則配置有閘極3 0 8。此外,薄膜電晶體3 0 2係由一含氫介 電層310所覆蓋,而圖案化導體層312則是覆蓋於含氫介電8538twf1.pt c Page 11 1249853 _ Case No. 92Π4349_年月曰 Revision _ V. Description of invention (6) (organic film), water-based spin-on glass (S0 G), organic material layer and A mixture of oxonium halides/nitrides or a mixture of aqueous spin-on glass and oxonium/nitroxides. Further, the material of the hydrogen-containing dielectric layer 210 may be, for example, an S〇-gel film containing an S 1 - Η bond or a Si-〇 H bond. Referring to FIG. 2, for example, a flat layer 2 1 4 is disposed on the hydrogen-containing dielectric layer 210, and the material of the flat layer 2 14 may be the same as the material of the hydrogen-containing dielectric layer 2 1 0, or It is an inorganic dielectric material such as an oxygen halide or a nitrogen halide. A patterned conductor layer 2 16 is disposed on the flat layer 2 14 , and the patterned conductor layer 2 16 is electrically connected to the source/drain metal layer 2 1 2 by, for example, an opening 2 15 . The patterned conductor layer 2 16 can be controlled by the thin film crystal 2 0 2 . In other words, the patterned conductor layer 2 16 is a so-called transmissive pixel electrode. In the present embodiment, the conductor layer 2 16 is, for example, a transparent material such as indium tin oxide (I T 0 ) or indium zinc oxide. 3 is a cross-sectional view showing a reflective thin film transistor array substrate in accordance with a preferred embodiment of the present invention. Referring to FIG. 3, a plurality of thin film transistors 3 0 2 arranged in an array are arranged on the transparent substrate 300, and a polycrystalline germanium thin film transistor 3 0 2 of a top electrode type is taken as an example, which is mainly composed of an island polysilicon. 3 0 4, a gate insulating layer 3 0 6, and a gate 3 0 8 constitute. The island-shaped polysilicon 300 includes a channel layer 3 0 4a and a two-source/drain-doped region 3 0 4 b, and the gate insulating layer 3 0 6 is disposed on the transparent substrate 300 and covered. The island-shaped polysilicon 3 0 4 and the gate insulating layer 3 0 6 corresponding to the channel layer 3 0 4 a are provided with a gate 3 0 8 . In addition, the thin film transistor 302 is covered by a hydrogen containing dielectric layer 310, and the patterned conductor layer 312 is covered with a hydrogen containing dielectric.
8538twf1.p t c 第12頁 1249853 _案號92114349_年月日__ 五、發明說明(7) 層3 1 0上。 含氫介電層3 1 0係用以作為反射凸塊層,其在表面上 具有多個反射凸塊310a,而配置在含氫介電層310上之圖 案化導體層3 1 2則包含源極/汲極金屬3 1 2 a與反射式畫素電 極312b兩部份,源極/;及極金屬312a貫穿含氫介電層310與 源極/汲極摻雜區域3 0 4 b電性連接,以使得源極/汲極摻雜 區域3 0 4 b得以對外連接。此外,由於含氫介電層3 1 0的表 面具有反射凸塊310a,故反射式畫素電極312b將可以更有 效且均勻地將外界或是前光源(f r ο n t 1 i g h t )的光線反 射,以達到顯示的目的。 上述實施例中,含氫介電層除了可以作為陣列基板上 的内介電層、平坦層(含氫介電層210)、反射凸塊層 (含氫介電層310)之外,亦可作為廣視角凸塊層。這些 膜層不但各自具有其功能,且同時兼具了修補閘極絕緣層 的功效,由上述可知,本實施例能夠有效地與薄膜電晶體 陣列基板的製程整合,且能夠改善元件的效能。 綜上所述,本發明之薄膜電晶體陣列基板結構至少具 有下列優點: 1 .本發明之薄膜電晶體陣列基板結構可以有效對閘極 絕緣層進行修補,以增進元件的效能。 2 .本發明之薄膜電晶體陣列基板結構中,含氫介電層 可以作為内介電層、平坦層、反射凸塊層,或是廣視角凸 塊層,其可適用於各種型態(穿透式、反射式)之面板。 雖然本發明已以一較佳實施例揭露如上,然其並非用8538twf1.p t c Page 12 1249853 _ Case No. 92114349_年月日日__ V. Description of invention (7) Layer 3 1 0. The hydrogen-containing dielectric layer 310 is used as a reflective bump layer having a plurality of reflective bumps 310a on the surface, and the patterned conductor layer 3 1 2 disposed on the hydrogen-containing dielectric layer 310 includes a source. The pole/deuterium metal 3 1 2 a and the reflective pixel electrode 312b are two parts, the source/; and the pole metal 312a penetrates the hydrogen-containing dielectric layer 310 and the source/drain doped region 3 0 4 b The connections are made such that the source/drain doped regions 3 0 4 b are externally connected. In addition, since the surface of the hydrogen-containing dielectric layer 310 has reflective bumps 310a, the reflective pixel electrode 312b can reflect the light of the outside or the front light source (fr ο nt 1 ight ) more effectively and uniformly. In order to achieve the purpose of display. In the above embodiments, the hydrogen-containing dielectric layer may be used as an inner dielectric layer, a flat layer (hydrogen-containing dielectric layer 210), and a reflective bump layer (hydrogen-containing dielectric layer 310) on the array substrate. As a wide viewing angle bump layer. These layers not only have their functions, but also have the effect of repairing the gate insulating layer. From the above, the present embodiment can effectively integrate with the process of the thin film transistor array substrate and can improve the performance of the device. In summary, the thin film transistor array substrate structure of the present invention has at least the following advantages: 1. The thin film transistor array substrate structure of the present invention can effectively repair the gate insulating layer to improve the performance of the device. 2. In the thin film transistor array substrate structure of the present invention, the hydrogen-containing dielectric layer can be used as an inner dielectric layer, a flat layer, a reflective bump layer, or a wide viewing angle bump layer, which can be applied to various types (wearing Transparent, reflective) panel. Although the present invention has been disclosed above in a preferred embodiment, it is not
8538twf1.ptc 第13頁 1249853 _案號92114349_年月曰 修正_ 五、發明說明(8) 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍内,當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。8538 twf1.ptc Page 13 1249853 _ Case No. 92114349 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The scope of protection of the present invention is defined by the scope of the appended claims.
8538twf1.ptc 第14頁 1249853 _案號92114349_年月曰 修正_ 圖式簡單說明 [圖式簡單說明] 第1圖繪示為依照本發明一較佳實施例薄膜電晶體陣 列基板之佈局示意圖; 第2圖繪示為依照本發明一較佳實施例穿透式薄膜電 晶體陣列基板之剖面示意圖;以及 第3圖繪示為依照本發明一較佳實施例反射式薄膜電 晶體陣列基板之剖面示意圖。 [圖式標示說明] 1 0 0 :透明基板 1 0 2 :薄膜電晶體 1 〇 4 :掃描配線 1 0 6 :資料配線 1 0 8 :晝素電極 200、300 :透明基板 2 0 2、3 0 2 :薄膜電晶體 204 、304 :島狀多晶石夕(polysilicon island) 2 0 4a、3 0 4a :通道層 2 0 4 b、3 0 4 b :源極/汲極摻雜區域 2 0 6、3 0 6 :閘極絕緣層 2 0 8、3 0 8 :閘極 210、310 :含氫介電層 212、312a :源極/汲極金屬層(S/D metal) 2 1 4 :平坦層 2 1 5 :開口8538 twf1.ptc page 14 1249853 _ case number 92114349 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 2 is a cross-sectional view showing a transmissive thin film transistor array substrate according to a preferred embodiment of the present invention; and FIG. 3 is a cross-sectional view showing a reflective thin film transistor array substrate according to a preferred embodiment of the present invention. schematic diagram. [Illustration description] 1 0 0 : Transparent substrate 1 0 2 : Thin film transistor 1 〇 4 : Scanning wiring 1 0 6 : Data wiring 1 0 8 : Alizarin electrode 200, 300: Transparent substrate 2 0 2, 3 0 2: thin film transistor 204, 304: island polycrystalline silicon (polysilicon island) 2 0 4a, 3 0 4a: channel layer 2 0 4 b, 3 0 4 b : source/drain doping region 2 0 6 , 3 0 6 : gate insulating layer 2 0 8 , 3 0 8 : gate 210, 310: hydrogen-containing dielectric layer 212, 312a: source/drain metal layer (S/D metal) 2 1 4 : flat Layer 2 1 5 : opening
8538twf1.ptc 第15頁 12498538538twf1.ptc Page 15 1249853
8538twf1.pt c 第16頁8538twf1.pt c Page 16
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW92114349A TWI249853B (en) | 2003-05-28 | 2003-05-28 | Thin film transistor array structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW92114349A TWI249853B (en) | 2003-05-28 | 2003-05-28 | Thin film transistor array structure |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200427092A TW200427092A (en) | 2004-12-01 |
TWI249853B true TWI249853B (en) | 2006-02-21 |
Family
ID=37430227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW92114349A TWI249853B (en) | 2003-05-28 | 2003-05-28 | Thin film transistor array structure |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI249853B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI626497B (en) * | 2017-02-15 | 2018-06-11 | 友達光電股份有限公司 | Active device array substrate and display device using the same |
-
2003
- 2003-05-28 TW TW92114349A patent/TWI249853B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW200427092A (en) | 2004-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9780124B2 (en) | Display device including pixel comprising first transistor second transistor and light-emitting element | |
TWI227031B (en) | A capacitor structure | |
US6639244B1 (en) | Semiconductor device and method of fabricating the same | |
CN101494202B (en) | Preparation method for thin-film transistor array substrate and liquid crystal display panel | |
US7164164B2 (en) | Display device and photoelectric conversion device | |
TW503337B (en) | Electrooptic device, method of manufacture thereof, and electronic device | |
US6765637B2 (en) | Translucent reflection type electro-optic devices and methods for manufacturing the same | |
JP2015228504A (en) | Semiconductor device | |
CN105487315A (en) | TFT (thin film transistor) array substrate | |
TW200947089A (en) | System for displaying images and fabrication method thereof | |
WO2018126676A1 (en) | Pixel structure and method for manufacturing same, array substrate, and display device | |
US20020036724A1 (en) | Liquid crystal display device and the fabricating method thereof | |
JP4896314B2 (en) | Display device | |
TW201042341A (en) | Active array substrate, liquid crystal display panel and method for manufacturing the same | |
JP3454340B2 (en) | Liquid crystal display | |
JP2782020B2 (en) | Liquid crystal electro-optical device and manufacturing method thereof | |
US6818922B2 (en) | Thin film transistor array and driving circuit structure | |
TW594160B (en) | Reflective electrooptic device and electronic apparatus | |
JPH10142636A (en) | Active matrix type display circuit | |
TWI249853B (en) | Thin film transistor array structure | |
WO2024065111A1 (en) | Array substrate and manufacturing method therefor, and display panel | |
KR101294693B1 (en) | The array substrate for liquid crystal display device | |
TW200419275A (en) | Pixel structure and method of repairing the same | |
JP2004246315A (en) | Method for manufacturing electrooptical substrate, method for manufacturing electrooptical device, electrooptical device, and electronic equipment | |
JP2005351934A (en) | Active matrix display element |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |