1249807 〇5406twfl .doc/006 94.12.8 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路(Integrated Circuits，1C) 元件隔離(Isolation)之製造方法，且特別是有關於一種淺溝 渠隔離（Shallow Trench Isolation，STI)之製造方法。 【先前技術】 一完整的積體電路，通常是由成千上萬個金氧半導體 (Metal Oxide Semiconductor，M0S)電晶體（Transistor)所組 成，爲防止這些相鄰的電晶體間發生短路的現象，因此必 須在相鄰的電晶體間加入用以電性隔絕的隔離結構。 傳統半導體製程所使用的隔離結構爲場氧化層(Field Oxide，FOX)，其形成方法係使用區域氧化法（Local Oxidation，LOCOS)，然而，由於區域氧化法所形成之場氧 化層存在著多項缺點，包括應力產生之相關問題，以及隔 離結構周圍鳥嘴區(Bird’s Beak)之形成等，特別是鳥嘴區的 形成，導致在尺寸逐漸縮小的元件製造上，此種場氧化層 隔離結構已不能提供有效的隔離效果。 爲因應兀件臨界尺寸（Critical Dimension，CD)逐漸縮 小的趨勢，在微小尺寸下具有良好隔離效果的淺溝渠隔離 結構’成了深次微米(Deep Sub Micron)製程主要的隔離結 構。 第1A至1C圖係繪示傳統淺溝渠隔離結構之製造流程 剖面示意圖。 梦照桌1A圖，首先在基底1〇〇的表面依序形成一 1249807 05406twfl .doc/006 94.12.8 墊氧化層(Pad Oxide)102以及一罩幕層l〇4，然後利用一微 影餓刻(Photo Lithography & Etching)製程’以在基底 1〇〇 中定義出一淺溝渠106，其中，此墊氧化層1 〇2形成所使用 的方法爲熱氧化法（Thermal Oxidation)。 接著，於淺溝渠106中所暴露出的基底1〇〇表面形成 一襯氧化層(Liner Oxide)108，此襯氧化層108形成所使用 的方法爲熱氧化法。 請參照第1B圖，然後形成一氧化層110塡入淺溝渠 106，此氧化層110塡入淺溝渠106所使用的方法，係先形 成一氧化層（圖未示）覆蓋罩幕層104,同時並塡入淺溝渠 106，接著再以化學機械硏磨法（Chemical Mechanical Polishing’ CMP)，將覆蓋在罩幕層104表面之氧化層去除。 此氧化層110的形成，通常是以臭氧（Ozone，〇3)與 4-乙院基-正-石夕酸鹽（Tetra-Etl·lyl-Ortho-Silicate，TEOS)爲反 應氣體源，經由化學氣相沉積法（Chemical Vapor Deposition，CVD)而製成。 請參照第1C圖，接著將第1B圖中所示之墊氧化層 1〇2與罩幕層104去除，則淺溝渠隔離結構製造完成，此墊 氧化層1〇2與罩幕層1〇4去除所使用之方式爲濕式蝕刻法。 然而，由於淺溝渠具有一定的高寬比(Aspect RatiQ， AR)’亦即淺溝渠之深度具有較淺溝渠之寬度爲大的尺寸， 因此，當元件臨界尺寸持續縮小時，淺溝渠所具有的高寬 比將逐漸增大，導致氧化層塡入淺溝渠的困難度增加。 【發明内容】 1249807 05406twfl .doc/006 因此本發明就是在提供一種淺溝渠隔離之製造方 法，用以解決習知在具有一定高寬比的淺溝渠中塡入氧化 層時，所可能發生塡隙（GaP Fil1)情形不佳的問題。 本發明提出一種淺溝渠隔離之製造方法，包括提供一 基底，先形成一墊氧化層覆蓋此基底，再形成一罩幕層覆 蓋此墊氧化層，然後，進行一微影蝕刻製程，以在基底中 形成一淺溝渠，接著，形成一襯氧化層於淺溝渠周圍之基 底表面，再形成一第一介電層覆蓋罩幕層與襯氧化層，然 後，對此第一介電層進行一回蝕刻製程，以形成一間隙壁， 覆蓋淺溝渠之側壁，同時使位於淺溝渠底部之基底裸露出 來，接著，進行一熱氧化製程，以在淺溝渠底部之基底處 形成一氧化層，然後，形成一第二介電層覆蓋罩幕層、間 隙壁與氧化層，並塡滿淺溝渠，再進行一平坦化製程，以 將形成於罩幕層表面之第二介電層去除，然後再去除罩幕 層，以及，去除墊氧化層。 本發明係先在一淺溝渠的側壁形成一可防止淺溝渠 側壁遭受氧化的間隙壁（Spacer)，同時，使位於淺溝渠底部 之基底暴露出來，然後進行一熱氧化製程，使於淺溝渠底 部之基底處，得以非等向性之方式形成一氧化層，然後再 於淺溝渠中塡入一介電層，以形成淺溝渠隔離。 本發明係在淺溝渠的底部先形成氧化層，因此可大幅 降低淺溝渠的局寬比，使後續形成之介電層，可輕易塡入 淺溝渠中。 爲讓本發明之上述和其他目的、特徵、和優點能更明 94.12.8 1249807 05406twfl.doc/006 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 第2 A至2F圖係繪示依據本發明較佳實施例之一種淺 溝渠隔離結構之製造流程剖面示意圖。 請參照第2A圖，首先，在基底2〇Q的表面依序形成 一墊氧化層202以及一罩幕層2〇4,然後利用一微影蝕刻製 程，以在基底2〇〇中定義出一淺溝渠206。 其中，此墊氧化層202形成所使用的方法，譬如是熱 氧化法，其厚度譬如約略爲1〇〇至3 00埃(Angstrom)，而罩 幕層2〇4所使用的材料譬如是氮化矽，其形成所使用的方 法，譬如是化學氣相沉積法，其厚度譬如約略爲1500至 2000埃，至於經微影蝕刻製程而形成的淺溝渠206，其深 度則譬如約略爲3000至5000 ；t矣。 接者’於淺溝渠206中所暴露出的基底200表面形成 一襯氧化層208，此襯氧化層2〇8形成所使用的方法，譬如 是熱氧化法’其厚度譬如約略爲1〇0至250埃。 sra篸Pm桌2B圖，然後，形成一介電層21 〇，共形地覆 蓋罩幕層2〇4與淺溝渠2〇6中的襯氧化層2〇8。 此介電層210所使用的材料，譬如是氮化矽，其形成 所使用的方法，譬如是化學氣相沉積法。 請參照第2C圖，接著，以位於淺溝渠2〇6底部之基 底區域200a爲飩刻終止層，對介電層210進行一回鈾刻製 程，以使介電層21〇在淺溝渠2〇6的側壁，形成間隙壁212, 94.12.8 I249807〇6twfLd〇c/〇〇6 並由於是以位於淺溝渠2 Ο 6底部之基底區域2 Ο 0 a爲蝕刻終 止層，因此，此回蝕刻製程同時會將位於淺溝渠206底部 之襯氧化層208的部分去除，使位於淺溝渠206底部之基 底區域200a暴露出來。 其中，形成此間隙壁212所使用的回蝕刻製程，譬如 是以反應性離子蝕刻法(Reactive Ion Etching，RIE)來完成。 請參照第2D圖，接著，進行一熱氧化製程，以在淺 溝渠206底部之基底區域200a處形成一氧化層214。 此氧化層214之所以只會形成於淺溝渠206底部之基 底區域2〇Oa處的原因，是由於氧化層214的形成係使用熱 氧化製程，而基底200與淺溝渠206的側壁分別被罩幕層 2〇4與間隙壁212所覆蓋，只有位於淺溝渠2〇6底部之基底 區域2〇Oa被暴露出來，因此，氧化層214只會形成於淺溝 渠206底部之基底區域200a處。 配合此種只有位於淺溝渠206底部之基底區域200a 被暴露出來的結構’且利用熱氧化製程所形成的氧化層 214，其成長僅爲單一方向，因此，形成此氧化層所使 用的熱氧化製程，爲一非等向性(Anis〇tr〇pic)熱氧化製程。 §靑篸照第2E圖，然後，形成一介電層216覆蓋罩幕 層204、間隙壁212與氧化層214，此介電層216同時塡滿 淺溝渠206。 其中，介電層川臓用的材料譬如是氧化砂，其形 成所使用的方法譬如是化學氣相沉積法。其中，較佳的化 4力絲士麵鹽爲反 94.12.8 I249807〇6twfl,〇c/O06 應氣體源來進行’或是’使用高密度電漿化學氣相沉積法 (High Density Plasma Chemical Vapor Deposition ， HDPCVD)。 由於淺溝渠206的底部已先形成有氧化層214，因此 可大幅降低淺溝渠206的高寬比，致使介電層216可輕易 地塡入淺溝渠206中。 請參照第2F圖，然後，對介電層216進行一平坦化 製程(Planarization)，將覆蓋在罩幕層204表面之介電層216 的部分去除，此去除覆蓋在罩幕層204表面之介電層216 所使用的方法，譬如是以罩幕層204爲硏磨終止層，進行 一化學機械研磨製程。 接著，將墊氧化層202與罩幕層204去除，同時，間 隙壁212將變成間隙壁212a，而介電層216將只剩下塡於 淺溝渠206中之介電層216a，此墊氧化層202與罩幕層204 去除所使用之方式，譬如是濕式蝕刻法。 本發明係先在一淺溝渠的側壁形成一可防止淺溝渠 側壁遭受氧化的間隙壁，同時，使位於淺溝渠底部之基底 暴露出來’然後進行一熱氧化製程，使於淺溝渠底部之基 底處’得以非等向性之方式形成一氧化層，然後再於淺溝 渠中桃入一介電層，以形成淺溝渠隔離。 本發明係在淺溝渠的底部先形成氧化層，因此可大幅 降低淺溝渠的高寬比，使後續形成之介電層，可輕易塡入 淺溝渠中。 雖然本發明已以一較佳實施例揭露如上，然其並非用 1249807 05406twfl.doc/006 94.12.8 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 第1A至1C圖係繪示傳統淺溝渠隔離結構之製造流程 剖面示意圖；以及 第2A至2F圖係繪示依據本發明較佳實施例之一種淺 溝渠隔離結構之製造流程剖面示意圖。 【主要元件符號說明】 100、200、200a ··基底 102、202 :墊氧化層 104、204 :罩幕層 106、206 :淺溝渠 108、208 :襯氧化層 110、214 :氧化層 210、216、216a :介電層 212、212a :間隙壁 101249807 〇5406twfl .doc/006 94.12.8 IX. Description of the Invention: [Technical Field] The present invention relates to a method for manufacturing an integrated circuit (IC) component isolation, and in particular A method of manufacturing Shallow Trench Isolation (STI). [Prior Art] A complete integrated circuit is usually composed of thousands of Metal Oxide Semiconductor (M0S) transistors to prevent short circuits between these adjacent transistors. Therefore, an isolation structure for electrically isolating must be added between adjacent transistors. The isolation structure used in the conventional semiconductor process is Field Oxide (FOX), and the formation method is Local Oxidation (LOCOS). However, there are many disadvantages of the field oxide layer formed by the regional oxidation method. , including problems related to stress generation, and the formation of Bird's Beak around the isolation structure, especially the formation of the bird's beak area, which leads to the formation of such a field oxide isolation structure in the manufacture of components with gradually reduced dimensions. Provide effective isolation. In order to cope with the trend of shrinking the critical dimension (CD), the shallow trench isolation structure with good isolation in a small size has become the main isolation structure of the Deep Sub Micron process. Figures 1A to 1C are schematic cross-sectional views showing the manufacturing process of a conventional shallow trench isolation structure. 1A picture of the dream table, firstly forming a 1249807 05406twfl .doc/006 94.12.8 pad oxide layer (Pad Oxide) 102 and a mask layer l〇4 on the surface of the substrate 1〇〇, and then using a lithography hungry The Photo Lithography & Etching process defines a shallow trench 106 in the substrate 1 , wherein the method of forming the pad oxide layer 1 〇 2 is Thermal Oxidation. Next, a liner oxide layer 108 is formed on the surface of the substrate 1 exposed in the shallow trench 106. The method for forming the liner oxide layer 108 is a thermal oxidation method. Referring to FIG. 1B, an oxide layer 110 is formed and immersed in the shallow trench 106. The oxide layer 110 is immersed in the shallow trench 106 by forming an oxide layer (not shown) to cover the mask layer 104. The shallow trench 106 is then broken into, and then the oxide layer covering the surface of the mask layer 104 is removed by chemical mechanical polishing (CMP). The formation of the oxide layer 110 is usually carried out by using ozone (Ozone, 〇3) and Tetra-Etl·lyl-Ortho-Silicate (TEOS) as a reaction gas source through chemistry. It is made by Chemical Vapor Deposition (CVD). Referring to FIG. 1C, the pad oxide layer 1〇2 and the mask layer 104 shown in FIG. 1B are removed, and the shallow trench isolation structure is completed. The pad oxide layer 1〇2 and the mask layer 1〇4 The method used for the removal is a wet etching method. However, since the shallow trench has a certain aspect ratio (Aspect RatiQ, AR), that is, the depth of the shallow trench has a larger width than that of the shallow trench, when the critical dimension of the component continues to shrink, the shallow trench has The aspect ratio will gradually increase, resulting in an increase in the difficulty of the oxide layer breaking into shallow trenches. SUMMARY OF THE INVENTION The present invention is directed to a method of fabricating a shallow trench isolation for solving the problem of gaps that may occur when a shallow trench is formed in a shallow trench having a certain aspect ratio. (GaP Fil1) The problem of poor situation. The invention provides a method for manufacturing shallow trench isolation, comprising providing a substrate, first forming a pad oxide layer to cover the substrate, forming a mask layer covering the pad oxide layer, and then performing a lithography etching process on the substrate Forming a shallow trench, and then forming a lining oxide layer on the surface of the substrate around the shallow trench, and then forming a first dielectric layer covering the mask layer and the lining oxide layer, and then performing the first dielectric layer Etching process to form a spacer covering the sidewall of the shallow trench while exposing the substrate at the bottom of the shallow trench, and then performing a thermal oxidation process to form an oxide layer at the bottom of the shallow trench and then forming a second dielectric layer covers the mask layer, the spacer and the oxide layer, and fills the shallow trench, and then performs a planarization process to remove the second dielectric layer formed on the surface of the mask layer, and then remove the mask The curtain layer, as well, removes the pad oxide layer. The invention firstly forms a spacer on the side wall of a shallow trench to prevent oxidation of the side wall of the shallow trench, and exposes the substrate at the bottom of the shallow trench, and then performs a thermal oxidation process to make the bottom of the shallow trench At the base, an oxide layer is formed in an anisotropic manner, and then a dielectric layer is interposed in the shallow trench to form a shallow trench isolation. The invention first forms an oxide layer at the bottom of the shallow trench, so that the aspect ratio of the shallow trench can be greatly reduced, so that the subsequently formed dielectric layer can be easily broken into the shallow trench. The above and other objects, features, and advantages of the present invention will become more apparent from the following description of the appended claims <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; [Embodiment] FIGS. 2A to 2F are schematic cross-sectional views showing a manufacturing process of a shallow trench isolation structure according to a preferred embodiment of the present invention. Referring to FIG. 2A, first, a pad oxide layer 202 and a mask layer 2〇4 are sequentially formed on the surface of the substrate 2〇Q, and then a lithography process is used to define one in the substrate 2〇〇. Shallow ditches 206. Wherein, the pad oxide layer 202 is formed by a method such as thermal oxidation, the thickness of which is, for example, about 1 Å to 300 angstroms (Angstrom), and the material used for the mask layer 2 〇 4 is, for example, nitriding.矽, the method used for the formation, for example, chemical vapor deposition, the thickness is, for example, about 1500 to 2000 angstroms, and the shallow trench 206 formed by the lithography process has a depth of about 3,000 to 5,000; t矣. The substrate is formed on the surface of the substrate 200 exposed in the shallow trench 206 to form a liner oxide layer 208. The liner oxide layer 2〇8 is formed by a method such as thermal oxidation method whose thickness is, for example, approximately 1〇0. 250 angstroms. The sra 篸 Pm table 2B is then formed with a dielectric layer 21 〇 which conformally covers the lining oxide layer 2 〇 8 in the mask layer 2 〇 4 and the shallow trench 2 〇 6 . The material used for the dielectric layer 210, such as tantalum nitride, is formed by a method such as chemical vapor deposition. Referring to FIG. 2C, next, the base region 200a at the bottom of the shallow trench 2〇6 is used as a etch stop layer, and the dielectric layer 210 is subjected to an uranium engraving process so that the dielectric layer 21 is smashed in the shallow trench 2〇. The sidewall of 6 forms a spacer 212, 94.12.8 I249807〇6twfLd〇c/〇〇6 and since the base region 2 Ο 0 a at the bottom of the shallow trench 2 Ο 6 is an etch stop layer, the etch back process At the same time, the portion of the liner oxide layer 208 at the bottom of the shallow trench 206 is removed, exposing the substrate region 200a at the bottom of the shallow trench 206. The etch back process used to form the spacers 212 is accomplished, for example, by reactive ion etching (RIE). Referring to Figure 2D, a thermal oxidation process is then performed to form an oxide layer 214 at the base region 200a at the bottom of the shallow trench 206. The reason why the oxide layer 214 is formed only in the base region 2〇Oa at the bottom of the shallow trench 206 is that the formation of the oxide layer 214 is performed by a thermal oxidation process, and the sidewalls of the substrate 200 and the shallow trench 206 are respectively covered by the mask layer. 2〇4 is covered by the spacer 212, and only the base region 2〇Oa at the bottom of the shallow trench 2〇6 is exposed. Therefore, the oxide layer 214 is formed only at the base region 200a at the bottom of the shallow trench 206. The oxide layer 214 formed by the thermal oxidation process is only a single direction in combination with the structure in which only the base region 200a at the bottom of the shallow trench 206 is exposed, and thus the thermal oxidation process used to form the oxide layer is formed. , is an anisotropic (Anis〇tr〇pic) thermal oxidation process. Referring to Figure 2E, a dielectric layer 216 is then formed overlying the mask layer 204, the spacers 212, and the oxide layer 214, which simultaneously fills the shallow trenches 206. Among them, the material for the dielectric layer, such as oxidized sand, is formed by a method such as chemical vapor deposition. Among them, the preferred 4 force silk salt is anti-94.12.8 I249807〇6twfl, 〇c/O06 should be used for gas source 'or' using high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor) Deposition, HDPCVD). Since the oxide layer 214 is formed on the bottom of the shallow trench 206, the aspect ratio of the shallow trench 206 can be greatly reduced, so that the dielectric layer 216 can be easily broken into the shallow trench 206. Referring to FIG. 2F, a planarization process (Planarization) is performed on the dielectric layer 216 to remove a portion of the dielectric layer 216 overlying the surface of the mask layer 204, which is removed from the surface of the mask layer 204. The method used by the electrical layer 216, such as the masking layer 204 as a honing stop layer, is subjected to a chemical mechanical polishing process. Next, the pad oxide layer 202 and the mask layer 204 are removed, while the spacers 212 will become the spacers 212a, and the dielectric layer 216 will remain only the dielectric layer 216a in the shallow trenches 206. The manner in which the 202 and the mask layer 204 are removed is, for example, a wet etching method. The invention firstly forms a gap on the side wall of a shallow trench to prevent oxidation of the side wall of the shallow trench, and at the same time exposes the substrate at the bottom of the shallow trench, and then performs a thermal oxidation process to the base of the bottom of the shallow trench. 'An oxide layer is formed in an unequal manner, and then a dielectric layer is placed in the shallow trench to form a shallow trench isolation. The invention first forms an oxide layer at the bottom of the shallow trench, so that the aspect ratio of the shallow trench can be greatly reduced, so that the subsequently formed dielectric layer can be easily broken into the shallow trench. Although the present invention has been disclosed in a preferred embodiment as above, it is not intended to limit the invention, and it is intended to be within the spirit and scope of the present invention. Various modifications and refinements are made, and the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are schematic cross-sectional views showing a manufacturing process of a conventional shallow trench isolation structure; and FIGS. 2A to 2F are diagrams showing a manufacturing process of a shallow trench isolation structure according to a preferred embodiment of the present invention. Schematic diagram of the section. [Main component symbol description] 100, 200, 200a · Base 102, 202: pad oxide layer 104, 204: mask layer 106, 206: shallow trench 108, 208: lining oxide layer 110, 214: oxide layer 210, 216 216a: dielectric layer 212, 212a: spacer 10