1312549 09889twf2.d〇c/〇〇6 96-4-20 九、發明1¾¾ 【發明所斷技術領域】 曰本發明是有關於一種積體電路元件的製造方法，且特 別是有關於〜種淺溝渠隔離結構（Shallow trench iSQlati〇n STI)的製造方法。 ， 【先前技術】 在半導體元件之積集度日趨緊密的今日，元件之間的 隔離變得十分重要’爲防止相鄰的元件發生短路，通常會 在其間加以一隔離層，其中製作隔離層最傳統普遍的技術 爲區域局部氧化法（LOCOS) ’而能夠以較低的成本獲得信 賴度高且有效之元件隔離結構。然而，區域局部氧化法仍 具有多項缺點’包括已知應力產生之相關問題，與LOCOS 場隔離結構之周圍鳥嘴區(bird’s beak)的形成等。特別是鳥 嘴區之形成，對元件積集度之提升造成妨礙，有鑑於此， 已有其他的元件隔離方法持續被發展出來，而現今應用最 廣泛的方法之一 ’即是利用形成淺溝渠隔離結構的方法以 製造元件的隔離結構。 第1A圖至第1C圖描述習知一種淺溝渠隔離結構製 程，請參照第1A圖，提供一個依序形成有墊氧化層(pad oxide layer)l〇2與氮化矽層1〇4的基底100，並定義蝕刻氮 化矽層104、墊氧化層1〇2與基底100以形成溝渠106。 接著’請參照第1B圖，使用熱氧化法於溝渠106之 內表面上進行氧化，得到一襯氧化層（liner oxide 96-4-20 layer)108，接著再沉積一層氧化層110以塡滿溝渠1〇6並 覆蓋於氮化矽層1〇4上。 接著，請參照第1C圖，對襯氧化層1〇8進行化學機 械硏磨（chemical mechanical polishing，CMP)，將氧化層 11〇 表面磨平至露出氮化矽層1(M以變成一氧化塡塞物110a。 接著，使用熱磷酸(hot phosphoric acid)去除氮化砂層1〇4， 然後使用氫氟酸(HF)去除墊氧化層102。 然而，在習知的淺溝渠隔離結構製程中，由於襯氧化 層108係藉由熱氧化溝渠106內的矽所形成，亦即是代表 必須消耗溝渠106內表面的砂以形成襯氧化層1 〇8，如此將 會使得淺溝渠隔離結構的輪廓與尺寸變大，使得實際可利 用之主動區域縮小以及增加設計、佈局上的變數，因而不 利於元件的縮小化。 而且，由於在去除氮化矽層104、墊氧化層1〇2的過 程中，會對氧化塡塞物110a的邊角侵飽而形成包覆圓化 (wrap rounding)現象進而造成凹陷m。此凹陷U2會累積 電荷’繼之在積體電路中造成元件的次臨限漏電流 (sub-threshold leakage current)，此即所謂的頸結效應（kink effect)，進而使得元件的可靠度與良率降低。 【發明內容】 因此’本發明的目的在提供一種淺溝渠隔離結構之製 造方法，能夠避免淺溝渠隔離結構的輪廓與尺寸變大，以 增加主動區域的可利用面積。 1312總—。6 96-4-20 本發明的另一目的在提出一種淺溝渠隔離結構制 電流。 免元件漏 本發明提出一種淺溝渠隔離結構之製造方法， 、 係在基底上依序形成墊氧化層和罩幕層，再依序定義執^ 化層、罩幕層和部分基底以形成溝渠，接著，在溝渠^執 面與罩幕層表面形成共形的緩衝層，再以熱氧化法g緩衝 層氧化爲氧化物層，然後，於淺溝渠內與基底上形成絕，緣 層以塡滿溝渠’再移除溝渠之外之絕緣層與氧化物層，直 至暴露出罩幕層表面’最後再移除罩幕層及墊氧化層以形 成淺溝渠隔離結構。 / 由上述可知，由於本發明係將另外形成的緩衝層氧化 以形成襯氧化層（氧化物層），因此襯氧化層的形成只會消耗 溝渠內表面極少的矽，從而使得淺溝渠隔離結構的輪廓與 尺寸不致變大太多，進而能夠得到較習知更大的主動區域。 而且，由於此氧化物層亦生成於墊氧化層與罩幕層之 側壁，尙且，由於此氧化物層係以熱氧化法所形成’因此 氧化物層的結構較爲緻密而具有較佳的抗蝕刻 (anti-etching)能力。因此，即使經由去除罩幕餍以及墊氧化 層的蝕刻製程，亦能夠保持較佳的絕緣塡塞物的完整性。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式’作詳 細說明如下： I312^twf2 .doc/006 96-4-20 【實施方式】 第2A圖至第2G圖係繪示根據本發明一較佳實施例之 一種淺溝渠隔離結構之製造流程的剖面示意圖。 首先，請參照第2A圖，提供一半導體基底2〇〇，接著 於半導體基底200上依序形成墊氧化層2〇2與罩幕層204。 其中形成墊氧化層202的方法例如是利用熱氧化法。且罩 幕層204的材質例如是氮化矽，形成罩幕層204的方法例 如是使用化學氣相沉積法（chemical vapor deposition，CVD) 形成一氮化砂層於墊氧化層202上。 接著，請參照第2B圖，去除部份的罩幕層204、墊氧 化層202以及基底200以形成溝渠206。其中形成溝渠206 的方法例如是在罩幕層204上形成圖案化之光阻層（未圖 示）。再以光阻層爲罩幕，以非等向性蝕刻法去除罩幕層 204、墊氧化層202與部分基底200以形成溝渠206。 接著，請參照第2C圖’於溝渠206內表面與覃幕層 2〇4表面形成共形的一緩衝層208，其中緩衝層208的材質 例如是採用可氧化的材質，較佳爲使用多晶矽，形成此緩 衝層208的方法例如是使用化學氣相沈積法，沈積一層多 晶矽層於溝渠206暴露出之矽基底200表面上、墊氧化層 202之側壁表面上以及罩幕層204之側壁及表面上。 接著，請參照第2D圖，將此緩衝層208轉變成氧化 物層208a，其中使緩衝層2〇8轉變成氧化物層208a的方 法，例如是使用熱氧化法氧化緩衝層208以形成氧化物層 208a。此時氧化物層208a即用以作爲此淺溝渠隔離結構的 8 f2 .doc/006 96-4-20 襯氧化層。 在上述第2C、2D圖的步驟中，由於作爲襯氧化層的 氧化物層208a主要係由形成於溝渠206內表面與覃幕層 204表面的緩衝層2〇8氧化而得，亦即是襯氧化層的形成只 會消耗溝渠2〇6中極少的矽基底200表面，因此淺溝渠隔 離結構的輪廓與尺寸因而不致變大太多，進而能夠得到較 習知更大的主動區域。 接著，請參照第2E圖，於基底200上形成一層絕緣 層210以塡滿溝渠2〇6並覆蓋整個基底200，其中絕緣餍 210的材質例如是氧化矽，形成此絕緣層210的方法例如是 使用局密度電獎化學氣相沈積法（high density plasma chemical vapor deposition, HDPCVD)以於基底上形成一氧 化砂層。 接著，請參照第2F圖，去除溝渠206之外的絕緣層 210與氧化物層2〇8a至露出罩幕層204的表面爲止，以形 成一平坦的絕緣塡塞物210a。其中去除部分的絕緣層210 與氧化物層的方法例如是以罩幕層2〇4爲硏磨終止 層，以化學機械硏磨法去除溝渠206之外的絕緣層210與 氧化物層208a，亦或是以罩幕層204爲蝕刻終止層，以非 等向性鈾刻法回蝕(etch back)去除溝渠206之外的絕緣層 210與氧化物層208a。 接著，請參照第2G圖，依序去除罩幕層2〇4以及墊 氧化層2〇2，以形成淺溝渠隔離結構。其中，去除罩幕層 2〇4的方法例如是使用熱磷酸浸蝕的濕式蝕刻法。去除墊氧 I31250紹 9twf2.doc/006 96-4-20 化層202的方法例如是以氫氟酸(HF)浸餓的濕式鈾刻法。 由於在第2D圖的步驟中所生成的氧化物層208a(襯氧 化層）不僅生成淺溝渠206所暴露出之矽基底表面上，亦生 成於墊氧化層202與罩幕層204之側壁，尙且，由於此氧 化物層208a係以熱氧化法所形成，氧化物層208a的結構 會較爲緻密而具有較佳的抗蝕刻（anti-etching)能力。因此， 即使經由去除罩幕層204以及墊氧化層202的鈾刻製程， 亦能夠保持較佳地絕緣塡塞物210a的完整性而不會造成嚴 重地凹陷現象。 綜上所述，本發明至少具有下述的優點： 1·由於本發明係在溝渠之內表面與罩幕層表面形成一 層緩衝層，再熱氧化此緩衝層以作爲襯氧化層，因此襯氧 化層的形成並只會消耗溝渠中極少的砂表面，從而使得所 形成之淺溝渠隔離結構的輪廓與尺寸不致變大太多，進而 能夠得到較習知更大的主動區域。 2·由於前述由緩衝層熱氧化所形成的氧化物層（襯氧 化層）不僅生成淺溝渠所暴露出之矽基底表面上，亦生成於 墊氧化層與罩幕層之側壁，尙且，由於以熱氧化法所形成 的襯氧化層其結構會較爲緻密而具有較佳的抗蝕刻能力。 因此，即使經由去除罩幕層以及墊氧化層的蝕刻製程，亦 能夠保持較佳地絕緣塡塞物的完整性而不會造成嚴重地凹 陷現象。 雖然本發明已以一較佳實施例揭露如上’然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 10 1312549 wf2.d〇c/〇〇6 96-4-20 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 第1A圖至第1C圖所繪示爲習知一種淺溝渠隔離結構 之製造流程的剖面示意圖；以及 第2A圖至第2G圖所繪示根據本發明一較佳實施例之 一種淺溝渠隔離結構之製造流程的剖面示意圖。 【主要元件符號說明】 100、200 :基底 102、202 :墊氧化層 104 :氮化矽層 106、206 :溝渠 108 :襯氧化層 110 :氧化層 110a :氧化塡充物 112 :凹陷 204 :罩幕層 208 :緩衝層 208a :氧化物層 210 :絕緣層 210a :絕緣塡塞物1312549 09889twf2.d〇c/〇〇6 96-4-20 IX. Invention 13⁄43⁄4 [Technical Field of the Invention] The present invention relates to a method of manufacturing an integrated circuit component, and in particular to a shallow trench Manufacturing method of the isolation structure (Shallow trench iSQlati〇n STI). [Prior Art] In today's increasingly tight integration of semiconductor components, isolation between components becomes very important. 'To prevent short-circuiting of adjacent components, an isolation layer is usually provided between them. The traditionally popular technique is Regional Local Oxidation (LOCOS), which enables highly reliable and efficient component isolation structures at a lower cost. However, the regional partial oxidation method still has a number of disadvantages' including problems associated with known stress generation, formation of bird's beak around the LOCOS field isolation structure, and the like. In particular, the formation of the bird's beak area has hampered the increase in component integration. In view of this, other component isolation methods have been developed, and one of the most widely used methods today is to use shallow trenches. A method of isolating a structure to fabricate an isolation structure of the component. 1A to 1C illustrate a conventional shallow trench isolation structure process. Referring to FIG. 1A, a substrate having a pad oxide layer 10 and a tantalum nitride layer 1〇4 is sequentially provided. 100, and defining an etched tantalum nitride layer 104, a pad oxide layer 1〇2 and a substrate 100 to form a trench 106. Then, please refer to FIG. 1B to perform oxidation on the inner surface of the trench 106 by thermal oxidation to obtain a liner oxide 96-4-20 layer 108, and then deposit an oxide layer 110 to fill the trench. 1〇6 and overlying the tantalum nitride layer 1〇4. Next, referring to FIG. 1C, a chemical mechanical polishing (CMP) is performed on the underlying oxide layer 1〇8, and the surface of the oxide layer 11 is smoothed to expose the tantalum nitride layer 1 (M to become niobium monoxide). Plug 110a. Next, the nitrid sand layer 1〇4 is removed using hot phosphoric acid, and then the pad oxide layer 102 is removed using hydrofluoric acid (HF). However, in the conventional shallow trench isolation structure process, The lining oxide layer 108 is formed by the ruthenium in the thermal oxidation trench 106, that is, the sand which must consume the inner surface of the trench 106 to form the lining oxide layer 1 〇8, which will make the outline and size of the shallow trench isolation structure As the size of the active area is reduced, and the variables in the design and layout are increased, it is not conducive to the reduction of components. Moreover, in the process of removing the tantalum nitride layer 104 and the pad oxide layer 1〇2, The wrap rounding phenomenon is formed on the corners of the yttrium oxide plug 110a to form a wrap rounding phenomenon, which causes the recess m. This recess U2 accumulates a charge' followed by a secondary leakage current of the element in the integrated circuit ( Sub-thr Eshold leakage current), which is the so-called kink effect, which in turn reduces the reliability and yield of the component. [Invention] Therefore, the object of the present invention is to provide a method for manufacturing a shallow trench isolation structure capable of Avoiding the contour and size of the shallow trench isolation structure to increase the available area of the active area. 1312 -6. 96-4-20 Another object of the present invention is to provide a shallow trench isolation structure for current production. The invention provides a method for manufacturing a shallow trench isolation structure, which sequentially forms a pad oxide layer and a mask layer on a substrate, and then sequentially defines an implementation layer, a mask layer and a part of the substrate to form a trench, and then The trench surface and the surface of the mask layer form a conformal buffer layer, and then the buffer layer is oxidized to an oxide layer by a thermal oxidation method, and then formed in the shallow trench and the substrate, and the edge layer is filled with a trench. The insulating layer and the oxide layer outside the trench are removed until the surface of the mask layer is exposed. Finally, the mask layer and the pad oxide layer are removed to form a shallow trench isolation structure. Since the present invention oxidizes the additionally formed buffer layer to form a liner oxide layer (oxide layer), the formation of the liner oxide layer only consumes very few defects on the inner surface of the trench, so that the contour and size of the shallow trench isolation structure are not changed. Too much, and thus a more active active region can be obtained. Moreover, since the oxide layer is also formed on the sidewalls of the pad oxide layer and the mask layer, and since the oxide layer is thermally oxidized Forming 'therefore the oxide layer is more dense and has better anti-etching ability. Therefore, even if the etching process is performed by removing the mask and the pad oxide layer, a better insulating plug can be maintained. The integrity of the object. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 4-20 Embodiments FIGS. 2A to 2G are schematic cross-sectional views showing a manufacturing process of a shallow trench isolation structure according to a preferred embodiment of the present invention. First, referring to FIG. 2A, a semiconductor substrate 2 is provided, and then a pad oxide layer 2〇2 and a mask layer 204 are sequentially formed on the semiconductor substrate 200. The method in which the pad oxide layer 202 is formed is, for example, a thermal oxidation method. Further, the material of the mask layer 204 is, for example, tantalum nitride. The method of forming the mask layer 204 is, for example, formation of a layer of nitriding sand on the pad oxide layer 202 by chemical vapor deposition (CVD). Next, referring to FIG. 2B, a portion of the mask layer 204, the pad oxide layer 202, and the substrate 200 are removed to form the trench 206. The method in which the trench 206 is formed is, for example, to form a patterned photoresist layer (not shown) on the mask layer 204. The mask layer 204, the pad oxide layer 202 and a portion of the substrate 200 are removed by an anisotropic etching to form the trench 206 by using a photoresist layer as a mask. Next, please refer to FIG. 2C' to form a buffer layer 208 conforming to the surface of the trench 206 and the surface of the curtain layer 2〇4. The material of the buffer layer 208 is, for example, an oxidizable material, preferably polycrystalline germanium. The method of forming the buffer layer 208 is, for example, using a chemical vapor deposition method to deposit a polysilicon layer on the surface of the germanium substrate 200 exposed by the trench 206, on the sidewall surface of the pad oxide layer 202, and on the sidewalls and surfaces of the mask layer 204. . Next, referring to FIG. 2D, the buffer layer 208 is converted into an oxide layer 208a, wherein the buffer layer 2〇8 is converted into the oxide layer 208a, for example, by oxidizing the buffer layer 208 to form an oxide using thermal oxidation. Layer 208a. At this time, the oxide layer 208a is used as the 8 f2 .doc/006 96-4-20 lining oxide layer of the shallow trench isolation structure. In the steps of the second and second embodiments, the oxide layer 208a as the lining oxide layer is mainly oxidized by the buffer layer 2〇8 formed on the inner surface of the trench 206 and the surface of the curtain layer 204, that is, the lining. The formation of the oxide layer only consumes very few of the surface of the crucible substrate 200 in the trench 2〇6, so that the outline and size of the shallow trench isolation structure are not so large, and a more active active region can be obtained. Next, referring to FIG. 2E, an insulating layer 210 is formed on the substrate 200 to fill the trenches 2〇6 and cover the entire substrate 200. The material of the insulating germanium 210 is, for example, tantalum oxide. The method for forming the insulating layer 210 is, for example, A high density plasma chemical vapor deposition (HDPCVD) is used to form a layer of oxidized sand on the substrate. Next, referring to FIG. 2F, the insulating layer 210 and the oxide layer 2〇8a outside the trench 206 are removed to expose the surface of the mask layer 204 to form a flat insulating plug 210a. The method for removing a portion of the insulating layer 210 and the oxide layer is, for example, using the mask layer 2〇4 as a honing stop layer, and removing the insulating layer 210 and the oxide layer 208a outside the trench 206 by chemical mechanical honing. Alternatively, the mask layer 204 is used as an etch stop layer, and the insulating layer 210 and the oxide layer 208a outside the trench 206 are removed by an anisotropic uranium etch back. Next, referring to Fig. 2G, the mask layer 2〇4 and the pad oxide layer 2〇2 are sequentially removed to form a shallow trench isolation structure. Among them, the method of removing the mask layer 2〇4 is, for example, a wet etching method using hot phosphoric acid etching. Removal of Oxygen I31250 绍 9twf2.doc/006 96-4-20 The method of layer 202 is, for example, a wet uranium engraving method in which hydrofluoric acid (HF) is immersed. Since the oxide layer 208a (liner oxide layer) generated in the step of FIG. 2D is not only formed on the surface of the germanium substrate exposed by the shallow trench 206, but also formed on the sidewalls of the pad oxide layer 202 and the mask layer 204, Moreover, since the oxide layer 208a is formed by thermal oxidation, the structure of the oxide layer 208a is denser and has better anti-etching ability. Therefore, even by the uranium engraving process of removing the mask layer 204 and the pad oxide layer 202, it is possible to maintain the integrity of the insulating plug 210a without causing severe dishing. In summary, the present invention has at least the following advantages: 1. The present invention forms a buffer layer on the inner surface of the trench and the surface of the mask layer, and then thermally oxidizes the buffer layer to serve as a liner oxide layer, thereby lining oxidation. The formation of the layer only consumes very little sand surface in the trench, so that the contour and size of the formed shallow trench isolation structure does not become too large, and a more active active region can be obtained. 2. The oxide layer (liner oxide layer) formed by the thermal oxidation of the buffer layer is not only formed on the surface of the germanium substrate exposed by the shallow trench, but also formed on the sidewall of the pad oxide layer and the mask layer, and The lining oxide layer formed by the thermal oxidation method is denser in structure and has better etching resistance. Therefore, even by the etching process of removing the mask layer and the pad oxide layer, it is possible to maintain the integrity of the insulating dam plug without causing a serious recess. Although the present invention has been disclosed in a preferred embodiment as described above, it is not intended to limit the invention, and anyone skilled in the art, without departing from the essence of the invention, 10 1312549 wf2.d〇c/〇〇6 96-4- 20 The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are schematic cross-sectional views showing a manufacturing process of a conventional shallow trench isolation structure; and FIGS. 2A to 2G are diagrams showing a preferred embodiment of the present invention. A schematic cross-sectional view of a manufacturing process for a shallow trench isolation structure. [Main component symbol description] 100, 200: substrate 102, 202: pad oxide layer 104: tantalum nitride layer 106, 206: trench 108: lining oxide layer 110: oxide layer 110a: yttrium oxide filling 112: recess 204: cover Curtain layer 208: buffer layer 208a: oxide layer 210: insulating layer 210a: insulating plug