TWI245912B - Circuit testing with ring-connected test instrument modules - Google Patents

Abstract

Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Description

1245912 发明. Description of the invention [Technical field to which the invention belongs] The present invention relates to the testing of electronic circuits such as integrated circuits. [Previous Technology] Test equipment is usually used to electrically test the ability of an assembled circuit to perform its preset functions. Devices designed to test integrated circuits are often operated in conjunction with other devices, such as computer devices. These devices and other devices are commonly referred to as integrated circuit test systems or test systems. A unique feature of traditional test systems is that they include one or several main clock signals, and they also tend to include at least one synchronization signal. This signal will wait for execution in the pipeline at the same time or sequentially, and is distributed to all test circuits as a whole. To indicate when a test will begin. Testing of integrated circuits generally involves applying a specific stimuli to one or more of the pins of the circuit, and then obtaining signals from one or more of the pins of the circuit by appropriate measuring equipment to determine the result. . A test system usually incorporates all required test circuits in close proximity to the circuit under test and is driven by an external controller that communicates the requirements of the test to the most diverse test circuit and collects the results of the test. The function of the test circuit is to generate any or a large number of stimuli, and to control any or a large number of measurements as required by the test details of the circuit under test. [Summary] The systems and technologies described herein provide devices and methods, including computer programs 3, 1245912-type products and test systems' for performing any one or more of a wide variety of tests-for example, AC parameters, DC parameters, Digital functional, SCAN-based structural, Direct-Access-Test mode structural > Analog, functional, structural, operational or other testing On a single or multiple circuits. Generally speaking, in one aspect, the systems and techniques described herein provide a control and data signal distribution architecture that allows a test system to perform measurements simultaneously on one or more test devices without the need for a main clock Distribute any signal at the same time as the device in the system. A test device, possibly implemented in a module ' typically includes a test circuit system as described above. A modularized test equipment is commonly referred to as a test equipment module. In addition to including test equipment modules, this test system can include modules with other functions. These other modules include, but are not limited to, pin electronics (pE) modules, 'precision measurement unit (PMU) modules, and time measurement unit (TMU) modules. Modules, and device power supply (DPS) modules. Generally speaking, attack modules can provide any testing function, and any number and form of modules can be combined to form a multifunctional module. In addition to having different functions, the modules can be configured differently. In the embodiment, the module is an arrangement of chip pins (p i n s 1 i c e). This type of drum is only known as a chip pin module, and each of them contains a memory, a resistance spear 1 thunder / I tower system, and is used to generate a test signal to a component during the test. Yes — 5 'eve. This patch pin configuration is described in US Patent No. 5,461,310, owned by Cheung and Graeve. ~ The test equipment of the test equipment is prepared. The module does not consider the configuration and function. The module usually contains a circuit system for receiving a main clock signal from a main clock source, and even the receiving and sending numbers. The electric coil system is a component of a communication ring. The control and signal signal distribution architecture described here allows communication between the modules of the test system, except for the main clock, which does not require the assignment of any signals simultaneously to all such devices in the system. In general, on the other hand, a control and data distribution framework provides the ability to schedule different and unrelated tests for similar or non-similar devices, even when the execution times of these tests overlap. Does not interfere with the test of another device in time or space. The architecture described here also provides the ability to derive funding from most modules in an interleaved and structured format. The architecture described here allows the test process to be summarized by a test device with a standard structure. This device is consistent in physical dimensions (physica 1 dimensi ο η), power requirements, communication connections, etc., and is the same as the one being tested. Or many pins (contacts) connected. Furthermore, one or all of the test process can be used off-the-shelf as a communication device, and the communication ring is used in other parts of the test system. As discussed above, the test equipment can be used as a module, whether it is ready or not. Any group can appear anywhere in the communication ring arrangement. Each module can be operated as an independent module and includes the ability of the module to self-test and diagnose. A test equipment module described herein that is designed to operate in a test system may include circuitry to perform tests for which the test equipment module is designed. In the central part of the system, it can form some special test systems first, and then link and pass other models or control the power supply standby or electrical operation when there is no master control. Under the control of the test controller and a system clock, The test equipment modules of the test system can perform tests independently or synchronously with some or all other modules in the system. A test system so configured uses as few equipment modules as there are one or most of these test equipment modules, and usually as many as necessary, for the operation of the test to test a certain single or majority of integrated circuits . ,, first in all the modules. The module is connected to a ring configuration. The "from" port of a second module is used to connect the "to (t0)" port of a second module to the "start" port of the second module to a third module. The "to" port continues until the last module is connected, and the "start" port of the last module is supplemented to the "to" port of the first module. The data communication port will control and synchronize the signal along the module's ring, so that each module can operate with any or all of the groups in the ring as I # 4,, ". The main clock and test control of the system Device can be: Tian Zuo M group is included in the ring. In either case, the test system pulse will be the main B, and the clock signal will be given to all the modules, and the test system will usually communicate in the initial ring. The module can be connected to one or the scrambled pins. One or more signals or special features of a test device, such as a test equipment module, depends on the setting of the JW function. Or change the current according to time to supply current I and guarantee two SI flows: electricity [Each module can be according to the scheduled information. Each module has-internal time == appropriate time to execute the test 4 test instructions; r temporary storage The theft and scheduled information can include the internal time value register is driven by the main clock 6 1245912 and synchronized with the time value register of other modules in the test system. This synchronization allows all modules to Implement test events in synchronization with the time when other module test activities in the system are implemented Or perform measurement. Because the test equipment module can generate high-resolution time signals internally, the synchronization can be performed at a time resolution that is very less than a main clock cycle, and at the skew of the scheduled test (skew ) Or other devices in the system are also less than one clock cycle. On the other hand, a system that controls one or more test devices to test one or more integrated circuits usually includes a main clock and a control The test equipment is connected to form a communication ring. The main clock is connected to each test device and is configured to provide a clock signal to one or more test devices. The controller is connected to the communication ring and is configured to calibrate The counter of the test equipment enables it to obtain a common clock time value from the clock signal. The controller is also used to generate and send data words into the communication ring to communicate the data characters to the test equipment. The data character contains at least one data character indicating an executed test event, a common clock time value, and at least one test device, at least one or more of which The test equipment is configured to execute test events at the time specified by the common clock time value. On the other hand, in general, the data and control signal distribution system in an automatic circuit test system includes a communication ring, a main Clock and a dedicated clock signal path between each device in the test system and the main clock circuit. The test system contains test equipment for testing electronic circuits. The communication ring integrates the system in the form of a Daisy Chain The test equipment is coupled to each other, and the communication ring is configured to connect 1245912 test equipment from a single input port and a single output port. The main clock circuit is very suitable for a main clock signal. The dedicated time signal path simultaneously distributes the main clock signal To all test equipment. The communication ring is the exclusive channel of the test equipment in the test system. When a test is performed, the synchronization signal and the command signal are sent to each other, and the main clock signal received from a dedicated signal path is provided to the test. Exclusive universal clock signal for test equipment in the system. On the other hand, in general, a computer program product is used to control one or more modules configured to test one or more integrated circuits according to a test process. The product includes a process The device executes the following instructions: confirms at least one of the one or more modules participating in the test process; confirms a test thread belonging to the confirmed device in an independent test thread, and the test thread includes An instruction to generate data characters to be sent to other modules; and send a test thread to the confirmed device. The process is tangibly stored on a machine-readable medium. On the other hand, in general, a method for controlling and synchronizing one or more test devices includes using a common clock signal of a main clock to set and maintain an internal time register pair of each test device. Synchronization of a common clock cycle, which provides a common clock time value for the scheduled test events. The test equipment is connected in a communication ring to test an electronic circuit. This method includes inserting a bus character into a communication ring, transmitting the bus character to each test device, the inserted bus character including at least one bus character, and specifying a scheduled shared clock time value for a target test device to execute A test event. This method involves using the target test equipment to read 8 1245912 out of the internal / busbar test equipment to determine when to perform the test. The advantages of the system described here. The test system can be signaled. No need for system integration. It is possible to arrange similar or non-execution of these tests. Time or space interference. There is a staggered and structured test system that can be extended by the package group. Perform multiple sequential arrangements. These or a group of similar devices are applied to different devices. The system can be used for co-location. The test system enables data to be obtained from the module. A test system controller does not have many high-resolution and many modules synchronized to match the accuracy and accuracy of each unit, and uses a common event in a scheduled common time register. . Systems and techniques can be applied to simultaneously test one or more modules with any differences and similarities between all modules and similar devices, testing one device at a time. Most modules in this format have one or more pins that provide additional definitions and scheduling rules. These tests are combined with independent tests, and the tests can be related to each other, or they can be on the same device. The data characters of different parts of the product testing and diagnosis results can be composed and used as data. Apply this method to measure the timing of luxury signal distribution with good resolution. The accuracy of synchronized stand-alone modules is limited by the clock time value and clock cycle value to determine one or more of the following groups, except for the signal of a main clock. The test system is related to the test, and even if the test is installed, the test system can provide data capabilities. Measuring stimuli or measuring modules. Synchronize and link any kind of module. It is not necessary that these tests be applied to a single device that is not related or separable from each other. In particular, this break test is presented to the test system from a large number of single characters at a similar installation point in time. Compared to a cycle, arbitrary accuracy can be made only by clock division. Even if a synchronous operation 9 1245912 is in progress' at the same time, any module of the test system can introduce a message into the serial loop. Details of one or more embodiments are set forth in the accompanying drawings and description below. Other features and advantages will be presented in the narrative, drawings, and patent applications. [Embodiment] Test System Overview As shown in Figure 1, a test system 100 includes a test controller 102, which controls the test processing process, including dispatching test functions and synchronizing their execution. In order to communicate with other components of the test system 100, the test controller 102 includes an interface unit 104. In the embodiment illustrated in FIG. 1, the test system 100 has a test head 100 as a traditional pin module, such as a device module, a PE module, a TMU module, and a PMU module. Groups and DSP modules can be physically installed. When the system is configured to test one or more circuits, this module will include a test head interface 106 (THIF), one or more test circuit system modules, such as a piece of pin module 1 0 8, and usually one or more power modules, such as a DP S module 1 1 0. The test head interface 106 differs from other modules in that it does not need to include test equipment that provides signals to or measures signals from a circuit under test. The module as the test head interface is used to make the communication between the test controller 102 and other modules easy. Although specific modules have been described, the test system 100 can be combined with any number of 10 1245912 and what type of module meets the dimensions and connection standards of the test system design. These standards are described below. The test system 100 also includes a systemic cancer monitor (s y s t e m s t a t u s m ο n i t or r, SM). This SM does not participate in the test 'but is configured to program the programmable components, such as Field-Programmable Gate Arrays (FPGAs) contained in individual modules, which are used to receive module detection To any status signal indicated by a fault such as a power failure or overheating condition, and a reset command will be issued in case the detected status is true. In one embodiment, the communication of the system status monitoring may be completed by a data character called a SM message or character. The test system 100 includes a controller connection 2 for communication between the test controller 100 and the module of the test system 100. The test system 丨 〇〇 also includes a serial communication ring 1 1 4 for communication between the modules, and also for communication between the module and the test-type controller 102. Connect the transmission port of one module to the receiving port of the other module until all the modules are included in it to establish the ring 1 1 4. Then, the transmission port of the last module is connected to the reception port of the first module to form a ring configuration. In one embodiment, the ring 114 supports a transmission rate of 8 million bits per second (MB / s). Ideally, connection 112 supports the same transmission rate as ring 1 1 4. The test system also includes an SM connection for exchanging status monitoring messages between the test controller tool 02 and the branch group. & sm connection includes the connection η2, the control module 1 02 receives and sends signals to the test interface i 04, and the: the test head interface 106 propagates the communication connection between the test controller 102 and the module 1 1 6. Λ SM connection can also be selected to connect directly to the 1245912 test controller 1 1 2 and each module with a unique line. SM messages can be passed from or through serial communication rings like other data characters. The system 100 includes a system main clock 107, which is illustrated in the test head interface module. The main clock of the system can also be included in any other module, or it can be provided as a completely independent device without being connected to the test system. The module that owns the master clock is the master clock module. The main clock module generates a main clock signal (the pulse); and simultaneously and directly assigns the signal group with the ^ pulse connection, the connection is connected to the controller 1 1 2, the ring i 丨 4 and the connection 1 i 6 Clock connection 1 1 7 can be implemented by a cable from the main clock module to each other module. During operation, the test controller 102 and the main clock module — control and synchronize all the modules. Test The controller 102 requires the control module to be executed, and instructs the modules to perform their respective tests and then to eliminate the power. The test controller 102 guides to the module, reads 屮, and ^ δ-type board groups. Test results and transfer instructions. Test the controller from its connection

The word enters the communication ring, and M ^ ^ passes its control signal. In the system, all the systems communicate with Tian Tian and Shi “5. The data characters inserted in the ring can be used to communicate with any other components. Bekozi 109, ^ 丨 仟 扪 Use this technology to communicate. 口 口 102 的 一Control the ten head test head interface 1 00 114. A packet containing the data word SM connection for any A group command is selected in the example, except that the group is said to "separate each mode when the master. Coaxial electrical operation to The control includes an example of sending data according to the specified time test operation. The test control communication ring is called a 12 1245912 control data character. The control data character can indicate a write or operation. The control data character will be described below. There are more descriptions. Generally, the controller 102 generates control data characters. The synchronization data characters can be 108 and 1 10, which are generated during the test execution and during the test process. You can also choose one. Or more modules to generate a control element. For example, a first module can generate a register of control data characters and a second module. Furthermore, in this alternative, , Test controller 1 02 can be generated together Step characters. The test head interface 1 06 will respond to a command from the test controller 102 to synchronize all the modules into a common clock cycle. Then the main distribution allows the modules to synchronize themselves to a Better resolution. Synchronization of the resolution of the sub-clock cycle enables all execution time related to the test activities of other modules in the system. This correlation includes a time period that is much less than a clock cycle. The ability to set a test or measurement, and the measurement of other modules in the skew system that is scheduled for testing is also less than a clock cycle. During a test process, the modules coordinate with each other according to the test process being performed. The test is performed. The module uses the main clock signal and the test guidelines received by the controller 102 to coordinate. As set in the discussion, it synchronizes into a common clock cycle, and it synchronizes according to the main clock (sub-cyc 1 e ) Resolution. The module uses the synchronized data characters sent to and received by the communication ring to confirm an event of a test process. The same character can therefore be entered by any module into the ring 11 4. It will be more funded below More descriptions of the material characters. Read out that the equipment calls them data words to read the clock cycle module test power resolution rate of the specific clock of the embodiment or the processing. Once a week 114, the data pair is synchronized. 13 1245912 Once a data character reaches the communication ring 1 1 4, ring 1 1 4 transmits the data character along the module ring. In each main clock cycle, a data character usually travels to The next slot, the slot can be a downstream module, or if a module has multiple pipelines and stages of data characters, it can be the next pipeline stage in the module. A last stage stored in a module The data characters are sent to adjacent downstream modules. Therefore, when a module has multiple pipeline stages, each pipeline stage stores one data character in one main clock cycle. There are more descriptions of pipeline classes below. A module can also temporarily store data characters during processing up to a certain maximum time. The maximum value is determined by the system's configuration and operating parameters, and is designed to prevent bus timeouts. After the processing is completed, the module returns the data character to the communication ring. When each module receives a data character and the data character is sent back to the original module, one cycle is counted as complete. A module corresponds to and performs test functions based on received data characters, including waiting for the appropriate time to execute and coordinate with any or all other modules. In an alternative embodiment, the system main clock can be placed, so it is not part of any module in ring 1 1 4 or the test controller 10 2 can be included in ring 1 1 4. In all options, the system main clock simultaneously distributes a clock signal to all devices. The test controller 102 usually starts and terminates the control communication in the ring, and any device can insert synchronous data characters into the ring. Method for testing one or more circuits 14 1245912 Figure 2 shows a method for testing one or more circuits. A test system, as shown in Figure 1, executes method 200 to determine the placement of the module ring (step 202). As discussed, this ring may contain any number and type of test equipment used to test one or more circuits. In one implementation, a test controller, such as test controller 102 (Figure i), determines the type of test equipment, the location of the test equipment in the ring, and the ring delay. There will be more descriptions of bad delay decisions. The test controller also performs other decisions known in the art. Test the system stylized module (step 204). Stylization includes stylizing the pulse offset value into the module, allocating resources and function codes, and configuring the device for mapping using read back data. In the following, there will be more descriptions of the clock offset value, code allocation, and read back data. The measurement and subtraction system performs a universal clock counter calibration (step 206). The pulse counter calibration is also called synchronizing to a common clock cycle. The calibration allows the modules to set their respective counters to count the same on the exact clock edge. For example, at the same time, all counts will reach one count and five. In one embodiment, the test controller uses a main clock, such as the main clock 107 (FIG. 1), to perform universal clock calibration. The controller 102 broadcasts a message and uses the mechanism described above to restart the counters for each clock. Because the topology of the module ring is known, the delay between the time when a newly activated message is sent and the time it reaches a specified module is known. Therefore, the test controller can program the modules with a representative delay clock offset value. The module can use the clock offset value during the restart operation to delay restarting its counter. Use this test configuration to determine what can be done at any time. Use the quasi-phase control method 15 1245912 method, test each module of the system, and start their own counters at exactly the same clock edge. Zero, or any other meter test system can be selected to perform the test process and collection test (I 2 0 8). As discussed, the test process may include performing one or more test operations with one or more. In one embodiment, the test control command is sent to the device to control the test process and to collect test information. The device itself can send characters, such as part of each other or to the test controller to perform the test. The characters in the test step are freely interchangeable with other types of characters. Common Module Architecture FIG. 3 illustrates an embodiment of a common module architecture 300. The architecture 300 includes a bus and a synchronous interface 300, which is implemented on a FGPA. The bus and interface 302 provides an interface "start" and "to". In order to support the bus with the CPU3 10 and the interface 3 02 there is an interface with the CPU bus 3 12 and the interface 302 also has an interface to receive the main clock signal 1 1 7 divided by two divided by two. With a main clock input of 400 million rhymes, the divider 3 14 will provide a main component of 200 MHz. When the main clock signal is 200MHz, you can choose 3 1 4. Alternatively, an architecture can be used to provide a circuit pulse signal, such as a multiplier. The bus and interface 302 are also configured to control data character bits to the module's appropriate circuitry. For example, it provides an interface to a bit, which bit represents a confirmed margin, multiples. "Material (steps with multiple devices to send material to the device. During the step character, the same, as it can be used in the ring 1 1 4 a module, the bus device 3 14 to 14; z (MHz) hours The pulse mode needs to be divided to double the timing. For example, the synchronization type 16 1245912 304, a confirmed synchronization accurate time 3 06, and a synchronization requirement 3 08. The sink, charge, and interface 302 has a board level (Board- level) interface supporting signals. — The chip pin module will include a memory control circuit system 3 1 6 which is configured to synchronize the chip pin with the rest of the test system, and store the test Function and implementation data. The bus and interface 3 0 2 can also be programmed or included in the circuit system to perform other operations described in this manual. Control and control data characters ^ Figure 4A shows An embodiment of a control data character includes two parts, a bus interface part and a function-resource (F / D) or data part. The first part, character 3 2-3 5 to make the module ready to receive the first parts list The second component, characters 0-3 1, contains data indicating a resource, function, or both. Therefore, the function-resource component indicates those that will be read or written by subsequent control data cycles. Resources or functions in the bus interface component. If the read / write (R / W) bit is 1, it indicates a read cycle, and 0 indicates a write cycle. A control data word indicates a write operation. The element is called a write control data character, and a control data character that indicates a read operation is called a read control data character. If the F / D bit is 1, it means a work and goods; Cycle, and 0 represents a data cycle. A data cycle is a read cycle or a write cycle. If F / D is!, Then R / W must be 0. The graphic format allows future expansion and allows modules such as The chip pins generate and send data characters. Therefore, the original character 17 1245912 34-3 5 is 00. The start of a read cycle and the right time ..._ All data bits with Bezier TL are Zero. Each addressed module executes an np 〇R plane for the data stored and received by it. Data bit. A p — u ^ address group can delay the transmission of the periodic characters (observe some maximum value J. This maximum value is determined by the requirements of the test controller and is set to prevent auditing. , Gu Can, and people meet. Generally, it will be less than one millisecond to allow the operation of the inner Λ neighbouring sheet pins (pins 1 ice) can occur. Ring 114 has many slots, and one slot occupies the ring S1. The slot in the communication ring can be empty and filled by any module. Figure 4B shows an empty child element 32-37 including the empty character mark "quot.00〇〇〇〇11 ,. Fig. 5 shows an embodiment format of a functional resource component. (A resource is called an I module, and a function is called a test event). When the test controller 102 changes the test character, the test head interface 106 sends the data character to the communication ring 114. As shown, the function code A is 16 bits. Each device decodes a specific common register on page zero (ie, function code 0000-00 3F). Other function codes required by a particular type of device can be assigned by the authority during an assignment process. The resource code is 5 bits, which is suitable for addressing about 32,000 resources. When G = 丨, the position of a group represents a group of resources. All modules provide at least 4,000 location decodes. Any device will provide less than a maximum of 32,000 decodes'. It must be determined that the most significant bits (MSBs) are zero. The special resource code 0xFFFF is decoded by all facilities to mean "all resources". The resource code OxFFFF is reserved for logical manipulation of participate masks. The logical operation of the shared mask is described in more detail in U.S. Patent No. 4,493, 〇79 by Hughes, which is fully incorporated herein by reference. When G = 〇, bits 3 0-16 are resource digital codes as follows: 〇〇〇〇— 〇〇F 〇 is a hard-coded slot number (0-253), and 0100- 7FFF is a channel number, which is assigned by software according to the device. The function and resource code allocation will be described in more detail later. Hard-coded slot addressing only requires access to the page 0 registers required by other parts of the configuration process, including installation of "channel number" -based decoding. The resource code can also be 13 bits, suitable for addressing 8 1 9 2 resources. When G-1 ’a group of addresses represents a group of resources. In this case, all models provide a maximum of 8K position decodings. When G = 0, bits 16-21 are pin numbers (0-63), and bits 22-2 8 are chip pin numbers (0-: 126). This format offers the possibility to consider expansion. The chip pin number 127 indicates access to one of the 64 modules, such as DPSs that are not chip pins. Free characters are available for future expansion, so they are 00. The specific embodiments described above are not limited to resources and function codes. Rather, resources and function codes can be coded in various ways to indicate specific modules, module components, and their respective functions. Allocation of resource codes In order to ensure the effective use of limited addressing space and even allow the development of third-party (thii * d-party) equipment, the test controller 10 can be used to allocate functions and resource codes at runtime during runtime configuration software space. 19 1245912 The range is to make Γ through 苐. For example, the program can be digitized before it can be completed. In the embodiment, each device type can be assigned a unique function code ′ in the 16-bit space 0040-FFBF. The range FFCO-FFFF area unit 104 (Figure 1) is reserved. The required connection code number can be created using the FUNCBASEADDR (function base address) page 0 register. All devices of the same type require the same number of registers. Each individual device is assigned a unique range of resource codes, ranging from 15 digits to a channel number of 0100-7FFF. The required connection code number can be created using the register RESBASEADDR (resource base address) on page 〇. The controller on page 0 is written by software, such as a computer that tests the controller ’and is used to give functions and resource codes an assigned start address. Function codes start in any position. However, the resource code can be configured at a huge start. That's because they must be a large number of multiples of equal or large length. Both resources and function codes occupy a single block. Use any feature or resource code that exceeds the required length. The δ-type control benefit 102 is not made to wait for the write cycle as usual (write cycle-the write control data character passes through the communication ring 丨 J 4 and the save cycle is a read control data character passes through the communication ring I) Write operations are as fast as they are received by the test controller. However, 'modules are not required to write at a maximum 200MHz rate. They can decide the process independently and regionally, and even use different times for different functions. In order to achieve 20 1245912 this kind of flexibility without using software to consume time 'I modules have their own first-in-first-out (FIFO) crying temporarily | Slave; θ state as a buffer for the write cycle . In order to avoid the overflow of the claws, the basic F's overflow control technology is used by each module as described below. In one embodiment, the FIF of each module is 2K (kilobytes). Capacity. When a module's fif0 reaches a threshold that is almost full, such as 75%, a "stop flow control data character and the module's confirmation are sent to the test head T interface 106. The test header δ 106 eliminates all such words & and uses some exception mechanisms such as a stop notification to stop the test controller 10 from sending more written data characters. Once the Fif〇 drops When the restart threshold is reached, such as when 70% is full, the module sends a "restart" process control word A 'and then resumes normal operation. Therefore, timeouts and bus errors can be avoided. 帛 6 The figure shows the _writer process control data characters.-A stop / restart (stOp / Resume (S / R) value is "stop" when the value is ι, and an S / R value of 0 is "restart". The read operation is likely to overtake the write operation due to buffering. Unexpected results. At this point, the module needs to stop the read operation until all pending writes have occurred.-The occurrence of writes will be defined according to each module and each function. Then @, at least temporarily stored After the device is written, it will be read out with the register to ensure that new written data will be read back. The overflow control mechanism described here has a significant impact on performance. Therefore, other methods are used to avoid approaching the overflow. Bit (near_〇verfi〇w) status, for example, the auditing software process generates sequential writes to ensure that the processing is successful, or provides sufficient FIFO memory. The readback mapping is to support more than most devices. Data characters are read back, some mappings of the read back data, such as those captured random access memory (RAM), are used to support certain digital modules. The This feature is especially used to reorganize the digitized analog samples captured by most digital pins. The reorganization is performed by using the reconstructed sampling characters to turn the read operation around the serial communication ring 1 1 4 The process (Figure 1). The characteristics can be combined with the following description of the conversion features related to upHnking. The device can insert characters at any position of the combined characters. The extraction can be rotated Based on the mask, it effectively makes the captured data non-successful. DMA read mode In order to increase the speed of block read, you can use _direct memory access (direct CCAM) DMA read mode. In the .A readout mode, 'except for the interface unit 104 and the test head interface 10', there is no ... to perform the readout operation differently. Θ The interface unit 104 uses a nickname to start addressing from the special DMA (DMA-start -address) register and _ DMa m ^,. T A (counter register). If these registers are earlier than a read operation) are temporarily repeated a specific number of times (as indicated by the count value), the memory of the controller will start to be loaded into the test at a specific position The use of this mode will be restricted, so in reading mode 22 1245912, other test controller bus operations will become impossible. However, it is possible to perform a synchronous operation in the DMA read mode. A DMA operation can be directly followed by an operation that is not DMA. This operation can be sent to the serial communication ring 1 1 4 without waiting for the result of DMA reading. DMA write mode DMA write mode is similar to DMA read mode, except that in write mode, data is sent from the test controller to a module. In order to speed up the loading of the memory, the test head interface 106 may include a data decompression program to decompress the compressed data sent from the test controller 102. Decompression can be achieved with ordinary write operations. Neither the interface unit 104 nor the device need to perform special steps; the test head interface 106 implements this feature. Each module can optionally include a decompression program, so the test head interface 106 does not need to excessively consume computing resources to decompress all data from the test head controller. Bus interface performance The latency of normal writing is variable and depends on the position of the module in the ring relative to the test head interface 106. A normal write is from the controller 102 to the memory in the module. The normal waiting time for reading from chip pins, for example, is mainly determined by the number of modules and the number of pipeline stages in each module. A normal readout is when the test controller 102 initiates a readout request and a module receives a data character. A pipeline class can be referred to as a buffer in a module to hold and process data characters. As discussed, each time the module ticks, the module moves the data characters from one pipeline stage to the next 23 2345912 line. In one embodiment, there are 64 modules and each module has 2 pipelines. The waiting time for readout is close to 65 nanoseconds (ns). The test system can maintain a circulation of 800MB / S for the same resource, and the read and write operations and a specific test function (assuming that the module and test controller 102 can go hand in hand, and no synchronization activity will waste bandwidth) . Multiple device testing and location selection As is well known in the art, test systems are often used to test one device at a time (ie, parallel testing). An embodiment of the test system 100 uses individual software threads for each location to support most test locations, making testing easy. If the device under test occupies this location or an error occurs, it needs to be tested again to determine whether the location is valid or invalid, but it must be fixed until a multi-site handler can remove them. The tester uses shared memory and a special software tool called a position mask) to provide simultaneous register writes to all locations and all resources. The test system can support independent test head register access thread. The access thread contains its own resource code and location mask. For each implementation, the test head interface 104 maintains an independent current position digital temporary register. The position mask register allows 1K positions.

When needed, the test controller will automatically update the current resource code mask. The test controller performs an update following a thread exchanger earlier than the first or write operation. Not all positions of the position mask are written; they must start at zero. The device can support all 1 K levels. The test and control devices are not only tested and not maintained to move (site effect bit. Each source and bit readout can be in position 24 1245912, but it must support at least 2 5 6. And the position numbers and masks must be fully decoded. Synchronous operation and synchronization character test controller 102 and all synchronization between modules use the same communication ring and message protocol. Test controller 102 and any module A sync character can be used with a proper internal purpose, or a sync character can be generated. Any part of the test system can generate a sync character. There are some and certain sync characters. A certain sync character can be obtained from A part of the synchronization character may be generated directly. A certain synchronization character is a message indicating a specific synchronization event, such as a test function, which has been determined to have occurred. A certain synchronization character gives the time when the event occurred. .Universal synchronization, such as start, stop, and failure, are special cases that determine synchronization. A certain synchronization character will be terminated in the ring by the module that generated it. Part Synchronization is when the system 100 coordinates one or more events when information needs to be executed. Through this system's mechanism, it is distributed across two or more modules. Part of the synchronization combines information that spans most modules. This is possible Features of selection. Part of the synchronization combined pins span most modules, so a synchronization event will only occur when all the pins are in a previously defined type, or some other series of simultaneous conditions will occur. Test Head Interface 1 〇6 can monitor all confirmed synchronizations, including failures, for debugging and process control. All confirmed synchronizations are passed to memory control devices, such as the memory controller 216 used by them if appropriate. At the same time, For accurate event localization, 25-1245912 (that is, the second clock cycle time) of the precise resolution event is also transmitted to all devices in the ring. For the synchronization of the silt part, the test system 100 did not transmit the accurate event time. Section 7 The figure shows an embodiment of a certain synchronization character. "Type" represents the type of the event to be synchronized, and in one embodiment, it is A 4-bit synchronization type. In this embodiment, there are at least fifteen independent general-purpose synchronizations, with types ranging from 1 to 15. These fifteen can be used in partial or acknowledged synchronization characters. Type = 0 Only confirmed sync characters are used. This indicates that one of the 16 independent general sync types is described in detail in the subtype area. Table 1 shows the sync type in an embodiment. Type Subtype Use 1-15 X General purpose synchronization 0 0 General start 0 1 General stop 0 2 General failure 0 3-15 An idle general synchronization table-a module can participate in any type of multi-synchronization operation in full and in parallel. In one embodiment, Each chip pin has two general purpose synchronizations-one of each pin group is controlled by the same memory controller. As shown in Figure 7, the clock zone is an 8-bit general-purpose clock number, giving the time of the synchronization event a resolution of 5 nanoseconds (that is, a 200MHz clock). All modules in the system are required to make their internal time value registers 26 1245912 consistent, so the 5H synchronization mechanism will only work at the correct time. Cross the entire system. The counter calibration process that achieves this mechanism will be described later. The steps of subdivide the subdivide resolution from 5 nanoseconds to approximately femtosecond (fs). This feature can only be used for confirmed synchronization. Let ’s say, ‘the synchronization generated by most modules only has a resolution of 5 nanoseconds. When a part of the synchronization is converted into a confirmed synchronization, the confirmation area is set to zero. A 5 tolerant synchronization indicates the start time of the "in-sync" state. Therefore, any device that uses a confirmed synchronization time must add a fixed (and stylized) wait time before execution. The general confirmation synchronization follows the same rules: the waiting time must still be added (the number of additions is determined by the module that generates the synchronization characters). FIG. 8 shows an example of a part of the synchronization characters. In this example, the type is a 4-bit sync type, similar to the confirmed sync character type. Types have values ranging from 1 to 15. The state history is a bit area of states in the synchronization of the previous 3 2 clocks. A one-bit value of 1 indicates a sync status. A value of all zeros indicates that there is no synchronization and is not transmitted. A particular module generates partial synchronization characters based on its internal synchronization status' with a specific synchronization type. This module is next to the ring and produces the same type of monitoring used to monitor this part of the synchronization characters. This module performs a logical AND on the incoming state history and the state history generated below the same time frame. It will only be passed if the resulting state history is non-zero. If there is any additional contribution, this process will continue. The number of seconds is 0, and the time of the set-up of the zero-term set is 0. 27 1245912 Once a non-zero part of the synchronization character of the correct type to a synchronization can be confirmed and the synchronization character will be converted into an exact Independent acknowledgement synchronization is generated for each group of bits. Because it does contain a clock number, the waiting time of the process is accessible. Partial synchronization can only analyze the five-nanosecond clock. There is no possibility. In order to judge correctly, the time represented by the state history is known. The protocol is a state history and general clock synchronization statement) under a fixed calibration. For example, to 31 is nominally in the first state history, 3 2 to 63 is in the history, 64 to 95 is in the third state history, and so on. Some synchronization characters are only transmitted when relevant. Each module has a "dial-a-pipe" configuration (usually -FIFO configuration) to confirm its local state history, which is generated by the approximate steps of the input data characters. For simple processing, these words The element can use sequential correctness for the sequential order and the device-to-ring delay of all devices in the communication ring are known when the ring is configured. (The ring configuration is described later in the chapter "Ring configuration"). Note that the extra synchronous character insertion method is inserted into the ring 1 1 4. When they are placed downstream of the element, they will affect the number, because they delay the data entry character will cause a worst case, that is, less than less than small. For similar reasons, the signalling module has the ability to convert the unit into a universal clock number. The sync character is inserted after the originator, and the sync is recognized. The sync character of. Since I delay the information. The frame must be digital (see Confirming the General Clock 0. The second state history state history is used when the non-zero-variable length and a possible end-of-pipe are used for calibration. , Use the characters in this data. There will be more descriptions of 28 1245912 in the plane confirmed by the generals of the history of interpolating.-Part of the synchronization can be reviewed at random time, so they only occur in multiples of the spacing. See After describing the insertion of synchronization characters after periodic triggering, in order to avoid congestion-related questions, an extra clock stage can be used to step the characters into the ring. Only when there is a non When a blank character is used, this is used to prevent the synchronization character from being transmitted. The extra class can absorb the next blank character and be deleted. Due to the specific embodiment described, there is a maximum of 31 synchronizations, all of which can be used. The maximum value of each class increases briefly. If a character is transmitted after passing an extra class but it has not been released, a synchronous overflow error will occur. Periodic triggering is simple. The deterministic periodic touch of each test interface 106 can use this idle universal trigger type to generate a confirmation synchronization character. This function can be used to generate a minimum (denominater) type of trigger, possibly in a system Split-timing and multi-time zone features will be needed. Two independent test frequencies are provided in the trial. This period is programmable and sent in the form of 200MHz half-periods, which is 2.5 nanoseconds. The resolution can be 'sometime' next section. Problem, the module is inserted together with an extra level for the length of the ring in this module. With the new synchronization, the test has regularity & the same number # separation timing in During / test period (half official use / 24 29 1245912 bit counter, use a general start to restart · start to a programmable initial phase. This feature can also be used to synchronize any part of the authentication, so this This kind of synchronization can only be confirmed on a periodic basis. In this example, the period is the entire number of the 20 MHz clock. The clock counter calibration synchronization mechanism uses the concept of a universal clock number, which must be guaranteed. All modules are operating correctly in the steps. The following paragraphs describe the entire system to restart the required 8-bit counter technology at the same time. Any other technology that can achieve the same result can also be used The test controller 102 uses the described communication ring mechanism to broadcast a message to all modules to restart the counter. This message can be part of a general restart command. The sequence and timing of the ring are known. Therefore, the number of 2000MHz clock cycles required for a character transmitted from any device to any other device is known. The test head interface 丨 〇 6 first program each module with a clock offset value, during the restart command, each module will use this value to delay the restart of the counter. With these offsets, a restart operation will cause all counters in the entire system to reach zero at exactly the same clock edge. No synchronization operation can be performed during this process. 400MHz to 200MHz Calibration In order to confirm the correct operation of the bus, the clock required for the bus clock 30 1245912 The conversion from 400MHz to 200MHz of the clock must be in phase on all modules. A method used to achieve this is that when the power is turned on, the gate controls 4 0 Μ Η z clock 'so that it will only be generated after it is stable and all modules have been restarted (including a divider 314 (No. 3 Figure)). Although this operation only needs to be performed once, the SM can be initialized in this order at any time. A 200MHz main clock can be selected instead of 400μΗζ. This replacement does not require a divider, but it may be necessary to replace a multiplier to generate a 400 MHz signal to a module component that requires this signal. Synchronization mechanism performance The latency of confirming synchronization is similar to that of a read operation. The waiting time for a partial synchronization is longer than twice as long as the confirmation synchronization, because the partial synchronization will be converted into an acknowledgment synchronization, and this process must cross the ring again. Partial synchronization can use most of the bandwidth. In the worst case, partial synchronization consumes 50% of the total bus bandwidth. If a synchronization character cannot be placed in the ring due to congestion, the FPGA of the source module of the synchronization character will wait for the next empty slot. The maximum value of the waiting time ume) must be included in the latency, so the stylized offset between this synchronization event and the two times it acts is also the same. In any event, its time cannot exceed the stylized limit of some synchronization characters (i.e., 31 periods of the 200 MHz clock of the described embodiment); otherwise, some synchronization: the system will lose its effect. If there are no slots available before the stylized limit (maximum 3 ", the bus overflow error will be marked 31 1245912 using the sM interface. The synchronization message of the error processing confirmation can be used to handle an error mechanism. Some modifications to Required for standard communication protocols, because errors can occur across (or nearly simultaneously) the entire system, and because the components corresponding to the error may need to operate consistently to avoid the device under test (device under test, DUT) confusion. Any module can generate error messages. However, if the same module has generated an error message, or an error message has been received, the generation will be suppressed. The time value of the synchronization message is a test guide. Start. Therefore, the clock numbers can be used to compare the relative time of the error message alone. When there is only a message error, the error will be removed and the ring will be set. The device time is set to rf. The use of equipment that causes the device to receive or receive the same type of information, or the same information will cause the wrong production error. The other time is as it is, if it is right first, it is the best way to perform when you are resolute, and Puda is held to the top of the ranking. 5 In the message error, error, etc., or Cui Daben d Original) * This comparison requires the word to be a factor factor. The time is slightly different (if the value of interest will be restored to 0 I v ^ tl earlier), the usual behavior is used as a determinable agreement. If this kind of influence is affected, the hopeless type can not be allowed to do what he wants, and he can make no mistakes, and the ordering system is determined. Therefore, the decision of the case can be determined systematically. Since it is the inconsistency of the unassigned association, the system is wrong, except for the well-known problem of the system of tactics 32 1245912. The method of determining the ring configuration will be described later. I. Module Type The nature of each module is determined. Each module contains a small electronically erasable programmable read-only memory (EPPROM) to store module information. For example: module type, version And history. The information can be accessed from the s M interface. The module location test system 100 includes one or more mechanisms for determining the location of the module. These mechanisms include location inference from a unique The SM is connected to and from a suitable load board. Due to the possible gaps between the modules, the ring position is not suitable. Any technology is suitable in which the module can read its position from the slot in which it is installed. 3. Ring Delay For proper ring operation, the delay between modules, that is, the time it takes for a character to travel from one module to the next module in the ring must be known. The internal delay is known from the design specifications of the module type and is not critical to the operation of the ring. Usually there are no external pipes in the adjacent ring stages of the module, they are very close. However, longer connections, such as for debugging or bridging large gaps, may be needed. Providing this connection with a delay of multiples of 5 nanoseconds (200 MHz clock cycle), the operation of the ring will work accurately. However, to properly calibrate the internal clock counter, the location of such delays must be known. 33 1245912 The solution is an automatic determination of the loop delay. This technique will be performed later. The latter technique is performed after power-on to determine whether there is a significant delay in the connection between any modules. This technology is performed under control and no other bus or synchronization operations can be performed. a · '° The head interface 106 sends a source + MEASURE_TOKEN_ DELAY function to address all modules. The r ^ 4 interface 106 sends a 200MHz pulse with 33 data writes (). The value in the least significant 6 bits is 00-20. To ensure pulse operation, these writes can be synthesized by hardware rather than software. c. The test 4 controller uses the traditional readout operation from the test head interface. [6] Gray out the delays that have been determined for each module. Use MEASURE_TOKEN DELAY again. Each module decodes and passes these writes as usual. However, it will also do the following operations. If bit 5 = 〇, bit m is inverted in the direction. The input of the previous module in the ring becomes the output of the previous module, and the output of the next module in the ring becomes the input of the next module. In addition, the value received by the next module at bits 7-11 is subtracted from the bit's current value 'and the result is stored in a register. The current value of this bit also drives bit 7-Π back to the previous module in the ring. If bits 5 = 1, bits 7-1 1 return to their usual directions. The impairments detailed above can still occur, assuming that the input data is registered. The re-enabling of the bit 11 driver is delayed by several clock cycles to prevent collisions. The storage result of this impairment is the round trip delay from the test controller 1 02 to the module (r oon t d t r p d e 1 a y), ticked at the clock, 34 1245912 plus a small fixed and fixed pipeline elapsed time. One of the advantages of this technique is the determination of the clock value, which is not fast. There will be several signals in the ring bus. In the application ^, '% must be double. The second technology is as follows: 1. In a series of connections forming a communication ring, the force

; Up—signal CNFG TM and CNFG —extra part of OUT. This signal is also a B—such as -1N 疋 —ring, which is called an order ring. This configuration ring propagates in the opposite direction of the communication ring. In normal operation,

Except for the test head interface 106, each module simply propagates in the T ^ pulse cycle of each eye in its logical layer of CNFG —IN signal to CNFG — 0U Ding Xun. The test controller CNFG —OUT is continuously maintained at a logical level. Therefore, the entire signal ring connecting CNFG_rn of a module to CNFG IN of the PREVI0US module is connected to a LOW layer after the number of clock cycles required to propagate the signal throughout the ring. When the test head interface 106 issues a special command DESCRIBE_CONFIGURATION ^), different orders of operations occur. When this command is issued, the test head interface 106 will set a counter to zero. The counter is incremented after each bus clock cycle. The low level (i0w-〇rder) in the DES CRIBE_CONFIGURATION command contains 10 digits. Each module in the ring receives this command, and records and reduces the number. If the result of the reduce operation is non-zero, the command is passed through the ring. If the result is zero, the command stops in the module, and the module generates a serial data stream. This module no longer propagates CNFG_IN to CNFG — OUT. Instead, it transmits a serial data stream, one bit 'every clock cycle passes its CNFG —OUT pin to the previous module in the ring. 35 1245912 The body stream is transmitted in this way, one module after another, and finally the f test head interface 106. The data stream is determined by the module; however, the first bit is HIGH (indicating the test head interface 106 that the bit stream is turned on = down (roughly) 12 bits indicating the number of bits left in the data stream The bit under 2 contains information that may be useful for the test controller. Its content is not important here. When the high of the data stream reaches the test head interface 106, the counter will stop. Inside the counter Say, from the issue of the DESCRIBE_CONFIGURATION command, how many periods have elapsed from the position of the device N of the test system controller? The test controller 1 2 can accurately determine the module order and a communication event in the ring. The exact number of clock cycles required for ring transmission is U. The test head interface calculates its time shift from each device itself. The test controller 102 can also choose to calculate the time offset. The final step in the configuration process It is the internal clock time of all devices at the beginning of the test head interface 106. The initial memory of the test head interface to a reasonable initial value (about 1 000), and then issued a command to write to the inside of each module in the ring. Clock register For the ring group, the value of the write device is in the test head interface ι〇6: the memory plus the time offset of the module in the ring, and then add this to write its internal clock temporary storage The time of the device is determined. With this method, the internal clock of the main clock is temporarily written. The value will be exactly the same as the number contained in the internal clock of Test 6. This configuration The advantages of the processing process and structure are that the test controller 102 has the ability to determine how many devices can react back to its beginning). word. , But the bit content is distributed to the pulse of the pulse. When the mode of the central clock is in the middle of the ring, the mode of the clock group is 36, 1245912 bits, which is where the first fault occurs in the ring. Figure 9 illustrates an example of a write operation of a test controller to write a module. In this example, the test controller writes a data character into a first module 920 and a second module 93. Detect 忒 Controller 1 〇2 sends a function + negative source (? 1111 (^ 011 + 1 ^ 30111 *. 6 戸 4 ~ public, ^ e 't + R) characters (that is, contains a function-resource code Control data characters) Enter the generalist „m. Zhala. Data character refers to

It indicates that the test controller write-write data characters enter the __module 920 and the second module 930. Function + resource word το enters the communication ring from the transmission port 9 1 2 of the test head interface 9 丨 〇. In the next common clock cycle, the function + resource character is transmitted to the receiving port 921 of the first module 920. In the next common clock cycle, the first module 920 decodes and announces the function of writing a data character + resource character, waits for the writing of a data character (indicated by a double line in Figure 9), and then moves the function + Data word 70 to port 9 2 2. By passing the function + resource character from the port to the port in each common clock cycle, each module in the ring receives the function + resource character 'to process (ie decode) it, and then sends it to the next class. After receiving the function + shell character, a third module 940

There is no waiting for writing data characters which are only addressed to the first and second modules. After a short time (two cycles) after sending the function + resource character, the test head interface 9 1 〇 sends the write data (WD) character to the communication ring from 9 璋 2. When the second module 920 and the second module 930 receive the writing data characters (indicated by a thick frame in FIG. 9), the writing operation is 70%. When the two data characters reach the test interface 9 10, they will be removed from the ring. 37 1245912 Read operation example Figure 10 illustrates the read operation of the test controller to read the data stored in a module. In this example, the test controller is reading characters from the first module 920 and the second module 930. The test controller sends a first read character request to the test head interface 9100, which proposes a function + resource character to enter the loop. Each module in the ring receives the function + resource character, processes (ie decodes) it, and sends it to the next class. The data characters instruct the test controller to read data from the first module 9230 and the second module 9300. After receiving the function + data character, the first and second modules wait to read the data character (indicated by the double line in Figure 10). After a short time (two cycles) after sending the function + resource character, the test head interface 9 10 proposes to read data (r e a d d at a, RD) characters from the transmission port 9 1 2 to the communication ring. At the reception of the first read data character, using an operation such as an OR, the first and second modules add corresponding data to the first read data character (represented by RD 1 and RD 1 2 respectively). ). Note that the first module 920 has delayed a common clock period before transmitting the first read data character. The test head interface removes the first read data character from the ring and sends it to the test controller. The test controller waits until the first read data character is received and the corresponding return 0 is received before sending the second read character request. Example of restarting as a whole. Figure 11 illustrates a start of the whole operation. The test controller Schedule a test with one or more modules. In this example, the test controller schedules a test performed with 38 1245912 first module 9 2 0 and second module 9 3 0. The test controller sends a confirmation synchronization character (c ο n f i r m d s y n c word, CSW) from the test head interface 910 into the communication ring. A confirmation sync character indicates that the test is scheduled to begin at a common clock time value of 4 and includes the first and second modules. Each module in the ring receives the confirmation synchronization character, decodes it, schedules a pair of triggers with a common clock time value of 4 (indicated by the double line in Figure 11), and then sends the synchronization character to the next class . At the scheduled common clock time value of 4, the scheduled trigger will cause the first and second modules to start testing (indicated by the thick box in Figure 11). The scheduled trigger does not cause the third module 940 to perform the test because the third module is not required in the confirmation synchronization character. Example of Partial Synchronization Figure 12 illustrates the operation of partial synchronization. Initially, two or more modules confirm the synchronization character. This example uses the same modules as shown in the ninth to eleventh figures, and the first module 9230 and the second module 9 30 are initially a confirmation synchronization character. For example, the third module is scheduled. The beginning of 940. In order to initially confirm the synchronization characters, the first and second modules first need to find a synchronization status in the co-incident confirmation in their status history. The first and second modules have a first register 924 and a second register 9 3 4 respectively. First and second synchronization register login status history. A status history is a bit area corresponding to the status of the module during the previous 3 or 2 clock cycles. In this example, the first module has synchronization status at common clock times 9 6 and 9 8 (indicated by the black arrow in Figure 12), while the second module has a total clock time of 39 1245912 It is in sync with 99 o'clock. The first and second synchronous registers complete a first (A000000) and second (30000) status history at a common clock time value of 12 8 hours. In the next common clock cycle, the first and second state history are transferred to a first state history register 925 and a second history register 935, respectively. At the common clock time 1 29, the first module 9 2 0 inserts a part of synchronization characters into the communication ring. This part of the sync character carries the first state history. The second module 930 performs an AND operation of the first (A0000000) and the second (30000000) state of sad history, and transmits the result from the communication ring to the first module 92 ′ as a merged state history (2000). 〇〇〇〇〇). At the common clock time M 137, the first module removes the merged state history from the communication ring and puts it into an internal register 928. In the next common clock cycle, the first board group shifts the history of the merged state in the internal register 92 8 to the left, until a non-zero most important genius generates a confirmation synchronization character, and schedules the start of the third module 940. Make sure to visit, shop 1 1 'Bubu Ziyuan will be brought to the communication ring. The second module 9 3 0 can modify the scheduled start time in this a ° heart beat step element to trigger the start of the third module 940.

An embodiment is described below, in which the test controller 102 (Fig. 1) is in a workstation, such as one of Sun MicroSyetem-a usable object, and the interface unit 104 (Fig. 1) is an CPU Interface Panel The CPU interface panel is inserted into an empty backplane slot in the workstation. The CPU " panel can contain a high-performance FPGA, such as one for XUinx which can use 40 1245912 objects. Backplane and CPU interface board # ^

It uses the 64-bit / 66MHz PCI standard, which enables it to have a continuous transmission rate of approximately 240MB / sec and a maximum theoretical transmission rate of 52 8MB / Sec. For the CPU interface panel, the first operation can be performed in a blocking or non-blocking manner. Yiyang also p, blocking the operation will cause the CPU interface panel to hinder the further error of the data. —

^ The non-blocking operation will not cause the CP interface interface to hinder the further promotion of the data. This further transfer. The write operation to monitor the status of the test head (that is, the test head / s Μ write option, θ trillion u 1 baht operation) is non-blocking, and no response is required. Write errors, such as those caused by FIF0 overflow, can cause—exceptions. The readout operation to monitor the status of the test head (ie, test head / SM output operation) is not affected until the readout result is available. A stylized overrun contains at least 32 microseconds to! In the millisecond range. In some restricted cases, the test_Ale Wushuo / SM readout operation can optionally be delayed and unobstructed. -Implementation and description of the inter-interface. The interface between the interface unit 104 and the test head interface 106 is a serial connection at approximately 3 billion bytes per second (one call-operation). Test Heads® 106 can be a board containing

^ Serialization / deserialization (serialize / deseriaHze, SerDes) table setting, the serial data of the conversion interface unit becomes FpGA's reproducible flat data. An example of a SerDes device that can be used here is τΤ! ^ 21Λι & 3 1 0 1 which can be obtained by 4 ^ Deyi. The device can convert serial data into 16-bit characters. In order to send characters efficiently, 16-bit characters are divided into 4 41 1245912 ordinary nibMe. Each system operation can be described by one or more. Therefore, an operation can be coded by the SerDes device in multiple or partial 16-bit characters. ^ For the error that may occur in the link that can be b, there is no available to recover ^ 2H, and additional error correction is required to determine the link is for example, 'a detected residual error can be marked as control H! 02 Into a κ solid warning. The following provides an example of a wire ... ^ wwniink word, 102 is sent via the interface unit 104, and is connected to the test head interface 106. An example is shown in Figure 13A. Females above J are to seal · × · / ν ° ,,, a system operation can be coded less than ^ Wu. In these cases, blank characters and sub-breaks are used. | 面 早 Wu 104 is used to fill in padding to inform M Mu Guo indeed *, and any additional m is received-the last operation is completely To ground.帛 ΐ3β graph:

Character is an example of another down-chain character. Before sending one or two: The test controller sends 2 to 7 ° > (that is, a read character sent by the test head interface 106) before sending any other instructions. The DMA character indicated by waiting first is another downlink character 13C I ~ listed. The test clock οσ can send a special character command, including D # 早 八 傅 传 's calculation and description, reducing the number of sighs sent from the interface unit 104 to the test head interface. At present, this reduction reduces the size of the memory required for the FPGA (106 m). An additional benefit is the better control of the data flow on the test head (ie η curve 1 0 4 σΓ signal ring 1 1 4). X is at the bottom; with M + has the interruption shown in Figure 1 3D dmA 偻 诚 a ；; Lin Ziyuan, the ^ th digit of b is super. The pass is on the ground. The test includes: when the blank digits of the string are filled, read out, test response, 104 capacity order FIFO Turn on the write character shown in 42 1245912 in the example figure, the resource / function character shown in figure 1 F, and the SM write character shown in figure 13G. The interrupt DMA transfer character will Interrupting a DM A reading that is in progress. The format of the resource and function area of the resource / function character will be described in more detail below, and the format of the data range of the STM write character will also be described in more detail below. Many descriptions. The OxFE slot of the SM write character is immediately used to address a specific group of devices. The group can be defined by the normal write operation sent by the test controller to the test head interface. The following provides an uplink word An example of an uplink word, which contains characters, sent from the test head interface 1 06 to the interface unit 1 04 The blank characters and readout characters described above are examples of uplink characters. The test head interface 106 sends a readout character in response to receiving a write character from the interface unit 104. This is the interface unit 104. The characters to be read after the initial writing characters are sent. The test head interface may include a feature to convert the format of the read data based on the reading of a specific function code. This feature is used to convert by analogy Or the analog sample captured by the digital device is read back. The SM readout character shown in the figure 1 3 另一个 is another example of an uplink character, which can be used by the device or test head interface 1 〇 6 The test head interface 1 06 can process some SM characters generated by the device. In these cases, the test head interface does not pass SM read characters to the interface unit 104. The format of the data area of the SM read characters More details will be described later. Other examples of on-chain characters include the synchronization character shown in Figure 1 31, the flow control character shown in Figure 13 J, and the characters shown in Figure 13 K. DMA interrupt confirmation character indicated. Additional on-chain word It is shown in Table 2. 43 1245912 Bit Bit Bit Bit Bit Bit Meaning Remark Yuan Wu Wu Wu 7G Wu 7 6 5 4 3 2 1 0 1 0 0 0 0 1 0 1 SM overflow from module to test Head interface 1 0 0 0 0 1 1 0 The serial bus synchronizing characters from the test controller to the test head error interface table 2 device are sent to the test unit 1 04 for debugging and test flow control. The test head interface 106 uses the flow control characters described above to avoid its FIFO register overflow. The test head interface 106 sends a DMA interrupt confirmation character to the interface unit 104 in response to receiving an interrupted DMA transfer. After receiving a DMA interrupt character, the test head interface 1 06 will wait until all the data waiting to be read out of the serial communication ring 1 1 4 before sending the D M A interrupt confirmation character. Implementation of the SM Interface An embodiment of the SM interface is described below, including two unidirectional high-speed serial connections connecting the interface unit 104 and the test head interface 106, and three signal lines connecting the test head interface and each module. The SM interface is independent of the daisy-chain bus, and must be capable of operation even if the daisy-chain bus is not operating at the time. The SM interface has the following high-level functions: 44 1245912 • Reporting of temperature, power, or other system error conditions • Controlled shutdown and startup of the device • FPGA download • EEPROM access • System hardware restart • Slot ID Each device is connected to the test head interface 106 to centralize and buffer information. The test head interface has a connection to interface unit 104 to generate an error interrupt. A module should have at least three signal paths for transmitting data, grounding, and receiving data. The SM interface can also be part of the communication ring. That is, the test system can use the same communication equipment from sending control data characters to sending SM characters. Module Implementation Figure 14 shows an embodiment in which the module 2 0 0 is a piece of pin module 1 400. This embodiment is a test equipment module including one or more stimulation / measurement modules, such as a PE module, a TMU module, and a PMU module. Each stimulus / measurement module has its own specific stimulus or measurement task, and these specific tasks are scheduled by commands. These commands are synchronized according to the combination of the system's main clock and the device's internal time register. A dedicated bus connects the bus interface FPGA to one or more stimulus or measurement modules in the device. The module control data is transmitted to the stimulus / measurement module, and the data read by the stimulus / measurement module is transmitted with a maximum value of 45 1245912 at each cycle, and they are rising edges at the 100MHz clock (Rising edge) pass. In this embodiment, there are 37 signals: • 32-bit bidirectional data, reversed in reading

• 3-bit period type, CYC • BUSY: 0 = stop subsequent periods, 1 = normal operating data bus and BUSY comply with the standard of the transceiver transceiver logic plus (GTLP) (open collector )), Pull-ups to 3v3. CYC is a stub-series terminated logic (SSTL) and is driven by the bus F P G A. The data transmission acknowledgement (d a t a t r a n s f e r acknowledgement, DTACK) is connected to the bus FPGA and other Isabella by an Isabella, and is a low voltage transistor-transistor logic (LVTTL). Table 3 shows an example of a CYC code. CYC DTACK data bus 0 write is used by bus FPGA driver 1 read is used by configuration FPGA driver 2 function is used by configuration FPGA driver 3 no operation is ignored by bus FPGA driver 4 resources, bits 0- 31 Ignored by bus FPGA (useless data) 5 Resources, bits 32-63 Ignored by bus FPGA driven 6 Resources, bits 64-95 Ignored by bus FPGA driven 7 Resources, bits 96- 127 Ignored Driven by Bus FPGA 46 1245912 Table 3. In this embodiment, the function or resource cycle always uses one clock cycle. They cannot be extended with DTACK. If either or both of Isabella asserts DTACK, the read and write cycles will be extended. This cycle will complete when DTACK is not asserted at the next rising edge of 100 MHz. Both configuration FPGAs need to monitor DTACK to determine when a new cycle will begin. This cannot be assumed that any changes will be made to C Y C. Except for the read cycle, the bus FPGA sends data with normal polarity in all cases. In this case, the output of the FPGA is tri-stated, and the wire-AND of the two configured FPGAs will reverse the read data. This meets the requirements of the OR'ing mechanism. Each configuration FPGA also contains an image that allows read back bits to be coded. In a function cycle, the least significant 16 bits are the current function code. The basic positions have been subtracted, so they start from zero. Page 0 functions are not sent to Isabe 11a. The most significant 16 bits are the current resource number, which is encoded when it is on the system bus. If G = 0 (ie, bit 31 = 0) in the resource code, a single channel is being addressed. The resource mask set by period types 4-7 is not required and should be ignored. If G = 1, the remaining resource bits (ie, bits 3 1 -1 6) in the function cycle must be ignored. Addressed resources are defined using a mask instead. Masks written by cycle types 4-7 may occur before or after the function cycle. Using these cycles, a maximum of 1 2 8 resources will be addressed into any group 47 1245912. For bandwidth efficiency, CYC = 4 is defined to clear the mask bits 32-1 2 7 ′ and is therefore written before cycles 5-7 which may not be needed at all. Each configuration F P G A needs to know, for example, via a pin, whether it decodes high-order or low-order resources. At every 200 MHz clock, synchronization type and time information is passed between the configuration FPGA and the bus FPGA. Each signal is SSTL. The following describes a requirement of an embodiment regarding an acknowledgement synchronization. The 18 bits are transferred from the configuration FPGA to the FPGA, requiring a confirmation synchronization. The 18 bits include 12 bits of time, which has a resolution of approximately 1.22 picoseconds (P0 (that is, 5 nanoseconds / 4096), plus a 6-bit synchronization type Code. A synchronization type of zero indicates that the clock cycle does not include a synchronization. For low-accuracy triggering, the 12-bit time zone can select the six most significant bits (MSB) and sub-types of time. Six bits are used for encoding. The time information reflects the user time T 0 in the generation guide. The bus FPGA includes a feature that can map the synchronization type and / or the sub-type. The terminal capacity test mode is position independent. This mapping can be Limited, but will allow at least 64 synchronizations per configured FPGA. The following describes a requirement for some synchronization. Passing a bit from the configuration FpgA to the bus FPGA requires a partial synchronization. For this synchronization, there is a tragedy. During the period, the bit should be a logic high. If the synchronization state is claimed in the cycle and / or the claim is maintained at the end of the cycle, any 200MHz clock cycle will be marked as synchronized. In addition to failing, configure the FPGA May be used Any device that has the same dream (such as 48 1245912 opcode, EINST bit, match) can be configured as a part or a confirmation synchronization character. Failure only needs to be configured as a confirmation synchronization. The two requirements mechanism should be It can be independently functionalized, allowing different synchronizations to be generated at the same time. ^ One of the usages for confirming synchronization is described below. 18 bits are transferred from an FPGA to the configuration FP GA, indicating that a confirmation synchronization has occurred. They statically prioritize simultaneous synchronization. Events. These bits have the same format as described above. For general-purpose synchronization (that is, those that are not reserved for a specific purpose, such as test program start, stop, or failure), the FPGA is configured to have the ability to use the acknowledgement in two ways Synchronize time information: • Decide which guide contains the synchronization and follow the action, but maintain the test-program-defined guide period. • Shift the program's timing with the precise time of the synchronization, so later The guide and the synchronization event are exactly offset with a fixed wait. The generation of synchronization is also asynchronous This offset has nothing to do with the guidance period. In addition, the FPGA can be configured to ignore synchronizations that occur before the opcodes, the opcodes can wait for them, or they can treat these states as immediately contacted. Configurations that belong to this, and literal translation ο η) The two modes can be implemented with different operation codes, or according to the static configuration of the synchronization type. Due to the mapping mechanism, the FPGA configuration does not need to know the subtype in the synchronization usage. The bus FPGA contains a feature that can Mapping synchronization type and / or subclass 49 Type 1245912 allows the test mode to be position independent. This mapping can be limited, but will allow at least 64 synchronizations per configured FPGA. This configuration FPGA also requires a least-common-denominator type counter 'allow synchronous identification' which can be delayed until a suitable point. FIG. 15 shows an embodiment regarding the bus FPGA interface and module, such as a PU module, a PMU module, and a TMU module, which can be included in the chip pin module 140. In this embodiment, there are four such modules. The physical connection is a pair of full nibbles (n i b b 1 e-w i d e) one-way serial stream 'whose clock is at 1 2 · 5, 25, 50 or 100 MHz. Use a total of 10 connector pins (excluding ground). The typical transmission rate in this embodiment is 4

Mbytes / sec ° Except for low-voltage micro-distribution signals (LVDS), all nine signals are single-ended, compatible with LVTTL, and have 50W serial termination. All eight data are point-to-point (p〇int_t〇_point) between the bus interface FPga on the motherboard and the FPGA / EPLD (erasable programmable logic device) on the PE module. The bus FPGA generates the clock, and each interface can be programmed (丨 2.5, 25, 50, or ι00ΜΗζ). The default value is 12.5MΗζ. Clock reversal is used to confirm the optimal timing. Each module has an independent connection on the chip pins (such as PE, tmU and PMU). In response to a single read operation, the bus interface fpga is responsible for OR ing-reading data from most modules. 50 1245912 The following describes the lower bond (d o w η 1 i n k i n g) of the embodiment. The data is converted into 4-bit nibbles' or a series of nibbles, as follows: • 0x0: fill in the blanks. be ignored. • 0x4: Read data. The response is on the chain. • 0x5 + 8N: Write data with 32 bits of data, LS4b first. • 〇x7 + 4N: Write function with 16 bits of function code. • 0x8 + lN: The resource is written with 4 pre-decoded address bits. • 0 X 9 + 1 N: Write resource with 8 first decode address bits. • 〇xA + 1N: Write the resource with 16 first decode address bits. • 0 × Β + 1N: Write the resource with 32 first decode address bits. • 〇xF: restart. A minimum of nine is sent continuously. • Other: For future expansion. Data transmission is always 32 bits. The resource characters are decoded first by the bus f P G A. Each element corresponds to a pin, up to a maximum of 3 2 per PE module. If a bit is set, the pin is addressed. Most pins can be addressed simultaneously. PE modules are not expected to perform shared decode—this function is managed by the bus interface FPGA. If a resource write contains fewer bits than the module's maximum number of resources, the upper bits will be set to zero. A PE module does not need to handle resource writes larger than the legal size. Because the resource characters are decoded first, no slot type or module ID signal needs to be transmitted to the module for aid-decoding. The bus FPGA can filter useless bus transactions (that is, transactions that correspond to resources or functions that are not decoded by 51 1245912). The bus FPGA manages a fif0 rank of bus transactions on PE modules. = The following describes the winding up of the embodiment. Filling in the blank nibbles followed by Bei Jingjing took the down chain and passed $ until all 8 nibbles read out were connected to A on the chain. -Restart at the down chain (0xF) to discard the readout. Most of the time the key-up transmission will fill the blank nibbles (0χ〇). Only when there is a-legitimate data response to the first reading of the next chain, will it be a data transmission. In this " f column, ~ · 0 v 4 2 — The byte is followed by 8 data nibbles, LS4b first. The 轾 control mechanism will also be defined to allow the P β module to stop transmitting from the bus F p A & 卜, 1b, for example: to allow slow registers: the writer. If the PEE group can support operation at the maximum transmission rate, this mechanism need not be applied. The uplink nibble of xC tells the bus FP (3A to continue the (if: any-) current transmission ', but then delay additional transmission until one of the uplink nibbles of 0 is sent. , Fill the blank nibbles (οχο) are sent in the far off-chain. The only exception is-restart (㈣), in: the chain resumes normal operation. The on-chain data bits are pulled up, so the confluence The FPGA can use the 0xF code to see the characteristics of the modules that can not be found to detect them. Download the 'one- and five-wire standard jtag buses from the FPGA to each PE group. If necessary' This can be used as a debugging function for FpGA download. The device can also choose to use its ㈣fpga download configuration. Because it needs to support other FPGA vendors, the dedicated Xilinx 52 5245912 (such as DIN and PR0G) is not provided. In order to store the GA pin of the bus interface, two common jTAG control signals can be arranged in parallel to all four PE modules. However, the Tm and TD〇 lines are unique. Each PE module contains an EEPROM , Need to use it to determine the type of module. EEPROM is usually in The FPGA is accessed before downloading, because it will decide the configuration. It has two connector pins, both are LVTTL compatible. They belong to the PROM clock and pr0m data. The data line is a bidirectional open connection Stop on the motherboard. In order to store the FpGA pins of the bus interface, the EEPROM clock signal can be routed parallel to all four pE modules. However, the data line is unique. The 16th diagram is not an example, of which The module is included in the chip pin module 1 400. 'Contains a module interface FpGAs and a test circuit configuration to generate a sequential event of the test machine number. U.S. Patent No. 5 4 7 7 丨 3 9 and 5 2 1 244 Test performance of an event sequencer as described in No. 3. In this embodiment, each test circuit includes an independent serial interface with three LVTTL pins: • 100MHz clock • TxD (transmit data) One serial data from the module interface FPGA to the configuration FPGA (downlink) • RxD (receive data)-serial data from the test circuit to the module interface FPGA (uplink)

The idle states of TxD and RxD are high. All TxD messages start with a single bit and zero bits followed by a two bit message type and a variable length bearer (PaYl0ad). The LSB is transmitted first. No idle status is required between messages 53 1245912 status. RxD is the same, unless it is only used to read it back, so there is no message type. Table 4 shows an example of the configuration of the second type of message of the FPGA: Type Bearer Length Meaning TxD? RxD? 0 0 Whether to perform reading 1 31 bits to write data whether 2 16 bit resources, whether the decoding mask 3 16-bit function, based on whether zero / N / a 32-bit read data

TxD message type 0 (read data) requires the test circuit to respond to the data requested by RxD. The test circuit may take some time to respond, until no more data is passed. The PE module FPGA is responsible for OR’ing to read data from multiple test circuits together and respond to a single read operation. The 16-bit resource mask has one bit belonging to each addressable resource in each test circuit, with up to 16 resources. If the bit is set, the resource is addressed. These bits can be set in any combination to implement sharing-this is handled by the bus FPGA. It is not necessary to know the current MUX mode except for the test circuit, because the resource code used by the software will be the first resource assigned to the pin in the current mode, such as in a 4-to-l mode, s / w will address resources 0, 4, 8, etc. The 16-bit mask it contains can be directly translated into the current mode required by the test circuit. Figure 1 7 54 1245912 provides examples of functions, resources, write and read messages in this embodiment. Figure 18 shows an embodiment in which the module includes an alternative test circuit. There are 20 ECL-compatible signals: • TxC, which will clock the transmission. • UWORD: 0/1 belongs to LS / MS — 16 bits in 32-bit conversion. • S 0, S 1: encodes the cycle type. D0-1 5: Bidirectional data bus, wire-OR'd (wire-OR'd) timing and communication protocol are compatible with alternative test circuit devices. Because shared decoding is now managed by the BUS IF, shared memory that replaces test circuit components is not used. An embodiment of an interface between the bus and S M F P G A s is described below. There is a slow serial connection between the two units on the device's motherboard. This is used:

• Notify the bus FPGA of the slot ID it uses for resource decoding purposes. • Reset the device. • Signal error information sent back to the SM system. The SM FPGA must generate signals to program the bus FPGA and are not included in this section. These signals are vendor-specific and do not need to be standardized. In order to design and reuse efficiently and reduce the number of opto-couplers required, a two-wire (TxD + RxD) architecture is used, as indicated in Section 5.3. The downlink (SM EPLD to bus FPGA) byte is a programmed slot ID and is written when SM EPLD receives it. The only exception is: 55 1245912

OxFF is not literally translated into a slot I_D, but is seen as a general reset. As described below, it also retransmits any subsequent errors. If there are any current error conditions, OxFE will ask the bus FPGA to transmit them. Errors are usually transmitted only once and then silently cleared. The on-chain (bus FPGA to SM EPLD) bytes are encoded as error codes. The exact format is defined in Section 5.5. Unless there is an error, no transmission will occur. FIG. 19 shows a process for controlling one or more modules, which is configured to test one or more integrated circuits according to a test process. Confirm that at least one module is participating in the test process (step 1910). A test thread (step 1 920) among the independent test threads is confirmed, the test thread contains instructions for generating data characters to be sent to other modules, and the test thread is sent to the confirmed Module (step 193 0). Figure 20 illustrates a process for controlling and synchronizing one or more devices to test a circuit, where the test device is connected to a communication ring. By using a common clock signal of a main clock, the synchronization of an internal time register of each test device is set and maintained at a common clock cycle (step 20 10). This common clock period provides a common clock time value for scheduling test events. The bus characters are inserted into the communication ring (step 2020) to carry the bus characters to each test device. The inserted bus characters include at least one bus character, which specifies a scheduled shared clock time value for a test event to be executed by a target test device. The bus characters that specify a scheduled shared clock time value are read by the target test device (step 2300), and the scheduled common clock time value and the internal time of the target test device are used to temporarily The value of the common clock period in the register determines when to execute the 56 1245912 test event (step 2 0 4 0). · The methods and equipment described herein can be implemented in digital electronics, or computer hardware, firmware, software, or a combination of these methods and equipment can be implemented as a computer program product, that is, an electrical information carrier, For example, a machine-readable device or a transmitted signal is used by a data processing device to control its operation, such as a programmable brain or a majority of computers. A computer program can be in various forms; it can be composed or translated directly, and it can be included in any form as a stand-alone program or as a component, subroutine, or other suitable for the computer environment. Any component. A computer program can be deployed to run on a computer brain that is internally linked across multiple networks in a single location or distribution. A function performed by using one or more programmable processor-executable methods as input data and generating output to execute a computer program. A special purpose logic circuit system can also be used to implement or use the device described herein as the circuit system, such as a special application integrated circuit (ASIC). For example, a processor suitable for executing a computer program and a special purpose microprocessor, and any kind of digital or more processor. Generally speaking, a processor will receive commands and sub-electronics from a single random access memory or both. These formulas are executed in the storage device or the storage space. The programming language is written, and the package-modules, mini-modules, or most of the electronic devices are used and one step is used. • Method steps, an FPGA or integrated contains any read memory or data of a general computer. An electric 57 1245912 The basic elements of the brain, a processor for executing commands and a memory element for storing commands and data. Generally speaking, —fan_u — computers also contain one or more mass storage devices used to store data, such as. ^ #. Magnetic disks, magneto-optical disks (M0), or optical disks, which are operating, | Zhang was uncovered to receive or transmit data from it or both. Data carriers suitable for computer program commands and data contain various forms of non-volatile memory, such as semiconductor memory components, such as EpROM, EEPR, M and flash memory components, magnetic disks, Examples include internal hard drives and removable hard drives; magneto-optical discs; and CD-ROMs and DVD-ROMs. The processor and memory can be supplemented by, or included in, special purpose logic circuits. The method and apparatus have been described in the form of a specific embodiment. Other embodiments are also within the scope defined by the appended patent application scope. For example, the steps described may be performed in a different order and still achieve the desired result. The means for cooperating with off-the-shelf equipment may be included in the test head, or may optionally be included in each module. The module can have any structure to support the exchange of data from a communication ring, and is not limited by the embodiment described. The test system may pass the status monitoring word 'from a channel separated by the communication ring or alternatively such characters may be transmitted from the communication ring. [Schematic description] Figure 1 is a block diagram of a test system. Figure 2 shows a method for testing one or more circuits. Figure 3 is a block diagram of a common module configuration of a test system module. 58 1245912 Figure 4A shows a format of a control data character. Fig. 4B shows an example of a blank data character. FIG. 5 shows a format of a functional source part of a control data character. FIG. 6 shows a write flow control data character. Fig. 7 shows an example of a determined synchronization character. Fig. 8 shows an example of some synchronization characters. Figure 9 illustrates a test-controller-to-module write operation. Figure 10 illustrates a read operation of the test controller to read the data stored in a module. Figure 11 illustrates a general start operation. Figure 12 illustrates part of the synchronous operation. Figures 1 3 A-1 3 K show examples used in one embodiment. FIG. 14 shows an embodiment of the module 2000. FIG. 15 shows an embodiment of the connection between the BUS FPGA and a PE. Fig. 16 shows an embodiment of a communication interface in a PE, TMU or PMU module. Figure 17 shows examples of functions, resources, and write and read messages. Fig. 18 shows another embodiment of a communication interface in a PE, TMU or PMU module. Fig. 19 shows a process for controlling one or more modules according to a test process. Figure 20 illustrates a process for controlling and synchronizing one or more test devices to test a circuit. 59 1245912 Similar reference symbols in different drawings indicate dissimilar elements. [Simple description of component representative symbols] 100: test system 101 test head 102: test controller 104 interface unit 106: test head interface 107 main system clock 108: chip pin module 110 δ and power supply module 112 : Controller connection 114 Serial communication ring 116: Connection 117 Clock connection 200: Method 202 Step 204: Step 206 Step 208: Step 216 Memory controller 300: Common module architecture 302 Common interface and bus 304: Confirm synchronization Type 306 Confirm Synchronization Accurate Time 3 08: Synchronization Requirement 310 CPU 3 12: CPU Bus 3 14 Divide by Two Divider 3 16: Memory Control Circuitry 910: Test Head Interface 912 Transmission Port 920: First Module 921 Receive port 922:: Transfer port 924 First register 925 : First state history register 928:: Internal register 930:: Second module 934: Second register 93 5:: Second state history register 940: Third module 1 400: slice Pin module

Claims (1)

1245912 捌 、 Scope of patent application 1. A system for controlling one or more test equipment configured to test one or more integrated circuits, the system includes at least: a main clock, which is directly connected to two or more Each test device of the test device, the main clock is configured to provide a main clock signal to two or more test devices, the two or more test devices are connected to form a communication ring, two or more Each of the test equipment includes an input port and an output port. The output port of a first test device is only connected to the input port of a second test device and supplies a data word of the output port of the first test device. The unit is provided only by the output port of the first test device to the input port of the second test device; and a controller connected to the communication ring, the controller being configured to calibrate and test two or more The counter of the device is used to obtain a common clock time value from the main clock signal. The controller is further configured to generate and send data characters into the communication ring, and pass the data characters to each test device. The data characters include at least one data character to specify a test event to be executed, a common clock time value, and at least one test device of two or more test devices, of which two or more test devices At least one of them is configured to execute the test event at a time specified by the common clock time value. 2. The system according to item 1 of the patent application scope, wherein: at least one of the two or more test devices can delay a data character transmitted by the communication ring without coordinating the delay with other test devices . 61 1245912 3. As the word 4 • As the ring 5. As test 6 • As 7 • The system described in item 2 of the patent application scope of Liyuan Yuan, wherein: At least one of two or more test equipment is available A delayed element to replace a bus character passed in the communication ring. The system described in item 1 of the scope of patent application further includes:-converting one of two or more test devices into a module, the converter comprising a processor, memory, and a data bus configured for use To connect the processor and the memory to, and exchange one or more of the two or more test devices with the system described in the patent application item 4, wherein the transferred device includes a ready-made test device. The system described in item 1 of the scope of patent application, wherein: at least one of two or more test equipment is constructed to form a system described in item 1 of the scope of patent application, further comprising: a first converter and a A second converter, each converter is used for a first and a second test equipment to become a module, the first converter package and the logic converter inserting a part of the synchronization characters into the communication ring include a processor and adding synchronization Information to the part and return the part of the synchronization characters to the conversion bus of the first converter's logical bus, the communication data. The conversion test includes one place, the first synchronization word 62 1245912 8. The system described in item 7 of the scope of patent application, wherein the synchronization information added to the part of the synchronization characters includes a state of the second device history. 9. The system according to item 1 of the patent application scope, wherein the controller is configured to insert control data characters into the communication ring, and the control data characters pass the test function information to two or more One of the test equipment. 10. The system according to item 1 of the scope of patent application, wherein the controller is configured to insert a read data character into the communication ring, and the read data character requests a test device's capacity. Test data. 11. The system according to item 1 of the scope of patent application, wherein the communication ring is daisy chained from the output port of each test device of two or more test devices to the input port of an adjacent test device, Pass the bus characters. 1 2. The system according to item 1 of the scope of patent application, wherein the data character includes an address specifying at least one target test device. 1 3. The system described in item 1 of the scope of patent application, wherein the controller is configured to insert bus characters into the communication ring through a test head interface. 14. The system according to item 1 of the scope of patent application, wherein the controller is configured with 63 1245912 to insert data characters in the communication ring, and the data characters include information for testing a second integrated circuit The insertion occurs during a test of a first integrated circuit. 15. The system according to item 1 of the scope of patent application, further comprising: a condition monitoring device that receives reports from each of two or more test devices, and a report of a test device specifies the test device's State and ability. 16. The system according to item 15 of the scope of patent application, further comprising: a condition monitoring connection separated from the communication ring. 17. The system according to item 15 of the scope of patent application, wherein: the report contains data characters exchanged between the controller and two or more test devices on the communication ring. 18. The system according to item 1 of the scope of patent application, wherein: the first test device includes a first processor and logic configured to insert a data character into the communication ring, the data character including a description Information about a first test event, and the second test device includes a second processor and logic configured to add the data character to describe information about a second test event. 19. The system according to item 18 of the scope of patent application, wherein: 64 1245912 the information describing the first test event includes information obtained by the first test device; and the information describing the second test event includes Information obtained by the second test equipment. 20. The system according to item 19 of the scope of patent application, wherein: the measurement controller processes the data character. 2 1. The system according to item 19 of the scope of patent application, wherein: at least one of the test equipment processes the data character. 22. The system according to item 18 of the scope of patent application, wherein: the data character contains information specifying a common clock time value and a test event occurring at the common clock time value. 2 3. — A secondary system for data and control signal distribution of an automatic circuit test system, the automatic circuit test system having test equipment for performing tests on an electronic circuit, the secondary system includes at least: a communication ring, which The daisy-chaining of the test equipment in the system is mutually connected, and the communication ring is configured to connect to each test equipment through a single input port and a single output port; a main clock circuit, which provides a main time Pulse signal; and a dedicated clock signal path between the test equipment in the test system and the main clock circuit, the dedicated clock signal path simultaneously distributes the main clock signal to all Test equipment. The communication ring is a dedicated path of the test equipment in the test system. During the execution of a test, a synchronization signal and a command signal are sent to each other, and the main clock signal received from a dedicated signal path is provided to the test. A dedicated universal clock signal for test equipment in the system. 24. A computer program product specifically stored on a machine-readable medium, which is a module used to control one or more configurations to test one or more integrated circuits in accordance with a test process. The product Contains instructions for causing a processor to execute a function. The instructions include at least the following steps: confirming at least one module from one or more modules participating in the test process; from an independent test thread of the confirmed module To confirm a test thread, the test thread includes instructions to generate data characters to be sent to other modules, and sends the test thread to the confirmed module. 2 5. The computer program product described in item 24 of the scope of patent application, further includes the following instructions: Calibrate the counter of the module to a common clock cycle. 26. The computer program product described in item 25 of the scope of patent application, further comprising the following instructions: generate a data character that specifies a test event, a specific shared 66 1245912 clock cycle, and one or more of the modules The group tests the particular test event during the common clock cycle. 2 7. —A method for controlling and synchronizing one or more test devices. The test is connected in a communication ring to test an electronic circuit. The method has at least the following steps: Use a common clock signal of a main clock to set The same common clock cycle as an internal time register of each test device that maintains one or more test devices, the common clock cycle provides a common clock time to schedule test events; inserting bus characters into the communication ring To pass the bus to each of the test devices, the inserted bus characters including at least one row of characters that specify a scheduled common clock time for a test event to be performed by a target device; and the target test device The at least one bus character is read out, and the scheduled common clock time value and the common clock cycle value in an internal register of the target test device are used to determine when to execute the test piece. 28. The method described in item 27 of the scope of patent application, the method further includes the steps of: inserting a part of a synchronization character into the communication ring, the part synchronously describes a first mark of a specific test event , The first mark is monitored by a test device, and the execution device contains or step to the inter-character confluence test using the time test event with the following character 67th 1245912 Add information to the part of the synchronization character, the information describes the A second mark for a particular test event, the second mark being monitored by a second test device. 2 9. The method as described in item 28 of the scope of patent application, which further includes the following steps: processing the part of synchronization characters to determine whether the specific test event has been completed. 30. The secondary system as described in item 23 of the scope of patent application, further comprising the following: a converter that converts one of the test devices into a module, the converter comprising a processor, a memory and a A data bus configured to connect the processor and the memory to the communication ring and exchange data with one or more of the test devices. 31. The secondary system described in item 23 of the scope of patent application, further comprising the following: a first converter that converts the first test equipment into a module, the first converter including a processor and Logic for inserting a part of a synchronization character into the communication ring; and a second converter that converts the second test device into a module, the second converter includes a processor and adds synchronization information to the Part of the synchronization character and return the part of the synchronization character to the logic of the first converter. 68 1245912 3 2. The secondary system described in item 23 of the scope of patent application, further includes the following: Condition monitoring device, which receives reports from each of these test equipments, and a report of a test equipment specifies the test The status and capabilities of the device. 3 3 · — A system that controls two or more test devices configured to test one or more integrated circuits, the system includes at least: a main clock, which is connected to each of the two or more test devices Test equipment, the master clock configured to simultaneously provide a master clock signal to each of two or more test equipments via a dedicated clock signal path; and a controller connected to two or more test equipment The communication ring formed by connecting two test devices together, each test device includes an input port and an output port, and the output port of a test device in the communication ring is only connected to the subsequent test device in the communication ring. Input port. The input port of the test device is only connected to the output port of the preceding test device in the communication ring. The data characters are transmitted through the communication ring. Therefore, the input port is provided to the test device. A data character is provided to the input port of the subsequent test device only through the output port of the test device, and wherein the controller is configured to synchronize the two or more Preparation counter to the master clock signal derived from a common time when the pulse time value, even when during a data synchronization character is inserted in the communication loop, so that the controller can be also synchronized. 69